Memory device, integrated circuit device, and operating method of integrated circuit device

Abstract

An integrated circuit device, a memory device, and an operating method of the integrated circuit device are disclosed. The integrated circuit device may include a transmit driver and an equalizer. The transmission driver may be configured to transmit an output signal to the outside through the signal line in a transmission operation of outputting the output signal to the outside in response to transmission control data, and provide a termination resistance in a reception operation of receiving an input signal from the outside through the signal line. The equalizer may be configured to amplify a high frequency component of the output signal in a transmit operation and provide a termination resistance in a receive operation in response to equalizer control data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0105098 filed in the Korean Intellectual Property Office on August 10, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to semiconductor memories, and more particularly, to memory devices, integrated circuit devices, and operating methods of integrated circuit devices. Background Art

[0004] Semiconductor memories can be divided into volatile memory devices such as static random access memory (RAM) (SRAM) and dynamic RAM (DRAM), and nonvolatile memory devices that retain stored data even when power supplied thereto is disconnected such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RAM), and so on.

[0005] (RRAM) and ferroelectric RAM (FRAM).

[0006] Generally, a DRAM device communicates with a memory controller or a host by using a high-speed interface such as a double data rate (DDR) interface. At this time, since impedance matching of a signal line or a data line is not achieved, a signal provided via the signal line or the data line is reflected, and as a result, there is a problem of reduced signal quality. Summary of the invention

[0007] The inventive concept provides a memory device, an integrated circuit device, and an operating method of the integrated circuit device having reduced area and parasitic capacitance of the memory device.

[0008] According to one aspect of the present invention, an integrated circuit device may include a transmission driver and an equalizer. The transmission driver may be configured to transmit an output signal to the outside through a signal line in a transmission operation of outputting the output signal to the outside in response to transmission control data, and provide a terminal resistor in a receiving operation of receiving an input signal from the outside through the signal line. The equalizer may be configured to amplify a high frequency component of the output signal in a transmission operation in response to equalizer control data, and provide a terminal resistor in a receiving operation.

[0009] According to another aspect of the present invention, a memory device may include a memory cell array, a data line driver, and an equalizer control circuit. The memory cell array may include a plurality of memory cells configured to store data. The data line driver may be configured to send data to an external device via a data line in a data transmission operation, and to provide a terminal resistor in a data reception operation. The equalizer may be configured to perform a pre-emphasis operation in a data transmission operation, and to perform an on-die termination (ODT) operation in a data reception operation in response to equalizer control data. The equalizer control circuit may be configured to provide the equalizer control data to the equalizer.

[0010] According to another aspect of the present invention, an operating method of an integrated circuit device including an equalizer control circuit, a transmit driver, and an equalizer may include: receiving data and a selection signal indicating a receive operation of the integrated circuit device by the equalizer control circuit; selecting, by the equalizer control circuit, a second EQ code corresponding to a first EQ code corresponding to a pre-emphasis operation and a second EQ code corresponding to an on-die termination (ODT) operation as a first code in response to the selection signal indicating the receive operation; generating, by the equalizer control circuit, equalizer control data by encoding based on the first code and received data; outputting the generated equalizer control data to the equalizer; and providing a terminal resistance by the equalizer based on the equalizer control data. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic block diagram of an electronic system according to an embodiment;

[0013] Figure 2A and Figure 2B is a diagram describing the operation of an electronic system according to an example embodiment;

[0014] Figure 3 is a block diagram of a transmitting circuit according to an embodiment;

[0015] Figure 4 is a block diagram of an equalizer (EQ) control circuit and a transmission control circuit according to an embodiment;

[0016] Figure 5 is a diagram for describing a first code and a second code according to an example embodiment;

[0017] Figure 6 is a block diagram of an equalizer and a TX driver according to an embodiment;

[0018] Figure 7 is a block diagram of an equalizer and a TX driver according to an embodiment;

[0019] Figure 8 is a flow chart of the operation of an integrated circuit device according to an embodiment;

[0020] Fig. 9 is a diagram illustrating the operation of an integrated circuit device according to an embodiment;

[0021] Fig.10 is a diagram illustrating the operation of an integrated circuit device according to an embodiment;

[0022] Fig.11 is a block diagram of an equalizer and a TX driver according to an embodiment;

[0023] Fig. 12A and Figure 2B is a table for describing first codes and second codes according to example embodiments;

[0024] Fig.13 is a block diagram illustrating a memory system according to an embodiment;

[0025] Fig.14 is a block diagram showing a memory device according to an embodiment; and

[0026] Fig.15 is a diagram illustrating a system to which a memory device is applied according to an embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the inventive concept are described clearly and in detail so that one of ordinary skill in the art can easily implement the inventive concept.

[0028] Terms such as “block,” “unit,” “module,” “driver,” and “circuit” that perform specific functions or include specific functions as described below or shown in the drawings may be implemented as types of software, hardware, or a combination thereof.

[0029] Figure 1 is a schematic block diagram of an electronic system 10 according to an embodiment.

[0030] Reference Figure 1 , the electronic system 10 may include a first integrated circuit device 11 and a second integrated circuit device 12. In an embodiment, each of the first integrated circuit device 11 and the second integrated circuit device 12 may include a computing device such as a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a smart phone, a wearable device, a personal computer, a server, a workstation, and a notebook. Alternatively or alternatively, the first integrated circuit device 11 and the second integrated circuit device 12 may include various hardware components included in a user device, for example, a processor, a memory device, a storage device, or a control device.

[0031] The first integrated circuit device 11 and the second integrated circuit device 12 may transmit and receive signals SIG to each other via a signal line SL for communication. The first integrated circuit device 11 includes a transmitting circuit TXC_A and a receiving circuit RXC_A. The second integrated circuit device 12 may include a transmitting circuit TXC_B and a receiving circuit RXC_B.

[0032] The transmitting circuit TXC_A of the first integrated circuit device 11 may transmit information generated by the first integrated circuit device 11 as a signal SIG (or an output signal SIG) to the second integrated circuit device 12 via the signal line SL. The receiving circuit RXC_B of the second integrated circuit device 12 may receive the signal SIG (or an input signal SIG) transmitted from the transmitting circuit TXC_A of the first integrated circuit device 11 via the signal line SL. Similar to what has been described above, the transmitting circuit TXC_B of the second integrated circuit device 12 may transmit the signal SIG to the first integrated circuit device 11 via the signal line SL, and the receiving circuit RXC_A of the first integrated circuit device 11 may receive the signal SIG via the signal line SL. In other words, the electronic system 10 may include a bidirectional link system that transmits bidirectional data via one signal line SL or one channel.

[0033] In an embodiment, the signal line SL may include a signal line (i.e., a wired communication channel) electrically connected between the first integrated circuit device 11 and the second integrated circuit device 12. In other words, each of the transmitting circuits TXC_A, TXC_B and the receiving circuits RXC_A, RXC_B can transmit and receive various types of signals, such as electrical signals and optical signals. In the following, for ease of description, it is assumed that each of the transmitting circuits TXC_A, TXC_B and the receiving circuits RXC_A, RXC_B operates based on electrical signals.

[0034] In an embodiment, the transmitting circuit TXC_A and the receiving circuit RXC_A are separately shown in the first integrated circuit device 11, and the receiving circuit RXC_B and the transmitting circuit TXC_B are separately shown in the second integrated circuit device 12, but the transmitting circuit TXC_A and the receiving circuit RXC_A can be implemented as one transmitting / receiving circuit in the first integrated circuit device 11, and the transmitting circuit TXC_B and the receiving circuit RXC_B can be implemented as one transmitting / receiving circuit in the second integrated circuit device 12.

[0035] However, when the signal SIG is transmitted via the signal line SL, the signal SIG may be distorted due to the reflection characteristics of the signal line SL or due to noise caused by external factors. As such, information transmitted by the transmission circuits TXC_A, TXC_B and information received by the reception circuits RXC_A, RXC_B may be different from each other. In other words, information to be transmitted by the first integrated circuit device 11 and information received by the second integrated circuit device 12 may be different from each other, and as a result, an error or a malfunction may occur in the second integrated circuit device 12.

[0036] In order to prevent the above-mentioned errors or failures, the transmitting circuit TXC_A, TXC_B or the receiving circuit RXC_A, RXC_B may include a component and / or function for correcting signal distortion caused by reflection characteristics or noise caused by external factors. For example, the transmitting circuit TXC_A, TXC_B may include an equalizer configured to correct signal distortion caused by reflection characteristics of the signal line SL, and the receiving circuit RXC_A, RXC_B may include an equalizer configured to correct signal distortion caused by reflection characteristics of the signal line SL (not shown).

[0037] Hereinafter, it is assumed that the first integrated circuit device 11 transmits the signal SIG to the second integrated circuit device 12. In other words, the first integrated circuit device 11 may be a transmitting end, and the second integrated circuit device 12 may be a receiving end.

[0038] The receiving circuit RXC_A may include a deserializer 220_A (or a deserializer circuit) and a sampler 210_A (or a sampler circuit). The receiving circuit RXC_B may include a deserializer 220_B (or a deserializer circuit) and a sampler 210_B (or a sampler circuit). The samplers 210_A and 210_B may sample the signal SIG based on the clock signal. For example, the samplers 210_A and 210_B may sample the logic value of the signal SIG at the rising edge or the falling edge of the clock signal. The samplers 210_A and 210_B may include a trigger that latches, holds, and stores the logic value of the signal SIG at the rising edge or the falling edge of the clock signal. The deserializers 220_A and 210_B may parallelize the sampled logic values ​​to generate data.

[0039] The transmission circuit TXC_A may include an equalizer 110_A (or a transmission equalizer), a transmission (TX) driver 120_A, an equalizer control circuit 130_A (hereinafter, referred to as an “EQ control circuit”), a transmission (TX) control circuit 140_A, and a serializer 150_A.

[0040] The transmission circuit TXC_B may include an equalizer 110_B (or a transmission equalizer), a transmission (TX) driver 120_B, an equalizer control circuit 130_B (hereinafter, referred to as an “EQ control circuit”), a transmission (TX) control circuit 140_B, and a serializer 150_B.

[0041] In order to reduce inter-symbol interference (ISI) on the signal line during signal transmission, the equalizer 110_A, 110_B can reduce the low-frequency gain and increase the high-frequency gain. When the signal SIG is sent at high speed via the signal line SL, the bandwidth of the channel may be limited due to the load, skin effect, dielectric loss, ISI, etc. on the signal line SL, and the high-frequency component of the signal may be reduced. The equalizer 110_A, 110_B can be used to correct channel losses in a bidirectional link system. The equalizer 110_A, 110_B can amplify the high-frequency component of the output signal. Alternatively or alternatively, the equalizer 110_A, 110_B can enhance or strengthen the high-frequency component of the signal. For example, the equalizer 110_A, 110_B may include a feed-forward equalizer (FFE).

[0042] The equalizers 110_A and 110_B can amplify the high-frequency components of the signal SIG in a transmission operation of outputting the signal SIG to the outside (for example, to an external device). The equalizer 110_A at the transmitting end (that is, the equalizer 110_A of the first integrated circuit device 11) can be used as a pre-emphasis circuit (or a de-emphasis circuit). The equalizer 110_A can operate as a pre-emphasis circuit during a data transmission operation. The equalizer 110_A can perform a pre-emphasis operation (hereinafter, referred to as an "EMP operation") (or a de-emphasis operation). For example, the EMP operation can be referred to as an operation of amplifying the high-frequency components of the signal SIG. In this document, for ease of description, the terms of the transmission operation and the data transmission operation can be used interchangeably.

[0043] The equalizers 110_A and 110_B can provide terminal resistance in the reception operation of receiving the signal SIG from the outside. The equalizer 110_B at the receiving end (i.e., the equalizer 110_B of the second integrated circuit device 12) can be used as an on-die termination (ODT) circuit, and the equalizer 110_B can operate as an ODT circuit during the data reception operation. The equalizer 110_B can perform an ODT operation. For example, the ODT operation can be referred to as an operation of providing a terminal resistance. In this document, for ease of description, the terms of reception operation and data reception operation can be used interchangeably.

[0044] The TX drivers 120_A, 120_B may be configured to control or drive the signal line SL. The TX drivers 120_A, 120_B may transmit or output the signal SIG to an external device via the signal line SL. The TX drivers 120_A, 120_B may control the impedance of the signal line SL so as to obtain impedance matching with respect to the signal line SL.

[0045] The TX drivers 120_A and 120_B may drive the signal line SL to transmit the signal SIG to the outside in a transmission operation of outputting the signal SIG to the outside. The TX driver 120_A at the transmitting end (i.e., the TX driver 120_A of the first integrated circuit device 11) may be used as an off-chip driver (OCD) circuit. The TX driver 120_A may operate as an OCD circuit. The TX driver 120_A may perform an OCD operation. For example, the OCD operation may be referred to as an operation of driving the signal line SL and transmitting or outputting data to the outside.

[0046] The TX drivers 120_A and 120_B may provide a terminal resistor in a receiving operation of receiving a signal SIG from the outside. The TX driver 120_B at the receiving end (i.e., the TX driver 120_B of the second integrated circuit device 12) may be used as an ODT circuit. The TX driver 120_B may operate as an ODT circuit in a data receiving operation. The TX driver 120_B may perform an ODT operation. For example, the ODT operation may be referred to as an operation of providing a terminal resistor.

[0047] The EQ control circuit 130_A may control the equalizer 110_A. The EQ control circuit 130_B may control the equalizer 110_B. The EQ control circuits 130_A and 130_B may control the equalizers 110_A and 110_B to be activated or deactivated. The EQ control circuits 130_A and 130_B may control the equalizers 110_A and 110_B to be turned on or off. The EQ control circuits 130_A and 130_B may control the equalizers 110_A and 110_B to operate as a pre-emphasis circuit or as an ODT circuit. The EQ control circuits 130_A and 130_B may control the equalizers 110_A and 110_B to perform an EMP operation or an ODT operation. The EQ control circuits 130_A and 130_B may control the equalizer 110 to perform an EMP operation in a transmission operation. The EQ control circuits 130_A, 130_B may control the equalizers 110_A, 110_B to perform an ODT operation in a receiving operation.

[0048] In an embodiment, the EQ control circuits 130_A, 130_B may generate equalizer control data (hereinafter, referred to as "EQ control data") and output the EQ control data to the equalizers 110_A, 110_B. The TX control circuit 140_A may control the TX driver 120_A. The TX control circuit 140_B may control the TX driver 120_B. The TX control circuits 140_A, 140_B may generate transmit control data and output the transmit control data to the TX drivers 120_A, 120_B. The serializers 150_A, 150_B may serialize the data to generate a signal SIG.

[0049] As described above, the equalizers 110_A and 110_B according to the embodiment can operate as ODT circuits in the receiving operation. In other words, the equalizer 110_B of the second integrated circuit device 12 can be activated in the receiving operation and provide a terminal resistance. The first integrated circuit device 11 can increase the ODT range by using both the TX driver 120_A and the equalizer 110_A as ODT. The second integrated circuit device 12 can increase the ODT range by using both the TX driver 120_B and the equalizer 110_B as ODT. For example, the ODT circuit can be configured to have one or more ODT resistance values ​​without increasing the area of ​​the ODT circuit. Therefore, an integrated circuit device with a reduced area of ​​a chip forming an integrated circuit device and reduced parasitic capacitance can be provided. In addition, the signal reflection of the signal line SL can be reduced, and the reliability of the signal SIG can be improved. The configuration and operation of the above-mentioned transmitting circuits TXC_A and TXC_B will be described in more detail below with reference to the diagram.

[0050] Figure 2A and Figure 2B is a diagram for describing the operation of the electronic system 10 according to an example embodiment.

[0051] Reference Figure 2A , the equalizer 110_B of the second integrated circuit device 12 at the receiving end is deactivated. Figure 2B , the equalizer 110 of the second integrated circuit device 12_B at the receiving end is activated. Figure 2A, the first integrated circuit device 11 may transmit the signal SIG to the second integrated circuit device 12 via the signal line SL. The first integrated circuit device 11 may be used as a transmitting end that outputs the signal SIG via the signal line SL. The second integrated circuit device 12 may be used as a receiving end that receives the signal SIG via the signal line SL. In other words, the first integrated circuit device 11 may include a transmitting end, and the second integrated circuit device 12 may include a receiving end. The transmitting circuit TXC_A of the first integrated circuit device 11 may generate the signal SIG and output the signal to the second integrated circuit device 12. In other words, the transmitting circuit TXC_A of the first integrated circuit device 11 may be turned on, and the receiving circuit RXC_A of the first integrated circuit device 11 may be turned off. In some embodiments, the transmitting circuit TXC_A of the first integrated circuit device 11 may be turned off, and the receiving circuit RXC_A of the first integrated circuit device 11 may be turned on.

[0052] The receiving circuit RXC_B of the second integrated circuit device 12 may receive the signal SIG. The receiving circuit RXC_B of the second integrated circuit device 12 may be turned on. The TX driver 120_B of the second integrated circuit device 12 may be used as an ODT circuit. The TX driver 120_B of the second integrated circuit device 12 and the TX control circuit 140_B of the second integrated circuit device 12 may be turned on. The equalizer 110_B, the EQ control circuit 130_B, and the serializer 150_B of the second integrated circuit device 12 may be turned off.

[0053] Reference Figure 2B , the first integrated circuit device 11 may transmit the signal SIG to the second integrated circuit device 12 via the signal line SL. The first integrated circuit device 11 may include a transmitting end, and the second integrated circuit device 12 may include a receiving end. The transmitting circuit TXC_A of the first integrated circuit device 11 may generate the signal SIG and output the signal to the second integrated circuit device 12. In other words, the transmitting circuit TXC_A of the first integrated circuit device 11 may be turned on, and the receiving circuit RXC_A of the first integrated circuit device 11 may be turned off.

[0054] The receiving circuit RXC_B of the second integrated circuit device 12 may receive the signal SIG. The receiving circuit RXC_B of the second integrated circuit device 12 may be turned on. The receiving circuit RXC_B of the second integrated circuit device 12 may be activated. The TX driver 120_B of the second integrated circuit device 12 may be used as an ODT circuit. The TX driver 120_B of the second integrated circuit device 12 and the EQ control circuit 130_B of the second integrated circuit device 12 may be turned on. The TX driver 120_B of the second integrated circuit device 12 and the EQ control circuit 130_B of the second integrated circuit device 12 may be activated.

[0055] In an embodiment, the equalizer 110_B of the second integrated circuit device 12 may be used as an ODT circuit. When the second integrated circuit device 12 receives the signal SIG from the first integrated circuit device 11, the equalizer 110_B of the second integrated circuit device 12 may provide a terminal resistance. In a signal receiving operation, the equalizer 110_B of the second integrated circuit device 12 and the EQ control circuit 130_B of the second integrated circuit device 12 may be turned on. In some embodiments, in a signal receiving operation, the equalizer 110_B of the second integrated circuit device 12 and the EQ control circuit 130_B of the second integrated circuit device 12 may be turned on. The serializer 150_B of the second integrated circuit device 12 may be turned off.

[0056] As mentioned above, despite Figure 2A The equalizer 110_B of the second integrated circuit device 12 in the embodiment may be deactivated, but Figure 2B The equalizer 110_B of the second integrated circuit device 12 in the receiving end can be activated. Since the equalizer 110_B at the receiving end provides a terminal resistance, signal distortion due to reflected waves can be prevented at the receiving end. In addition, an integrated circuit device with a reduced area and reduced parasitic capacitance can be provided.

[0057] Figure 3 is a block diagram of a transmitting circuit TXC according to an embodiment.

[0058] Reference Figure 1 and Figure 3 The transmitting circuit TXC may include an equalizer 110 , a TX driver 120 , an EQ control circuit 130 , a TX control circuit 140 , a serializer 150 , a delay circuit 160 , and a calibration circuit 170 . Figure 3 The transmission circuit TXC can correspond to Figure 1 Transmitting circuits TXC_A and TXC_B. Figure 3 The equalizer 110 may correspond to Figure 1 Equalizers 110_A, 110_B. Figure 3 The TX driver 120 may correspond to Figure 1 TX drivers 120_A, 120_B. Figure 3 The EQ control circuit 130 may correspond to Figure 1 EQ control circuits 130_A, 130_B. Figure 3 The TX control circuit 140 may correspond to Figure 1 TX control circuits 140_A, 140_B. Figure 3 The serializer 150 may correspond to Figure 1 Serializers 150_A, 150_B.

[0059] The serializer 150 may serialize data. For example, the serializer 150 may receive output data ODATA outputted in parallel from a plurality of memory cells. The serializer 150 may serialize the output data ODATA to generate first data DT1. The serializer 150 may output the first data DT1 to the delay circuit 160. The serializer 150 may output the first data DT1 to the TX control circuit 140.

[0060] The delay circuit 160 may delay the received first data DT1. For example, the delay circuit 160 may delay the first data DT1 according to a predetermined duration value. The delay circuit 160 may delay the first data DT1 and output the second data DT2. The delay circuit 160 may output the second data DT2 to the EQ control circuit 130.

[0061] The calibration circuit 170 may perform a calibration operation (or a training operation) for the operation of the first integrated circuit device 11 and the second integrated circuit device 12. The calibration circuit 170 may adjust the operation parameters of the first integrated circuit device 11 and the second integrated circuit device 12. The calibration circuit 170 may generate a plurality of codes (or one code) for controlling the equalizer 110, and provide the code to the EQ control circuit 130. The calibration circuit 170 may generate a plurality of codes (or one code) for controlling the TX driver 120, and provide the code to the TX control circuit 140.

[0062] The calibration circuit 170 may adjust the amplification strength of the equalizer 110. The calibration circuit 170 may adjust the degree of amplification of high frequency components. The calibration circuit 170 may generate and provide a code for the equalizer 110 to perform an EMP operation. The calibration circuit 170 may generate and provide a code for the equalizer 110 to perform an ODT operation. The calibration circuit 170 may generate a code for controlling the pull-up driver and the pull-down driver of the equalizer 110. The calibration circuit 170 may provide an EQ code (or equalizer code) EC to the equalizer control circuit 130. For example, the EQ code EC may include a code for controlling the pull-up driver and the pull-down driver of the equalizer 110.

[0063] The calibration circuit 170 may control the impedance of the signal line SL to achieve impedance matching of the signal line SL. The calibration circuit 170 may generate and provide multiple codes (or one code) for the TX driver 120 to perform OCD operations. The calibration circuit 170 may generate and provide multiple codes (or one code) for the TX driver 120 to perform ODT operations. The calibration circuit 170 may generate a code for controlling the pull-up driver and the pull-down driver of the TX driver 120. The calibration circuit 170 may provide the TX code (or transmit code) TC to the TX control circuit 140. For example, the TX code TC may include a code for controlling the pull-up driver and the pull-down driver of the TX driver 120.

[0064] In an embodiment, the EQ code EC may include a first EQ code and a second EQ code. For example, the first EQ code may correspond to the EMP operation of the equalizer 110, and the second EQ code may correspond to the ODT operation of the equalizer 110. The TX code TC may include a first TX code and a second TX code. For example, the first TX code may correspond to the OCD operation of the TX driver 120, and the second TX code may correspond to the ODT operation of the TX driver 120.

[0065] As described above, the calibration circuit 170 may perform a calibration operation to determine the first EQ code, the second EQ code, the first TX code, and the second TX code. The calibration circuit 170 may provide the first EQ code and the second EQ code to the EQ control circuit 130. The calibration circuit 170 may provide the first TX code and the second TX code to the TX control circuit 140.

[0066] The EQ control circuit 130 may receive the second data DT2. The EQ control circuit 130 may receive the EQ code EC. The EQ control circuit 130 may perform encoding based on the second data DT2 and the EQ code EC. The EQ control circuit 130 may encode the second data DT2 and the EQ code EC to generate EQ control data EQCD. The EQ control circuit 130 may provide the EQ control data EQCD to the equalizer 110.

[0067] For example, the EQ control circuit 130 may generate EQ control data EQCD based on a first EQ code corresponding to an EMP operation in a transmitting operation. The EQ control circuit 130 may output the EQ control data EQCD generated during the transmitting operation to the equalizer 110. The EQ control circuit 130 may generate EQ control data EQCD based on a second EQ code corresponding to an ODT operation in a receiving operation. The EQ control circuit 130 may output the EQ control data EQCD generated in a receiving operation to the equalizer 110.

[0068] The TX control circuit 140 may control the TX driver 120. The TX control circuit 140 may control whether the TX driver 120 operates as an OCD circuit or an ODT circuit. The TX control circuit 140 may control the TX driver 120 to perform an OCD operation or an ODT operation. The TX control circuit 140 may control the TX driver 120 to perform an OCD operation in a transmission operation. The TX control circuit 140 may control the TX driver 120 to perform an ODT operation in a reception operation.

[0069] The TX control circuit 140 may receive the first data DT1. The TX control circuit 140 may receive the TX code TC. The TX control circuit 140 may perform encoding based on the first data DT1 and the TX code TC. The TX control circuit 140 may perform encoding based on the first data DT1 and the TX code TC to generate transmission control data TXCD. The TX control circuit 140 may output the transmission control data TXCD to the TX driver 120.

[0070] For example, the TX control circuit 140 may generate the transmission control data TXCD based on the first TX code corresponding to the OCD operation in the transmission operation. The TX control circuit 140 may output the transmission control data TXCD generated in the transmission operation to the TX driver 120. The TX control circuit 140 may generate the transmission control data TXCD based on the second TX code corresponding to the ODT operation in the reception operation. The TX control circuit 140 may output the transmission control data TXCD generated in the reception operation to the TX driver 120.

[0071] The equalizer 110 may receive the EQ control data EQCD. The equalizer 110 may perform an operation in response to the EQ control data EQCD. The equalizer 110 may perform an EMP operation based on the EQ control data EQCD. Alternatively or alternatively, the equalizer 110 may perform an ODT operation based on the EQ control data EQCD.

[0072] The TX driver 120 may receive the transmission control data TXCD. The TX driver 120 may perform an operation in response to the transmission control data TXCD. The TX driver 120 may perform an OCD operation based on the transmission control data TXCD. For example, the TX driver 120 may perform an OCD operation based on the transmission control data TXCD generated based on the first TX code. The TX driver 120 may perform an ODT operation based on the transmission control data TXCD. For example, the TX driver 120 may perform an ODT operation based on the transmission control data TXCD generated based on the second TX code.

[0073] Figure 4 is a block diagram of the EQ control circuit 130 and the TX control circuit 140 according to an embodiment. Figure 5 is a diagram for describing a first code CODE1 and a second code CODE2 according to example embodiments.

[0074] Reference Figure 3 , Figure 4 and Figure 5 , the EQ control circuit 130 may include a first encoder ENC1 and a first multiplexer MUX1. The EQ control circuit 130 may receive the second data DT2, the first EQ code EC1, the second EQ code EC2, and the selection signal SEL. The EQ control circuit 130 may receive the second data DT2 from the delay circuit 160. The EQ control circuit 130 may receive the EQ code EC from the calibration circuit 170. The EQ code EC may include the first EQ code EC1 and the second EQ code EC2. The EQ control circuit 130 may receive the first EQ code EC1 and the second EQ code EC2 from the calibration circuit 170.

[0075] The first EQ code EC1 may correspond to an EMP operation, and the second EQ code EC2 may correspond to an ODT operation. In other words, the first EQ code EC1 may include a code used in an EMP operation, and the second EQ code EC2 may include a code used in an ODT operation. The first EQ code EC1 may be used to perform or control an EMP operation, and may include information about an amplification strength. The second EQ code EC2 may be used to perform or control an ODT operation, and may include information about an ODT resistance value.

[0076] For example, the calibration circuit 170 may be configured to determine the optimal amplification strength of the EMP operation by using the calibration operation, and set the value corresponding to the optimal amplification strength as the first EQ code EC1. The calibration circuit 170 may be configured to determine the optimal resistance value of the ODT operation by using the calibration operation, and set the value corresponding to the optimal resistance value as the second EQ code EC2. The calibration circuit 170 may provide the first EQ code EC1 and the second EQ code EC2 to the EQ control circuit 130.

[0077] The first multiplexer MUX1 may receive a selection signal SEL, a first EQ code EC1, and a second EQ code EC2. The first multiplexer MUX1 may provide the first EQ code EC1 or the second EQ code EC2 as a first code CODE1 to the first encoder ENC1 in response to the selection signal SEL. The first multiplexer MUX1 may output the first EQ code EC1 corresponding to a pre-emphasis operation or the second EQ code EC2 corresponding to an on-die termination (ODT) operation as the first code CODE1 in response to the selection signal SEL.

[0078] In some embodiments, in the case where the transmission signal SIG is at the transmission end, the selection signal SEL may have a first value (e.g., "0"). In the case where the reception signal SIG is at the reception end, the selection signal SEL may have a second value (e.g., "1"). When the selection signal SEL has the first value (e.g., "0") (i.e., at the transmission end), the first multiplexer MUX1 may output the first EQ code EC1 as the first code CODE1 to the first encoder ENC1. When the selection signal SEL has the second value (e.g., "1") (i.e., at the reception end), the first multiplexer MUX1 may output the second EQ code EC2 as the first code CODE1 to the first encoder ENC1.

[0079] In other words, the first multiplexer MUX1 may output the first EQ code EC1 as the first code CODE1 in response to the selection signal SEL indicating the transmission operation. The first multiplexer MUX1 may output the second EQ code EC2 as the first code CODE1 in response to the selection signal SEL indicating the reception operation.

[0080] The first encoder ENC1 may receive the second data DT2 and the first code CODE1. The first encoder ENC1 may encode the second data DT2 and the first code CODE1 to generate EQ pull-up data EQ_PUD and EQ pull-down data EQ_PDD. The first encoder ENC1 may output the EQ pull-up data EQ_PUD and the EQ pull-down data EQ_PDD. The first encoder ENC1 may provide the EQ pull-up data EQ_PUD and the EQ pull-down data EQ_PDD to the equalizer 110. For example, the EQ pull-up data EQ_PUD may include a control value for controlling a plurality of pull-up drivers of the equalizer 110. The EQ pull-down data EQ_PDD may include a control value for controlling a plurality of pull-down drivers of the equalizer 110. In other words, the first encoder INC1 may encode the second data DT2 and the code provided by the first multiplexer MUX1 to output the EQ control data EQCD.

[0081] As described above, the EQ control circuit 130 may transmit the EQ control data EQCD to the equalizer 110. The EQ control data EQCD may include EQ pull-up data EQ_PUD and EQ pull-down data EQ_PDD. The EQ control circuit 130 may generate and output the EQ control data EQCD (e.g., EQ pull-up data EQ_PUD and EQ pull-down data EQ_PDD) based on the first EQ code EC1 corresponding to the EMP operation in the transmission operation. The EQ control circuit 130 may generate and output the EQ control data EQCD (e.g., EQ pull-up data EQ_PUD and EQ pull-down data EQ_PDD) based on the second EQ code EC2 corresponding to the ODT operation in the reception operation.

[0082] The TX control circuit 140 may include a second encoder ENC2 and a second multiplexer MUX2. The TX control circuit 140 may receive the first data DT1, the first TX code TC1, the second TX code TC2, and the selection signal SEL. The TX control circuit 140 may receive the first data DT1 from the serializer 150. The TX control circuit 140 may receive the TX code TC from the calibration circuit 170. The TX code TC may include the first TX code TC1 and the second TX code TC2. The TX control circuit 140 may receive the first TX code TC1 and the second TX code TC2 from the calibration circuit 170.

[0083] The first TX code TC1 may correspond to an OCD operation, and the second TX code TC2 may correspond to an ODT operation. In other words, the first TX code TC1 may include a code used in an OCD operation, and the second TX code TC2 may include a code used in an ODT operation. The first TX code TC1 may indicate an OCD operation, and may indicate an output strength. The second TX code TC2 may indicate an ODT operation, and may indicate an ODT resistance value.

[0084] For example, the calibration circuit 170 may determine the optimal output strength of the OCD operation based on the calibration operation, and set the value of the optimal output strength to the first TX code TC1. For example, the calibration circuit 170 may determine the optimal resistance value of the ODT operation based on the calibration operation, and set the optimal resistance value to the second TX code TC2. The calibration circuit 170 may provide the first TX code TC1 and the second TX code TC2 to the TX control circuit 140.

[0085] The second multiplexer MUX2 may receive a selection signal SEL, a first TX code TC1, and a second TX code TC2. The second multiplexer MUX2 may provide the first TX code TC1 or the second TX code TC2 to the second encoder ENC2 in response to the selection signal SEL. The second multiplexer MUX2 may output the first TX code TC1 corresponding to the off-chip driver (OCD) operation or the second TX code TC2 corresponding to the on-die terminal (ODT) operation as the second code CODE2 in response to the selection signal SEL.

[0086] For example, when the selection signal SEL has a first value (e.g., "0") (i.e., at the transmitting end), the second multiplexer MUX2 may output the first TX code TC1 as the second code CODE2 to the second encoder ENC2. When the selection signal SEL has a second value (e.g., "1") (i.e., at the receiving end), the second multiplexer MUX2 may output the second TX code TC2 as the second code CODE2 to the second encoder ENC2.

[0087] For example, the second multiplexer MUX2 may output the first TX code TC1 as the second code CODE2 in response to the selection signal SEL indicating the transmission operation. The second multiplexer MUX2 may output the second TX code TC2 as the second code CODE2 in response to the selection signal SEL indicating the reception operation.

[0088] The second encoder ENC2 may receive the first data DT1 and the second code CODE2. The second encoder ENC2 may encode the first data DT1 and the second code CODE2 to generate TX pull-up data TX_PUD and TX pull-down data TX_PDD. The second encoder ENC2 may output the TX pull-up data TX_PUD and the TX pull-down data TX_PDD. The second encoder ENC2 may provide the TX pull-up data TX_PUD and the TX pull-down data TX_PDD to the TX driver 120. For example, the TX pull-up data TX_PUD may include a control value for controlling a plurality of pull-up drivers of the TX driver 120. The TX pull-down data TX_PDD may include a control value for controlling a plurality of pull-down drivers of the TX driver 120. In other words, the second encoder ENC2 may encode the first data DT1 and the code provided by the second multiplexer MUX2, and may output the transmission control data TXCD.

[0089] As described above, the TX control circuit 140 may transmit the transmission control data TXCD to the TX driver 120. The transmission control data TXCD may include TX pull-up data TX_PUD and TX pull-down data TX_PDD. The TX control circuit 140 may generate and output the transmission control data TXCD (e.g., TX pull-up data TX_PUD and TX pull-down data TX_PDD) based on the first TX code TC1 corresponding to the OCD operation in the transmission operation. The TX control circuit 140 may generate and output the transmission control data TXCD (e.g., TX pull-up data TX_PUD and TX pull-down data TX_PDD) based on the second TX code TC2 corresponding to the ODT operation in the reception operation.

[0090] Figure 6 is a block diagram of the equalizer 110 and the TX driver 120 according to an embodiment.

[0091] Reference Figure 3 and Figure 6 , the equalizer 110 may include a plurality of first pull-up drivers PUU1 and a plurality of first pull-down drivers PDU1. Each of the plurality of first pull-up drivers PUU1 may be connected between a power supply voltage and a signal line SL. Each of the plurality of first pull-down drivers PDU1 may be connected between a signal line SL and a ground voltage GND.

[0092] As described above, the EQ control circuit 130 may output the EQ control data EQCD to the equalizer 110. For example, the EQ control circuit 130 may provide the EQ pull-up data EQ_PUD and the EQ pull-down data EQ_PDD to the equalizer 110. Each of the plurality of first pull-up drivers PUU1 may receive the EQ pull-up data EQ_PUD. Each of the plurality of first pull-down drivers PDU1 may receive the EQ pull-down data EQ_PDD. Each of the plurality of first pull-up drivers PUU1 may operate based on the EQ pull-up data EQ_PUD. Each of the plurality of first pull-down drivers PDU1 may operate based on the EQ pull-down data EQ_PDD.

[0093] The TX driver 120 may include a plurality of second pull-up drivers PUU2 and a plurality of second pull-down drivers PDU2. Each of the plurality of second pull-up drivers PUU2 may be connected between a power supply voltage and a signal line SL. Each of the plurality of second pull-down drivers PDU2 may be connected between a signal line SL and a ground voltage GND.

[0094] As described above, the TX control circuit 140 may output the transmit control data TXCD to the TX driver 120. For example, the TX control circuit 140 may provide the TX pull-up data TX_PUD and the TX pull-down data TX_PDD to the TX driver 120. Each of the plurality of second pull-up drivers PUU2 may receive the TX pull-up data TX_PUD. Each of the plurality of second pull-down drivers PDU2 may receive the TX pull-down data TX_PDD. Each of the plurality of second pull-up drivers PUU2 may operate based on the TX pull-up data TX_PUD. Each of the plurality of second pull-down drivers PDU2 may operate based on the TX pull-down data TX_PDD.

[0095] As described above, the equalizer 110 and the TX driver 120 may be connected to the signal line SL. The equalizer 110 and the TX driver 120 may be connected in parallel to each other. The impedance of the signal line SL may be adjusted by using a plurality of first pull-up drivers PUU1 and a plurality of second pull-up drivers PUU2 and a plurality of first pull-down drivers PDU1 and a plurality of second pull-down drivers PDU2.

[0096] Figure 7 is a block diagram of the equalizer 110 and the TX driver 120 according to an embodiment.

[0097] Reference Figure 3 and Figure 7, the equalizer 110 may include a plurality of first pull-up drivers PUU1 and a plurality of first pull-down drivers PDU1. Each of the plurality of first pull-up drivers PUU1 may include a first transistor TR1 and a first resistor R1 (or a resistor device). The first transistor TR1 may be connected between a power supply voltage and the first resistor R1. In other words, the first transistor TR1 may be connected between the power supply voltage and the first node n1. The first transistor TR1 may operate in response to the EQ pull-up data EQ_PUD. The first resistor R1 may be connected between the first transistor TR1 and the signal line SL. For example, the first resistor R1 may be connected between the first node n1 and the signal line SL.

[0098] Each of the plurality of first pull-down drivers PDU1 may include a second transistor TR2 and a second resistor R2. The second resistor R2 may be connected between the signal line SL and the second transistor TR2. In other words, the second resistor R2 may be connected between the signal line SL and the second node n2. The second transistor TR2 may be connected between the second resistor R2 and the ground voltage GND. For example, the second transistor TR2 may be connected between the second node n2 and the ground voltage GND. The second transistor TR2 may operate in response to the EQ pull-down data EQ_PDD.

[0099] The TX driver 120 may include a plurality of second pull-up drivers PUU2 and a plurality of second pull-down drivers PDU2. Each of the plurality of second pull-up drivers PUU2 may include a third transistor TR3 and a third resistor R3. The third transistor TR3 may be connected between the power supply voltage and the third resistor R3. For example, the third transistor TR3 may be connected between the power supply voltage and the third node n3. The third transistor TR3 may operate in response to the TX pull-up data TX_PUD. The third resistor R3 may be connected between the third transistor TR3 and the signal line SL. For example, the third resistor R3 may be connected between the third node n3 and the signal line SL.

[0100] Each of the plurality of second pull-down drivers PDU2 may include a fourth transistor TR4 and a fourth resistor R4. The fourth resistor R4 may be connected between the signal line SL and the fourth transistor TR4. For example, the fourth resistor R4 may be connected between the signal line SL and the fourth node n4. The fourth transistor TR4 may be connected between the fourth resistor R4 and the ground voltage GND. For example, the fourth transistor TR4 may be connected between the fourth node n4 and the ground voltage GND. The fourth transistor TR4 may operate in response to the TX pull-down data TX_PDD.

[0101] In an embodiment, when the equalizer 110 is used as an ODT, the second transistor TR2 may be disconnected. For example, when the equalizer 110 performs an ODT operation, the second transistor TR2 may be disconnected. For example, the second transistor TR2 may be disconnected in response to the EQ pull-down data EQ_PDD having a low level. When the TX driver 120 is used as an ODT, the fourth transistor TR4 may be disconnected. For example, when the TX driver 120 performs an ODT operation, the fourth transistor TR4 may be disconnected. For example, the fourth transistor TR may be disconnected in response to the TX pull-down data TX_PDD having a low level.

[0102] For example, when receiving the signal SIG, the first transistor TR1 may be turned on and the first resistor R1 may be connected between the power supply voltage and the signal line SL, and the second transistor TR2 may be turned off and the second resistor R2 may not be connected between the ground voltage GND and the signal line SL. When the first resistor R1 is connected between the power supply voltage and the signal line SL, the reflection of the signal SIG sent via the signal line SL may be suppressed. When receiving the signal SIG, the third transistor TR3 may be turned on and the third resistor R3 may be connected between the power supply voltage and the signal line SL, and the fourth transistor TR4 may be turned off and the fourth resistor R4 may not be connected between the ground voltage GND and the signal line SL. When the third resistor R3 is connected between the power supply voltage and the signal line SL, the reflection of the signal SIG sent via the signal line SL may be suppressed. Impedance matching of the signal line SL may be achieved by turning on or off the first transistor TR1 and the third transistor TR3 and turning off the second transistor TR2 and the fourth transistor TR4.

[0103] Figure 8 is a flowchart of operations of the first integrated circuit device 11 and the second integrated circuit device 12 according to the embodiment.

[0104] Reference Figure 8 , a calibration operation for generating codes of the first integrated circuit device 11 and the second integrated circuit device 12. However, the scope of the inventive concept is not limited thereto. Figure 1 , Figure 3 and Figure 8 , in operation S11 , the first integrated circuit device 11 and the second integrated circuit device 12 may be turned on.

[0105] In operation S12, the first integrated circuit device 11 and the second integrated circuit device 12 may perform an initialization operation. For example, the first integrated circuit device 11 and the second integrated circuit device 12 may perform an initialization operation of setting various information required for operating the first integrated circuit device 11 and the second integrated circuit device 12 according to a predefined method.

[0106] In operation S13, the first integrated circuit device 11 and the second integrated circuit device 12 may perform a calibration operation. In an embodiment, the first integrated circuit device 11 and the second integrated circuit device 12 may generate a code by using a calibration operation. Alternatively or alternatively, the first integrated circuit device 11 and the second integrated circuit device 12 may determine the value of the code by performing a calibration operation.

[0107] In an embodiment, the first integrated circuit device 11 and the second integrated circuit device 12 may generate an EQ code used by the equalizer 110. The first integrated circuit device 11 and the second integrated circuit device 12 may generate a first EQ code EC1 corresponding to the amplification strength of the equalizer 110. The first integrated circuit device 11 and the second integrated circuit device 12 may generate a first EQ code EC1 corresponding to the EMP operation of the equalizer 110 to remove signal interference. The first integrated circuit device 11 and the second integrated circuit device 12 may generate a second EQ code EC2 corresponding to the ODT resistance value of the equalizer 110. The first integrated circuit device 11 and the second integrated circuit device 12 may generate a second EQ code EC2 corresponding to the ODT operation of the equalizer 110 to prevent signal distortion caused by reflected waves.

[0108] In an embodiment, the first integrated circuit device 11 and the second integrated circuit device 12 may generate a TX code used by the TX driver 120. The first integrated circuit device 11 and the second integrated circuit device 12 may generate a first TX code TC1 corresponding to the output strength of the TX driver 120. The first integrated circuit device 11 and the second integrated circuit device 12 may generate a first TX code TC1 corresponding to the OCD operation of the TX driver 120 to achieve impedance matching of the data line. The first integrated circuit device 11 and the second integrated circuit device 12 may generate a second TX code TC2 corresponding to the ODT resistance value of the TX driver 120. The first integrated circuit device 11 and the second integrated circuit device 12 may generate a second TX code TC2 corresponding to the ODT operation of the TX driver 120 to prevent signal distortion caused by reflected waves.

[0109] In operation S14, the first integrated circuit device 11 and the second integrated circuit device 12 may perform normal operations. For example, the first integrated circuit device 11 and the second integrated circuit device 12 may determine whether a signal is received or transmitted. The first integrated circuit device 11 and the second integrated circuit device 12 may generate a selection signal SEL indicating a transmission operation or a reception operation. The first integrated circuit device 11 and the second integrated circuit device 12 may determine the first code CODE1 and the second code CODE2 based on the selection signal SEL.

[0110] During normal operation, the first integrated circuit device 11 and the second integrated circuit device 12 may encode the second data DT2 based on the first code CODE1, and control the equalizer 110 based on the encoded second data (e.g., EQ control data EQCD). The first integrated circuit device 11 and the second integrated circuit device 12 may encode the first data DT1 based on the second code CODE2, and control the TX driver 120 based on the encoded first data (e.g., transmission control data TXCD).

[0111] The operations of the first integrated circuit device 11 and the second integrated circuit device 12 described above are examples, and the scope of the inventive concept is not limited thereto. For example, the calibration operation may be performed in different ways. For example, when the first integrated circuit device 11 and the second integrated circuit device 12 are operating, the calibration operation may be performed according to various requirements such as temperature changes.

[0112] Fig. 9 is a diagram illustrating operations of the first integrated circuit device 11 and the second integrated circuit device 12 according to the embodiment. Fig.10 is a diagram illustrating operations of the first integrated circuit device 11 and the second integrated circuit device 12 according to the embodiment.

[0113] Reference Fig. 9 The operation of the first integrated circuit device 11 and the second integrated circuit device 12 at the transmitting end is described, and reference is made to Fig.10 The operations of the first integrated circuit device 11 and the second integrated circuit device 12 at the receiving end are described.

[0114] Reference Figure 1 , Figure 3 and Fig. 9 , at the transmitting end, the selection signal SEL may have a first value (e.g., “0”). For example, the first integrated circuit device 11 may further include a command decoder. The command decoder may set the selection signal SEL to a first value (e.g., “0”) in response to the read command. In some embodiments, the calibration circuit 170 may set the selection signal SEL to a first value (e.g., “0”).

[0115] In operation S110, the first multiplexer MUX1 may receive a selection signal SEL having a first value (eg, "0"). In other words, the first multiplexer MUX1 may receive the selection signal SEL indicating a transmission operation.

[0116] In operation S120, the first multiplexer MUX1 may output the first code CODE1 in response to the selection signal SEL having the first value. In response to the selection signal SEL indicating the transmission operation, the first multiplexer MUX1 may select the first EQ code EC1 corresponding to the EMP operation and the second EQ code EC2 corresponding to the ODT operation as the first code CODE1.

[0117] For example, because the selection signal SEL has a first value (e.g., "0"), the first multiplexer MUX1 may output the first EQ code EC1 as the first code CODE1. In other words, the first multiplexer MUX1 at the transmitting end (e.g., the first multiplexer MUX1 of the first integrated circuit device 11) may provide the first EQ code EC1 as a code corresponding to the EMP operation to the first encoder ENC1.

[0118] For example, the first EQ code EC1 may include Fig.11 Each of the plurality of first pull-up drivers PUU1 in the embodiment receives a code and a Fig.11 In one embodiment, the code of the first EQ code received by each of the plurality of first pull-up drivers PUU1 may be the same as or different from the code of the first EQ code received by each of the plurality of first pull-down drivers PDU1.

[0119] In operation S130, the first encoder ENC1 may generate EQ control data EQCD and output the generated EQ control data EQCD to the equalizer 110. The first encoder ENC1 may encode the second data DT2 and the first code CODE1 and generate EQ control data EQCD (e.g., EQ pull-up data EQ_PUD and EQ pull-down data EQ_PDD). The first encoder ENC1 may provide the EQ pull-up data EQ_PUD and the EQ pull-down data EQ_PDD to the equalizer 110.

[0120] For example, the first encoder ENC1 at the transmitting end (eg, the first encoder ENC1 of the first integrated circuit device 11) may generate EQ control data EQCD and output the EQ control data EQCD to the equalizer 110. For example, the EQ control data EQCD may include Fig.11The first EQ pull-up data EQ_PUD1', the second EQ pull-up data EQ_PUD2', the first EQ pull-down data EQ_PDD1', and the second EQ pull-down data EQ_PDD2' may include a control value for controlling each of the plurality of first pull-up drivers PUU1 of the equalizer 110 when performing the EMP operation. The first EQ pull-down data EQ_PDD1 and the second EQ pull-down data EQ_PDD2' may include a control value for controlling each of the plurality of first pull-down drivers PDU1 of the equalizer 110 when performing the EMP operation. In other words, the EQ control circuit 130 may output the EQ control data EQCD corresponding to the EMP operation to the equalizer 110.

[0121] In operation S140, the equalizer 110 may perform an EMP operation. The equalizer 110 may receive EQ control data EQCD. For example, the equalizer 110 may receive first EQ pull-up data EQ_PUD1', second EQ pull-up data EQ_PUD2', first EQ pull-down data EQ_PDD1', and second EQ pull-down data EQ_PDD2'. The equalizer 110 may perform an EMP operation based on the EQ control data EQCD. The equalizer 110 may enhance the high frequency component of the signal SIG based on the EQ control data EQCD.

[0122] In operation S210, the second multiplexer MUX2 may receive a selection signal SEL having a first value (eg, '0'). In other words, the second multiplexer MUX2 may receive the selection signal SEL indicating a transmission operation.

[0123] In operation S220, the second multiplexer MUX2 may output the second code CODE2 in response to the selection signal SEL having the first value. In response to the selection signal SEL indicating the transmission operation, the second multiplexer MUX2 may select the first TX code TC1 corresponding to the OCD operation and the second TX code TC2 corresponding to the ODT operation as the second code CODE2.

[0124] For example, because the selection signal SEL has a first value (e.g., "0"), the second multiplexer MUX2 may output the second code CODE2. In other words, the second multiplexer MUX2 at the transmitting end (e.g., the second multiplexer MUX2 of the first integrated circuit device 11) may provide the first TX code TC1, which is a code corresponding to the OCD operation, to the second encoder ENC2.

[0125] For example, the first TX code TC1 may include a code received by each of the plurality of second pull-up drivers PUU2 and a code received by each of the plurality of second pull-down drivers PDU2. In one embodiment, the code of the first TX code TC1 received by each of the plurality of second pull-up drivers PUU2 may be the same as or different from the code of the first TX code TC1 received by each of the plurality of second pull-down drivers PDU2.

[0126] In operation S230, the second encoder ENC2 may generate transmission control data TXCD and output the generated transmission control data TXCD to the TX driver 120. The second encoder ENC2 may encode the first data DT1 and the second code CODE2 and generate transmission control data TXCD (e.g., TX pull-up data TX_PUD and TX pull-down data TX_PDD). The second encoder ENC2 may provide the TX pull-up data TX_PUD and the TX pull-down data TX_PDD to the TX driver 120.

[0127] For example, the second encoder ENC2 at the transmitting end (for example, the second encoder ENC2 of the first integrated circuit device 11) may generate the transmission control data TXCD and output the transmission control data TXCD to the TX driver 120. For example, the transmission control data TXCD may include the first TX pull-up data TX_PUD1', the second TX pull-up data TX_PUD2', the first TX pull-down data TX_PDD1', and the second TX pull-down data TX_PDD2'. The first TX pull-up data TX_PUD1' and the second TX pull-up data TX_PUD2' may include a control value for controlling each of the plurality of second pull-up drivers PUU2 of the TX driver 120 when performing the OCD operation. The first TX pull-down data TX_PDD1' and the second TX pull-down data TX_PDD2' may include a control value for controlling each of the plurality of second pull-down drivers PDU2 of the TX driver 120 when performing the OCD operation. In other words, the TX control circuit 140 at the transmitting end may output the transmission control data TXCD corresponding to the OCD operation to the TX driver 120.

[0128] In operation S240, the TX driver 120 may perform an OCD operation. The TX driver 120 may receive the transmission control data TXCD. For example, the TX driver 120 may receive the first TX pull-up data TX_PUD1', the second TX pull-up data TX_PUD2', the first TX pull-down data TX_PDD1', and the second TX pull-down data TX_PDD2'. The TX driver 120 may perform an OCD operation based on the transmission control data TXCD. The TX driver 120 may drive the signal line SL based on the transmission control data TXCD.

[0129] Operations S110 to S140 may be performed simultaneously with operations S210 to S240, and may be performed in an interchangeable order. When one or more embodiments may be implemented differently, the order of specific operations may be performed differently from the above order. For example, two operations described in succession may be performed substantially simultaneously or in an order opposite to the described order.

[0130] Reference Figure 1 , Figure 3 and Fig.10 , at the receiving end, the selection signal SEL may have a second value (e.g., "1"). For example, the second integrated circuit device 12 may further include a command decoder. The command decoder may set the selection signal SEL to a second value (e.g., "1") in response to the write command. In some embodiments, the calibration circuit 170 may set the selection signal SEL to a second value (e.g., "1").

[0131] In operation S310, the first multiplexer MUX1 may receive a selection signal SEL having a second value (eg, '1'). In other words, the first multiplexer MUX1 may receive the selection signal SEL indicating a receiving operation.

[0132] In operation S320, the first multiplexer MUX1 may output the first code CODE1 in response to the selection signal SEL having the second value. In response to the selection signal SEL indicating the reception operation, the first multiplexer MUX1 may select the second EQ code EC2 among the first EQ code EC1 corresponding to the EMP operation and the second EQ code EC2 corresponding to the ODT operation as the first code CODE1.

[0133] For example, because the selection signal SEL has the second value (e.g., "1"), the first multiplexer MUX1 can output the second EQ code EC2 as the first code CODE1. In other words, the first multiplexer MUX1 at the receiving end (e.g., the first multiplexer MUX1 of the second integrated circuit device 12) can provide the second EQ code EC2 as a code corresponding to the ODT operation to the first encoder ENC1.

[0134] For example, the second EQ code EC2 may include a code received by each of the plurality of first pull-up drivers PUU1 and a code received by each of the plurality of first pull-down drivers PDU1. In one embodiment, the code of the second EQ code EC2 received by each of the plurality of first pull-up drivers PUU1 may be the same as or different from the code of the second EQ code EC2 received by each of the plurality of first pull-down drivers PDU1.

[0135] In operation S330, the first encoder ENC1 may generate EQ control data EQCD and output the generated EQ control data EQCD to the equalizer 110. The first encoder ENC1 may encode the second data DT2 and the first code CODE1 and generate EQ control data EQCD (e.g., EQ pull-up data EQ_PUD and EQ pull-down data EQ_PDD). The first encoder ENC1 may provide the EQ pull-up data EQ_PUD and the EQ pull-down data EQ_PDD to the equalizer 110.

[0136] For example, the first encoder ENC1 at the receiving end (e.g., the first encoder ENC1 of the second integrated circuit device 12) may generate EQ control data EQCD and output the EQ control data EQCD to the equalizer 110. For example, the EQ control data EQCD may include first EQ pull-up data EQ_PUD1', second EQ pull-up data EQ_PUD2', first EQ pull-down data EQ_PDD1', and second EQ pull-down data EQ_PDD2'. The first EQ pull-up data EQ_PUD1' and the second EQ pull-up data EQ_PUD2' may include a control value for controlling each of a plurality of first pull-up drivers PUU1 of the equalizer 110 when performing an ODT operation. The first EQ pull-down data EQ_PDD1' and the second EQ pull-down data EQ_PDD2' may include a control value for controlling each of a plurality of first pull-down drivers PDU1 of the equalizer 110 when performing an ODT operation. In other words, the EQ control circuit 130 at the receiving end may output EQ control data EQCD corresponding to the ODT operation to the equalizer 110.

[0137] In operation S340, the equalizer 110 may perform an ODT operation. The equalizer 110 may receive EQ control data EQCD. For example, the equalizer 110 may receive first EQ pull-up data EQ_PUD1', second EQ pull-up data EQ_PUD2', first EQ pull-down data EQ_PDD1', and second EQ pull-down data EQ_PDD2'. The equalizer 110 may perform an ODT operation based on the EQ control data EQCD. The equalizer 110 may determine the size of the ODT resistor based on the EQ control data EQCD. The equalizer 110 may prevent signal distortion due to reflected waves by using the ODT operation. The terminal resistance of the equalizer 110 may be determined based on the EQ control data EQCD. The terminal resistance value of the equalizer 110 may be adjusted to be equal to the impedance of the signal line SL. The equalizer 110 may absorb the energy of the signal transmitted via the signal line SL and prevent reflection of the signal at the receiving end.

[0138] In operation S410, the second multiplexer MUX2 may receive a selection signal SEL having a second value (eg, “1”). In other words, the second multiplexer MUX2 may receive the selection signal SEL indicating a receiving operation.

[0139] In operation S420, the second multiplexer MUX2 may output the second code CODE2 in response to the selection signal SEL having the second value. In response to the selection signal SEL indicating the receiving operation, the second multiplexer MUX2 may select the second TX code TC2 among the first TX code TC1 corresponding to the OCD operation and the second TX code TC2 corresponding to the ODT operation as the second code CODE2.

[0140] For example, because the selection signal SEL has a second value (e.g., "1"), the second multiplexer MUX2 may output the second code CODE2. In other words, the second multiplexer MUX2 at the receiving end (e.g., the second multiplexer MUX2 of the second integrated circuit device 12) may provide the second TX code TC2, which is a code corresponding to the ODT operation, to the second encoder ENC2.

[0141] For example, the second TX code TC2 may include a code received by each of the plurality of second pull-up drivers PUU2 and a code received by each of the plurality of second pull-down drivers PDU2. In one embodiment, the code of the second TX code TC2 received by each of the plurality of second pull-up drivers PUU2 may be the same as or different from the code of the second TX code TC2 received by each of the plurality of second pull-down drivers PDU2.

[0142] In operation S430, the second encoder ENC2 may generate transmission control data TXCD, and output the generated transmission control data TXCD to the TX driver 120. The second encoder ENC2 may encode the first data DT1 and the second code CODE2, and generate transmission control data TXCD (e.g., TX pull-up data TX_PUD and TX pull-down data TX_PDD). The second encoder ENC2 may provide the TX pull-up data TX_PUD and the TX pull-down data TX_PDD to the TX driver 120. For example, the second encoder ENC2 at the receiving end (e.g., the second encoder ENC2 of the second integrated circuit device 12) may generate the transmission control data TXCD, and output the transmission control data TXCD to the TX driver 120. For example, the transmission control data TXCD may include the first TX pull-up data TX_PUD1', the second TX pull-up data TX_PUD2', the first TX pull-down data TX_PDD1', and the second TX pull-down data TX_PDD2'. The first TX pull-up data TX_PUD1' and the second TX pull-up data TX_PUD2' may include a control value for controlling each of the plurality of second pull-up drivers PUU2 of the TX driver 120 when performing the ODT operation. The first TX pull-down data TX_PDD1' and the second TX pull-down data TX_PDD2' may include a control value for controlling each of the plurality of second pull-down drivers PDU2 of the TX driver 120 when performing the ODT operation. In other words, the TX control circuit 140 at the receiving end may output the transmission control data TXCD corresponding to the ODT operation to the TX driver 120.

[0143] In operation S440, the TX driver 120 may perform an ODT operation. The TX driver 120 may receive transmit control data TXCD. For example, the TX driver 120 may receive first TX pull-up data TX_PUD1', second TX pull-up data TX_PUD2', first TX pull-down data TX_PDD1', and second TX pull-down data TX_PDD2'. The TX driver 120 may perform an ODT operation based on the transmit control data TXCD. The terminal resistance value of the TX driver 120 may be determined based on the transmit control data TXCD. The terminal resistance value of the TX driver 120 may be adjusted to be equal to the impedance of the signal line SL. The TX driver 120 may absorb the energy of the signal transmitted via the signal line SL and prevent reflection of the signal at the receiving end.

[0144] Operation S310 to operation S340 can be performed simultaneously with operation S410 to operation S440, and can be performed in an interchangeable order. When one or more embodiments can be implemented differently, the order of specific operations can be performed differently from the above order. For example, two operations described in succession can be performed substantially simultaneously or in an order opposite to the described order.

[0145] Fig.11 is a block diagram of the equalizer 110 and the TX driver 120 according to an embodiment.

[0146] Reference Figure 3 , Figure 4 and Fig.11 , the EQ control circuit 130 may receive the second data DT2 from the delay circuit 160. The EQ control circuit 130 may receive the first EQ code EC1 and the second EQ code EC2 from the calibration circuit 170. The EQ control circuit 130 may receive a selection signal SEL indicating whether the signal SIG is being received or transmitted.

[0147] For example, the EQ control circuit 130 may select and output the first EQ code EC1 as the first code CODE1 in response to the selection signal SEL indicating the transmission operation. The EQ control circuit 130 may select and output the second EQ code EC2 as the first code CODE1 in response to the selection signal SEL indicating the reception operation. The EQ control circuit 130 may provide the EQ control data EQCD to the equalizer 110.

[0148] In an embodiment, the EQ control circuit 130 may provide the EQ control data EQCD to the equalizer 110. For example, the EQ control circuit 130 may provide the first EQ pull-up data EQ_PUD1′, the second EQ pull-up data EQ_PUD2′, the first EQ pull-down data EQ_PDD1′, and the second EQ pull-down data EQ_PDD2′ to the equalizer 110. In a receiving operation, the first EQ pull-up data EQ_PUD1′ and the first EQ pull-down data EQ_PDD1′ may be generated based on the first code CODE1, and the second EQ pull-up data EQ_PUD2′ and the second EQ pull-down data EQ_PDD2′ may be generated based on the second code CODE2. In a transmitting operation, the first TX pull-up data TX_PUD1′ and the first TX pull-down data TX_PDD1′ may be generated based on the first code CODE1, and the second TX pull-up data TX_PUD2′ and the second TX pull-down data TX_PDD2′ may be generated based on the second code CODE2.

[0149] The TX control circuit 140 may receive the first data DT1 from the serializer 150. The TX control circuit 140 may receive the first TX code TC1 and the second TX code TC2 from the calibration circuit 170. The TX control circuit 140 may receive a selection signal SEL indicating whether the signal SIG is being received or transmitted.

[0150] The TX control circuit 140 may select and output the first TX code TC1 among the first TX code TC1 and the second TX code TC2 as the second code CODE2 in response to the selection signal SEL indicating the transmission operation. Alternatively, the TX control circuit 140 may select and output the second TX code TC2 among the first TX code TC1 and the second TX code TC2 as the second code CODE2 in response to the selection signal SEL indicating the reception operation. The TX control circuit 140 may provide the transmission control data TXCD to the TX driver 120.

[0151] In an embodiment, the TX control circuit 140 may output the TX control data TXCD to the TX driver 120. For example, the TX control circuit 140 may provide the first TX pull-up data TX_PUD1', the second TX pull-up data TX_PUD2', the first TX pull-down data TX_PDD1', and the second TX pull-down data TX_PDD2' to the TX driver 120. The first TX pull-up data TX_PUD1' and the second TX pull-up data TX_PUD2' may be generated based on the second code CODE2, and the first TX pull-down data TX_PDD1' and the second TX pull-down data TX_PDD2' may be generated based on the first data DT1. In a receiving operation, the first TX pull-up data TX_PUD1' may be generated based on the second code CODE2, and the second TX pull-up data TX_PUD2', the first TX pull-down data TX_PDD1' and the second TX pull-down data TX_PDD2' may be fixed to low. In the transmission operation, the first TX pull-up data TX_PUD1 ′ and the first TX pull-down data TX_PDD1 ′ may be generated based on the second code CODE2 , and the second TX pull-up data TX_PUD2 ′ and the second TX pull-down data TX_PDD2 ′ may be generated based on the first data DT1 .

[0152] The equalizer 110 may include a plurality of first pull-up drivers PUU1 and a plurality of first pull-down drivers PDU1. Each of the plurality of first pull-up drivers PUU1 may include a first transistor TR1, a second transistor TR2, and a first resistor R1. The first transistor TR1 may be connected between a power supply voltage and the second transistor TR2. For example, the first transistor TR1 may be connected between the power supply voltage and the first node n1. The first transistor TR1 may operate in response to the first EQ pull-up data EQ_PUD1'. The second transistor TR2 may be connected between the first transistor TR1 and the first resistor R1. For example, the second transistor TR2 may be connected between the first node n1 and the second node n2. The second transistor TR2 may operate in response to the second EQ pull-up data EQ_PUD2'. The first resistor R1 may be connected between the second transistor TR2 and the signal line SL. For example, the first resistor R1 may be connected between the second node n2 and the signal line SL.

[0153] Each of the plurality of first pull-down drivers PDU1 may include a third transistor TR3, a fourth transistor TR4, and a second resistor R2. The second resistor R2 may be connected between the signal line SL and the third transistor TR3. For example, the second resistor R2 may be connected between the signal line SL and the third node n3. The third transistor TR3 may be connected between the second resistor R2 and the fourth transistor TR4. For example, the third transistor TR3 may be connected between the third node n3 and the fourth node n4. The third transistor TR3 may operate in response to the second EQ pull-down data EQ_PDD2'. The fourth transistor TR4 may be connected between the third transistor TR3 and the ground voltage GND. For example, the fourth transistor TR4 may be connected between the fourth node n4 and the ground voltage GND. The fourth transistor TR4 may operate in response to the first EQ pull-down data EQ_PDD1'.

[0154] The TX driver 120 may include a plurality of second pull-up drivers PUU2 and a plurality of second pull-down drivers PDU2. Each of the plurality of second pull-up drivers PUU2 may include a fifth transistor TR5, a sixth transistor TR6, and a third resistor R3. The fifth transistor TR5 may be connected between the power supply voltage and the sixth transistor TR6. For example, the fifth transistor TR5 may be connected between the power supply voltage and the fifth node n5. The fifth transistor TR5 may operate in response to the first TX pull-up data TX_PUD1'. The sixth transistor TR6 may be connected between the fifth transistor TR5 and the third resistor R3. For example, the sixth transistor TR6 may be connected between the fifth node n5 and the sixth node n6. The sixth transistor TR6 may operate in response to the second TX pull-up data TX_PUD2'. The third resistor R3 may be connected between the sixth transistor TR6 and the signal line SL. For example, the third resistor R3 may be connected between the sixth node n6 and the signal line SL.

[0155] Each of the plurality of second pull-down drivers PDU2 may include a seventh transistor TR7, an eighth transistor TR8, and a fourth resistor R4. The fourth resistor R4 may be connected between the signal line SL and the seventh transistor TR7. For example, the fourth resistor R4 may be connected between the signal line SL and the seventh node n7. The seventh transistor TR7 may be connected between the fourth resistor R4 and the eighth transistor TR8. For example, the seventh transistor TR7 may be connected between the seventh node n7 and the eighth node n8. The seventh transistor TR7 may operate in response to the second TX pull-down data TX_PDD2'. The eighth transistor TR8 may be connected between the seventh transistor TR7 and the ground voltage GND. For example, the eighth transistor TR8 may be connected between the eighth node n8 and the ground voltage GND. The eighth transistor TR8 may operate in response to the first TX pull-down data TX_PDD1'.

[0156] In an embodiment, when a signal SIG is received, the first transistor TR1 and the second transistor TR2 may be turned on and the first resistor R1 may be electrically connected between the power supply voltage and the signal line SL, and the third transistor TR3 and the fourth transistor TR4 may be turned off and the second resistor R2 may not be electrically connected between the ground voltage GND and the signal line SL. When the first resistor R1 is electrically connected between the power supply voltage and the signal line SL, reflection of the signal SIG sent via the signal line SL may be suppressed. Impedance matching of the signal line SL may be achieved by turning on or off the first transistor TR1, turning on the second transistor TR2, and turning off the third transistor TR3 and the fourth transistor TR4. For example, when the signal SIG is received, the second EQ pull-up data EQ_PUD2' and the second EQ pull-down data EQ_PDD2' may be fixed to a low level (e.g., GND).

[0157] In an embodiment, when the signal SIG is received, the fifth transistor TR5 and the sixth transistor TR6 may be turned on and the third resistor R3 may be electrically connected between the power supply voltage and the signal line SL, and the seventh transistor TR7 and the eighth transistor TR8 may be turned off and the fourth resistor R4 may not be electrically connected between the ground voltage GND and the signal line SL. When the third resistor R3 is electrically connected between the power supply voltage and the signal line SL, the reflection of the signal SIG sent via the signal line SL may be suppressed. The impedance matching of the signal line SL may be achieved by turning on or off the fifth transistor TR5, turning on the sixth transistor TR6, and turning off the seventh transistor TR7 and the eighth transistor TR8. For example, when the signal SIG is received, the second TX pull-up data TX_PUD2' and the second TX pull-down data TX_PDD2' may be fixed to a low level (e.g., GND).

[0158] Fig. 12A and Fig. 12B is a table for describing a first code CODE1 and a second code CODE2 according to example embodiments.

[0159] Reference Figure 3 and Fig. 12A In an embodiment, the equalizer 110 may perform an OCD operation in a transmission operation TX instead of an EMP operation. The equalizer 110 may operate as an OCD circuit in a transmission operation instead of operating as a pre-emphasis circuit. When the channel loss is small, the equalizer 110 at the transmission end may output a signal SIG by driving the signal line SL with the TX driver 120.

[0160] The calibration circuit 170 may transmit the third EQ code EC3 corresponding to the OCD operation of the equalizer 110 and the second EQ code EC2 corresponding to the ODT operation of the equalizer 110 to the EQ control circuit 130 .

[0161] The EQ control circuit 130 may receive the third EQ code EC3 and the second EQ code EC2 from the calibration circuit 170. The EQ control circuit 130 may select and output the third EQ code EC3 among the third EQ code EC3 and the second EQ code EC2 as the first code CODE1 in response to the selection signal SEL indicating the transmission operation. Alternatively, the EQ control circuit 130 may select and output the second EQ code EC2 among the third EQ code EC3 and the second EQ code EC2 as the first code CODE1 in response to the selection signal SEL indicating the reception operation RX. Detailed description of the second code CODE2 and reference Figure 5 The description given is the same and is therefore omitted.

[0162] Reference Figure 1 , Figure 3 and Fig. 12B In an embodiment, the integrated circuit devices 11 and 12 may generate a selection signal SEL indicating a first transmission operation TX1. The selection signal SEL indicating the first transmission operation TX1 may have a first value (e.g., “0”). The integrated circuit devices 11 and 12 may generate a selection signal SEL indicating a second transmission operation TX2. The selection signal SEL indicating the second transmission operation TX2 may have a second value (e.g., “1”). The integrated circuit devices 11 and 12 may generate a selection signal SEL indicating a reception operation RX. The selection signal SEL indicating the reception operation RX may have a third value (e.g., “2”).

[0163] For example, the first transmission operation TX1 may be referred to as an operation in which the equalizer 110 performs an EMP operation and outputs a signal due to channel loss. Because the channel loss in the second transmission operation TX2 is small, the equalizer 110 may perform an OCD operation instead of an EMP operation and indicate an operation of outputting a signal. The reception operation RX may be referred to as an operation of receiving a signal.

[0164] In an embodiment, the equalizer 110 may perform an OCD operation in a transmission operation instead of an EMP operation. The equalizer 110 may operate as a pre-emphasis circuit in a transmission operation instead of an OCD circuit. When the channel loss is large, the equalizer 110 at the transmission end may amplify the high frequency component of the signal SIG. When the channel loss is small, the equalizer 110 at the transmission end may output the signal SIG by driving the signal line SL with the TX driver 120.

[0165] The calibration circuit 170 may transmit a first EQ code EC1 corresponding to the EMP operation of the equalizer 110 , a second EQ code EC2 corresponding to the ODT operation of the equalizer 110 , and a third EQ code EC3 corresponding to the OCD operation to the EQ control circuit 130 .

[0166] The EQ control circuit 130 may receive the first to third EQ codes EC1 to EC3 from the calibration circuit 170. The EQ control circuit 130 may select and output the first EQ code EC1 among the first to third EQ codes EC1 to EC3 as the first code CODE1 in response to the selection signal SEL indicating the first transmission operation TX1. The EQ control circuit 130 may select and output the third EQ code EC3 among the first to third EQ codes EC1 to EC3 as the first code CODE1 in response to the selection signal SEL indicating the second transmission operation TX2. The EQ control circuit 130 may select and output the second EQ code EC2 among the first to third EQ codes EC1 to EC3 as the first code CODE1 in response to the selection signal SEL indicating the reception operation RX.

[0167] The TX control circuit 140 may receive the first TX code TC1 and the second TX code TC2 from the calibration circuit 170. The TX control circuit 140 may select and output the first TX code TC1 among the first TX code TC1 and the second TX code TC2 as the second code CODE2 in response to the selection signal SEL indicating the first transmission operation TX1 or the second transmission operation TX2. The TX control circuit 140 may select and output the second TX code TC2 among the first TX code TC1 and the second TX code TC2 as the second code CODE2 in response to the selection signal SEL indicating the reception operation RX.

[0168] As described above, the EQ control circuit 130 may output EQ control data EQCD indicating an EMP operation or EQ control data EQCD indicating an OCD operation in a transmitting operation, and may output EQ control data EQCD indicating an ODT operation in a receiving operation. The equalizer 110 may amplify the high frequency component of the signal SIG in response to the EQ control data EQCD indicating the EMP operation, or may drive the signal line SL to achieve impedance matching in response to the EQ control data EQCD indicating the OCD operation.

[0169] Fig.13 is a block diagram showing a memory system 20 according to an embodiment.

[0170] Reference Fig.13 , the memory system 20 may include a host 21 and a memory device 300. The host 21 and the memory device 300 may be integrated circuit devices 11 and 12, respectively.

[0171] In order to store data in the memory device 300 or read data stored in the memory device 300, the host 21 may send a system clock CK, a data clock WCK, a command CMD, and an address ADDR to the memory device 300. The host 21 may transmit and receive data to and from the memory device 300 via a plurality of data lines DQ (DQ1 to DQn), where n is a natural number greater than 1. As an example, the host 21 may include a memory controller or a central processing unit (CPU).

[0172] As an example embodiment, the host 21 may communicate with the memory device 300 based on a high-speed interface such as a double data rate (DDR) interface. However, the embodiment is not limited thereto, and the host 21 may communicate with the memory device 300 based on at least one of various interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), and a non-volatile memory (NVM) Express (NVMe).

[0173] The memory device 300 may store data received through the plurality of data lines DQ1 to DQn under the control of the host 21, or may transmit the stored data to the host 21 through the plurality of data lines DQ1 to DQn. Each of the plurality of data lines DQ1 to DQn may include Figure 1 The signal line SL in.

[0174] As an example embodiment, the memory device 300 may include a dynamic random access memory (RAM) (DRAM). However, the scope of the inventive concept is not limited thereto, and the memory device 300 may include at least one of various memory devices such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0175] The memory device 300 may include an equalizer 361 and a DQ driver 362. The DQ driver 362 may be configured to control each of the plurality of data lines DQ1 to DQn. For example, the DQ driver 362 may sense signals of the plurality of data lines DQ1 to DQn and identify data provided by the host 21. In other words, the DQ driver 362 may operate as a receiver. In an example embodiment, the DQ driver 362 may be at the receiving end previously described above. By controlling the voltage of each of the plurality of data lines DQ1 to DQn, the DQ driver 362 may send data to the host 21. In other words, the DQ driver 362 may operate as a transmitter. In an example embodiment, the DQ driver 362 may be at the transmitting end previously described above.

[0176] In an embodiment, when the memory device 300 performs a read operation in response to a read command, the memory device 300 may perform a transmit operation to output data to the host 21. When the memory device 300 performs a write operation in response to a write command, the memory device 300 may perform a receive operation to receive data from the host 21.

[0177] The equalizer 361 may be Figure 3 The equalizer 110 in FIG. 361 can perform reference Figure 1 , Figure 2A , Figure 2B , Figures 3 to 11 , Fig. 12A and Fig. 12B The EMP operation, OCD operation, and ODT operation described above. The DQ driver 362 may be Figure 3 The TX driver 120 in the DQ driver 362 can perform reference Figure 1 , Figure 2A , Figure 2B , Figures 3 to 11 , Fig. 12A and Fig. 12B The memory device 300 may further include an OCD operation and an ODT operation described above. Figure 3 The serializer 150, delay circuit 160, calibration circuit 170, EQ control circuit 130, TX control circuit 140, etc.

[0178] The equalizer 361 may operate as an ODT circuit of the receiving end. In this way, the ODT range of the memory device 300 may be increased. Therefore, the memory device 300 in which the area of ​​a chip forming the memory device 300 is reduced and the parasitic capacitance is reduced may be provided.

[0179] Fig.14 is a block diagram showing a memory device 300 according to an embodiment.

[0180] Reference Fig.13 and Fig.14 , the memory device 300 may include a calibration circuit 310, a memory cell array 320, a row decoder 330, a column decoder 340, a sense amplifier / write driver (SA / WD) 350, and an input / output (I / O) circuit 360. The calibration circuit 310 may be Figure 3 The calibration circuit 170 in FIG. 310 can perform a reference Figure 1 , Figure 2A , Figure 2B , Figures 3 to 11 , Fig. 12A and Fig. 12B Describes the calibration operation.

[0181] The memory cell array 320 may include a plurality of memory cells. Each of the plurality of memory cells may be connected to a word line WL and a bit line BL, respectively. Each of the plurality of memory cells may be configured to store data according to the control of the word line WL and the bit line BL. Each of the plurality of memory cells may include a storage capacitor and a DRAM cell including a pass transistor.

[0182] The row decoder 330 may be connected to the memory cell array 320 via a plurality of word lines WL. The row decoder 330 may control the voltage of the word line WL in response to an address ADDR and a command CMD. In an embodiment, the address ADDR may include a row address, and the command CMD may include a row address strobe (RAS) signal.

[0183] The column decoder 340 may be connected to the memory cell array 320 via a plurality of bit lines BL. The column decoder 340 may receive an address ADDR and a command CMD, and may select at least one bit line BL among the bit lines BL in response to the received signals. In an embodiment, the address ADDR may include a column address, and the command CMD may include a column address strobe (CAS) signal. SA / WD 350 may sense or control a voltage of the bit line BL selected by the column decoder 340.

[0184] The I / O circuit 360 may be connected to the plurality of data lines DQ1 to DQn, and may communicate with an external device (eg, Fig.13 In an embodiment, the I / O circuit 360 may include an equalizer 361 and a DQ driver 362.

[0185] EQ control data (not shown) may be generated and output to the equalizer 361 so that the equalizer 361 may perform a pre-emphasis operation during a data transmission operation, and EQ control data (not shown) may be generated and output to the equalizer 361 so that the equalizer 361 may perform an ODT operation during a data reception operation.

[0186] The equalizer 361 may amplify high frequency components during a data transmission operation based on the EQ control data EQCD, and provide a terminal resistance during a data reception operation.

[0187] The DQ driver 362 may transmit data to the host 21 through the plurality of data lines DQ1 to DQn during a data transmission operation, and provide a terminal resistance during a data reception operation.

[0188] Fig.15 is a diagram illustrating a system 1000 to which a memory device is applied according to an embodiment.

[0189] Fig.15 The system 1000 may basically include a mobile system (such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a health care device, or an Internet of Things (IoT) device). However, Fig.15 The system 1000 is not necessarily limited to a mobile system and may also include a PC, a laptop computer, a server, a media player, or an automotive device such as a navigation device.

[0190] Reference Fig.15 , system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and in addition, may include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0191] The main processor 1100 may control the overall operation of the system 1000, and more specifically, may control operations of other components constituting the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, an application processor, or the like.

[0192] The main processor 1100 may include one or more CPU cores 1110, and may further include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to an embodiment, the main processor 1100 may further include an accelerator 1130 as a dedicated circuit for high-speed data calculations such as artificial intelligence (AI) data calculations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), etc., and may be implemented as a separate chip physically independent of other components of the main processor 1100.

[0193] Memories 1200a and 1200b may be used as main memory devices of system 1000 and may include volatile memory such as SRAM and / or DRAM, but may also include NVM such as flash memory, PRAM and / or RRAM. Memories 1200a and 1200b may be implemented in the same package as main processor 1100.

[0194] The storage devices 1300a and 1300b may store data as nonvolatile storage devices regardless of power supply, and may have a relatively larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers (STRG CTRL) 1310a and 1310b, and nonvolatile memories (NVM) 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. The NVM 1320a and 1320b may include a V-NAND flash memory having a 2-dimensional (2D) or 3-dimensional (3D) vertical NAND structure, but may also include different types of NVMs (such as PRAM and / or RRAM).

[0195] The storage devices 1300a and 1300b may also be included in the system 1000 in a state physically separated from the main processor 1100, and may also be implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have the same shape as a solid state drive (SSD) or a memory card, and therefore, may also be detachably combined with other components of the system 1000 via an interface such as a connection interface 1480 to be described below. The storage devices 1300a and 1300b may include devices to which standard conventions such as universal flash storage (UFS), embedded multimedia card (eMMC), and NVM Express (NVMe) are applied, but are not necessarily limited thereto.

[0196] The image capture device 1410 may capture still images or video images and may include a still camera, a video camera, and / or a webcam, among others.

[0197] The user input device 1420 may receive various types of data input by a user of the system 1000 and may include a touch pad, a keyboard, a keypad, a mouse, and / or a microphone, among others.

[0198] The sensor 1430 may sense various types of physical quantities available from the outside of the system 1000 and may convert the sensed physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope, etc.

[0199] The communication device 1440 may perform transmission and reception of signals between other devices outside the system 1000 according to various communication conventions. The communication device 1440 may be implemented by including an antenna, a transceiver, and / or a modem, etc.

[0200] Display 1450 and speaker 1460 may be used as output devices for outputting visual information and audio information, respectively, to a user of system 1000 .

[0201] The power supply device 1470 may appropriately convert power supplied by a battery (not shown) embedded in the system 1000 and / or an external power source, and provide the converted power to each component of the system 1000 .

[0202] The connection interface 1480 may provide a connection between the system 1000 and an external device that is connected to the system 1000 and exchanges data with the system 1000. The connection interface 1480 may be implemented by using various interface methods such as ATA, SATA, external SATA (e-SATA), SCSI, serial attached SCSI (SAS), PCI, PCIe, NVMe, IEEE 1394, universal serial bus (USB), secure digital (SD) card, multimedia card (MMC), embedded MMC (eMMC), UFS, embedded UFS (eUFS), and compact flash (CF) card interface.

[0203] In an embodiment, various memory devices (eg, 1200a, 1200b, etc.) included in system 1000 may include reference Figure 1 , Figure 2A , Figure 2B , Figures 3 to 11 , Fig. 12A and Fig. 12B The integrated circuit devices 11 and 12 described above. The memory devices 1300a and 1300b included in the system 1000 may include reference Figure 1 , Figure 2A , Figure 2B , Figures 3 to 11 , Fig. 12A and Fig. 12B The integrated circuit devices 11 and 12 described. The equalizer included in the memory devices (e.g., 1200a and 1200b) and the storage devices 1300a and 1300b can operate as an ODT circuit during the receiving operation and provide a terminal resistance. Therefore, an integrated circuit device in which the area of ​​a chip forming one of the memories 1200a and 1200b is reduced and the parasitic capacitance is reduced can be provided. In addition, the signal reflection to the signal line SL can be reduced, and the reliability of the signal SIG can be improved.

[0204] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: a transmission driver configured to transmit the output signal to the outside through the signal line in a transmission operation in response to transmission control data, and to provide a terminal resistance in a reception operation of receiving an input signal from the outside through the signal line; as well as An equalizer is configured to amplify a high frequency component of the output signal in the transmission operation and provide the terminal resistance in the reception operation in response to equalizer control data.

2. The integrated circuit device according to claim 1, further comprising: an equalizer control circuit configured to receive second data and output to the equalizer the equalizer control data generated based on: The second data, a first equalizer code corresponding to a pre-emphasis operation in the transmitting operation, and A second equalizer code corresponds to an on-die termination operation in the receiving operation.

3. The integrated circuit device according to claim 2, further comprising: a transmission control circuit configured to receive first data and output the transmission control data generated based on the first data to the transmission driver, Wherein, the first data includes: a first transmission code corresponding to an off-chip driver operation in the transmission operation, and A second transmission code corresponds to the on-die termination operation in the receiving operation.

4. The integrated circuit device according to claim 3, further comprising: The calibration circuit is configured as follows: Perform a calibration operation, determining the first equalizer code, the second equalizer code, the first transmission code, and the second transmission code, providing the first equalizer code and the second equalizer code to the equalizer control circuit, and The first transmission code and the second transmission code are provided to the transmission control circuit.

5. The integrated circuit device according to claim 1, further comprising: an equalizer control circuit configured to receive second data and provide said equalizer control data to said equalizer, Wherein, the equalizer control circuit comprises: a multiplexer configured to receive a selection signal, a first equalizer code, and a second equalizer code, output the first equalizer code as a first code in response to the selection signal indicating the transmission operation, and output the second equalizer code as the first code in response to the selection signal indicating the reception operation; and An encoder is configured to output the equalizer control data by encoding the second data and the first code.

6. The integrated circuit device according to claim 1, further comprising: a transmission control circuit configured to receive first data and provide the transmission control data to the transmission driver, Wherein, the sending control circuit includes: a multiplexer configured to receive a selection signal and a first transmission code and a second transmission code, output the first transmission code as the second code in response to the selection signal indicating the transmission operation, and output the second transmission code as the second code in response to the selection signal indicating the reception operation; and An encoder is configured to output the transmission control data by encoding the first data and the second code.

7. The integrated circuit device according to claim 2, further comprising: a serializer configured to receive output data and output first data by serializing the output data; as well as a delay circuit configured to receive the first data and output the second data by delaying the first data, The equalizer control data includes equalizer pull-up data and equalizer pull-down data. Wherein, the equalizer comprises a first pull-up driver and a first pull-down driver, Wherein, the first pull-up driver comprises: a first resistor connected between the signal line and a first node; and a first transistor connected between the first node and a power supply voltage and configured to operate in response to the equalizer pull-up data, and Wherein, the first pull-down driver comprises: a second resistor connected between the signal line and a second node; and A second transistor is connected between the second node and a ground voltage and is configured to operate in response to the equalizer pull-down data.

8. The integrated circuit device according to claim 3, further comprising: a serializer configured to receive output data and output the first data by serializing the output data, Wherein, the sending control data includes sending pull-up data and sending pull-down data, Wherein, the transmission driver includes a second pull-up driver and a second pull-down driver, Wherein, the second pull-up driver comprises: a third resistor connected between the signal line and a third node; and a third transistor connected between the third node and a power supply voltage and configured to operate in response to the transmission pull-up data, and The second pull-down driver comprises: a fourth resistor connected between the signal line and a fourth node; and A fourth transistor is connected between the fourth node and a ground voltage and is configured to operate in response to the transmission pull-down data.

9. The integrated circuit device according to claim 1, further comprising: a serializer configured to receive output data and output first data by serializing the output data; a delay circuit configured to receive the first data and output second data by delaying the first data; as well as an equalizer control circuit configured to receive the second data and a first equalizer code and a second equalizer code, and provide the equalizer control data to the equalizer, Wherein, the equalizer control circuit comprises: a multiplexer configured to receive a selection signal, the first equalizer code, and the second equalizer code, and output, in response to the selection signal, the first equalizer code corresponding to a pre-emphasis operation or the second equalizer code corresponding to an on-die termination operation as a first code; and An encoder is configured to output the equalizer control data by encoding the second data and the first code.

10. The integrated circuit device according to claim 9, in, The equalizer control data includes first equalizer pull-up data and second equalizer pull-up data and first equalizer pull-down data and second equalizer pull-down data, Wherein, the equalizer comprises a first pull-up driver and a first pull-down driver, Wherein, the first pull-up driver comprises: a first transistor connected between a power supply voltage and a first node and configured to operate in response to the first equalizer pull-up data; a second transistor connected between the first node and a second node and configured to operate in response to the second equalizer pull-up data; and a first resistor connected between the second node and the signal line, and Wherein, the first pull-down driver comprises: a second resistor connected between the signal line and a third node; a third transistor connected between the third node and a fourth node and configured to operate in response to the second equalizer pull-down data; and A fourth transistor is connected between the fourth node and a ground voltage and is configured to operate in response to the first equalizer pull-down data.

11. The integrated circuit device according to claim 1 , further comprising: a serializer configured to receive output data and output first data by serializing the output data; as well as a transmission control circuit configured to receive the first data and a first transmission code and a second transmission code, and provide transmission control data to the transmission driver, Wherein, the sending control circuit includes: a multiplexer configured to receive a selection signal, the first transmission code, and the second transmission code, and output, in response to the selection signal, the first transmission code corresponding to an off-chip driver operation or the second transmission code corresponding to an on-die termination operation as a second code; and An encoder is configured to output the transmission control data by encoding the first data and the second code.

12. The integrated circuit device according to claim 11, in, The transmission control data includes first transmission pull-up data and second transmission pull-up data and first transmission pull-down data and second transmission pull-down data, Wherein, the transmission driver includes a second pull-up driver and a second pull-down driver, Wherein, the second pull-up driver comprises: a fifth transistor connected between a power supply voltage and a fifth node and configured to operate in response to the first transmit pull-up data; a sixth transistor connected between the fifth node and a sixth node and configured to operate in response to the second transmission pull-up data; and a third resistor connected between the sixth node and the signal line, and Wherein, the second pull-down driver comprises: a fourth resistor connected between the signal line and a seventh node; a seventh transistor connected between the seventh node and an eighth node and configured to operate in response to the second transmission pull-down data; and An eighth transistor is connected between the eighth node and a ground voltage and is configured to operate in response to the first transmission pull-down data.

13. The integrated circuit device according to claim 1, wherein: The equalizer is configured to be activated during the receiving operation.

14. The integrated circuit device according to claim 1, wherein: The transmission driver and the equalizer are connected in parallel to each other.

15. The integrated circuit device according to claim 1, further comprising: An equalizer control circuit is configured to output equalizer control data, the equalizer control data indicating: The pre-emphasis operation or off-chip driver operation in the transmission operation, and The receiving operation is terminated on-die, Wherein, the equalizer is configured as: amplifying a high frequency component of the output signal in response to the equalizer control data instructing the pre-emphasis operation, and The signal line is driven to achieve impedance matching in response to the equalizer control data instructing the off-chip driver to operate.

16. A memory device comprising: a memory cell array comprising a plurality of memory cells configured to store data; a data line driver configured to transmit the data to an external device via the data line in a data transmission operation and to provide a terminal resistance in a data reception operation; an equalizer configured to perform a pre-emphasis operation in the data transmission operation and to perform an on-die termination operation in the data reception operation in response to equalizer control data; as well as An equalizer control circuit is configured to provide the equalizer control data to the equalizer.

17. The memory device of claim 16, further comprising: a serializer configured to receive output data and output first data by serializing the output data; as well as a delay circuit configured to receive the first data and output second data by delaying the first data, Wherein, the equalizer control circuit comprises: a multiplexer configured to receive a selection signal, a first equalizer code, and a second equalizer code, and in response to the selection signal, output the first equalizer code corresponding to a pre-emphasis operation or the second equalizer code corresponding to an on-die termination operation as a first code; and an encoder configured to output the equalizer control data by encoding the second data and the first code, Wherein, the equalizer control data includes equalizer pull-up data and equalizer pull-down data: wherein the equalizer comprises at least one first pull-up driver and at least one first pull-down driver, Wherein, the at least one first pull-up driver comprises: a first resistor connected between the data line and a first node; and a first transistor connected between the first node and a power supply voltage and configured to operate in response to the equalizer pull-up data, and Wherein, the at least one first pull-down driver comprises: a second resistor connected between the data line and a second node; and A second transistor is connected between the second node and a ground voltage and is configured to operate in response to the equalizer pull-down data.

18. The memory device of claim 16, further comprising: a serializer configured to receive output data and output first data by serializing the output data; as well as a delay circuit configured to receive the first data and output second data by delaying the first data, Wherein, the equalizer control circuit comprises: a multiplexer configured to receive a selection signal, a first equalizer code, and a second equalizer code, and in response to the selection signal, output the first equalizer code corresponding to a pre-emphasis operation or the second equalizer code corresponding to an on-die termination operation as a first code; and An encoder is configured to output the equalizer control data by encoding the second data and the first code.

19. The memory device according to claim 18, in, The equalizer includes at least one first pull-up driver and at least one first pull-down driver, Wherein, the at least one first pull-up driver comprises: a first transistor connected between a power supply voltage and a first node and configured to operate in response to the first equalizer pull-up data; a second transistor connected between the first node and a second node and configured to operate in response to a second equalizer pull-up data; and a first resistor connected between the second node and the data line, and Wherein, the at least one first pull-down driver comprises: a second resistor connected between the data line and a third node; a third transistor connected between the third node and a fourth node and configured to operate in response to the second equalizer pull-down data; and A fourth transistor is connected between the fourth node and a ground voltage and is configured to operate in response to the first equalizer pull-down data.

20. An operating method of an integrated circuit device, the integrated circuit device comprising an equalizer control circuit, a transmission driver and an equalizer, the operating method comprising: receiving, by the equalizer control circuit, data and a selection signal instructing a receiving operation of the integrated circuit device; selecting, by the equalizer control circuit in response to the selection signal indicating the receiving operation, the second equalizer code from among a first equalizer code corresponding to a pre-emphasis operation and a second equalizer code corresponding to an on-die termination operation as a first code; generating, by the equalizer control circuit, equalizer control data by encoding based on the first code and the received data; outputting the generated equalizer control data to the equalizer; as well as The terminal resistance is provided by the equalizer based on the equalizer control data.

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