A high-speed interface signal detection circuit

Abstract

The present invention discloses a high-speed interface signal detection circuit. The input signal of the differential comparator amplifier is amplified, and the output signal is converted into signal D2S through a dual-to-single amplifier; signal D2S is inverted to form signal RSTB and given to a low-pass filter, and the low-pass filter realizes the filtering function; if the differential comparator amplifier detects data "1", the state of signal RSTB is "0", charging the capacitor array, and the voltage signal VLPF output by the low-pass filter is set to "1"; if the input of the differential comparator amplifier is always data "1", the voltage signal VLPF remains at a high level "1", when the input switches to data "0", the state of signal RSTB is "1", and the voltage signal VLPF discharges through the current array; select appropriate current and capacitor sizes to ensure that during the period when the state of RSTB is "1", the VLPF voltage remains above the threshold voltage of the Schmitt trigger, so that the output of the Schmitt trigger is always at a high level, realizing the detection of the received-end RX signal. The present invention can be used in both high-speed and low-speed modes and is adapted to a variety of interface circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a high-speed interface signal detection circuit. Background Art

[0002] In the application of high-speed serial interface circuits, when the transmitting end TX no longer transmits data, in order to save power, the receiving end RX usually enters a power-saving mode; when the transmitting end TX transmits data again, the receiving end RX must be woken up again. Therefore, the receiving end RX usually configures a signal detection module, whose function is to detect whether the transmitting end TX of the upstream port is transmitting data, so as to wake up the receiving end RX of the downstream port.

[0003] There are many implementation modes for the signal detection module of the receiving end RX. Therefore, there is an urgent need for a wide-band signal detector that can be compatible with multiple working modes and adapt to multiple interface protocols. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-speed interface signal detection circuit to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides a high-speed interface signal detection circuit that detects the data signal of the receiving end RX and outputs a high level, supporting both high and low frequency modes.

[0006] The high-speed interface signal detection circuit includes: a differential comparator amplifier, a dual-to-single amplifier, a low-pass filter, and a Schmitt trigger;

[0007] The input signals INP and INN of the differential comparator amplifier come from the receiving end RX. After being amplified by the differential comparator amplifier, the output signals O1P and O1N are obtained.

[0008] The signals O1P and O1N are converted into a single-ended full-swing signal D2S through a dual-to-single amplifier.

[0009] The single-ended full-swing signal D2S is inverted to form a signal RSTB and input to the low-pass filter. The low-pass filter realizes the filtering function by charging and discharging a capacitor array; if the differential comparator amplifier detects data "1", the state of the signal RSTB is "0", the capacitor array is charged, and the output voltage signal VLPF of the low-pass filter is set to "1"; if the input of the differential comparator amplifier is always data "1", the voltage signal VLPF remains at a high level "1". When the input switches to data "0", the state of the signal RSTB is "1", and the voltage signal VLPF discharges through the current array.

[0010] When appropriate current and capacitance values are selected, it can be ensured that during the period when the RSTB state is "1", the VLPF voltage remains above the threshold voltage of the Schmitt trigger, causing the output of the Schmitt trigger to always be at a high level, thus achieving the detection of the received RX signal.

[0011] In one embodiment, the differential comparator amplifier includes PMOS transistors MP1 to MP2, resistors R1 to R4, NMOS transistors MN1 to MN4, two Hall switches HS, a limit switch LS, and two current sources; the dual-to-single amplifier includes PMOS transistors MP3 to MP4, NMOS transistors MN5 to MN6; the low-pass filter includes PMOS transistor MP5, a current array, and a capacitance array;

[0012] The source terminals of PMOS transistor MP1 and PMOS transistor MP2 are both connected to the power supply voltage AVDD. The gate terminal of PMOS transistor MP1 is connected to the first end of resistor R1 through a Hall switch HS, and the gate terminal of PMOS transistor MP2 is connected to the second end of resistor R4 through another Hall switch HS; the drain terminal of PMOS transistor MP1 is simultaneously connected to the second end of resistor R1 and the first end of resistor R2, and the drain terminal of PMOS transistor MP2 is simultaneously connected to the second end of resistor R3 and the first end of resistor R4; a limit switch LS is connected between the second end of resistor R2 and the first end of resistor R3;

[0013] The gate terminal of NMOS transistor MN1 is connected to signal INP, and the drain terminal is simultaneously connected to the drain terminal of PMOS transistor MP1 and the drain terminal of NMOS transistor MN3; the gate terminal of NMOS transistor MN2 is connected to the comparison threshold voltage VREFP, and the drain terminal is simultaneously connected to the drain terminal of PMOS transistor MP2 and the drain terminal of NMOS transistor MN4; the source terminals of NMOS transistor MN1 and NMOS transistor MN2 are both grounded through a current source;

[0014] The gate terminal of NMOS transistor MN3 is connected to the comparison threshold voltage VREFN, and the drain terminal is connected to the gate terminal of PMOS transistor MP4; the gate terminal of NMOS transistor MN4 is connected to signal INN, and the drain terminal is connected to the gate terminal of PMOS transistor MP3; the source terminals of NMOS transistor MN3 and NMOS transistor MN4 are both grounded through another current source;

[0015] The source terminals of PMOS transistor MP3 and PMOS transistor MP4 are both connected to the power supply voltage AVDD. The drain terminal of PMOS transistor MP3 is connected to the drain terminal of NMOS transistor MN5, and the drain terminal of PMOS transistor MP4 is connected to the drain terminal of NMOS transistor MN6; the gate terminal of NMOS transistor MN5 is connected to its own drain terminal, and the source terminal is grounded to Vss. The gate terminal of NMOS transistor MN6 is connected to the gate terminal of NMOS transistor MN5, and the source terminal is grounded to Vss;

[0016] A D2S signal is generated at the connection between the drain terminal of PMOS transistor MP4 and the drain terminal of NMOS transistor MN6. The gate terminal of PMOS transistor MP5 is connected through an inverter INV. The source terminal of PMOS transistor MP5 is connected to the power supply voltage AVDD, and the drain terminal is connected to both the current array and the capacitor array at the same time. The input terminal of the Schmitt trigger is connected to the drain terminal of PMOS transistor MP5, and the OUT signal is output at the output terminal.

[0017] In an implementation manner, the input data of the receiving end RX is divided into two cases of "1" and "0". When the input data is "1", when INP - INN is greater than the comparison threshold voltage VREFP - VREFN of the differential comparison amplifier, the input is amplified and the signal D2S is at the "1" level; when the input is less than the comparison threshold voltage, the signal D2S is at the "0" level; when the input data is "0", the signal D2S is always at the "0" level; thus, the detection of data "1" is achieved.

[0018] A high-speed interface signal detection circuit provided by the present invention can quickly detect the signal sent by the upstream transmitting end TX and report the detection result to the digital logic, thereby controlling the opening of the analog part of the interface circuit and realizing the low-power working mode of the interface circuit. The detection circuit can effectively suppress noise while detecting high-frequency signals, thereby preventing noise from being mis-triggered. It can be used in both high-speed and low-speed modes and is adapted to a variety of interface circuits. The circuit function is simple, the logic is clear, it is easy to implement and convenient to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic structural diagram of a high-speed interface signal detection circuit provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The following further describes in detail a high-speed interface signal detection circuit proposed by the present invention in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0021] The present invention provides a high-speed interface signal detection circuit, and its structure is as Figure 1 shown, where INP / INN is the signal from the receiving end RX, and VREF / VREN is the comparison threshold voltage. This circuit realizes the detection of the data signal of the receiving end RX and outputs a high level, supporting both high and low frequency modes. The specific function description is as follows:

[0022] The circuit is divided into four functional modules, namely a differential comparator amplifier, a dual-to-single amplifier, a low-pass filter, and a Schmitt trigger. The differential comparator amplifier includes PMOS transistors MP1 to MP2, resistors R1 to R4, NMOS transistors MN1 to MN4, two Hall switches HS, a limit switch LS, and two current sources; the dual-to-single amplifier includes PMOS transistors MP3 to MP4, NMOS transistors MN5 to MN6; the low-pass filter includes PMOS transistor MP5, a current array, and a capacitor array.

[0023] The source terminals of PMOS transistor MP1 and PMOS transistor MP2 are both connected to the power supply voltage AVDD. The gate terminal of PMOS transistor MP1 is connected to the first terminal of resistor R1 through a Hall switch HS, and the gate terminal of PMOS transistor MP2 is connected to the second terminal of resistor R4 through another Hall switch HS. The drain terminal of PMOS transistor MP1 is simultaneously connected to the second terminal of resistor R1 and the first terminal of resistor R2, and the drain terminal of PMOS transistor MP2 is simultaneously connected to the second terminal of resistor R3 and the first terminal of resistor R4. The second terminal of resistor R2 and the first terminal of resistor R3 are connected through the limit switch LS. The gate terminal of NMOS transistor MN1 is connected to the signal INP, and the drain terminal is simultaneously connected to the drain terminal of PMOS transistor MP1 and the drain terminal of NMOS transistor MN3. The gate terminal of NMOS transistor MN2 is connected to the comparison threshold voltage VREFP, and the drain terminal is simultaneously connected to the drain terminal of PMOS transistor MP2 and the drain terminal of NMOS transistor MN4. The source terminals of NMOS transistor MN1 and NMOS transistor MN2 are both grounded through a current source. The gate terminal of NMOS transistor MN3 is connected to the comparison threshold voltage VREFN, and the drain terminal is connected to the gate terminal of PMOS transistor MP4. The gate terminal of NMOS transistor MN4 is connected to the signal INN, and the drain terminal is connected to the gate terminal of PMOS transistor MP3. The source terminals of NMOS transistor MN3 and NMOS transistor MN4 are both grounded through another current source. The source terminals of PMOS transistor MP3 and PMOS transistor MP4 are both connected to the power supply voltage AVDD. The drain terminal of PMOS transistor MP3 is connected to the drain terminal of NMOS transistor MN5, and the drain terminal of PMOS transistor MP4 is connected to the drain terminal of NMOS transistor MN6. The gate terminal of NMOS transistor MN5 is connected to its own drain terminal, and the source terminal is grounded to Vss. The gate terminal of NMOS transistor MN6 is connected to the gate terminal of NMOS transistor MN5, and the source terminal is grounded to Vss. A D2S signal is generated at the connection between the drain terminal of PMOS transistor MP4 and the drain terminal of NMOS transistor MN6, and is connected to the gate terminal of PMOS transistor MP5 through an inverter INV. The source terminal of PMOS transistor MP5 is connected to the power supply voltage AVDD, and the drain terminal is simultaneously connected to the current array and the capacitor array. The input terminal of the Schmitt trigger is connected to the drain terminal of PMOS transistor MP5, and the output terminal outputs the OUT signal.

[0024] When the Hall switch HS is closed and the limit switch LS is open, the resistors R1, PMOS transistor MP1, resistors R4, and PMOS transistor MP2 are equivalent to inductive loads, which can broaden the bandwidth of the comparator and are applied in the high-speed operating mode. When the limit switch LS is closed and the Hall switch HS is open, the comparator has a narrow bandwidth and is applied in the low-speed operating mode.

[0025] The input signals INP / INN of the differential comparator amplifier come from the receiver RX. Since the amplitude of the signal received by the receiver RX is attenuated, it first needs to be amplified by the differential comparator amplifier to output O1P / O1N, and then converted into a single-ended full-swing signal D2S through a double-to-single amplifier. The input data is divided into two cases: "1" and "0". When the input data is "1", that is, the differential input INP - INN > 0. When INP - INN is greater than the comparator threshold voltage VREFP - VREFN of the differential comparator amplifier, the input is amplified and D2S outputs a "1" level. When the input is less than the comparator threshold voltage, D2S outputs a "0" level. When the input data is "0", that is, the differential input INP - INN < 0, D2S always outputs a "0" level, thus realizing the detection of data "1". D2S is inverted to form a signal RSTB and input to the low-pass filter. The low-pass filter realizes the filtering function by charging and discharging the capacitor array. Once the differential comparator amplifier detects data "1", the state of RSTB is "0", and the capacitor array is charged by controlling the opening of the PMOS transistor MP5. The voltage signal VLPF output by the low-pass filter is quickly set to "1". When the input of the differential comparator amplifier is always data "1", the voltage signal VLPF remains at the high level "1". When the input switches to data "0", the state of RSTB is "1", the PMOS transistor MP5 is turned off and remains for a period of time. At this time, the voltage signal VLPF will discharge through the current array. When appropriate current and capacitor sizes are selected, it can be ensured that during the off period of the PMOS transistor MP5, the VLPF voltage remains above the threshold voltage of the Schmitt trigger, so that the output of the Schmitt trigger is always at a high level, thus realizing the detection of the signal of the receiver RX.

[0026] The circuit of the present invention supports two operating modes: low-speed operating mode (LS) and high-speed operating mode (HS). In the low-speed operating mode, the LS switch is closed and the HS switch is open, and the first-stage differential comparator amplifier operates in a high-gain low-bandwidth mode. In the high-speed operating mode, the HS switch is closed and the LS switch is open. The parasitic capacitance at the gate of the load transistor of the first-stage differential comparator amplifier is connected in series with a resistor to form an inductive load, adding a zero point at the output end of the differential comparator amplifier, thereby increasing the bandwidth of the differential comparator amplifier and making the differential comparator amplifier operate in a low-gain high-bandwidth mode.

[0027] The signal detection circuit provided by the present invention has a simple circuit structure. It realizes two working modes of high speed and low speed only by changing the connection mode of the gate resistance of the load transistor of the first-stage differential comparison amplifier, which has great advantages compared with the detection circuit that can only work at low frequencies. The present invention has a good anti-noise function through the setting of the threshold voltage of the differential comparison amplifier, which can prevent noise from being mis-triggered; the low-pass filter adopts a non-traditional method, saving area, and the capacitor and current array provide a variety of low-pass filtering bandwidth options, so that it can adapt to interface circuits of various rates and enhance the applicability of the circuit.

[0028] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the scope of protection of the claims.

Claims

1. A high-speed interface signal detection circuit, characterized in that Detect the data signal at the receiving end RX and output a high level, supporting both high and low frequency modes. The high-speed interface signal detection circuit includes: a differential comparator amplifier, a dual-to-single amplifier, a low-pass filter, and a Schmitt trigger. The input signals INP and INN of the differential comparator amplifier come from the receiving end RX. After being amplified by the differential comparator amplifier, the output signals O1P and O1N are obtained. The signals O1P and O1N are converted into a single-ended full-swing signal D2S through the dual-to-single amplifier. The single-ended full-swing signal D2S is inverted to form a signal RSTB and input to the low-pass filter. The low-pass filter realizes the filtering function by charging and discharging the capacitor array. If the differential comparator amplifier detects data "1", the state of the signal RSTB is "0", charging the capacitor array, and the output voltage signal VLPF of the low-pass filter is set to "1". If the input of the differential comparator amplifier is always data "1", the voltage signal VLPF remains at a high level "1". When the input switches to data "0", the state of the signal RSTB is "1", and the voltage signal VLPF discharges through the current array. When appropriate current and capacitor sizes are selected, it can be ensured that during the period when the state of RSTB is "1", the VLPF voltage remains above the threshold voltage of the Schmitt trigger, so that the output of the Schmitt trigger is always at a high level, realizing the detection of the signal at the receiving end RX. The differential comparator amplifier includes PMOS transistors MP1~MP2, resistors R1~R4, NMOS transistors MN1~MN4, two Hall switches HS, a limit switch LS, and two current sources. The dual-to-single amplifier includes PMOS transistors MP3~MP4 and NMOS transistors MN5~MN6. The low-pass filter includes a PMOS transistor MP5, a current array, and a capacitor array. The source terminals of PMOS transistor MP1 and PMOS transistor MP2 are both connected to the power supply voltage AVDD. The gate terminal of PMOS transistor MP1 is connected to the first end of resistor R1 through a Hall switch HS. The gate terminal of PMOS transistor MP2 is connected to the second end of resistor R4 through another Hall switch HS. The drain terminal of PMOS transistor MP1 is simultaneously connected to the second end of resistor R1 and the first end of resistor R2. The drain terminal of PMOS transistor MP2 is simultaneously connected to the second end of resistor R3 and the first end of resistor R4. The second end of resistor R2 and the first end of resistor R3 are connected through a limit switch LS. The gate terminal of NMOS transistor MN1 is connected to the signal INP, and the drain terminal is simultaneously connected to the drain terminals of PMOS transistor MP1 and NMOS transistor MN3. The gate terminal of NMOS transistor MN2 is connected to the comparison threshold voltage VREFP, and the drain terminal is simultaneously connected to the drain terminals of PMOS transistor MP2 and NMOS transistor MN4. The source terminals of NMOS transistor MN1 and NMOS transistor MN2 are both grounded through a current source. The gate terminal of NMOS transistor MN3 is connected to the comparison threshold voltage VREFN, and the drain terminal is connected to the gate terminal of PMOS transistor MP4; the gate terminal of NMOS transistor MN4 is connected to signal INN, and the drain terminal is connected to the gate terminal of PMOS transistor MP3; the source terminals of NMOS transistor MN3 and NMOS transistor MN4 are both grounded through another current source; The source terminals of PMOS transistor MP3 and PMOS transistor MP4 are both connected to the power supply voltage AVDD. The drain terminal of PMOS transistor MP3 is connected to the drain terminal of NMOS transistor MN5, and the drain terminal of PMOS transistor MP4 is connected to the drain terminal of NMOS transistor MN6; the gate terminal of NMOS transistor MN5 is connected to its own drain terminal, and the source terminal is grounded to Vss. The gate terminal of NMOS transistor MN6 is connected to the gate terminal of NMOS transistor MN5, and the source terminal is grounded to Vss; A D2S signal is generated at the connection between the drain terminal of PMOS transistor MP4 and the drain terminal of NMOS transistor MN6, and is connected to the gate terminal of PMOS transistor MP5 through an inverter INV. The source terminal of PMOS transistor MP5 is connected to the power supply voltage AVDD, and the drain terminal is connected to both the current array and the capacitor array at the same time; the input terminal of the Schmitt trigger is connected to the drain terminal of PMOS transistor MP5, and the output terminal outputs the OUT signal; The input data of the receiving end RX is divided into two cases of "1" and "0". When the input data is "1", when INP - INN is greater than the comparison threshold voltage VREFP - VREFN of the differential comparator, the input is amplified and the signal D2S is at the "1" level; when the input is less than the comparison threshold voltage, the signal D2S is at the "0" level; when the input data is "0", the signal D2S is always at the "0" level; thus realizing the detection of data "1".

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