PCIe clock gating circuit and PCIe clock control method

Abstract

The invention provides a PCIe clock gating circuit and a PCIe clock control method. The PCIe clock gating circuit comprises a link width control circuit, a link rate control circuit and a link state control circuit, the link width control circuit is used for outputting a control signal for closing a clock of a module not related to the current width when the current link width is smaller than the maximum width; the link rate control circuit is used for outputting a control signal for closing a clock of a non-current rate related module, and the link state control circuit is used for outputting a control signal for closing a clock of an abnormal working state related module when the current link state is an abnormal working state. The abnormal working state related modules comprise related modules corresponding to other link states except the current link state; and the link state control circuit is also used for outputting a control signal for closing clocks of the training code stream sending module, the training code stream receiving module and the link training related module in a normal working state.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a PCIe clock gating circuit and a PCIe clock control method. Background Art

[0002] With the iteration and upgrade of the PCIe protocol, the PCIe protocol has been updated to version 6.0. The power consumption of the PCIe system has gradually increased with the increase of functions and complexity. Although the PCIe system has its own low-power management (L1 state), entering the low-power state requires negotiation between both ends. At the same time, data transmission stops when the entire system enters the low-power mode. Therefore, the L1 low-power state of PCIe can only solve the power consumption problem when the link is idle. Summary of the invention

[0003] The purpose of the present application is to provide a PCIe clock gating circuit and a PCIe clock control method, aiming to solve the power consumption problem when the PCIe system link is idle.

[0004] According to a first aspect of the present application, a PCIe clock gating circuit is provided, comprising: a link width control circuit, a link rate control circuit and a link state control circuit; wherein,

[0005] The link width control circuit is used to output a control signal to turn off the clock of a module not related to the current width when the current link width is less than the maximum width; the module not related to the current width includes modules related to other channels other than the channel corresponding to the current link width, and modules related to other link widths other than the current link width;

[0006] The link rate control circuit is used to output a control signal for shutting down the clock of a module not related to the current rate, wherein the module not related to the current rate includes a module corresponding to a link rate other than the current link rate;

[0007] The link state control circuit is used to output a control signal for shutting down the clock of a module related to an abnormal working state when the current link state is an abnormal working state, and the module related to the abnormal working state includes a module corresponding to other link states other than the current link state;

[0008] The link state control circuit is also used to output a control signal for shutting down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules in a normal working state.

[0009] In an optional embodiment, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, an scrambling / de-scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link widths.

[0010] In an optional embodiment, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5, and at least one of a PAM4 encoding and decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module corresponding to Gen1 or Gen2 , at least one of a message receiving processing module and a message sending processing module, and at least one of a PAM4 encoding and decoding module, a message receiving processing module and a message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of an 8b / 10b conversion module, a message receiving processing module and a message sending processing module corresponding to Gen1 or Gen2, and at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module and a Gen5 precoding module corresponding to Gen3, Gen4 or Gen5.

[0011] In an optional implementation, the abnormal working state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching related modules and other modules other than the link width switching related modules; the abnormal working state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

[0012] In an optional implementation, the PCIe clock gating circuit further includes: a logic OR gate;

[0013] The logic OR gate is used to perform a logic OR operation on a plurality of control signals to be output to the same clock.

[0014] In an optional implementation, the PCIe clock gating circuit further includes: a register enable signal output circuit;

[0015] The register enable signal output circuit is used to output an enable signal to the logic OR gate according to the configuration information in the setting register, so as to enable the control signal output to the clock.

[0016] According to a second aspect of the present application, a PCIe clock control method is provided, comprising:

[0017] When the current link width is less than the maximum width, the link width control circuit outputs a control signal for shutting down the clock of a module not related to the current width; the module not related to the current width includes modules related to other channels other than the channel corresponding to the current link width, and modules corresponding to other link widths other than the current link width;

[0018] The link rate control circuit outputs a control signal for shutting down the clock of a module not related to the current rate, wherein the module not related to the current rate includes a module corresponding to a link rate other than the current link rate;

[0019] When the current link state is an abnormal working state, the link state control circuit outputs a control signal for shutting down the clock of a module related to the abnormal working state, wherein the module related to the abnormal working state includes a module corresponding to other link states other than the current link state;

[0020] When the current link state is a normal working state, the link state control circuit outputs a control signal for shutting down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules.

[0021] In an optional embodiment, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, an scrambling / de-scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link widths.

[0022] In an optional embodiment, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5, and at least one of a PAM4 encoding and decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module corresponding to Gen1 or Gen2 , at least one of a message receiving processing module and a message sending processing module, and at least one of a PAM4 encoding and decoding module, a message receiving processing module and a message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of an 8b / 10b conversion module, a message receiving processing module and a message sending processing module corresponding to Gen1 or Gen2, and at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module and a Gen5 precoding module corresponding to Gen3, Gen4 or Gen5.

[0023] In an optional implementation, the abnormal working state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching related modules and other modules other than the link width switching related modules; the abnormal working state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

[0024] In an optional embodiment, the method further comprises:

[0025] The plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

[0026] In an optional implementation manner, the plurality of control signals to be output to the same clock pass through a logic OR gate and are output to the clock by the logic OR gate, including:

[0027] The register enable signal output circuit outputs an enable signal to the logic OR gate;

[0028] The enable signal and the plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

[0029] Compared with the related art, the technical solution of this application has the following advantages:

[0030] The PCIe clock gating circuit proposed in this application can effectively reduce the dynamic power consumption of the entire PCIe system. The actual working modules are distinguished by PCIe link width, link rate, and link working scenario. Turning off the clock of the module that is not working can greatly reduce clock flips and logic flips. Compared with the clock gating of inserting registers in the related technology, the module-level clock module requires fewer hardware resources and is simpler in design.

[0031] In addition, the module-level clock gating circuit controls the clock on and off without software intervention, and all control is automatically completed by hardware; at the same time, the software can control the opening and closing of the clock gating, which increases the flexibility of the entire solution.

[0032] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 is a structural block diagram of a PCIe clock gating circuit according to an exemplary embodiment of the present application.

[0035] Figure 2 is a schematic diagram of a module clock controlled by a link width control circuit according to an exemplary embodiment of the present application.

[0036] Figure 3 It is a schematic diagram of a module clock controlled by a link rate control circuit according to an exemplary embodiment of the present application.

[0037] Figure 4 It is a schematic diagram of a module clock controlled by a link state control circuit according to an exemplary embodiment of the present application.

[0038] Figure 5 It is a schematic diagram of the working principle and effect of the PCIe clock control circuit according to the exemplary embodiment of the present application.

[0039] Figure 6is a flow chart of a PCIe clock control method according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] Since PCIe has many features and functions, and cannot enter a low-power state when the link is loaded, dynamic power consumption accounts for a high proportion of the total power consumption in the PCIe system, and the proportion of clock flip power consumption in dynamic power consumption is also very high. Generally, register gating is added during the design of the PCIe system to reduce the flip of the register D end and the flip of the clock. By adding register gating, dynamic power consumption can be reduced.

[0042] The maximum PCIe link width can support x16. When the system traffic is small, there is no need to use such a large link width. The PCIe system supports negotiation between both ends to reduce the link width. When the unused link enters electrical idle, the clock of the corresponding link can be turned off to reduce the dynamic power consumption of the PCIe system.

[0043] As the iteration of the PCIe protocol leads to an increase in functionality, the size of the PCIe system also increases. The PCIe system needs to be backward compatible with previous versions, resulting in the system needing to support many features and functions. Even if the functions of the old version are not used, its clock flip and logic flip will still cause dynamic power consumption. But in fact, most of the time PCIe will only work stably in one of the link configurations, which causes most of the modules responsible for different link widths and link speeds to be idle, so the dynamic power consumption caused by the clock flip of these modules can be avoided. In addition, a large part of the logic modules in the PCIe system are used for link training, but when the PCIe system is working (the state machine is in the L0 state), the modules responsible for link training do not need to work, and the clock flip and logic flip of these modules will cause dynamic power consumption expenditure.

[0044] In addition, the PCIe system in the related art reduces dynamic power consumption by adding register gating. Register gating has the following problems: 1. It consumes more control resources; 2. It has a negative impact on timing; 3. It has little effect on improving the efficiency of dynamic gating; 4. Register gating logic cannot be reused. Most of the module-level clock gating used in the related art is customized logic. When the PCIe system is iteratively upgraded or the application scenario is changed, the designed module-level clock gating cannot be reused.

[0045] Based on the above analysis, this application proposes a PCIe clock gating circuit, which has the following characteristics:

[0046] 1. Design clock gating by taking advantage of the PCIe system's characteristics of working at one link width (one of x1, x2, x4, x8 and x16) and one link rate (8b / 10b encoding for Gen1 or Gen2, 128b130b encoding for Gen3, Gen4 or Gen5, and PAM4 encoding for Gen6). Use module-level clock gating to shut down the clocks of other modules related to link width and link rate that are not working. This way, the clock flip and logic flip of related modules can be reduced, thereby reducing dynamic power consumption.

[0047] 2. Design clock gating by taking advantage of the fact that the PCIe system link training-related modules do not work in the L0 state, and use module-level clock gating to shut down the clocks of all modules related to link training.

[0048] 3. Use dedicated clock gating circuits and encapsulate them into universal clock gating component modules (CBB). Use circuits that are optimized for clock gating and can provide better performance and lower leakage current. After encapsulating them into modules, instantiate them at the top level to increase the reuse capability of module-level clock gating.

[0049] 4. Add register enable to module-level clock gating. The host can control the switch of clock gating by configuring registers. When the enable switch is turned on, the hardware controls whether the clock gating turns off the clock. When the enable switch is turned off, the clock gating always turns on the clock. This method can increase the stability and flexibility of the system.

[0050] See also Figure 1 As shown, the present application exemplarily proposes a PCIe clock gating circuit, including: a link width control circuit 101, a link rate control circuit 102 and a link state control circuit 103. Among them:

[0051] The link width control circuit 101 is used to output a control signal to turn off the clock of a module not related to the current width when the current link width is less than the maximum width; the module not related to the current width includes modules related to other channels other than the channel corresponding to the current link width, and modules related to other link widths other than the current link width;

[0052] The link rate control circuit 102 is used to output a control signal for shutting down the clock of a module not related to the current rate, wherein the module not related to the current rate includes a module corresponding to a link rate other than the current link rate;

[0053] The link state control circuit 103 is used to output a control signal to shut down the clock of the abnormal working state related module when the current link state is an abnormal working state, and the abnormal working state related module includes related modules corresponding to other link states other than the current link state;

[0054] The link state control circuit 103 is also used to output a control signal to turn off the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules in the normal working state.

[0055] In some embodiments, when the current link width is less than the maximum width supported by the PCIe system, unused channels, i.e., other channels other than the current channel, will enter an electrical idle state, at which time the logic of the other channels is not used, and the clocks of the corresponding modules, i.e., the modules not related to the current width, can be turned off. It is understandable that when the current link width is the maximum width, since all channels will be used, there is no need to turn off the clocks of the corresponding modules. For example, if the current link width is 4 and the maximum width is 16, then the related modules corresponding to the other link widths can be modules that are used only when the other channels are turned on except for the 4 channels corresponding to the current link width among the 16 channels.

[0056] In some optional implementations, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, an scrambling / de-scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link widths.

[0057] See also Figure 2 As shown, in some embodiments, the training code stream (TS) related module, Deskew module (de-skew module), scrambling module and message bus module are instantiated according to the number of channels in the PCIe system, that is, each channel will correspond to the above modules. When the current link width is less than the maximum width, the link width control circuit can generate a control signal to turn off the clock of the corresponding module, thereby turning off the above modules corresponding to other unused channels (that is, the training code stream (TS) related module, Deskew module (de-skew module), scrambling module and message bus module, wherein the training code stream (TS) related module is a link training related module, which is always turned off under normal working conditions). The above modules can be called channel related modules.

[0058] Exemplarily, the non-current width related modules also include path related modules. The conversion of 8b / 10b and 128b / 130b in the data path is also instantiated by the number of channels. When the current link width is less than the maximum width, the clock corresponding to the rate conversion module related to the conversion of 8b / 10b and 128b / 130b corresponding to other channels can be turned off. Among them, the rate conversion module corresponding to other channels belongs to the path related module.

[0059] Exemplarily, the sending and receiving of messages in the data path is related to the width of the current PCIe link. The current link width of PCIe determines the position of the symbol code (identification code) and token code (token code) of the message, and different link widths have different decoding logics. Therefore, the PCIe system only needs to turn on the clocks of the message sending module and message receiving module related to the current link width, and the clocks of the message sending modules and receiving modules of other link widths can be turned off. Among them, the message sending module or message receiving module corresponding to other link widths belongs to the path-related module.

[0060] In some optional implementations, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5, and at least one of a PAM4 encoding and decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module corresponding to Gen1 or Gen2 block, at least one of a message receiving processing module and a message sending processing module, and at least one of a PAM4 encoding and decoding module, a message receiving processing module and a message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of an 8b / 10b conversion module, a message receiving processing module and a message sending processing module corresponding to Gen1 or Gen2, and at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module and a Gen5 precoding module corresponding to Gen3, Gen4 or Gen5.

[0061] See also Figure 3As shown, exemplarily, when the current link rate is Gen1 or Gen2, the clocks of the training stream (TS) sending / receiving module, 8b / 10b conversion module and data sending / receiving module corresponding to Gen1 or Gen2 are all turned on, while the clocks of these modules are turned off at other link rates. That is to say, when the current link rate is Gen1 or Gen2, the non-current rate related modules include the related modules corresponding to Gen3, Gen4 or Gen5 and Gen6, and the link rate control circuit outputs a control signal for turning on the clock to the related modules corresponding to Gen1 or Gen2, and outputs a control signal for turning off the clock to the related modules corresponding to Gen3, Gen4 or Gen5 and Gen6.

[0062] When the current link rate is Gen3, Gen4 or Gen5, the clocks of the training stream (TS) sending / receiving module, 128b / 130b conversion module, message receiving processing module, message sending processing module and precoding module (only works when Gen5) corresponding to Gen3, Gen4 or Gen5 are turned on, and the clocks of the above modules are turned off at other link rates. That is to say, when the current link rate is Gen3, Gen4 or Gen5, the non-current rate related modules include the related modules corresponding to Gen1 or Gen2 and Gen6, and the link rate control circuit outputs a control signal for turning on the clock to the related modules corresponding to Gen3, Gen4 or Gen5, and outputs a control signal for turning off the clock to the related modules of Gen1 or Gen2 and Gen6.

[0063] When the current link rate is Gen6, the clocks of the PAM4 encoding and decoding module, the message receiving processing module and the message sending processing module corresponding to Gen6 are turned on, while the clocks of these modules are turned off at other link rates. That is to say, when the current link rate is Gen6, the non-current rate related modules include the related modules corresponding to Gen1 or Gen2 and Gen3, Gen4 or Gen5, and the link rate control circuit outputs a control signal for turning on the clock to the related modules corresponding to Gen6, and outputs a control signal for turning off the clock to the related modules corresponding to Gen1 or Gen2 and Gen3, Gen4 or Gen5.

[0064] In some optional implementations, the abnormal working state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching-related modules and other modules other than the link width switching-related modules; the abnormal working state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

[0065] See also Figure 4 As shown, exemplarily, currently in the link establishment (configuration) stage, the clocks of the training code stream (TS) sending module, the training code stream (TS) receiving module, the link peer detection module, the link polling module and the link equalization module can be turned on, while the clocks of other modules can be turned off.

[0066] Currently in the link recovery phase, the clocks of the training stream (TS) sending module, the training stream (TS) receiving module, the link rate switching and link width switching related modules can be turned on, while the clocks of other modules can be turned off.

[0067] When currently in a low power consumption state, the clock of the corresponding low power consumption sub-state related module can be turned on according to the current LTSSM state, such as turning on the clock of the L1 related module in L1ss, and the clocks of other modules can be turned off. Exemplarily, the low power consumption sub-state related modules include an L0s management module, an L0p management module, an L1ss management module, and an L2 management module.

[0068] The link establishment phase, link recovery phase and low power consumption state are all abnormal working states, and other states are normal working states. In normal working state, the clocks of modules related to link training can be turned off, such as the training code stream (TS) sending module, the training code stream (TS) receiving module and the link training related modules. It should be noted that Figure 4 The clocks of the above three modules corresponding to the normal working state can be turned off. The shutdown of other modules is controlled by the link width control circuit and the link rate control circuit. In other words, the control signals output by the link width control circuit and the link rate control circuit are valid under normal working state and invalid under abnormal working state. Under abnormal working state, the control signals output by the link state control circuit are used to control the clocks of various modules.

[0069] In some optional implementations, the PCIe clock gating circuit further includes: a logic OR gate;

[0070] The logic OR gate is used to perform a logic OR operation on a plurality of control signals to be output to the same clock.

[0071] For example, under normal working conditions, the link width control circuit, link rate control circuit and link status control circuit output control signals to the clocks of each module according to their respective logics, where multiple control signals may be output to the clock of the same module. Therefore, a logic OR gate may be set before the clock of the same module, so that multiple control signals are output to the clock after the logic OR operation of the logic OR gate. In this way, as long as there is a control signal to turn on the clock, the clock will be turned on, and if all control signals output to the same clock are shutdown signals, the clock will be turned off. It should also be noted that under normal working conditions, the clocks of modules related to link training are all turned off.

[0072] In some optional implementations, the PCIe clock gating circuit further includes: a register enable signal output circuit;

[0073] The register enable signal output circuit is used to output an enable signal to the logic OR gate according to the configuration information in the setting register, so as to enable the control signal output to the clock.

[0074] See also Figure 5 As shown, exemplarily, the enable signal output by the register enable signal output circuit is also output to the logic OR gate so as to perform a logic OR operation with the control signal output by the link width control circuit, the link rate control circuit and the link state control circuit. The enable signal output by the register enable signal output circuit depends on the configuration information of the register. If the configuration information is to enable the control signal output by the link width control circuit, the link rate control circuit and the link state control circuit, a low level is output, so that the control signal finally output to the clock is based on the control signal output by the link width control circuit, the link rate control circuit and the link state control circuit. If the configuration information is to invalidate the control signal output by the link width control circuit, the link rate control circuit and the link state control circuit, a high level is output, so that the control signal finally output to the clock is always a high level and is not affected by the control signal output by the link width control circuit, the link rate control circuit and the link state control circuit.

[0075] Refer to the following Figure 5The design of the PCIe clock gating circuit is described as follows, where the control circuit A represents a circuit including a link width control circuit, a link rate control circuit, and a link status control circuit, CLK Gate represents a clock, and modules A and B represent modules that need to be turned off or on:

[0076] ① Design clock enable control signals for different scenarios based on PCIe link width, link rate, and link working scenarios;

[0077] ② The configuration register generates an enable signal. When the enable signal is at a low level, the hardware controls whether the clock gating turns off the clock; when the enable signal is at a high level, the clock gating is always on.

[0078] ③ Generate dedicated clock gating circuits and encapsulate them into general clock gating component modules (CLK Gate CBB). These circuits are specially optimized for clock gating and can provide better performance and lower leakage current.

[0079] ④Use the control signal to connect the universal clock gating component module, turn on the clock when the control signal is valid, turn off the clock when the control signal is invalid, and output the controlled gated clock. Finally, input the gated output clock to the controlled module.

[0080] The above is the PCIe clock gating circuit proposed in this application, which can effectively reduce the dynamic power consumption of the entire PCIe system. The actual working modules are distinguished by PCIe link width, link rate, and link working scenario. Turning off the clock of the module that is not working can greatly reduce clock flips and logic flips. Compared with the clock gating of inserting registers in the related technology, the module-level clock module requires fewer hardware resources and is simpler in design.

[0081] In addition, the module-level clock gating circuit controls the clock on and off without software intervention, and all control is automatically completed by hardware; at the same time, the software can control the opening and closing of the clock gating, which increases the flexibility of the entire solution.

[0082] This application can support different versions of the PCIe protocol and can reduce the dynamic power consumption of the PCIe controller in various business scenarios. According to simulation verification, in the PCIe controller IDLE mode (L1ss), the system power consumption can be reduced by 70%; single channel (x1) in normal business scenarios (L0), the system power consumption can be reduced by 30%; full channel (x16) in normal business scenarios (L0), the system power consumption can be reduced by 10%.

[0083] Accordingly, see Figure 6 As shown, the present application exemplarily provides a PCIe clock control method, including:

[0084] In step S601, when the current link width is less than the maximum width, the link width control circuit outputs a control signal for shutting down the clock of a module not related to the current width; the module not related to the current width includes modules related to other channels other than the channel corresponding to the current link width, and modules corresponding to other link widths other than the current link width;

[0085] In step S602, the link rate control circuit outputs a control signal for shutting down the clock of the module not related to the current rate, wherein the module not related to the current rate includes the module corresponding to the other link rates other than the current link rate;

[0086] In step S603, when the current link state is an abnormal working state, the link state control circuit outputs a control signal for shutting down the clock of a module related to the abnormal working state, wherein the module related to the abnormal working state includes a module corresponding to other link states other than the current link state;

[0087] In step S604, when the current link state is a normal working state, the link state control circuit outputs a control signal for shutting down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules.

[0088] In some optional implementations, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, an scrambling / de-scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link widths.

[0089] In some optional implementations, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5, and at least one of a PAM4 encoding and decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module corresponding to Gen1 or Gen2 block, at least one of a message receiving processing module and a message sending processing module, and at least one of a PAM4 encoding and decoding module, a message receiving processing module and a message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of an 8b / 10b conversion module, a message receiving processing module and a message sending processing module corresponding to Gen1 or Gen2, and at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module and a Gen5 precoding module corresponding to Gen3, Gen4 or Gen5.

[0090] In some optional implementations, the abnormal working state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching-related modules and other modules other than the link width switching-related modules; the abnormal working state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

[0091] In some optional implementations, the method further includes:

[0092] The plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

[0093] In some optional implementations, the plurality of control signals to be output to the same clock are output to the clock by the logic OR gate after passing through the logic OR gate, including:

[0094] The register enable signal output circuit outputs an enable signal to the logic OR gate;

[0095] The enable signal and the plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

[0096] The above PCIe clock control method can be implemented by the PCIe clock gating circuit provided in the above embodiment. The specific implementation method can refer to the description of the PCIe clock gating circuit in the above embodiment, which will not be repeated here.

[0097] It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.

[0098] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A PCIe clock gating circuit, characterized in that: include: link width control circuit, link rate control circuit and link status control circuit; wherein, The link width control circuit is used to output a control signal to turn off the clock of a module not related to the current width when the current link width is less than the maximum width; the module not related to the current width includes modules related to other channels other than the channel corresponding to the current link width, and modules related to other link widths other than the current link width; The link rate control circuit is used to output a control signal for shutting down the clock of a module not related to the current rate, wherein the module not related to the current rate includes a module corresponding to a link rate other than the current link rate; The link state control circuit is used to output a control signal for shutting down the clock of a module related to an abnormal working state when the current link state is an abnormal working state, and the module related to the abnormal working state includes a module corresponding to other link states other than the current link state; The link state control circuit is also used to output a control signal for shutting down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules in a normal working state.

2. The PCIe clock gating circuit according to claim 1, characterized in that: The non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, a scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link widths.

3. The PCIe clock gating circuit according to claim 1, characterized in that: When the current link rate is Gen1 or Gen2, the non-current rate related modules include at least one of the 128b / 130b conversion module, message receiving processing module, message sending processing module and Gen5 precoding module corresponding to Gen3, Gen4 or Gen5, and at least one of the PAM4 encoding and decoding module, message receiving processing module and message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4 or Gen5, the non-current rate related modules include the 8b / 10b conversion module, message receiving processing module and message sending processing module corresponding to Gen1 or Gen2 At least one of the processing module and the message sending processing module, and at least one of the PAM4 encoding and decoding module, the message receiving processing module and the message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of the 8b / 10b conversion module, the message receiving processing module and the message sending processing module corresponding to Gen1 or Gen2, and at least one of the 128b / 130b conversion module, the message receiving processing module, the message sending processing module and the Gen5 precoding module corresponding to Gen3, Gen4 or Gen5.

4. The PCIe clock gating circuit according to claim 1, characterized in that: The abnormal working state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching related modules and the link width switching related modules other than the modules; the abnormal working state related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

5. The PCIe clock gating circuit according to any one of claims 1 to 4, characterized in that: Also includes: Logic OR gate; The logic OR gate is used to perform a logic OR operation on a plurality of control signals to be output to the same clock.

6. The PCIe clock gating circuit according to claim 5, characterized in that: Also includes: Register enable signal output circuit; The register enable signal output circuit is used to output an enable signal to the logic OR gate according to the configuration information in the setting register, so as to enable the control signal output to the clock.

7. A PCIe clock control method, characterized in that: include: When the current link width is less than the maximum width, the link width control circuit outputs a control signal for shutting down the clock of a module not related to the current width; the module not related to the current width includes modules related to other channels other than the channel corresponding to the current link width, and modules corresponding to other link widths other than the current link width; The link rate control circuit outputs a control signal for shutting down the clock of a module not related to the current rate, wherein the module not related to the current rate includes a module corresponding to a link rate other than the current link rate; When the current link state is an abnormal working state, the link state control circuit outputs a control signal for shutting down the clock of a module related to the abnormal working state, wherein the module related to the abnormal working state includes a module corresponding to other link states other than the current link state; When the current link state is a normal working state, the link state control circuit outputs a control signal for shutting down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules.

8. The PCIe clock control method according to claim 7, characterized in that: The non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, a scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link widths.

9. The PCIe clock control method according to claim 7, characterized in that: When the current link rate is Gen1 or Gen2, the non-current rate related modules include at least one of the 128b / 130b conversion module, message receiving processing module, message sending processing module and Gen5 precoding module corresponding to Gen3, Gen4 or Gen5, and at least one of the PAM4 encoding and decoding module, message receiving processing module and message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4 or Gen5, the non-current rate related modules include the 8b / 10b conversion module, message receiving processing module and message sending processing module corresponding to Gen1 or Gen2 At least one of the processing module and the message sending processing module, and at least one of the PAM4 encoding and decoding module, the message receiving processing module and the message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of the 8b / 10b conversion module, the message receiving processing module and the message sending processing module corresponding to Gen1 or Gen2, and at least one of the 128b / 130b conversion module, the message receiving processing module, the message sending processing module and the Gen5 precoding module corresponding to Gen3, Gen4 or Gen5.

10. The PCIe clock control method according to claim 7, characterized in that: The abnormal working state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching related modules and the link width switching related modules other than the modules; the abnormal working state related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

11. The PCIe clock control method according to any one of claims 7 to 10, characterized in that: Also includes: The plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

12. The PCIe clock control method according to claim 11, characterized in that: The plurality of control signals to be output to the same clock are output to the clock by the logic OR gate after passing through the logic OR gate, including: The register enable signal output circuit outputs an enable signal to the logic OR gate; The enable signal and the plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

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