A tb-rm circuit logic detection method, storage medium and device

Abstract

The present application relates to a kind of TB-RM circuit logic detection method, storage medium and equipment, the method includes the following steps: reading Boolean logic circuit to be detected;Extract any k variable logic function, judge whether the k variable logic function satisfies RM logic general judgment condition;When satisfying the RM logic general judgment condition, traverse multivariate parent layer structure and multivariate sublayer structure layer by layer, carry out positive / negative variable condition judgment to each layer structure;Obtain logic judgment result, determine the logic function representation mode suitable for the circuit to be detected according to the logic judgment result.Compared with prior art, the present application has the advantages of improving logic detection efficiency while ensuring the accuracy of logic detection.

Description

Technical Field

[0001] The present invention relates to the technical field of TB-RM (Traditional Boolean and Reed-Muller) logic circuit optimization, and in particular to a TB-RM circuit logic detection method, storage medium, and device. Background Art

[0002] Early IC design focused primarily on Boolean logic. In fact, digital circuits can also be implemented using Reed-Muller (RM) logic based on XNOR / XOR (exclusive OR / exclusive OR) operations, achieving complete logical functionality. Research has shown that digital circuits using RM-based logic (such as arithmetic logic circuits and parity check circuits) offer advantages over traditional Boolean logic in terms of power consumption, area, speed, and testability. Existing EDA (Electronic Design Automation) software almost exclusively designs circuits based on Traditional Boolean (TB) logic. This prevents circuits suitable for RM logic from achieving optimal performance at the logic level, thus limiting circuit performance improvements. Conversely, using RM logic to comprehensively optimize circuits suitable for TB logic can make the circuit expression more complex, the circuit structure more complicated, and reduce circuit performance. For most circuits, a TB-RM dual-logic optimization approach combining RM and TB logic can significantly improve circuit performance. However, research on logic probing methods is still in its early stages, and the relevant theory is still immature. The growth in scale, complexity, and integration of integrated circuits has significantly increased the complexity of logic circuit structures. Furthermore, truth tables, Karnaugh maps, and sum-of-products-based descriptive forms are not conducive to capturing circuit details and analyzing circuits, and their manipulation of logic functions is inefficient. Furthermore, existing research has only combined the basic XOR operation with TB logic for single-variable synthesis, without fully considering the XNOR operator and multivariable synthesis. Therefore, front-end design requires rapid analysis of which nodes are suitable for XOR / XNOR logic synthesis and which nodes are suitable for TB logic synthesis.

[0003] For the existing large-scale circuit optimization field, it is urgent to study an effective logic synthesis method. Summary of the Invention

[0004] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a TB-RM circuit logic detection method, storage medium and device with high accuracy and high detection efficiency.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] A TB-RM circuit logic detection method includes the following steps:

[0007] Read the Boolean logic circuit to be detected;

[0008] Extract any k-variable logic function and determine whether the k-variable logic function meets the general judgment conditions of RM logic;

[0009] When the general judgment condition of RM logic is met, the logic function MROBDD traverses the multi-variable parent layer structure and the multi-variable child layer structure layer by layer, and performs positive / negative variable condition judgment on each layer structure;

[0010] A logic judgment result is obtained, and a logic function representation method applicable to the circuit to be detected is determined according to the logic judgment result.

[0011] Furthermore, the general judgment condition of the RM logic is expressed as:

[0012]

[0013] Among them, f(x1,x2,...,x k ) is a k-variable logistic function, parent (1) ,parent (2) ,…,parent (n) Represents the parent node group, child (1) ,child (2) ,…,child (m) Represents a child node group, which is divided into low-edge child nodes child L(j) and high-edge child node child R(j) , x parent(i) For the node parent (i) Function of the variable, x child-L(j) For node child L(j) Function of the variable, x child-R(j) For node child R(j) Function of variables, f L (x1,x2,...,x k ),f R (x1,x2,...,x k ) indicates a pointer to a node or function.

[0014] Furthermore, the layer-by-layer traversal is specifically as follows:

[0015] Starting from the 0th layer where the root node of the logic function MROBDD is located, the positive / negative variable judgment of the variable parent layer structure and the multi-variable child layer structure is performed layer by layer.

[0016] Furthermore, the positive / negative variable conditions of the multivariable parent layer structure are specifically:

[0017] There exists parent(i+1)=low[parent(i)], such that

[0018]

[0019] Where i∈[1,…,n], low[parent] and high[parent] represent the non-terminal left and right child nodes in the parent layer structure, parent(i) represents the i-th parent node, and x parent(i) Expressed as an inverse variable, x parent(i) For the node parent (i) Variable function, child L(1) Represents a low-edge child node.

[0020] Furthermore, the positive / negative variable conditions of the multivariable sub-layer structure are specifically:

[0021] Child exists L(j+1) =low[child L(j) ], child R(j+1) =low[child R(j) ], making

[0022]

[0023] Where j∈[1,…,m], low[child] and high[child] represent the non-terminal left and right child nodes in the sub-layer structure, and x child(j) Expressed as an inverse variable, x child(j) For node child (j) Variable function, child L(j) 、child R(j) Represents a child node.

[0024] Furthermore, the logic function representation includes RM logic representation, TB logic representation and TB-RM logic representation.

[0025] Furthermore, determining the logic function representation mode applicable to the circuit to be detected according to the logic judgment result specifically includes:

[0026] If, except for the layer with only one "low" edge pointing to the "0" terminal node, the positive / negative variable conditions of the multivariable parent layer structure and the positive / negative variable conditions of the multivariable child layer structure are met between two adjacent layers, then the logic function of the circuit to be detected is suitable for expression using RM logic;

[0027] If the above conditions are not met between any two adjacent layers, the logic function of the circuit to be detected is suitable for expression using TB logic;

[0028] If there are some adjacent layers that meet the above conditions, then the logic function of the circuit to be detected is suitable for being represented by TB-RM logic.

[0029] Furthermore, when the TB-RM logic representation is adopted, the number of nodes of the TB-RM logic function is represented by calculating the number of all operation bases after the logic detection.

[0030] The present invention also provides a computer-readable storage medium comprising one or more programs for execution by one or more processors of an electronic device, wherein the one or more programs include instructions for executing the TB-RM circuit logic detection method as described above.

[0031] The present invention also provides an electronic device, comprising one or more processors, a memory, and one or more programs stored in the memory, wherein the one or more programs include instructions for executing the TB-RM circuit logic detection method as described above.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] (1) Optimizing the logic level in integrated circuit design can often reduce the area of ​​the integrated circuit. Logic detection is to determine which logic is suitable for the circuit and output the optimal expression, thereby improving the quality of the circuit design. It cannot be ignored in the implementation of logic circuit optimization. Existing logic detection methods for large-scale circuits have limitations (only suitable for small-scale logic circuits) or low efficiency. Therefore, what is most needed at present is to find a logic detection method that can quickly and accurately detect large-scale logic circuits. By analyzing and detecting the MROBDD of the logic function based on the characteristics of multi-variable XOR logic and multi-variable XNOR logic, it can be determined whether the RM logic synthesis part of a function is suitable for logic synthesis based on OR / XNOR logic, AND / XOR, or a combination of the two. It can also identify and determine whether it is suitable for multi-variable RM logic synthesis, thereby improving the accuracy of the MROBDD-based logic detection method.

[0034] (2) Using the simplest MROBDD structure to describe logic functions can improve the efficiency of logic function operations, thereby improving the efficiency of logic detection. Starting directly from the characteristics of multi-variable XOR logic and multi-variable XNOR logic, the logic function is analyzed and detected directly according to the characteristics of RM logic. This can improve the efficiency of logic detection while ensuring the accuracy of logic detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1It is a schematic diagram of the process of the present invention;

[0036] Figure 2 Schematic diagram of the multivariable RM logic structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0038] like Figure 1 As shown, this embodiment provides a TB-RM circuit logic detection method, including the following steps:

[0039] Step 1: Read the Boolean logic circuit.

[0040] Step 2: Perform universal judgment on any k-variable logic function.

[0041] The nodes of RM logic relation MROBDD (Multi-valued Reduced Ordered Binary Decision Diagram) can correspond to the identities of “parent” and “child” respectively, so the k-variable logic function f(x1, x2,…, x k ) of the MROBDD, there must be a "parent" node group parent (1) ,parent (2) ,…,parent (n) and the "child" node group child (1) ,child (2) ,…,child (m) , the child node group can be divided into low-edge child nodes child L(j) and high-edge child node child R(j) , where m∈N * ,n∈N * ,m+n=k.

[0042] In this step, a general RM logic judgment is performed on any k-variable logic function, such as Figure 2 As shown, the general judgment condition is expressed as:

[0043]

[0044] If the above formula is satisfied, the final point is the same node or function f L (x1,x2,...,x k ) and f R (x1,x2,...,xk ), that is, f L and f R , then parent (1) ,parent (2) ,…,parent (n) and child (1) ,child (2) ,…,child (m) There is an RM logical relationship between them. Where i∈n,j∈m,x parent(i) For the node parent (i) Function of the variable, x child-L(j) For node child L(j) Function of the variable, x child-R(j) For node child R(j) Function of the variable, x fL f L (x1,x2,...,x k ), that is, node f L Function of the variable, x fR f R (x1,x2,...,x k ), that is, node f R Function of the variable, x fL ≠x fR The logical function expression of RM logic universal judgment is as follows:

[0045]

[0046] Step 3: Perform positive / negative variable judgment on the multivariate parent layer structure.

[0047] The positive / negative variable judgment of the multivariable parent layer structure is expressed as follows: Under the general judgment condition of step 2, if parent(i+1)=low[parent(i)], then

[0048]

[0049] Where i∈[1,…,n], low[parent] and high[parent] represent the non-terminal left and right child nodes in the parent layer structure, which are low edges and high edges respectively. When the above equation is satisfied, that is, the high edge of parent(i) points to child L(1) , then x parent(i) Expressed as an inverse variable.

[0050] Step 4: Perform positive / negative variable judgment on the multivariate sub-layer structure.

[0051] The positive / negative variable judgment of the multivariable sub-layer structure is expressed as follows: Under the general judgment conditions of step 2, if the child L(j+1) =low[child L(j) ], child R(j+1) =low[child R(j) ], making

[0052]

[0053] Where j∈[1,…,m], low[child] and high[child] represent the non-terminal left and right child nodes in the sub-layer structure. When the above equation is satisfied, that is, one of the child nodes is satisfied. L(j) The high side of the node points to f L , and satisfies one of the child R(j) The high side of the node points to f R , then x child(j) Expressed as an inverse variable.

[0054] Finally, the multivariable RM logic function expression is as follows:

[0055]

[0056] Step 5: Output the logical judgment results of the binary decision diagram layer by layer, that is, the node variables, by using the classic pre-order traversal method.

[0057] In this step, starting at level 0, where the root node of the logic function MROBDD resides, each level verifies whether any two adjacent levels meet the general judgment criteria, the multivariable parent level structure criteria, and the multivariable child level structure criteria. If all adjacent levels in the decision diagram meet these criteria, except for levels with only one "low" edge pointing to a "0" terminal node, the logic function is suitable for RM logic representation. If none of these conditions are met between adjacent levels, the logic function is suitable for TB logic representation. If some adjacent levels meet these conditions, the logic function is suitable for TB-RM logic representation.

[0058] Finally, the dual logic function of the test circuit is output based on the pre-order traversal and logic detection results of the MROBDD. Here, the number of nodes of the TB-RM logic function is represented by counting the number of all operation bases after logic detection.

[0059] If the above method is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0060] In another embodiment, an electronic device is also provided, including one or more processors, a memory, and one or more programs stored in the memory, the one or more programs including instructions for performing the TB-RM circuit logic probing method as described above.

[0061] The computer program instructions can also be stored in a computer readable storage medium that can direct the computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable storage medium produce a product including instruction means, which realizes the functions specified in the flow Figure 1 One or more flows and / or blocks Figure 1 One or more blocks or multiple blocks.

[0062] The computer program instructions can also be loaded into a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer implemented process, so that the instructions executed on the computer or other programmable device provide steps for realizing the functions specified in the flow Figure 1 One or more flows and / or blocks Figure 1 One or more blocks or multiple blocks.

[0063] The above detailed the preferred embodiments of the present application. It should be understood that those skilled in the art can make many modifications and changes without creative labor based on the concept of the present application. Therefore, any technical solution that can be obtained by logical analysis, reasoning or limited experiment based on the prior art according to the concept of the present application shall be within the protection scope determined by the claims.

Claims

1. A TB-RM circuit logic detection method, characterized in that: The following steps are involved: Read the Boolean logic circuit to be detected; Extract any k Variable logic function, judge the k Whether the variable logic function meets the general judgment conditions of RM logic; When the general judgment condition of RM logic is met, the logic function MROBDD traverses the multi-variable parent layer structure and the multi-variable child layer structure layer by layer, and performs positive / negative variable condition judgment on each layer structure; Obtaining a logic judgment result, and determining a logic function representation method applicable to the circuit to be detected according to the logic judgment result; The general judgment condition of the RM logic is expressed as: in, for k variable logic functions, parent (1) , parent (2) ,…, parent (n) Represents the parent node group, child (1) , child (2) ,…, child (m) Represents a sub-node group, which is divided into low-edge sub-nodes child L(j) and high-edge subnodes child R(j) , x parent(i) For nodes parent (i) Variable function, x child-L(j) For nodes child L(j) Variable function, x child-R(j) For nodes child R(j) Variable function, 、 Indicates pointing to a node; The positive / negative variable conditions of the multivariable parent layer structure are specifically: exist parent ( i +1) = low [ parent ( i )], so that in , low [ parent ]and high [ parent ] represents the non-terminal left and right child nodes in the parent layer structure, parent ( i ) indicates the i A parent node, represents the lower edge subnode, then x parent(i) Expressed as an inverse variable, x parent(i) For nodes parent (i) Variable function of ; The positive / negative variable conditions of the multivariable sub-layer structure are specifically: exist child L(j+1) = low [ child L(j) ], child R(j+1) = low [ child R(j) ], making in , low [ child ]and high [ child ] represents the non-terminal left and right child nodes in the sub-layer structure, child L(j) 、 child R(j) Represents a child node, 、 Represents a point to a node, then x child(j) Expressed as an inverse variable, x child(j) For nodes child (j) Variable function of ; Determining the logic function representation suitable for the circuit to be detected according to the logic judgment result specifically includes: If, except for the layer with only one "low" edge pointing to the "0" terminal node, the positive / negative variable conditions of the multivariable parent layer structure and the positive / negative variable conditions of the multivariable child layer structure are met between two adjacent layers, then the logic function of the circuit to be detected is suitable for RM logic representation; If the above conditions are not met between any two adjacent layers, the logic function of the circuit to be detected is suitable for expression using TB logic; If there are some adjacent layers that meet the above conditions, then the logic function of the circuit to be detected is suitable for being represented by TB-RM logic.

2. The TB-RM circuit logic detection method according to claim 1, characterized in that: The layer-by-layer traversal is specifically as follows: Starting from the 0th layer where the root node of the logic function MROBDD is located, the positive / negative variable judgment of the variable parent layer structure and the multi-variable child layer structure is performed layer by layer.

3. The TB-RM circuit logic detection method according to claim 1, characterized in that: The logic function representation includes RM logic representation, TB logic representation and TB-RM logic representation.

4. The TB-RM circuit logic detection method according to claim 3, characterized in that: When the TB-RM logic representation is adopted, the number of nodes of the TB-RM logic function is represented by calculating the number of all operation bases after the logic detection.

5. A computer-readable storage medium, characterized in that It comprises one or more programs for execution by one or more processors of an electronic device, wherein the one or more programs comprise instructions for executing the TB-RM circuit logic detection method according to any one of claims 1 to 4.

6. An electronic device, characterized in that: The system comprises one or more processors, a memory and one or more programs stored in the memory, wherein the one or more programs include instructions for executing the TB-RM circuit logic detection method according to any one of claims 1 to 4.

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