A method and system for integrated circuit layout design based on circuit applications.

Abstract

The present invention discloses a circuit usage-based integrated circuit layout design method and system, which relates to the technical field of circuit design, including: obtaining a gate-level netlist generated after synthesis of a front-end chip design; establishing a three-dimensional space and chip model of an integrated circuit; using a nonlinear programming method to solve the minimum value of an objective function to obtain the spatial position distribution of electronic components; distributing spatially uniformly distributed units on each chip layer; performing actual physical wiring connection processing of integrated circuit signal lines; converting a detailed layout into a two-dimensional detailed layout inside each chip layer; realizing a power supply network; filling gaps in a chip layout, and physically verifying and simulating the chip layout based on the circuit usage of the integrated circuit. By setting a data processing module, a circuit layout module, and a circuit detection module, interconnection delay is reduced, routing density is reduced, and circuit safety and reliability are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to an integrated circuit layout design method and system based on circuit usage. Background Art

[0002] Inherited circuit logic design must be combined with physical characteristics to accurately give targets such as delay, power consumption, area, and routability. However, increasingly complex designs have caused more and more serious interconnect effects, such as low power consumption, crosstalk noise, voltage drop, and power supply noise, which greatly increases the factors that need to be considered in the design process. How to effectively reduce interconnect delay, reduce routing density, and ensure circuit safety and reliability has become a problem that needs to be solved urgently. Summary of the invention

[0003] In order to solve the above technical problems, a method and system for designing integrated circuit layout based on circuit usage are provided. This technical solution solves the problems raised in the above background technology.

[0004] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0005] A method for designing integrated circuit layout based on circuit usage, comprising:

[0006] Prepare the layout and routing data of the integrated circuit and obtain the gate-level netlist generated by the front-end chip design after synthesis;

[0007] Based on the circuit usage of the integrated circuit, establish the three-dimensional space and chip model of the integrated circuit;

[0008] The nonlinear line length target and distribution target of each electronic component are unified into an objective function, and a nonlinear programming method is used to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic components, wherein the electronic components include transistors, resistors and capacitors;

[0009] Distribute spatially uniformly distributed cells on each chip layer;

[0010] According to all the connection relationships in the gate-level netlist, actual physical wiring connection processing of the integrated circuit signal lines is performed;

[0011] By decomposing the vertical network, the connection between the units of the same network in different chip layers is cut off, and the detailed layout is converted into a two-dimensional detailed layout inside each chip layer;

[0012] Obtain the design requirements for voltage drop in integrated circuits and implement power supply networks;

[0013] Fill the gaps in the chip layout, perform physical verification and simulation testing on the chip layout based on the circuit usage of the integrated circuit, and export the integrated circuit layout design data that passes the test.

[0014] Preferably, the step of preparing layout and routing data of the integrated circuit and obtaining a gate-level netlist generated after synthesis of the front-end chip design specifically includes:

[0015] Output the connection relationship between the CPU, memory and subsystems as a system-level description of the gate-level netlist;

[0016] Output the connection relationship between hardware modules into an algorithmic description of a gate-level netlist using computer language;

[0017] The connection relationship between logic gates and triggers is output as a logic layer description of the gate-level netlist using Boolean equations;

[0018] The connection relationship between electronic components is output as a circuit layer description of the gate-level netlist using circuit differential equations;

[0019] The Boolean equations are: ,

[0020] In the formula, is the nth logic gate, is the sth trigger, is the mth feasible logic gate connection method, is the mth feasible trigger connection mode;

[0021] The circuit differential equation is: ,

[0022] In the formula, is the inductance value of the electronic component, is the resistance value of the electronic component, is the current value function of the electronic component, For time, is the power supply voltage, is the capacitance value of the electronic component, is the voltage value function of the electronic component, is the reciprocal resistance of electronic components, is the short circuit current.

[0023] Preferably, the establishing of the three-dimensional space and chip model of the integrated circuit based on the circuit usage of the integrated circuit specifically includes:

[0024] Determine the size parameters of the layout cube space of the integrated circuit based on the circuit usage of the integrated circuit;

[0025] Each electronic component is set as a small cube, and the ratio of the height of the layout cube to the number of chip layers is output as the vertical height of each electronic component;

[0026] The electronic components are evenly distributed in the space of the layout cube and output as a chip model.

[0027] Preferably, unifying the nonlinear line length target and distribution target of each electronic component into an objective function, and using a nonlinear programming method to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic component specifically includes:

[0028] The total length of each layer of electronic components is calculated using the wire length model formula;

[0029] Preset a wire length parameter to optimize the wire network, and gradually reduce the wire length parameter, while optimizing the wire network after the wire length parameter is reduced;

[0030] Using the overlap formula, the overlap between the grid and the electronic components is calculated to evaluate the layout density;

[0031] Determine whether the layout density is lower than a preset threshold. If so, output the current layout as the overall layout. If not, re-layout;

[0032] The line length model formula is: ,

[0033] In the formula, is the total length of the electronic components in this layer, For adjustable line length parameters, is the length of the i-th electronic component in this layer, is the width of the i-th electronic component in this layer, is the total number of electronic components in this layer;

[0034] The overlap formula is: ,

[0035] In the formula, is the overlap between the k-th chip and the g-th cube, , , are the overlap between the ith electronic component on the kth layer chip and the gth cube in the x, y, and z directions, respectively.

[0036] Preferably, distributing the spatially uniformly distributed units on each chip layer specifically includes:

[0037] Arrange at least one electronic component in descending order of coordinates in the vertical direction, and scan each electronic component from bottom to top;

[0038] The default subspace level is N;

[0039] Divide each layer of chips into N*N subspaces;

[0040] Calculate the layered cost of each electronic component using the cost function;

[0041] Based on the layering cost of each electronic component in each layer of the chip, at least one electronic component is allocated to each layer of the chip;

[0042] The cost function is: ,

[0043] In the formula, is the delamination cost of electronic components, are respectively the first preset weight, the second preset weight and the third preset weight, is the number of vertical through holes, is the total area occupied by the electronic components in this layer, is the density of electronic components in the i-th subspace, is the subspace series.

[0044] Preferably, decomposing the vertical wire net to cut off the connection between the units of the same wire net in different chip layers, and converting the detailed layout into a two-dimensional detailed layout inside each chip layer specifically includes:

[0045] Cut off the connection between electronic components in different layers and decompose the wire net at the cut point into two wire nets;

[0046] A new soldering block is generated at the cut position and fixed on the chip layer;

[0047] The coordinates of the welding block are selected as the average values ​​of the horizontal coordinates and the vertical coordinates of all the electronic components included in the wire mesh;

[0048] Sort the electronic components horizontally according to their coordinate positions;

[0049] Place each electronic component on the left border of the row in turn, and modify the left border of the row to the right border of the current electronic component;

[0050] Set the movement cost to the movement amount of the electronic component;

[0051] Select the row with the lowest moving cost to place each electronic component.

[0052] Furthermore, a circuit usage-based integrated circuit layout design system is proposed, which is used to implement the circuit usage-based integrated circuit layout design method as described above, comprising:

[0053] A data processing module, which is used to prepare the layout and routing data of the integrated circuit, obtain the gate-level netlist generated by the front-end chip design after synthesis, and establish a three-dimensional space and chip model of the integrated circuit based on the circuit usage of the integrated circuit;

[0054] A circuit layout module, the circuit layout module is used to unify the nonlinear line length target and distribution target of each electronic component into an objective function, use a nonlinear programming method to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic components, distribute the spatially uniformly distributed units on each chip layer, perform actual physical wiring connection processing of the integrated circuit signal line according to all connection relationships in the gate-level netlist, decompose the vertical line network to cut off the connection between the units of the same line network in different chip layers, and convert the detailed layout into a two-dimensional detailed layout inside each chip layer;

[0055] The circuit detection module is used to obtain the design requirements for voltage drop in the integrated circuit, realize the power supply network, fill the gaps in the chip layout, and perform physical verification and simulation testing on the chip layout based on the circuit usage of the integrated circuit, and export the integrated circuit layout design data that passes the test.

[0056] Optionally, the data processing module specifically includes:

[0057] A data acquisition unit, the data acquisition unit is used to prepare the layout and routing data of the integrated circuit and obtain the gate-level netlist generated after the front-end chip design is synthesized;

[0058] A model building unit, the model building unit is used to build a three-dimensional space and chip model of the integrated circuit based on the circuit usage of the integrated circuit;

[0059] The circuit layout module specifically includes:

[0060] A global layout unit, wherein the global layout unit is used to unify the nonlinear line length target and the distribution target of each electronic component into an objective function, and use a nonlinear programming method to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic component;

[0061] A layer allocation unit, the layer allocation unit is used to distribute the spatially uniformly distributed units on each chip layer;

[0062] A physical wiring unit, the physical wiring unit is used to perform actual physical wiring connection processing of integrated circuit signal lines according to all connection relationships in the gate-level netlist;

[0063] A detailed layout unit, wherein the detailed layout unit is used to decompose the vertical line net to cut off the connection between the units of the same line net in different chip layers, and convert the detailed layout into a two-dimensional detailed layout inside each chip layer;

[0064] The circuit detection module specifically includes:

[0065] A power supply design unit, the power supply design unit is used to obtain the design requirements of the voltage drop in the integrated circuit and realize the power supply network;

[0066] A simulation test unit is used to fill the gaps in the chip layout, and to perform physical verification and simulation testing on the chip layout based on the circuit usage of the integrated circuit, and to derive the integrated circuit layout design data that passes the test.

[0067] Compared with the prior art, the present invention has the following beneficial effects:

[0068] By designing the three-dimensional structure of integrated circuits and utilizing vertical interconnections between chips, the length of interconnection lines between devices can be effectively shortened to avoid winding, thereby reducing connection complexity and congestion, reducing interconnection delays, reducing routing density, and ensuring circuit safety and reliability. At the same time, three-dimensional circuits can also effectively improve transistor integration and reduce circuit area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 A flow chart of the integrated circuit layout design method based on circuit usage of the present invention;

[0070] Figure 2 A flow chart of a method for obtaining a gate-level netlist generated after synthesis of a front-end chip design according to the present invention;

[0071] Figure 3 A flow chart of the method for establishing a three-dimensional space and chip model of an integrated circuit according to the present invention;

[0072] Figure 4 A flow chart of a method for obtaining the spatial position distribution of electronic components according to the present invention;

[0073] Figure 5 A flow chart of a method for distributing spatially uniformly distributed units on each chip layer according to the present invention;

[0074] Figure 6 This is a flow chart of the method for converting a detailed layout into a two-dimensional detailed layout inside each chip layer according to the present invention. DETAILED DESCRIPTION

[0075] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art may think of other obvious variations.

[0076] Reference Figure 1 As shown, a method for designing integrated circuit layout based on circuit usage includes:

[0077] Prepare the layout and routing data of the integrated circuit and obtain the gate-level netlist generated by the front-end chip design after synthesis;

[0078] Based on the circuit usage of the integrated circuit, establish the three-dimensional space and chip model of the integrated circuit;

[0079] The nonlinear line length target and distribution target of each electronic component are unified into an objective function, and a nonlinear programming method is used to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic components, wherein the electronic components include transistors, resistors and capacitors;

[0080] Distribute spatially uniformly distributed cells on each chip layer;

[0081] According to all the connection relationships in the gate-level netlist, actual physical wiring connection processing of the integrated circuit signal lines is performed;

[0082] By decomposing the vertical network, the connection between the units of the same network in different chip layers is cut off, and the detailed layout is converted into a two-dimensional detailed layout inside each chip layer;

[0083] Obtain the design requirements for voltage drop in integrated circuits and implement power supply networks;

[0084] Fill the gaps in the chip layout, perform physical verification and simulation testing on the chip layout based on the circuit usage of the integrated circuit, and export the integrated circuit layout design data that passes the test.

[0085] Reference Figure 2 As shown, preparing the layout and routing data of the integrated circuit and obtaining the gate-level netlist generated by the front-end chip design after synthesis specifically includes:

[0086] Output the connection relationship between the CPU, memory and subsystems as a system-level description of the gate-level netlist;

[0087] Output the connection relationship between hardware modules into an algorithmic description of a gate-level netlist using computer language;

[0088] The connection relationship between logic gates and triggers is output as a logic layer description of the gate-level netlist using Boolean equations;

[0089] The connection relationship between electronic components is output as a circuit layer description of the gate-level netlist using circuit differential equations;

[0090] The Boolean equations are: ,

[0091] In the formula, is the nth logic gate, is the sth trigger, is the mth feasible logic gate connection method, is the mth feasible trigger connection mode;

[0092] The circuit differential equation is: ,

[0093] In the formula, is the inductance value of the electronic component, is the resistance value of the electronic component, is the current value function of the electronic component, For time, is the power supply voltage, is the capacitance value of the electronic component, is the voltage value function of the electronic component, is the reciprocal resistance of electronic components, is the short circuit current.

[0094] The code that combines data flow and behavioral structure actually corresponds to the structural description of numerous arithmetic units, multiplexers, registers, etc., and these modules are actually composed of various logic gates (NAND gates, NOR gates, etc.) and basic triggers (D triggers, JK triggers, etc.). The process of logic synthesis is to further expand the circuit described in the file and convert it into a circuit built with logic gates and triggers. The file used to describe the connection relationship between these logic gates and triggers is the gate-level netlist file.

[0095] Reference Figure 3 As shown, based on the circuit usage of the integrated circuit, establishing the three-dimensional space and chip model of the integrated circuit specifically includes:

[0096] Determine the size parameters of the layout cube space of the integrated circuit based on the circuit usage of the integrated circuit;

[0097] Each electronic component is set as a small cube, and the ratio of the height of the layout cube to the number of chip layers is output as the vertical height of each electronic component;

[0098] The electronic components are evenly distributed in the space of the layout cube and output as a chip model.

[0099] Initialize the structural model of the electronic components and the integrated circuit, and disperse the positions of the electronic components so as to allocate the positions of the electronic components relative to the integrated circuit later.

[0100] Reference Figure 4 As shown, the nonlinear line length target and distribution target of each electronic component are unified into an objective function, and the nonlinear programming method is used to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic component, which specifically includes:

[0101] The total length of each layer of electronic components is calculated using the wire length model formula;

[0102] Preset a wire length parameter to optimize the wire network, and gradually reduce the wire length parameter, while optimizing the wire network after the wire length parameter is reduced;

[0103] Using the overlap formula, the overlap between the grid and the electronic components is calculated to evaluate the layout density;

[0104] Determine whether the layout density is lower than a preset threshold. If so, output the current layout as the overall layout. If not, re-layout;

[0105] The line length model formula is: ,

[0106] In the formula, is the total length of the electronic components in this layer, For adjustable line length parameters, is the length of the i-th electronic component in this layer, is the width of the i-th electronic component in this layer, is the total number of electronic components in this layer;

[0107] The overlap formula is: ,

[0108] In the formula, is the overlap between the k-th chip and the g-th cube, , , are the overlap between the ith electronic component on the kth layer chip and the gth cube in the x, y, and z directions, respectively.

[0109] The goal of the overall layout is to ensure the uniform distribution of the unit in the three-dimensional space while ensuring the optimal line length. The overall layout adopts a nonlinear programming unified modeling method, which unifies the nonlinear line length target of the unit and the distribution target of the unit into an objective function, and uses the nonlinear programming method to solve the minimum value of the objective function to obtain the spatial position distribution of the unit.

[0110] Reference Figure 5As shown, distributing the spatially uniformly distributed units on each chip layer specifically includes:

[0111] Arrange at least one electronic component in descending order of coordinates in the vertical direction, and scan each electronic component from bottom to top;

[0112] The default subspace level is N;

[0113] Divide each layer of chips into N*N subspaces;

[0114] Calculate the layered cost of each electronic component using the cost function;

[0115] Based on the layering cost of each electronic component in each layer of the chip, at least one electronic component is allocated to each layer of the chip;

[0116] The cost function is: ,

[0117] In the formula, is the delamination cost of electronic components, are respectively the first preset weight, the second preset weight and the third preset weight, is the number of vertical through holes, is the total area occupied by the electronic components in this layer, is the density of electronic components in the i-th subspace, is the subspace series.

[0118] The ultimate goal of three-dimensional layout is to distribute units to different chip layers. The result of the overall layout is the distribution of units in three-dimensional space. The position of the units is continuous in space, but ultimately the units need to be distributed to discrete chip layers. Therefore, layer allocation is to distribute the units that are continuously distributed in the vertical direction to discrete chip layers while meeting certain target requirements.

[0119] Reference Figure 6 As shown, by decomposing the vertical network, the connection between the units of the same network in different chip layers is cut off, and the detailed layout is converted into a two-dimensional detailed layout inside each chip layer, which specifically includes:

[0120] Cut off the connection between electronic components in different layers and decompose the wire net at the cut point into two wire nets;

[0121] A new soldering block is generated at the cut position and fixed on the chip layer;

[0122] The coordinates of the welding block are selected as the average values ​​of the horizontal coordinates and the vertical coordinates of all the electronic components included in the wire mesh;

[0123] Sort the electronic components horizontally according to their coordinate positions;

[0124] Place each electronic component on the left border of the row in turn, and modify the left border of the row to the right border of the current electronic component;

[0125] Set the movement cost to the movement amount of the electronic component;

[0126] Select the row with the lowest moving cost to place each electronic component.

[0127] After completing the layer allocation, the chip layer where the unit is located is determined, and then the detailed layout will be carried out. The main task of the detailed layout is to eliminate the overlap between units and optimize the line length. Through the wire network decomposition, the three-dimensional layout is converted into a two-dimensional detailed layout on each layer, so that the detailed layout of each layer becomes an independent layout that does not interfere with each other.

[0128] Further, based on the same inventive concept as the above-mentioned integrated circuit layout design method based on circuit usage, the present solution also proposes an integrated circuit layout design system based on circuit usage, including:

[0129] A data processing module, which is used to prepare the layout and routing data of the integrated circuit, obtain the gate-level netlist generated by the front-end chip design after synthesis, and establish a three-dimensional space and chip model of the integrated circuit based on the circuit usage of the integrated circuit;

[0130] A circuit layout module, the circuit layout module is used to unify the nonlinear line length target and distribution target of each electronic component into an objective function, use a nonlinear programming method to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic components, distribute the spatially uniformly distributed units on each chip layer, perform actual physical wiring connection processing of the integrated circuit signal line according to all connection relationships in the gate-level netlist, decompose the vertical line network to cut off the connection between the units of the same line network in different chip layers, and convert the detailed layout into a two-dimensional detailed layout inside each chip layer;

[0131] The circuit detection module is used to obtain the design requirements for voltage drop in the integrated circuit, realize the power supply network, fill the gaps in the chip layout, and perform physical verification and simulation testing on the chip layout based on the circuit usage of the integrated circuit, and export the integrated circuit layout design data that passes the test.

[0132] The data processing module specifically includes:

[0133] A data acquisition unit, the data acquisition unit is used to prepare the layout and routing data of the integrated circuit and obtain the gate-level netlist generated after the front-end chip design is synthesized;

[0134] A model building unit, the model building unit is used to build a three-dimensional space and chip model of the integrated circuit based on the circuit usage of the integrated circuit;

[0135] The circuit layout module specifically includes:

[0136] A global layout unit, wherein the global layout unit is used to unify the nonlinear line length target and the distribution target of each electronic component into an objective function, and use a nonlinear programming method to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic component;

[0137] A layer allocation unit, the layer allocation unit is used to distribute the spatially uniformly distributed units on each chip layer;

[0138] A physical wiring unit, the physical wiring unit is used to perform actual physical wiring connection processing of integrated circuit signal lines according to all connection relationships in the gate-level netlist;

[0139] A detailed layout unit, wherein the detailed layout unit is used to decompose the vertical line net to cut off the connection between the units of the same line net in different chip layers, and convert the detailed layout into a two-dimensional detailed layout inside each chip layer;

[0140] The circuit detection module specifically includes:

[0141] A power supply design unit, the power supply design unit is used to obtain the design requirements of the voltage drop in the integrated circuit and realize the power supply network;

[0142] A simulation test unit is used to fill the gaps in the chip layout, and to perform physical verification and simulation testing on the chip layout based on the circuit usage of the integrated circuit, and to derive the integrated circuit layout design data that passes the test.

[0143] Furthermore, the present solution also proposes a computer-readable storage medium on which a computer-readable program is stored. When the computer-readable program is called, the above-mentioned integrated circuit layout design method based on circuit usage is executed.

[0144] It is understandable that the storage medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; an optical medium, such as a DVD; or a semiconductor medium, such as a solid state drive (SSD).

[0145] In summary, the advantages of the present invention are: by designing the three-dimensional structure of the integrated circuit and utilizing the vertical interconnection between chips, the length of the interconnection lines between devices can be effectively shortened to avoid winding, thereby reducing the complexity and congestion of the connection, reducing the interconnection delay, reducing the density of the routing, and ensuring the safety and reliability of the circuit. At the same time, the three-dimensional circuit can also effectively improve the integration of transistors and reduce the circuit area and power consumption.

[0146] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention. These changes and improvements fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for designing integrated circuit layout based on circuit usage, characterized in that: include: Prepare the layout and routing data of the integrated circuit and obtain the gate-level netlist generated by the front-end chip design after synthesis; Based on the circuit usage of the integrated circuit, establish the three-dimensional space and chip model of the integrated circuit; The nonlinear line length target and distribution target of each electronic component are unified into an objective function, and a nonlinear programming method is used to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic components, wherein the electronic components include transistors, resistors and capacitors; Distribute spatially uniformly distributed cells on each chip layer; According to all the connection relationships in the gate-level netlist, actual physical wiring connection processing of the integrated circuit signal lines is performed; By decomposing the vertical network, the connection between the units of the same network in different chip layers is cut off, and the detailed layout is converted into a two-dimensional detailed layout inside each chip layer; Obtain the design requirements for voltage drop in integrated circuits and implement power supply networks; Fill the gaps in the chip layout, perform physical verification and simulation testing on the chip layout based on the circuit usage of the integrated circuit, and export the integrated circuit layout design data that has passed the test; The step of preparing the layout and routing data of the integrated circuit and obtaining the gate-level netlist generated after the front-end chip design is synthesized specifically includes: Output the connection relationship between the CPU, memory and subsystems as a system-level description of the gate-level netlist; Output the connection relationship between hardware modules into an algorithmic description of a gate-level netlist using computer language; The connection relationship between logic gates and triggers is output as a logic layer description of the gate-level netlist using Boolean equations; The connection relationship between electronic components is output as a circuit layer description of the gate-level netlist using circuit differential equations; The Boolean equations are: , In the formula, is the nth logic gate, is the sth trigger, is the mth feasible logic gate connection method, is the mth feasible trigger connection mode; The circuit differential equation is: , In the formula, is the inductance value of the electronic component, is the resistance value of the electronic component, is the current value function of the electronic component, For time, is the power supply voltage, is the capacitance value of the electronic component, is the voltage value function of the electronic component, is the reciprocal resistance of electronic components, is the short circuit current.

2. The integrated circuit layout design method based on circuit usage according to claim 1, characterized in that: The establishment of the three-dimensional space and chip model of the integrated circuit based on the circuit usage of the integrated circuit specifically includes: Determine the size parameters of the layout cube space of the integrated circuit based on the circuit usage of the integrated circuit; Each electronic component is set as a small cube, and the ratio of the height of the layout cube to the number of chip layers is output as the vertical height of each electronic component; The electronic components are evenly distributed in the space of the layout cube and output as a chip model.

3. The integrated circuit layout design method based on circuit usage according to claim 2, characterized in that: The nonlinear line length target and distribution target of each electronic component are unified into an objective function, and the nonlinear programming method is used to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic component, which specifically includes: The total length of each layer of electronic components is calculated using the wire length model formula; Preset a wire length parameter to optimize the wire network, and gradually reduce the wire length parameter, while optimizing the wire network after the wire length parameter is reduced; Using the overlap formula, the overlap between the grid and the electronic components is calculated to evaluate the layout density; Determine whether the layout density is lower than a preset threshold. If so, output the current layout as the overall layout. If not, re-layout; The line length model formula is: , In the formula, is the total length of the electronic components in this layer, For adjustable line length parameters, is the length of the i-th electronic component in this layer, is the width of the i-th electronic component in this layer, is the total number of electronic components in this layer; The overlap formula is: , In the formula, is the overlap between the k-th chip and the g-th cube, , , are the overlap between the ith electronic component on the kth layer chip and the gth cube in the x, y, and z directions, respectively.

4. The integrated circuit layout design method based on circuit usage according to claim 3, characterized in that: The step of distributing the spatially uniformly distributed units on each chip layer specifically includes: Arrange at least one electronic component in descending order of coordinates in the vertical direction, and scan each electronic component from bottom to top; The default subspace level is N; Divide each layer of chips into N*N subspaces; Calculate the layered cost of each electronic component using the cost function; Based on the layering cost of each electronic component in each layer of the chip, at least one electronic component is allocated to each layer of the chip; The cost function is: , In the formula, is the delamination cost of electronic components, are respectively the first preset weight, the second preset weight and the third preset weight, is the number of vertical through holes, is the total area occupied by the electronic components in this layer, is the density of electronic components in the i-th subspace, is the subspace series.

5. The integrated circuit layout design method based on circuit usage according to claim 4, characterized in that: The vertical network is decomposed to cut off the connection between the units of the same network in different chip layers, and the detailed layout is converted into a two-dimensional detailed layout inside each chip layer, which specifically includes: Cut off the connection between electronic components in different layers and decompose the wire net at the cut point into two wire nets; A new soldering block is generated at the cut position and fixed on the chip layer; The coordinates of the welding block are selected as the average values ​​of the horizontal coordinates and the vertical coordinates of all the electronic components included in the wire mesh; Sort the electronic components horizontally according to their coordinate positions; Place each electronic component on the left border of the row in turn, and modify the left border of the row to the right border of the current electronic component; Set the movement cost to the movement amount of the electronic component; Select the row with the lowest moving cost to place each electronic component.

6. An integrated circuit layout design system based on circuit usage, used to implement the integrated circuit layout design method based on circuit usage as claimed in any one of claims 1 to 5, characterized in that: include: A data processing module, which is used to prepare the layout and routing data of the integrated circuit, obtain the gate-level netlist generated by the front-end chip design after synthesis, and establish a three-dimensional space and chip model of the integrated circuit based on the circuit usage of the integrated circuit; A circuit layout module, the circuit layout module is used to unify the nonlinear line length target and distribution target of each electronic component into an objective function, use a nonlinear programming method to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic components, distribute the spatially uniformly distributed units on each chip layer, perform actual physical wiring connection processing of the integrated circuit signal line according to all connection relationships in the gate-level netlist, decompose the vertical line network to cut off the connection between the units of the same line network in different chip layers, and convert the detailed layout into a two-dimensional detailed layout inside each chip layer; The circuit detection module is used to obtain the design requirements for voltage drop in the integrated circuit, realize the power supply network, fill the gaps in the chip layout, and perform physical verification and simulation testing on the chip layout based on the circuit usage of the integrated circuit, and export the integrated circuit layout design data that passes the test.

7. The integrated circuit layout design system based on circuit usage according to claim 6, characterized in that: The data processing module specifically includes: A data acquisition unit, the data acquisition unit is used to prepare the layout and routing data of the integrated circuit and obtain the gate-level netlist generated after the front-end chip design is synthesized; A model building unit, the model building unit is used to build a three-dimensional space and chip model of the integrated circuit based on the circuit usage of the integrated circuit; The circuit layout module specifically includes: A global layout unit, wherein the global layout unit is used to unify the nonlinear line length target and the distribution target of each electronic component into an objective function, and use a nonlinear programming method to solve the minimum value of the objective function to obtain the spatial position distribution of the electronic component; A layer allocation unit, the layer allocation unit is used to distribute the spatially uniformly distributed units on each chip layer; A physical wiring unit, the physical wiring unit is used to perform actual physical wiring connection processing of integrated circuit signal lines according to all connection relationships in the gate-level netlist; A detailed layout unit, wherein the detailed layout unit is used to decompose the vertical line net to cut off the connection between the units of the same line net in different chip layers, and convert the detailed layout into a two-dimensional detailed layout inside each chip layer; The circuit detection module specifically includes: A power supply design unit, the power supply design unit is used to obtain the design requirements of the voltage drop in the integrated circuit and realize the power supply network; A simulation test unit is used to fill the gaps in the chip layout, and to perform physical verification and simulation testing on the chip layout based on the circuit usage of the integrated circuit, and to derive the integrated circuit layout design data that passes the test.

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