An optimized design method and apparatus for chip simulation verification

Abstract

This invention provides an optimization design method and apparatus for chip simulation verification. The method includes: generating candidate solutions based on the current solution during simulation verification of a target chip; performing simulated annealing calculations based on a preset algorithm cost function, the current solution, and the candidate solutions; determining whether to replace the current solution with a candidate solution; iteratively calculating until a termination condition is met to obtain the optimal constraint solution for the target chip; selecting at least one assertion from a preset assertion group; performing simulation based on at least one assertion and the optimal constraint solution to collect coverage data of external modules; if the collected coverage data is found to be insufficient, adjusting the initial solution based on the collected coverage data to optimize the obtained optimal constraint solution; adjusting at least one assertion selected from the assertion group; re-executing the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution to collect the adjusted coverage data of external modules until the coverage data meets the requirements.

Description

Technical Field

[0001] This invention relates to the field of chip simulation and verification technology, and in particular to an optimized design method and apparatus for chip simulation and verification. Background Technology

[0002] With the rapid development of semiconductor technology, the complexity and scale of chip design are constantly increasing, and the requirements for chip design verification are also becoming more stringent.

[0003] Before actual chip manufacturing, designers need to use simulation tools and techniques to evaluate the chip's performance and reliability, ensuring that the design meets expected functional and performance specifications. Chip simulation verification is a critical step in the chip design process, involving the use of computer software, models, and algorithms to simulate and analyze the accuracy and stability of the chip circuit design.

[0004] Traditional chip simulation and verification methods mainly rely on manually writing test cases or using automated tools to generate test data. These methods are effective for small-scale, simple chip designs, but as the design scale and complexity increase, these methods face the following challenges: constructing test cases that fully cover all possible execution paths becomes extremely difficult, especially in complex control or data flows. Summary of the Invention

[0005] This invention provides an optimized design method and apparatus for chip simulation verification, which solves the problem that the existing technology is difficult to achieve full coverage of complex design paths and data flows, resulting in potential blind spots in verification.

[0006] This invention provides an optimized design method for chip simulation verification, comprising:

[0007] During the simulation verification of the target chip, candidate solutions are generated based on the current solution, and simulated annealing calculations are performed based on the preset algorithm cost function, the current solution, and the candidate solutions to determine whether to replace the current solution with the candidate solution. The calculation is iterated until the termination condition is met to obtain the optimal constraint solution of the target chip.

[0008] At least one assertion is selected from a preset assertion group, and simulation is performed based on the selected at least one assertion and the optimal constraint solution to collect coverage data of external modules; wherein, the assertion has a corresponding binding relationship with the external module;

[0009] If the collected coverage data is found to be insufficient, the initial solution is adjusted based on the collected coverage data to optimize the obtained optimal constraint solution; wherein, the initial solution is the starting point for simulation verification of the target chip;

[0010] Adjust at least one assertion selected within the assertion group, re-execute the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution, and collect the adjusted coverage data of the external module until the coverage data meets the target.

[0011] According to the optimization design method for chip simulation verification provided by the present invention, candidate solutions are generated based on the current solution, and simulated annealing calculations are performed based on a preset algorithm cost function, the current solution, and the candidate solutions to determine whether to replace the current solution with a candidate solution. The calculations are iteratively performed until a termination condition is met to obtain the optimal constrained solution for the target chip. Specifically, the method includes:

[0012] Based on the preset algorithm cost function and the current solution, calculate the function value corresponding to the current solution;

[0013] Enable macro commands or call random embedded functions to randomly generate candidate solutions within the range of the current solution;

[0014] Based on the preset algorithm cost function and the candidate solutions, calculate the function value corresponding to the candidate solutions;

[0015] The function value corresponding to the current solution is compared with the function value corresponding to the candidate solution. If the function value corresponding to the candidate solution is less than the function value corresponding to the current solution, the current solution is replaced with the candidate solution.

[0016] If the function value corresponding to the candidate solution is greater than or equal to the function value corresponding to the current solution, calculate the acceptance probability corresponding to the candidate solution based on the function value corresponding to the candidate solution and the function value corresponding to the current solution, and generate a random number between 0 and 1. If the random number is less than the acceptance probability, replace the current solution with the candidate solution; if the random number is greater than or equal to the acceptance probability, retain the current solution.

[0017] Continue iteratively executing the step of randomly generating candidate solutions within the range of the current solution until the termination condition is met. The obtained current solution is taken as the optimal constraint solution of the target chip. The termination condition includes: reaching a specified number of iterations, the current solution remaining unchanged for multiple consecutive iterations, and the current solution reaching a set solution threshold.

[0018] According to the chip simulation verification optimization design method provided by the present invention, the algorithm cost function is used to calculate the algorithm cost based on the code coverage achieved by the amount of data generated by the current solution. The code coverage includes register flip coverage, digital design modeling code branch condition coverage, state machine state coverage, and design modeling code line coverage.

[0019] Based on the preset algorithm cost function and the current solution, the function value corresponding to the current solution is calculated, specifically including: obtaining the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the current solution; calculating the function value corresponding to the current solution based on the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the current solution.

[0020] According to the chip simulation verification optimization design method provided by the present invention, the receiving probability corresponding to the candidate solution is calculated based on the function value corresponding to the candidate solution and the function value corresponding to the current solution. Specifically, the method includes: determining the current temperature parameter, wherein the current temperature parameter is obtained by multiplying the previous temperature parameter by a decreasing coefficient; and calculating the receiving probability corresponding to the candidate solution based on the difference between the function value corresponding to the candidate solution and the function value corresponding to the current solution, and the current temperature parameter.

[0021] According to the chip simulation verification optimization design method provided by the present invention, simulation is performed based on the selected at least one assertion and the optimal constraint solution, and coverage data of external modules is collected. Specifically, the method includes: performing simulation based on the selected at least one assertion and the optimal constraint solution, and collecting assertion results of the external modules corresponding to the at least one assertion; wherein the assertions include external interface assertions, internal module assertions, bus assertions, memory assertions, and fan-in resource assertions, and the external modules include chip modeling external signal modules, internal functional modules, bus modules, memory modules, and combinational logic modules; and obtaining coverage data of external modules based on the assertion results; wherein the coverage data includes at least one of code coverage, assertion coverage, scene coverage, and path coverage.

[0022] According to the chip simulation verification optimization design method provided by the present invention, the simulation is re-executed based on at least one adjusted assertion and the optimized optimal constraint solution, and the coverage data of the adjusted external module is collected. Specifically, the method includes: increasing the number of random simulations and random seeds, and re-executing the simulation based on at least one adjusted assertion and the optimized optimal constraint solution, and collecting the coverage data of the external module corresponding to at least one adjusted assertion.

[0023] The present invention also provides an optimized design apparatus for chip simulation verification, comprising:

[0024] The simulated annealing calculation module is used to generate candidate solutions based on the current solution during the simulation verification of the target chip, and to perform simulated annealing calculation based on the preset algorithm cost function, the current solution and the candidate solutions to determine whether to replace the current solution with the candidate solution. The calculation is iterated until the termination condition is met to obtain the optimal constraint solution of the target chip.

[0025] The coverage data collection module is used to select at least one assertion from a preset assertion group, perform simulation based on the selected at least one assertion and the optimal constraint solution, and collect coverage data of the external module; wherein, the assertion has a corresponding binding relationship with the external module;

[0026] The initial solution adjustment module is used to adjust the initial solution based on the collected coverage data when it is determined that the coverage data collected does not meet the standard, so as to optimize the obtained optimal constraint solution; wherein, the initial solution is the starting point for simulation verification of the target chip;

[0027] The coverage data adjustment module is used to adjust at least one assertion selected within the assertion group, re-execute the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution, and collect the adjusted coverage data of the external module until the coverage data meets the standard.

[0028] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the optimized design method for chip simulation verification as described above.

[0029] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the optimized design method for chip simulation verification as described above.

[0030] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the optimized design method for chip simulation verification as described above.

[0031] The chip simulation verification optimization design method and apparatus provided by this invention automatically obtains the optimal constraint solution of the target chip using the simulated annealing algorithm. Simulation is performed based on at least one assertion and the optimal constraint solution to collect coverage data of external modules. The coverage data of external modules is collected through selected assertions. If the collected coverage data does not meet the standard, the initial solution and the selected assertions are adjusted to re-execute the simulation to collect coverage data until the coverage data meets the standard. Thus, the optimal constraint solution obtained by the simulated annealing algorithm is used to influence the subsequent simulation results, ensuring that the collected coverage data can fully cover all possible execution paths in the chip simulation verification process. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the simulation verification platform provided in an embodiment of the present invention.

[0034] Figure 2 This is one of the flowcharts of the optimized design method for chip simulation verification provided in the embodiments of the present invention.

[0035] Figure 3 This is the second flowchart of the optimized design method for chip simulation verification provided in this embodiment of the invention.

[0036] Figure 4 This is a schematic diagram of the external coverage collection module of the simulation verification platform according to an embodiment of the present invention.

[0037] Figure 5 This is a flowchart illustrating the method for collecting external coverage data provided in an embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of the structure of the optimized design device for chip simulation verification provided in an embodiment of the present invention.

[0039] Figure 7 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0041] In addition to the technical defects mentioned in the background section, traditional technical solutions also have the following technical defects:

[0042] 1) Real-time collection of coverage data is difficult, especially during hardware simulation. This requires capturing and recording coverage data without interfering with the normal operation of chip modeling. Furthermore, the amount of data collected in real-time is enormous, necessitating efficient storage and processing mechanisms.

[0043] 2) Accurately measuring coverage is another challenge. Besides code coverage (such as line coverage, branch coverage, etc.), other types of coverage need to be considered, such as feature coverage, scenario coverage, etc. These metrics need careful design to ensure they accurately reflect the verification status of the design.

[0044] To overcome the technical shortcomings of existing technologies that make it difficult to achieve comprehensive coverage of complex design paths and data flows, resulting in potential blind spots in verification, this invention automatically obtains the optimal constraint solution of the target chip through simulated annealing algorithm. Then, it collects coverage data of external modules through assertions. If the collected coverage data does not meet the standard, it adjusts the initial solution and the selected assertions to re-execute the simulation to collect coverage data until the coverage data meets the standard, thereby ensuring comprehensive coverage of the design path and data flow.

[0045] The following is combined Figures 1-5 This invention describes an optimized design method for chip simulation verification according to an embodiment of the present invention.

[0046] The method of this invention can model the behavior of a simulation platform based on the simulated annealing algorithm using SystemVerilog, realizing a high-efficiency verification platform that can converge quickly and collect data in real time. The design and implementation are presented in SystemVerilog. Based on the logical principles, this design proposes the implementation principles and implements the platform logic in SystemVerilog, verifying the feasibility of the scheme.

[0047] SystemVerilog is a hardware description and verification language built on top of Verilog. It combines concepts from Verilog, VHDL, and C++, along with verification platform and assertion languages, enhancing design modeling capabilities at a higher level of abstraction. Primarily focused on chip implementation and verification processes, it integrates object-oriented programming, dynamic threading, and inter-thread communication features. As an industry-standard language, SystemVerilog comprehensively integrates RTL design, test platforms, assertions, and coverage, providing robust support for system-level design and verification.

[0048] The Simulated Annealing Algorithm (SA) is a heuristic random search algorithm, whose design inspiration comes from the annealing process in physics, especially the annealing process of solid substances (such as metals). The Simulated Annealing Algorithm solves optimization problems by simulating the process of gradually cooling a solid after heating it to a sufficiently high temperature. During the operation of the algorithm, the Simulated Annealing Algorithm starts from a relatively high initial temperature. As the temperature gradually decreases, the algorithm randomly searches for the global optimal solution of the objective function in the solution space. At each temperature level, the algorithm repeats the iterative process of "generating a new solution → calculating the difference of the objective function → accepting or rejecting". If the objective function value of the new solution is better, the new solution is accepted; otherwise, it is decided whether to accept the new solution according to a certain probability, which is usually related to the relative magnitudes of the current temperature and the difference of the objective function.

[0049] The general steps of the search process of the Simulated Annealing Algorithm (taking the maximization as an example) can be shown by the following simple flowchart:

[0050] (1) Randomly generate a solution A and calculate the objective function value f(A) corresponding to solution A.

[0051] (2) Randomly generate a solution B near solution A and calculate the objective function value f(B) corresponding to solution B.

[0052] (3) If f(B) > f(A), then assign solution B to solution A, and then repeat the above steps in a loop iteration manner.

[0053] (4) If f(B) ≤ f(A), then calculate the probability P of accepting solution B t = e -|f(xj) –f(xi)*Ct , and then generate a random number r between [0, 1]. If r < p, replace solution A with solution B and repeat the above steps; otherwise, return to step (2), generate a random number A near the original solution A, and then perform step (3) and repeat the iteration.

[0054] The conditions for stopping the iteration: reaching the specified number of iterations, reaching the solution threshold, and the solution remaining unchanged for multiple consecutive times.

[0055] Chip front-end verification is an important part of the chip design process, which mainly focuses on verifying whether the chip design meets the predetermined specifications and requirements.

[0056] Coverage collection is an indispensable and important part of the verification work. Coverage refers to the degree of coverage of the design or implementation in the verification work, and it can evaluate the effect of the verification work by quantifying the progress of the verification and ensuring the completeness of the verification. The purpose of coverage collection is to understand the progress of the verification work and whether all design requirements and function points are covered.

[0057] Figure 1 The diagram shown is a schematic diagram of the simulation verification platform involved in an embodiment of the present invention.

[0058] Here, DUT (Device Under Test) refers to the device under test, which in this embodiment refers to the chip under test. The DUT is then connected to the simulation verification platform, and simulation verification begins.

[0059] driver: requests sequence_item (transaction) from sequencer and drives the information in the packet to the DUT port (through interface) according to the bus protocol.

[0060] The sequencer manages both sequence and driver requests. When the driver requests data and the sequence also sends a sequence_item request, the sequencer sends the sequence_item generated by the sequence to the driver.

[0061] sequence (not part of the verification platform): creates randomized transactions through the task body in the sequence, generates incentive content, and sends it to the sequencer.

[0062] Monitor: Receives data (including input and output) from the DUT, transforms it into transaction-level sequence items, sends the input data to the reference model to generate the expected results, and sends the output data to the scoreboard for comparison.

[0063] Reference model: Uses a high-level language to simulate the functionality of the DUT and generates expected results for the scoreboard to use as a judgment standard.

[0064] scoreboard: Receives data from the reference model and monitor, compares it, and determines whether the DUT function is correct.

[0065] The agent encapsulates the driver, sequencer, and monitor together, improving code reusability. The agent includes an enumeration parameter `is_active` (with two modes: `UVM_ACTIVE` and `UVM_PASSIVE`) to control the instantiated components. Agent-in and Agent-out correspond to...

[0066] env: Encapsulates the components on the verification platform together and configures the communication ports between the components to achieve the reusability of the verification environment. When running different test cases, you only need to instantiate env.

[0067] Verification platform such as Figure 1 As shown, UVM verification of randomness typically involves enabling the uvm-do macro command or directly calling the embedded random function assert.tr.randomize() when calling the sequence component, while simultaneously applying random constraints to obtain candidate solutions.

[0068] Figure 2 This is one of the flowcharts illustrating the optimized design method for chip simulation verification provided by this invention, such as... Figure 2 As shown, the method includes the following:

[0069] Step 201: During the simulation verification of the target chip, candidate solutions are generated based on the current solution, and simulated annealing calculations are performed based on the preset algorithm cost function, the current solution, and the candidate solutions to determine whether to replace the current solution with the candidate solution. The calculation is iterated until the termination condition is met to obtain the optimal constraint solution of the target chip.

[0070] The optimal constraint solution is the solution with the lowest algorithm cost, meaning that the solution can cover the critical path, and using this constraint solution can achieve a high code coverage rate.

[0071] Initially, a random initial solution is generated, or an empirically selected starting solution is chosen, as the starting point for simulation verification. Then, a pre-defined algorithmic cost function is used to evaluate the current solution, and its corresponding function value is calculated. This function value will be used for subsequent comparisons with candidate solutions.

[0072] Within the solution space of the current solution, a new candidate solution is generated through random perturbation or a specific strategy. The function value of the candidate solution is calculated using the same algorithmic cost function.

[0073] The function value of the current solution is then compared with the function values ​​of the candidate solutions to determine whether to replace the current solution with a candidate solution. The temperature parameter is then reduced according to the cooling scheme to prepare for the next iteration.

[0074] The algorithm determines whether the termination condition is met, such as reaching the maximum number of iterations, failing to accept new solutions multiple times consecutively, or the solution quality reaching a preset threshold. If the termination condition is not met, new candidate solutions are generated and evaluated. When the termination condition is met, the current solution is output as the optimal constraint solution, which is the optimal or near-optimal solution found during simulated annealing. The obtained optimal constraint solution is used in subsequent simulation verification steps to guide the generation of test vectors and the simulation process.

[0075] Step 202: Select at least one assertion from the preset assertion group, perform simulation based on the selected at least one assertion and the optimal constraint solution, and collect coverage data of external modules; wherein, the assertion has a corresponding binding relationship with the external module.

[0076] An assertion is a verification mechanism used in software engineering, hardware verification, and system design to ensure that a program or system behaves as expected under specific conditions. During the verification process, assertion coverage can serve as a metric for evaluating the comprehensiveness of the verification.

[0077] It should be noted that an assertion group contains multiple assertions, each of which is bound to a corresponding external module. Assertions include external interface assertions, internal module assertions, bus assertions, memory assertions, and fan-in resource assertions. External modules include chip modeling external signal modules, internal functional modules, bus modules, memory modules, and combinational logic modules.

[0078] Within a predefined set of assertions, at least one assertion is selected based on the characteristics of the optimal constraint solution. These assertions will be used to guide the verification of specific functions or paths during the simulation process.

[0079] The simulation process is executed using the optimal constraint solution as the initial condition. During the simulation, the selected assertions are applied to check whether the target chip behaves as expected.

[0080] During simulation, the results for each assertion are collected. This includes whether the assertion is satisfied, violated, or cannot be determined. Based on the assertion results, coverage data is generated. This data may include code coverage (such as line coverage, branch coverage, etc.), assertion coverage, scenario coverage, and path coverage.

[0081] The collected coverage data is analyzed to determine whether the validation objectives have been met. If the coverage data does not meet the standards, it is necessary to identify uncovered or insufficiently tested areas.

[0082] If certain critical paths or functionalities are found to be uncovered, it may be necessary to adjust or add assertions to allow for more comprehensive testing in subsequent simulations. After adjusting the assertions, re-run the simulation and collect coverage data again to verify the effectiveness of the adjustments.

[0083] Step 202 ensures that simulation verification is not only based on the optimal constraint solution, but also comprehensively tests and verifies the target chip design, thereby improving the quality and efficiency of verification. This process helps identify and fix potential problems, ensuring that the chip design meets all predetermined specifications and requirements before production.

[0084] Step 203: If the collected coverage data does not meet the standard, adjust the initial solution based on the collected coverage data to optimize the obtained optimal constraint solution.

[0085] The initial solution serves as the starting point for simulation verification of the target chip.

[0086] Review the collected coverage data to identify non-compliant areas, including uncovered or insufficiently covered lines of code, branches, and state machine states. Based on the coverage data, determine the initial solution parameters that need adjustment to improve the coverage of non-compliant areas. Decide on the adjustment strategy, which may include modifying simulation parameters, changing input stimuli, and optimizing the weights of the algorithm's cost function.

[0087] Adjusting the initial solution based on the strategy may involve modifying the test vectors, adjusting the simulation environment settings, or changing the algorithm's starting conditions.

[0088] If the adjustments affect the simulation model or test platform, update the corresponding components to reflect the new initial solution. Recalculate the algorithm's cost function using the updated initial solution to ensure that the adjusted solution still meets the cost-effectiveness requirements. Feed the adjusted initial solution back to the simulated annealing algorithm and restart the algorithm's iterative process. Based on the new initial solution, continue the iterative calculation of the simulated annealing algorithm to find a better constrained solution.

[0089] By implementing step 203, it can be ensured that the simulation verification process can not only discover potential coverage deficiencies, but also find solutions that meet all verification criteria through iterative optimization algorithms.

[0090] Step 204: Adjust at least one of the selected assertions in the assertion group, re-execute the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution, and collect the coverage data of the adjusted external module until the coverage data meets the standard.

[0091] Integrate the modified assertions into the simulation environment and ensure that all relevant components and bindings are updated.

[0092] To explore the solution space more comprehensively, it may be necessary to increase the number of stochastic simulations and vary the random seed to generate more diverse test vectors. Re-execute the simulation process using the updated assertions and simulation environment.

[0093] After re-running the simulation, collect and analyze the new coverage data to check whether the predetermined coverage standard has been met.

[0094] If the coverage data still does not fully meet the requirements, repeat the process in step 204 to continue adjusting the assertion and simulation parameters.

[0095] Through an iterative process, the assertion set is optimized to achieve more comprehensive coverage while reducing redundant or unnecessary assertions. Simulation performance is monitored during assertion tuning to ensure that added assertions do not negatively impact simulation efficiency.

[0096] By implementing step 204, the simulation verification process can be adaptively adjusted to achieve the goal of comprehensive coverage, thereby improving the verification quality and reliability of chip design.

[0097] The optimized design method for chip simulation verification provided in this invention uses a simulated annealing algorithm to automatically obtain the optimal constraint solution of the target chip. Simulation is performed based on at least one assertion and the optimal constraint solution to collect coverage data of external modules. The coverage data of external modules is collected through selected assertions. If the collected coverage data does not meet the standard, the initial solution and the selected assertions are adjusted to re-execute the simulation to collect coverage data until the coverage data meets the standard. Thus, the optimal constraint solution obtained by the simulated annealing algorithm is used to influence the subsequent simulation results, ensuring that the collected coverage data can fully cover all possible execution paths in the chip simulation verification process.

[0098] See Figure 3 Step 201 uses the simulated annealing algorithm to obtain the optimal constraint solution for the target chip, specifically including:

[0099] 300. Initialization Phase: Set various parameters, input various parameters for algorithm modeling, solution space of simulation constraints, initial value of design path, median of constraint solution space, coverage parameters, initial temperature, annealing coefficient, and initial solution.

[0100] 301. Based on the preset algorithm cost function and the current solution, calculate the function value corresponding to the current solution.

[0101] Step 301 includes: obtaining the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the current solution; and calculating the function value corresponding to the current solution based on the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the current solution.

[0102] Code coverage includes register toggle coverage, digital design modeling code branch condition coverage, state machine state coverage, and design modeling code line coverage.

[0103] Register toggle coverage: measures the coverage of register state changes during simulation.

[0104] Digital design modeling code branch condition coverage: measures the coverage of different branch paths in simulation.

[0105] State machine state coverage: measures the coverage of each state of a state machine.

[0106] Design modeling code line coverage: measures whether each line of code in the code is executed.

[0107] Specifically, the code coverage is calculated using the following formula (1):

[0108] (1)

[0109] Where f(x) is the algorithm cost calculation, the lower the cost, the better the verification effect;

[0110] c(x) is the score for the covered hardware design path;

[0111] Code coverage is achieved by using the amount of data generated through constraints. 0~ 3 represents the weight of each coverage level; For register toggle coverage; Digital design modeling code branch condition coverage, This refers to the state machine's state coverage. Design modeling code line coverage;

[0112] This is a fixed parameter for cost calculation; it is configurable and defaults to 1.

[0113] Analyze the correlation between the amount of data generated by the current solution and various code coverage metrics to determine their impact on algorithm cost. Combine hardware design path scoring and code coverage, use the algorithm cost function to calculate the function value of the current solution. Analyze the calculated function value to evaluate the quality of the current solution. The lower the function value, the lower the algorithm cost and the higher the coverage of the current solution.

[0114] Based on the evaluation results of the function values, adjust the algorithm parameters, such as simulation inputs and constraints, to optimize algorithm performance.

[0115] 302. Enable macro commands or call random embedded functions to randomly generate candidate solutions within the range of the current solution.

[0116] In this step, the uvm-do macro command is enabled or the built-in random function assert.tr.randomize() is called directly to randomly generate candidate solutions within the range of the current solution.

[0117] The range of the current solution can be a preset range. For example, the goal of a task is to find the minimum value within a certain interval [0, 100], and the current solution is x=50. A fixed range can be set, such as ±5, so that candidate solutions will be randomly generated between 45 and 55.

[0118] 303. Based on the preset algorithm cost function and the candidate solution, calculate the function value corresponding to the candidate solution.

[0119] Step 303 includes: obtaining the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the candidate solution; and calculating the function value corresponding to the candidate solution based on the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the candidate solution.

[0120] The calculation method for candidate solutions is the same as that for the current solution, so it will not be repeated here.

[0121] 304. Compare the function value corresponding to the current solution with the function value corresponding to the candidate solution.

[0122] 305. If the function value corresponding to the candidate solution is less than the function value corresponding to the current solution, replace the current solution with the candidate solution.

[0123] 306. If the function value corresponding to the candidate solution is greater than or equal to the function value corresponding to the current solution, calculate the acceptance probability corresponding to the candidate solution based on the function value corresponding to the candidate solution and the function value corresponding to the current solution, and generate a random number between 0 and 1. If the random number is less than the acceptance probability, replace the current solution with the candidate solution; if the random number is greater than or equal to the acceptance probability, retain the current solution.

[0124] Step 306 calculates the reception probability corresponding to the candidate solution based on the function value corresponding to the candidate solution and the function value corresponding to the current solution. Specifically, this includes: determining the current temperature parameter, wherein the current temperature parameter is obtained by multiplying the previous temperature parameter by a decreasing coefficient; and calculating the reception probability corresponding to the candidate solution based on the difference between the function value corresponding to the candidate solution and the function value corresponding to the current solution, and the current temperature parameter.

[0125] Specifically, see the following formula (2):

[0126]

[0127] (2)

[0128] in, The previous temperature parameter,

[0129] P is the probability of acceptance;

[0130] This is the cooling factor, also known as the decreasing coefficient, used to improve search efficiency and reduce algorithm time. It can be set to 0.95 or 0.99, depending on the number of iterations acceptable to the simulation platform.

[0131] T is the initial temperature, which can be set to 100;

[0132] f(B) and f(A) are the function values ​​corresponding to the candidate solutions and the current solution, respectively.

[0133] 307. Continue iteratively executing the step of randomly generating candidate solutions within the range of the current solution until the termination condition is met, and take the obtained current solution as the optimal constraint solution of the target chip.

[0134] The termination conditions include: reaching a specified number of iterations, the current solution remaining unchanged for multiple consecutive iterations, and the current solution reaching a set solution threshold.

[0135] Within the range of the current solution, new candidate solutions are generated using macro commands or randomized embedded functions. This step is the core of the algorithm's exploration of the solution space.

[0136] For each newly generated candidate solution, its corresponding function value is calculated using a pre-defined algorithm cost function and compared with the function value of the current solution. If the function value of the candidate solution is better than that of the current solution, the candidate solution is accepted as the new current solution; if the function value of the candidate solution is not better than that of the current solution, the acceptance probability is calculated, and a random number in the range [0,1] is generated. The decision on whether to accept the candidate solution is based on the probability.

[0137] Update the current temperature parameters based on the cooling scheme. The temperature parameters typically decrease gradually with increasing iteration count.

[0138] At the end of each iteration, check whether the termination condition is met, and record the current solution, candidate solutions, function values ​​and temperature parameters for each iteration to analyze the convergence and search efficiency of the algorithm.

[0139] Furthermore, during the iteration process, the convergence of the algorithm is monitored to ensure that the algorithm can find the optimal or near-optimal solution within a reasonable number of iterations.

[0140] Through iterative processes, the algorithm continuously explores the solution space, attempting to escape local optima and find the global optimum.

[0141] Steps 300-307 ensure that the simulated annealing algorithm systematically explores the solution space while effectively balancing exploration and utilization during the search for the optimal constraint solution, ultimately achieving algorithm convergence and determining the optimal solution. This process helps improve the quality and efficiency of chip simulation verification, ensuring that the design meets the expected functional and performance specifications.

[0142] Specifically, see Figure 4 , Figure 4 The diagram shows the external coverage collection module of the simulation verification platform described in this embodiment. Coverage is collected using assertions; the core consists of the assertion part and the internal module mapping part; the interface of the assertion group is linked to the internal mapping module group using the bind method.

[0143] The assertions include external interface assertions, internal module assertions, bus assertions, memory assertions, and fan-in resource assertions. The external modules include chip modeling external signal modules, internal functional modules, bus modules, memory modules, and combinational logic modules.

[0144] Specifically, External Interface Assertions: These assertions are used to verify whether the interface between the chip and an external system interacts correctly according to a predetermined protocol. If the chip has an SPI interface for data transmission, assertions can be set to check whether the SPI clock and data signals are synchronized.

[0145] Internal Module Assertions: These are used to check whether the functions of various modules within the chip are working properly, such as processing units and arithmetic logic units. Setting an assertion for the multiplication module of a processor ensures that all multiplication operations are completed within the expected time.

[0146] Bus Assertions: These assertions are used to verify the correctness of data transmission on the chip's internal buses, including the address bus and data bus. Assertions are set on the system bus to ensure that no bus conflicts or erroneous data transmissions occur.

[0147] Memory assertions: Used to ensure the correctness of memory read and write operations, including cache coherency and memory access permissions. Assertions are set on the chip's on-chip memory to check whether memory write and read operations conform to the expected data patterns.

[0148] Fan-in Resource Assertions: These assertions are used to verify the effect of multiple input signals on a single logic unit, ensuring that the logic unit can correctly process multiple inputs. Setting an assertion on a logic gate with multiple inputs ensures that the output conforms to the logical function under all possible input combinations.

[0149] Specifically, the workflow of this design method is as follows: First, through the modeling and algorithm execution processes described earlier in this paper, the algorithm calculates the optimal constraint solution for the target chip. Figure 4 The assertion groups and bind links of the shown modules are used to select assertions, and then the simulation step begins. After the simulation is completed, the assertion results are collected, and various coverage data are obtained through EDA tools. Part of the coverage data is collected and fed back to the algorithm calculation step to change the initial values ​​in order to achieve the goal of optimizing the solution. Part of the coverage data is fed back to the assertion selection step to update the modules in the assertion group and the mapping group that are not covered. At the same time, it is determined whether the overall coverage meets the standard. If it does not meet the standard, the number of random simulations and the random seed are increased, and the simulation step is re-entered until the coverage meets the standard.

[0150] For details, please refer to [link / document / etc.]. Figure 5 Correspondingly, step 202 specifically includes: selecting at least one assertion in a preset assertion group, performing simulation based on the selected at least one assertion and the optimal constraint solution, collecting assertion results of the external modules corresponding to the at least one assertion, and obtaining coverage data of the external modules based on the assertion results.

[0151] Coverage data includes at least one of code coverage, assertion coverage, scenario coverage, and path coverage.

[0152] Step 204 specifically includes: increasing the number of random simulations and the random seed, and re-executing the simulation based on at least one adjusted assertion and the optimized optimal constraint solution, and collecting the coverage data of the external modules corresponding to at least one adjusted assertion.

[0153] The method of this invention further achieves the following technical effects:

[0154] 1) The simulated annealing algorithm is adopted to intelligently select random constraints of the verification platform, thereby covering the design path and data flow, selecting the optimal path and data flow, reducing manpower and material consumption, and improving efficiency.

[0155] 2) Coverage is collected in real time through an external coverage collection module without interfering with the chip, and the collected data is stored in external storage.

[0156] 3) Existing technologies use dedicated EDA tools to measure code coverage, such as VCS and URG. However, there are various types of coverage, such as functional coverage and scenario coverage. Due to the significant differences between different chip projects, there is no unified EDA or method for measurement. The method in this embodiment utilizes the results of simulated annealing algorithm, combined with functional and scenario verification principles, to perform coverage statistics.

[0157] The following describes the optimized design apparatus for chip simulation verification provided in the embodiments of the present invention. The optimized design apparatus for chip simulation verification described below and the optimized design method for chip simulation verification described above can be referred to in correspondence with each other.

[0158] This invention provides an optimized design apparatus for chip simulation and verification. (See attached image.) Figure 6 ,include:

[0159] The simulated annealing calculation module 601 is used to generate candidate solutions based on the current solution during the simulation verification of the target chip, and to perform simulated annealing calculation based on the preset algorithm cost function, the current solution and the candidate solutions to determine whether to replace the current solution with the candidate solution, and to iterate the calculation until the termination condition is met to obtain the optimal constraint solution of the target chip.

[0160] The coverage data collection module 602 is used to select at least one assertion from a preset assertion group, perform simulation based on the selected at least one assertion and the optimal constraint solution, and collect coverage data of the external module; wherein, the assertion has a corresponding binding relationship with the external module;

[0161] The initial solution adjustment module 603 is used to adjust the initial solution based on the collected coverage data when it is determined that the collected coverage data does not meet the standard, so as to optimize the obtained optimal constraint solution; wherein, the initial solution is the starting point for simulation verification of the target chip;

[0162] The coverage data adjustment module 604 is used to adjust at least one assertion selected within the assertion group, re-execute the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution, and collect the adjusted coverage data of the external module until the coverage data meets the standard.

[0163] Optionally, the simulated annealing calculation module 601 is specifically used for: calculating the function value corresponding to the current solution based on the preset algorithm cost function and the current solution; enabling macro commands or calling random embedded functions to randomly generate candidate solutions within the range of the current solution; calculating the function value corresponding to the candidate solution based on the preset algorithm cost function and the candidate solution; comparing the function value corresponding to the current solution and the function value corresponding to the candidate solution; if the function value corresponding to the candidate solution is less than the function value corresponding to the current solution, replacing the current solution with the candidate solution; if the function value corresponding to the candidate solution is greater than or equal to the function value corresponding to the current solution... The receiving probability of the candidate solution is calculated based on the function value corresponding to the candidate solution and the function value corresponding to the current solution. A random number between 0 and 1 is generated. If the random number is less than the receiving probability, the current solution is replaced with the candidate solution. If the random number is greater than or equal to the receiving probability, the current solution is retained. The step of randomly generating candidate solutions within the range of the current solution is continued iteratively until the termination condition is met. The obtained current solution is taken as the optimal constraint solution of the target chip. The termination condition includes: reaching a specified number of iterations, the current solution remaining unchanged for multiple consecutive iterations, and the current solution reaching a set solution threshold.

[0164] Optionally, the algorithm cost function is used to calculate the algorithm cost based on the code coverage achieved by the amount of data generated by the current solution. The code coverage includes register flip coverage, digital design modeling code branch condition coverage, state machine state coverage, and design modeling code line coverage.

[0165] The simulated annealing calculation module 601 is specifically used for: obtaining the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the current solution; and calculating the function value corresponding to the current solution based on the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the current solution.

[0166] Optionally, the simulated annealing calculation module 601 is specifically used to: determine the current temperature parameter, wherein the current temperature parameter is obtained by multiplying the previous temperature parameter by a decreasing coefficient; and calculate the acceptance probability corresponding to the candidate solution based on the difference between the function value corresponding to the candidate solution and the function value corresponding to the current solution, and the current temperature parameter.

[0167] Optionally, the coverage data collection module 602 is specifically used for: performing simulation based on the selected at least one assertion and the optimal constraint solution, and collecting assertion results of the external modules corresponding to the at least one assertion; wherein the assertions include external interface assertions, internal module assertions, bus assertions, memory assertions, and fan-in resource assertions, and the external modules include chip modeling external signal modules, internal functional modules, bus modules, memory modules, and combinational logic modules; obtaining coverage data of the external modules based on the assertion results; wherein the coverage data includes at least one of code coverage, assertion coverage, scene coverage, and path coverage.

[0168] Optionally, the coverage data adjustment module 604 is specifically used to: increase the number of random simulations and the random seed, and re-execute the simulation based on at least one adjusted assertion and the optimized optimal constraint solution, and collect the coverage data of the external module corresponding to at least one adjusted assertion.

[0169] The optimized design apparatus for chip simulation verification provided in this embodiment of the invention uses a simulated annealing algorithm to automatically obtain the optimal constraint solution of the target chip. It performs simulation based on at least one assertion and the optimal constraint solution, collects coverage data of external modules, and collects the coverage data of external modules through selected assertions. If the collected coverage data does not meet the standard, the initial solution and the selected assertions are adjusted to re-execute the simulation to collect coverage data until the coverage data meets the standard. In this way, the optimal constraint solution obtained by the simulated annealing algorithm is used to influence the subsequent simulation results, ensuring that the collected coverage data can fully cover all possible execution paths in the chip simulation verification process.

[0170] Figure 7 Example: A schematic diagram of the physical structure of an electronic device, such as... Figure 7As shown, the electronic device may include: a processor 710, a communications interface 720, a memory 730, and a communications bus 740, wherein the processor 710, the communications interface 720, and the memory 730 communicate with each other through the communications bus 740. The processor 710 can call logic instructions in the memory 730 to execute an optimized design method for chip simulation verification, including: during the simulation verification of the target chip, generating candidate solutions based on the current solution, and performing simulated annealing calculations based on a preset algorithm cost function, the current solution, and the candidate solutions to determine whether to replace the current solution with a candidate solution, iterating until the termination condition is met to obtain the optimal constraint solution of the target chip; selecting at least one assertion in a preset assertion group, performing simulation based on the selected at least one assertion and the optimal constraint solution, and collecting coverage data of external modules; wherein the assertions have a corresponding binding relationship with the external modules; if it is determined that the collected coverage data does not meet the standard, adjusting the initial solution based on the collected coverage data to optimize the obtained optimal constraint solution; adjusting at least one assertion selected in the assertion group, re-executing the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution, and collecting the adjusted coverage data of the external modules until the coverage data meets the standard.

[0171] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0172] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the optimized design method for chip simulation verification provided by the above methods, including: during the simulation verification of the target chip, generating candidate solutions based on the current solution, and performing simulated annealing calculations based on a preset algorithm cost function, the current solution, and the candidate solutions to determine whether to replace the current solution with a candidate solution, iterating until the termination condition is met to obtain the optimal constraint solution of the target chip; selecting at least one assertion in a preset assertion group, performing simulation based on the selected at least one assertion and the optimal constraint solution, and collecting coverage data of external modules; wherein the assertion has a corresponding binding relationship with the external module; if it is determined that the collected coverage data does not meet the standard, adjusting the initial solution based on the collected coverage data to optimize the obtained optimal constraint solution; adjusting at least one assertion selected in the assertion group, re-executing the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution, and collecting the adjusted coverage data of the external modules until the coverage data meets the standard.

[0173] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements an optimized design method for chip simulation verification provided by the above methods, comprising: during the simulation verification of a target chip, generating candidate solutions based on the current solution, and performing simulated annealing calculations based on a preset algorithm cost function, the current solution, and the candidate solutions to determine whether to replace the current solution with a candidate solution, iterating until a termination condition is met to obtain the optimal constraint solution of the target chip; selecting at least one assertion in a preset assertion group, performing simulation based on the selected at least one assertion and the optimal constraint solution, and collecting coverage data of external modules; wherein the assertions have a corresponding binding relationship with the external modules; if it is determined that the collected coverage data does not meet the standard, adjusting the initial solution based on the collected coverage data to optimize the obtained optimal constraint solution; adjusting at least one assertion selected in the assertion group, re-executing the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution, and collecting the adjusted coverage data of the external modules until the coverage data meets the standard.

[0174] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0175] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0176] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An optimized design method for chip simulation verification, characterized in that, include: During the simulation verification of the target chip, candidate solutions are generated based on the current solution, and simulated annealing calculations are performed based on the preset algorithm cost function, the current solution, and the candidate solutions to determine whether to replace the current solution with the candidate solution. The calculation is iterated until the termination condition is met to obtain the optimal constraint solution of the target chip. At least one assertion is selected from a preset assertion group, and simulation is performed based on the selected at least one assertion and the optimal constraint solution to collect coverage data of external modules; wherein, the assertion has a corresponding binding relationship with the external module; If the collected coverage data is found to be insufficient, the initial solution is adjusted based on the collected coverage data to optimize the obtained optimal constraint solution; wherein, the initial solution is the starting point for simulation verification of the target chip; Adjust at least one assertion selected within the assertion group, re-execute the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution, and collect the adjusted coverage data of the external module until the coverage data meets the target. The algorithm cost function is used to calculate the algorithm cost based on the code coverage achieved by the amount of data generated by the current solution. The code coverage includes register flip coverage, digital design modeling code branch condition coverage, state machine state coverage, and design modeling code line coverage. Based on the preset algorithm cost function and the current solution, the function value corresponding to the current solution is calculated, specifically including: Obtain the hardware design path score covered by the current solution and the code coverage achieved by the amount of data generated by the current solution; The function value corresponding to the current solution is calculated based on the hardware design path score covered by the current solution and the code coverage achieved by the amount of data generated by the current solution. The following formula is used to calculate code coverage: ； Where f(x) is the algorithm cost calculation, the lower the cost, the better the verification effect; c(x) is the score for the covered hardware design path; Code coverage is achieved by using the amount of data generated through constraints. The weight for each coverage level; For register toggle coverage; Modeling code branch condition coverage for digital design This refers to the state machine's state coverage. To model code line coverage for design; This is a fixed parameter for cost calculation; it is configurable and defaults to 1.

2. The optimized design method for chip simulation verification according to claim 1, characterized in that, Candidate solutions are generated based on the current solution, and simulated annealing is performed based on the preset algorithm cost function, the current solution, and the candidate solutions to determine whether to replace the current solution with a candidate solution. The calculation is iterated until the termination condition is met to obtain the optimal constraint solution of the target chip, specifically including: Enable macro commands or call random embedded functions to randomly generate candidate solutions within the range of the current solution; Based on the preset algorithm cost function and the candidate solutions, calculate the function value corresponding to the candidate solutions; The function value corresponding to the current solution is compared with the function value corresponding to the candidate solution. If the function value corresponding to the candidate solution is less than the function value corresponding to the current solution, the current solution is replaced with the candidate solution. If the function value corresponding to the candidate solution is greater than or equal to the function value corresponding to the current solution, calculate the acceptance probability corresponding to the candidate solution based on the function value corresponding to the candidate solution and the function value corresponding to the current solution, and generate a random number between 0 and 1. If the random number is less than the acceptance probability, replace the current solution with the candidate solution; if the random number is greater than or equal to the acceptance probability, retain the current solution. Continue iteratively executing the step of randomly generating candidate solutions within the range of the current solution until the termination condition is met. The obtained current solution is taken as the optimal constraint solution of the target chip. The termination condition includes: reaching a specified number of iterations, the current solution remaining unchanged for multiple consecutive iterations, and the current solution reaching a set solution threshold.

3. The optimized design method for chip simulation verification according to claim 2, characterized in that, The receiving probability of the candidate solution is calculated based on the function value corresponding to the candidate solution and the function value corresponding to the current solution, specifically including: Determine the current temperature parameter, wherein the current temperature parameter is obtained by multiplying the previous temperature parameter by a decrease factor; The receiving probability corresponding to the candidate solution is calculated based on the difference between the function value corresponding to the candidate solution and the function value corresponding to the current solution, as well as the current temperature parameter.

4. The optimized design method for chip simulation verification according to claim 1, characterized in that, Simulations are performed based on the selected at least one assertion and the optimal constraint solution, collecting coverage data for external modules, specifically including: Simulations are performed based on the selected at least one assertion and the optimal constraint solution, and assertion results of the external modules corresponding to the at least one assertion are collected; wherein, the assertions include external interface assertions, internal module assertions, bus assertions, memory assertions and fan-in resource assertions, and the external modules include chip modeling external signal modules, internal functional modules, bus modules, memory modules and combinational logic modules; The coverage data of the external module is obtained based on the assertion results; wherein the coverage data includes at least one of code coverage, assertion coverage, scenario coverage, and path coverage.

5. The optimized design method for chip simulation verification according to claim 1, characterized in that, The simulation is re-executed based on at least one adjusted assertion and the optimized optimal constraint solution, and the coverage data of the adjusted external module is collected, specifically including: Increase the number of random simulations and the random seed, and re-execute the simulation based on at least one adjusted assertion and the optimized optimal constraint solution, and collect the coverage data of the external modules corresponding to at least one adjusted assertion.

6. An optimized design apparatus for chip simulation verification, characterized in that, include: The simulated annealing calculation module is used to generate candidate solutions based on the current solution during the simulation verification of the target chip, and to perform simulated annealing calculation based on the preset algorithm cost function, the current solution and the candidate solutions to determine whether to replace the current solution with the candidate solution. The calculation is iterated until the termination condition is met to obtain the optimal constraint solution of the target chip. The coverage data collection module is used to select at least one assertion from a preset assertion group, perform simulation based on the selected at least one assertion and the optimal constraint solution, and collect coverage data of the external module; wherein, the assertion has a corresponding binding relationship with the external module; The initial solution adjustment module is used to adjust the initial solution based on the collected coverage data when it is determined that the coverage data collected does not meet the standard, so as to optimize the obtained optimal constraint solution; wherein, the initial solution is the starting point for simulation verification of the target chip; The coverage data adjustment module is used to adjust at least one assertion selected within the assertion group, re-execute the simulation based on the adjusted at least one assertion and the optimized optimal constraint solution, and collect the adjusted coverage data of the external module until the coverage data meets the standard. The algorithm cost function is used to calculate the algorithm cost based on the code coverage achieved by the amount of data generated by the current solution. The code coverage includes register flip coverage, digital design modeling code branch condition coverage, state machine state coverage, and design modeling code line coverage. The simulated annealing calculation module is used to calculate the function value corresponding to the current solution based on the preset algorithm cost function and the current solution, specifically including: Obtain the hardware design path score covered by the current solution and the code coverage achieved by the amount of data generated by the current solution; The function value corresponding to the current solution is calculated based on the hardware design path score covered by the current solution and the code coverage achieved by the amount of data generated by the current solution. The following formula is used to calculate code coverage: ； Where f(x) is the algorithm cost calculation, the lower the cost, the better the verification effect; c(x) is the score for the covered hardware design path; Code coverage is achieved by using the amount of data generated through constraints. The weight for each coverage level; For register toggle coverage; Modeling code branch condition coverage for digital design This refers to the state machine's state coverage. To model code line coverage for design; This is a fixed parameter for cost calculation; it is configurable and defaults to 1.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the optimized design method for chip simulation verification as described in any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the optimized design method for chip simulation verification as described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the optimized design method for chip simulation verification as described in any one of claims 1 to 5.

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