Chip verification method and device for automatic log analysis and feature extraction

Abstract

The invention discloses a chip verification method and device for automatic log analysis and feature extraction, and the method comprises the steps: log data analysis and feature extraction based on a UVM, log collection, obtaining of original data and preprocessing, learning of feature vectors through a machine learning method, and log anomaly detection based on chip verification. A model is established according to the abnormality type reason of each log file in a data set used during training, log multi-type abnormality diagnosis based on chip verification is performed, and personalized model updating based on incremental learning is performed. According to the method, in the field of bug detection and positioning, the semi-structured simulation log file is used as input, and through research in the aspects of log data analysis and feature extraction, log anomaly detection, log multi-type anomaly diagnosis, personalized model updating and optimization and the like, verification developers can timely and rapidly repair the bug, and the labor cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a chip verification method and device for automated log parsing and feature extraction. Background Art

[0002] Chip Verification refers to the verification of whether the chip works correctly according to the design requirements and specifications through various methods and tools after the chip design is completed. The purpose of verification is to ensure that the logical function, performance, interface, timing and other aspects of the chip meet the design expectations. However, with the increasing complexity of chip design, the time and resource proportion used for the verification stage on each generation of chips are increasing. The growth rate of the verification stage work exceeds that of other stages of the chip development project, and it faces more and more challenges, especially when dealing with UVM (Universal Verification Methodology) logs.

[0003] However, in the actual verification process, due to the large-scale and heterogeneous nature of UVM logs and the non-uniform format, the verification team must check the UVM logs and debug the causes of failure every time a regression fails. The log data is not labeled, making log parsing and feature extraction extremely difficult.

[0004] Existing chip verification log classification methods, such as a chip verification method and device, electronic device, and storage medium disclosed in publication number CN114357918A, use scripts to verify test cases and traverse all test case directories. First, check whether the simulation log contains the keyword "PASSED" to determine whether the case has passed. Then count the number of passed case studies and record the number of passed case studies. For failed case studies, extract the error information in the simulation log and classify it. Classify the error information, count the number of case studies for each type of error, and finally calculate the total pass rate. Sort the severity of the error type according to the number of case studies for each type of error.

[0005] The above technical solution improves the degree of automation to a certain extent, but still requires manual definition of classification rules, lacking flexibility and adaptability. In addition, the maintenance cost is high, and the script needs to be regularly maintained and updated. In particular, when the test case or error type changes, the script method is difficult to expand and optimize. In view of this, the present invention proposes a chip verification method for automated log parsing and feature extraction. Summary of the invention

[0006] In view of the deficiencies of the prior art, the present invention provides a chip verification method and device for automated log parsing and feature extraction, which solves the problem in the prior art that the chip verification process consumes a lot of time and resources.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions: a chip verification method for automated log parsing and feature extraction, comprising the following steps:

[0008] S1: Log collection, obtaining raw data and preprocessing it to remove invalid information from the log data, including duplicate information and useless information;

[0009] S2: Anomaly detection mainly uses machine learning methods to learn feature vectors and generate an anomaly detection model;

[0010] S3: Multi-type anomaly diagnosis, which builds a model based on the anomaly type causes of each log file in the dataset used during training. The input is the simulated log file, and the corresponding output is the root cause of the test failure.

[0011] S4: Update and optimize models for different users, explore incremental learning methods, enable trained models to accept new data sets and labels, and train and adjust based on existing models.

[0012] Preferably, the S1 log data parsing and feature extraction based on UVM includes:

[0013] S1.1: Analyze the log structure and information, and obtain the log template for each event;

[0014] S1.2: For the situation where all UVM_INFO, UVM_WARNING, UVM_ERROR and UVM_FATAL are mixed in the UVM log file, extract meaningful features accordingly.

[0015] Preferably, the machine learning algorithms involved in the log anomaly detection based on chip verification in S2 include cluster analysis, decision tree, and deep learning, and the step of establishing an abnormal information detection model through the machine learning algorithm includes:

[0016] S2.1: Convert the extracted log characteristic information into feature vectors for processing by machine learning algorithms;

[0017] S2.2: Using the extracted feature vectors and known normal and abnormal log data, train an anomaly detection model, and distinguish normal and abnormal behaviors through the established anomaly detection model;

[0018] S2.3: Evaluate the accuracy and generalization ability of the model through cross-validation and data confidence scoring methods, and optimize the model iteratively based on the evaluation results.

[0019] Preferably, in the multi-type anomaly diagnosis of logs based on chip verification in S3, the anomaly information detection model established in S2 is mainly used to analyze the causes of anomalies in the simulated log files in the data set files used in the training process, and an anomaly judgment model is established based on this, in which the input is the simulated log file and the output is the root cause of the test failure.

[0020] Preferably, the S4 is used to explore the incremental learning method in the personalized model update based on incremental learning, and includes the following steps:

[0021] S4.1: Use the trained model as a starting point and import the learning model used on the old dataset;

[0022] S4.2: Modularize the model data according to its algorithmic characteristics, and support data adjustment and reorganization of the modular data after splitting;

[0023] S4.3: Design new models and interfaces, and support users to adjust labels in a customized way within a certain range.

[0024] Preferably, in the extraction of characteristic information from the log S1.2, string matching and hash function processing are used to compare hash values ​​of the information, and for information with the same hash value, timestamp judgment is used for auxiliary judgment.

[0025] Preferably, confidence data is used in the S2.3 process to determine the accuracy and generalization ability of the model. First, it is necessary to define a probability number as a confidence scoring standard. At the same time, the confidence judgment result is divided into three groups of judgment ranges, namely "credible", "questionable data", and "abnormal data", and their range intervals are defined. After the confidence data is obtained through actual calculation, the judgment conclusion is output according to the defined result interval.

[0026] Preferably, in the S3 based on the multi-type abnormality diagnosis of the chip verification log, an abnormal status database is established according to the abnormal status that may exist in the chip verification process, and different abnormal data are encoded and classified. When the abnormal data in the verification process is obtained, the abnormal data is matched with the abnormal type in the abnormal database, and the three most similar groups of abnormal data are encoded and output to the foreground according to the matching similarity.

[0027] Preferably, in the S4.3 custom label and interface process, the model data that was modularly split and reorganized in S4.2 will be reorganized, and it will be determined whether it can execute the running program, and an adaptive enhanced model will be used to calibrate and report abnormal situations that may be involved in the running program.

[0028] The second aspect of the present invention relates to a chip verification device for automatic log parsing and feature extraction, comprising a memory and one or more processors, wherein the memory stores executable code, and when the one or more processors execute the executable code, they are used to implement the chip verification method for automatic log parsing and feature extraction of the present invention.

[0029] A third aspect of the present invention relates to a computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the chip verification method of the present invention for automated log parsing and feature extraction.

[0030] The present invention solves the problem in the prior art that the chip verification process consumes a lot of time and resources. The main innovations are as follows:

[0031] (1) The present invention uses semi-structured simulated log files as input in the field of bug detection and location, and conducts research on log data parsing and feature extraction, log anomaly detection, log multi-type anomaly diagnosis, personalized model updating and optimization, etc., so that verification developers can fix bugs in a timely and rapid manner and reduce labor costs.

[0032] (2) The present invention uses an incremental learning method to enable the model to adapt to new data sets and labels, and uses the trained model to perform incremental learning on old data. Combined with multi-type anomaly diagnosis, the anomaly type matching is performed for different types of abnormal data, and anomaly detection results and corresponding processing suggestions are generated. In addition, through custom labels and interfaces, users can adjust the model according to their own needs.

[0033] (3) The present invention splits and reorganizes model data in a modular way. For example, for a feature vector generation module, the feature extraction method and parameters can be adjusted according to the characteristics of new log data. By independently improving different modules, the model performance can be improved in a more targeted manner without causing excessive impact on the entire model.

[0034] In summary, the present invention automates the preprocessing and parsing of log data, extracts meaningful features and generates classification models, so that verification developers can fix bugs in a timely and rapid manner, reducing labor costs, and enabling the model to adapt to new data sets and labels, thereby improving the flexibility, adaptability and personalization of the model, extending the service life of the model, reducing resource consumption for repeated training, and reducing repeated debugging time due to misdiagnosis.

[0035] The present invention has the following beneficial effects:

[0036] (1) The present invention uses semi-structured simulated log files as input in the field of bug detection and location, and conducts research on log data parsing and feature extraction, log anomaly detection, log multi-type anomaly diagnosis, personalized model updating and optimization, etc.

[0037] (2) The present invention uses an incremental learning method to enable the model to adapt to new data sets and labels, and uses an already trained model to import old data to perform incremental learning on the model.

[0038] (3) The present invention can perform anomaly type matching for different types of abnormal data through multi-type anomaly diagnosis, and generate anomaly detection results and corresponding processing suggestions based on the matching results.

[0039] (4) The present invention enables users to adjust the model according to their own needs through customized tags and interfaces.

[0040] (5) The present invention splits and reorganizes model data in a modular way. For example, for a feature vector generation module, the feature extraction method and parameters can be adjusted according to the characteristics of new log data. By independently improving different modules, the model performance can be improved in a more targeted manner without causing excessive impact on the entire model. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 Flowchart of the chip verification method for automated log parsing and feature extraction;

[0043] Figure 2 is a flow chart of the S1 method of the present invention;

[0044] Figure 3 is a flow chart of the S2 method of the present invention;

[0045] Figure 4 is a flow chart of the S4 method of the present invention;

[0046] Figure 5 This is a tree diagram of the anomaly detection process of the present invention. DETAILED DESCRIPTION

[0047] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as limiting the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0048] It should be understood that the terms described in the present invention are only for describing special embodiments and are not intended to limit the present invention. In addition, for the numerical range in the present invention, it should be understood that each intermediate value between the upper and lower limits of the scope is also specifically disclosed. Each smaller range between the intermediate value in any stated value or stated range and any other stated value or intermediate value in the described range is also included in the present invention. The upper and lower limits of these smaller ranges can be independently included or excluded in the scope.

[0049] Unless otherwise indicated, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the art. Although the present invention describes only preferred methods and materials, any methods and materials similar or equivalent to those described herein may also be used in the implementation or testing of the present invention. All documents mentioned in this specification are incorporated by reference to disclose and describe the methods and / or materials associated with the documents. In the event of a conflict with any incorporated document, the content of this specification shall prevail.

[0050] It will be apparent to those skilled in the art that various modifications and variations may be made to the specific embodiments of the present invention description without departing from the scope or spirit of the present invention. Other embodiments derived from the present invention description will be apparent to those skilled in the art. The present application description and examples are exemplary only.

[0051] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0052] Example 1

[0053] This embodiment provides a chip verification method for automated log parsing and feature extraction, including the following steps:

[0054] Log analysis:

[0055] S1: Log collection, obtaining raw data and preprocessing it to remove invalid information from the log data, including duplicate information and useless information.

[0056] The S1 log data parsing and feature extraction based on UVM includes:

[0057] S1.1: At this stage, the log files need to be deeply analyzed and parsed. First, the structure of the log needs to be imported through machine learning in order to understand its organization and the functions of each part. Then, the template information for each specific event in the log is extracted; in this way, the event type, occurrence time, involved components, and related detailed information recorded in the log can be better understood; this process will help the present invention build a clear log template for subsequent log analysis and problem diagnosis.

[0058] S1.2: When processing UVM (Universal Verification Methodology) log files, various types of information are often mixed in the log files, including UVM_INFO, UVM_WARNING, UVM_ERROR and UVM_FATAL. In order to effectively process this information, the present invention needs to extract meaningful characteristic information in a targeted manner; this means that the present invention will focus on identifying and extracting key information that can reflect the system operation status and potential problems; in this way, a large amount of disorganized log data can be converted into valuable information, thereby providing strong support for subsequent analysis and problem solving.

[0059] When extracting characteristic information of the S1.2 log, the present invention adopts a variety of methods to ensure the accuracy and uniqueness of the information. First, the present invention uses string matching technology to identify and extract information fragments with specific characteristics by comparing the strings in the log one by one; this method can effectively filter out the key information required by the present invention from a large amount of data.

[0060] Secondly, in order to further improve the accuracy and efficiency of information extraction, a hash function processing method is used; a hash function can convert input data of any length into an output value of a fixed length, namely a hash value. By calculating the hash value of log information, the same or similar information fragments can be quickly compared and identified. This method not only improves the processing speed, but also reduces the computational burden caused by string matching.

[0061] However, relying solely on hash values ​​to compare information may sometimes lead to hash conflicts, i.e. different pieces of information may generate the same hash value. To deal with this situation, a timestamp judgment method is introduced as an auxiliary means. By comparing the timestamps of information with the same hash value, the present invention can further confirm whether the information is exactly the same. As a unique identifier for each log entry, the timestamp can provide additional judgment basis to ensure the uniqueness and accuracy of the information.

[0062] Log anomaly detection:

[0063] S2: It mainly uses machine learning methods to learn feature vectors and generate an anomaly detection model.

[0064] The step of establishing an abnormal information detection model by using a machine learning algorithm in the log anomaly detection based on chip verification in S2 includes:

[0065] S2.1: Convert the extracted log characteristic information into feature vectors for processing by machine learning algorithms;

[0066] S2.2: Using the extracted feature vectors and known normal and abnormal log data, train an anomaly detection model, and distinguish normal and abnormal behaviors through the established anomaly detection model;

[0067] S2.3: Evaluate the accuracy and generalization ability of the model through cross-validation and data confidence scoring methods, and optimize and iterate the model based on the evaluation results;

[0068] In the S2.3 process, in order to ensure the accuracy and generalization ability of the model, the present invention uses confidence data for evaluation; first, the present invention defines a probability number as a confidence scoring standard to quantify the credibility of the model; then, the present invention subdivides the confidence judgment result into three different judgment ranges, namely "credible", "data questionable" and "data abnormality"; in order to clarify these ranges, the present invention defines specific interval values ​​for each range; in the actual operation process, after obtaining the confidence data, the present invention will output the corresponding judgment conclusion according to these pre-defined result intervals; in this way, not only can the performance of the model be evaluated, but also the reliability of the data can be classified, thereby providing a more accurate basis for subsequent decision-making.

[0069] Multiple types of log anomaly diagnosis:

[0070] S3: Build a model based on the causes of the anomaly types of each log file in the dataset used during training. The input is the log file from the simulation, and the corresponding output is the root cause of the test failure.

[0071] In the S3 chip-verified log multi-type anomaly diagnosis process, the anomaly information detection model established in the S2 stage is mainly used; this model is applied to conduct in-depth anomaly cause analysis on the simulated log files in the data set files used in the training process; through this analysis, the present invention can further establish a more accurate anomaly judgment model; in this model, the input part is the simulated log file, and the output part is the root cause of the test failure.

[0072] Specifically, the multi-type abnormality diagnosis work of the chip verification log in the S3 stage will first establish a comprehensive abnormal status database based on the various abnormal states that may occur in the chip verification process; this database contains various possible abnormal types, and these abnormal data are encoded and classified in detail; when the present invention encounters abnormal data in the chip verification process, the present invention will perform detailed data matching of these abnormal data with the abnormal types in the abnormal database; through this matching, the present invention can determine the specific type of abnormal data, and according to the similarity of the matching, the present invention can find the three most similar sets of abnormal data encodings; these codes will then be output to the front desk for further analysis and processing by relevant personnel; in this way, the present invention can effectively identify and diagnose various abnormal situations that occur in the chip verification process, thereby improving the efficiency and accuracy of the entire verification process.

[0073] Personalized model update based on incremental learning:

[0074] S4: Update and optimize models for different users, explore incremental learning methods, enable trained models to accept new data sets and labels, and train and adjust based on existing models.

[0075] The S4 is used to explore the incremental learning method in the personalized model update based on incremental learning, and includes the following steps:

[0076] S4.1: Use the trained model as a starting point and import the learning model used on the old dataset;

[0077] S4.2: Modularize the model data according to its algorithmic characteristics, and support data adjustment and reorganization of the modular data after splitting;

[0078] S4.3: Design new models and interfaces, and support users to adjust labels in a customized way within a certain range;

[0079] In the process of customizing labels and interfaces in S4.3, the model data that has been modularly split and reorganized in S4.2 will be reorganized, and it will be determined whether it can execute the running program. The adaptive enhancement model will be used to calibrate and report abnormal situations that may be involved in the running program. The sample weight update formula in the established adaptive enhancement model is as follows:

[0080] First, initialize the weight of each sample to w1. Where N is the total number of samples; in the tth iteration, if sample i is correctly classified, its weight is updated to w t+1 ,

[0081] If sample i is misclassified, its weight is updated to w t+1 :

[0082] where α t is the weight coefficient of the tth weak classifier, Z t is the normalization factor so that the sum of all sample weights is 1;

[0083] The calculation formula of the weak classifier weight coefficient in the established adaptive enhancement model is as follows:

[0084]

[0085] Among them, ε t is the error rate of the tth weak classifier, that is, the sum of the weights of the misclassified samples;

[0086] The final prediction formula in the established adaptive enhancement model is as follows:

[0087] For a new sample x, the final prediction result is:

[0088]

[0089] Where T is the total number of weak classification items, h t (x) is the prediction result of the t-th weak classifier for sample x, \sign is the sign function, and the final classification is determined based on the positive or negative result, and this is used as the basis for outputting whether to perform abnormal judgment in the end.

[0090] Suppose we conduct verification log analysis on the NVIDIA Tegra X1 chip, which is used in some complex embedded systems and mobile devices. A large number of log files are generated during the verification process. We directly arrange the log analysis, and there is a set of sample data representing different log situations, with a total of 10 samples.

[0091] Initialization phase:

[0092] The initial weight of each sample is 1 / 10=0.1.

[0093] First iteration:

[0094] Assume that there is a simple weak classifier that determines whether a log is abnormal based on a certain log feature. After being judged by this weak classifier, 7 samples are correctly classified and 3 samples are incorrectly classified;

[0095] For samples that are correctly classified, their weights are updated as: Assume that a = 0.5, the normalization factor Z tIt needs to be calculated based on the updated sum of all sample weights. First, calculate the sum of the new weights of the correctly classified samples. For 7 samples, each weight becomes 0.1×e -0.5×1 The sum is about 0.47; for the misclassified samples, their weights are updated as: Similarly, the sum of the new weights of the three misclassified samples is calculated, which is about 0.53; at this time, the sum of the weights of all samples is 1, and the normalization factor Z is calculated t ≈0.47+0.53=1.

[0096] Calculate the weak classifier weight coefficient:

[0097] Assume that the sum of the weights of the misclassified samples is 0.53, that is, the error rate ε t =0.53; Weak classifier weight coefficient Substituting into the calculation, we can get α t The value of .

[0098] Subsequent iterations:

[0099] Continue to the next round of iteration, classify and update the weights again according to the new sample weights and weak classifiers, and repeat the above process until the set number of iterations is reached or other stopping conditions are met.

[0100] Final prediction:

[0101] When a new log sample x of the NVIDIA Tegra X1 chip appears, the prediction results h of each weak classifier for sample x are t (x), and the corresponding weak classifier weight coefficient α t , use the final prediction formula to make a judgment. If the final result is greater than 0, it is judged as normal; if it is less than 0, it is judged as abnormal, and the final abnormal judgment result is output.

[0102] The present invention can be applied to chip verification tasks in real scenarios, which can greatly improve the efficiency of verification personnel and save time and resources.

[0103] In summary, the present invention uses semi-structured simulated log files as input in the field of bug detection and location, and conducts research on log data parsing and feature extraction, log anomaly detection, log multi-type anomaly diagnosis, personalized model updating and optimization, etc., so that verification developers can fix bugs in a timely and rapid manner and reduce labor costs.

[0104] Example 2

[0105] The present embodiment relates to a chip verification device for automatic log parsing and feature extraction, including a memory and one or more processors, wherein the memory stores executable code, and when the one or more processors execute the executable code, they are used to implement the chip verification method for automatic log parsing and feature extraction of Example 1.

[0106] Example 3

[0107] This embodiment relates to a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the chip verification method of automated log parsing and feature extraction of Embodiment 1 is implemented.

[0108] The embodiments described above are only descriptions of the preferred modes of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A chip verification method for automated log parsing and feature extraction, characterized in that: The following steps are involved: S1: Log collection, obtaining raw data and preprocessing. Eliminate invalid information in the log data, including duplicate information and useless information; S2: Anomaly detection mainly uses machine learning methods to learn feature vectors and generate an anomaly detection model; S3: Multi-type anomaly diagnosis, which builds a model based on the anomaly type causes of each log file in the dataset used during training. The input is the simulated log file, and the corresponding output is the root cause of the test failure. S4: Update and optimize models for different users, explore incremental learning methods, enable trained models to accept new data sets and labels, and train and adjust based on existing models.

2. According to claim 1, a chip verification method for automated log analysis and feature extraction is characterized in that: The S1 log data parsing and feature extraction based on UVM includes: S1.1: Analyze the log structure and information, and obtain the log template for each event; S1.2: For the situation where all UVM_INFO, UVM_WARNING, UVM_ERROR and UVM_FATAL are mixed in the UVM log file, extract meaningful features accordingly.

3. The chip verification method of automatic log analysis and feature extraction according to claim 1, characterized in that: The machine learning algorithms involved in the log anomaly detection based on chip verification of S2 include cluster analysis, decision tree, and deep learning, and the steps of establishing an abnormal information detection model through the machine learning algorithm include: S2.1: Convert the extracted log characteristic information into feature vectors for processing by machine learning algorithms; S2.2: Using the extracted feature vectors and known normal and abnormal log data, train an anomaly detection model, and distinguish normal and abnormal behaviors through the established anomaly detection model; S2.3: Evaluate the accuracy and generalization ability of the model through cross-validation and data confidence scoring methods, and optimize the model iteratively based on the evaluation results.

4. The chip verification method of automatic log analysis and feature extraction according to claim 1, characterized in that: In the multi-type anomaly diagnosis of chip-verified logs in S3, the anomaly information detection model established in S2 is mainly used to analyze the causes of anomalies in the simulated log files in the data set files used in the training process, and an anomaly judgment model is established based on this, in which the input is the simulated log file and the output is the root cause of the test failure.

5. The chip verification method of automatic log analysis and feature extraction according to claim 1, characterized in that: The S4 is used to explore the incremental learning method in the personalized model update based on incremental learning, and includes the following steps: S4.1: Use the trained model as a starting point and import the learning model used on the old dataset; S4.2: Modularize the model data according to its algorithmic characteristics, and support data adjustment and reorganization of the modular data after splitting; S4.3: Design new models and interfaces, and support users to adjust labels in a customized way within a certain range.

6. The chip verification method of automatic log analysis and feature extraction according to claim 2, characterized in that: In the extraction of characteristic information from the log S1.2, string matching and hash function processing are used to compare the hash values ​​of the information. At the same time, for information with the same hash value, timestamp judgment is used for auxiliary judgment.

7. The chip verification method of automatic log analysis and feature extraction according to claim 3 is characterized in that: In the S2.3 process, confidence data is used to determine the accuracy and generalization ability of the model. First, it is necessary to define a probability number as a confidence scoring standard. At the same time, the confidence judgment result is divided into three groups of judgment ranges: "credible", "data questionable", and "data abnormal", and their range intervals are defined. After the confidence data is obtained through actual calculation, the judgment conclusion is output according to the defined result interval.

8. The chip verification method of automatic log analysis and feature extraction according to claim 4, characterized in that: In the S3 chip verification-based log multi-type anomaly diagnosis, an abnormal state database is established according to the abnormal states that may exist in the chip verification process, and different abnormal data are encoded and classified. When abnormal data in the verification process is obtained, the abnormal data is matched with the abnormal type in the abnormal database, and the three most similar sets of abnormal data are encoded and output to the front end according to the matching similarity.

9. The chip verification method of automatic log analysis and feature extraction according to claim 5, characterized in that: In the S4.3 custom label and interface process, the model data that was modularly split and reorganized in S4.2 will be reorganized, and it will be determined whether it can execute the running program, and the adaptive enhancement model will be used to calibrate and report abnormal situations that may be involved in the running program.

10. A chip verification device for automated log parsing and feature extraction, characterized in that: It comprises a memory and one or more processors, wherein the memory stores executable code, and when the one or more processors execute the executable code, it is used to implement the chip verification method for automated log parsing and feature extraction as described in any one of claims 1 to 9.

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