A memristor simulator equivalent circuit, control method and electronic device

Abstract

The present invention discloses a memristor simulator equivalent circuit, control method and electronic device, belonging to the technical field of circuit element simulators. The memristor simulator equivalent circuit provided by the present invention utilizes a combination of a multiplier and an operational amplifier to reproduce the characteristics of a memristor and replace the memristor for use. It not only supports long-term debugging and use, but also avoids the use of complex hardware circuit design and high device costs, and solves the problem of performance degradation under non-ideal conditions. By introducing an integrator composed of a second operational amplifier and an integrating capacitor, the dynamic characteristics of the memristor can be accurately simulated, ensuring the stability of the conductivity in the non-conducting state and reducing errors caused by the non-ideal characteristics of the operational amplifier (such as input offset voltage and input bias current); by providing a single-pole double-throw switch, the circuit can be flexibly switched between different operating modes, making it easy to adjust the circuit parameters according to actual application requirements, thereby optimizing the simulator performance.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit element simulators, and in particular to a memristor simulator equivalent circuit, a control method and an electronic device. Background Art

[0002] Deep learning and artificial neural network technologies have played a pivotal role in the rapid development of artificial intelligence. Deeply inspired by the structure of the human brain, these technologies simplify and simulate the connections between neurons and synapses within the brain, enabling precise processing of complex tasks such as motor control, logical reasoning, and object recognition. However, current artificial neural networks still lag significantly behind the performance of the human brain. To more closely mimic the workings of the human brain, spiking neural networks have emerged. They specifically process discrete spike signals by meticulously modeling the brain's neurons and synapses.

[0003] Compared to traditional artificial neural network algorithms, the training process of spiking neural networks is more complex, the design of their synaptic circuits is also extremely challenging, and the cost of electronic components is high. These factors together constitute a major obstacle to building large-scale hardware neural networks.

[0004] Memristors, as innovative electronic components, change their resistance in response to the passage of current. This change is non-volatile and reversible, maintaining the memory properties of resistance. This bears striking resemblance to the dynamic changes in biological synaptic weights. Furthermore, memristors offer significant advantages in high density, low power consumption, high-speed switching, and are fully compatible with traditional CMOS processes. Therefore, memristors demonstrate tremendous potential for building efficient neural network circuits. Synaptic circuits constructed using memristors can achieve significant improvements in device count, energy consumption, and efficiency compared to previously complex CMOS synaptic circuits.

[0005] Although feasible preparation methods have been developed in the field of memristor device research, directly using these real memristor devices to build neural networks still faces many challenges. From nanoscale material synthesis to complex device structure design, existing memristor preparation methods are quite difficult, and the prepared memristors have strict requirements for the operating environment, and their memristive properties are not ideal under certain conditions. For commercial memristor solutions, high operating costs and limited power cycle life have become stumbling blocks to their widespread application. In particular, in the application scenario of spiking neural networks, the memristor needs to be repeatedly powered on, which undoubtedly poses a serious challenge to its long-term debugging and stability.

[0006] Currently, the industry has proposed building memristor simulators using equivalent circuits to replace actual memristors for hardware implementations of spiking neural networks. However, these approaches are typically complex and costly. Furthermore, in actual hardware circuits, operational amplifiers are not completely ideal, and their performance is affected by input offset voltage and input bias current. In the application of spiking neural networks, DC pulses must be repeatedly applied to the memristor unit to change its conductance. At the same time, the memristor must maintain a relatively stable conductance during a relatively long period of non-conducting state. However, under non-ideal conditions, a memristor simulator will continue to flow a current in its non-conducting state, which will affect the voltage across the internal capacitor and cause unwanted changes in conductance.

[0007] In view of this, how to use common circuit components such as operational amplifiers to design a simple and easy-to-implement memristor simulator and take practical and effective measures to mitigate the adverse effects of the non-ideal characteristics of operational amplifiers on conductivity has become a key technical problem that technicians in this field urgently need to solve. Summary of the Invention

[0008] The purpose of the present invention is to provide a memristor simulator equivalent circuit, control method and electronic device, aiming to solve the problems of complex design and practical application of the memristor simulator equivalent circuit and conductivity performance degradation under the non-ideal characteristics of the operational amplifier.

[0009] The present invention solves the above technical problems through the following technical solutions:

[0010] A memristor simulator equivalent circuit includes a first operational amplifier U1, a second operational amplifier U2, a first multiplier M1, a second multiplier M2, a first resistor R1, a second resistor R2, a third resistor R3, an integrating capacitor C, and a single-pole double-throw switch SW;

[0011] The first input terminal u1 of the first operational amplifier 1x , the second input terminal n2 of the second multiplier M2 and the first terminal r1 of the second resistor R2 21 Both are electrically connected to the voltage input terminal a of the equivalent circuit, and the voltage output terminal b of the equivalent circuit is grounded;

[0012] The first terminal r of the first resistor R1 11 are electrically connected to the second input terminal u1 of the first operational amplifier U1 1y and output u 1z , the second end r of the first resistor R1 12 electrically connected to a first throw terminal s1 of a single-pole double-throw switch SW;

[0013] The second throw terminal s2 of the single-pole double-throw switch SW is grounded via the third resistor R3, and the common terminal s0 of the single-pole double-throw switch SW is electrically connected to the second input terminal u1 of the second operational amplifier U2.2y , the first input terminal u of the second operational amplifier U2 2x grounding;

[0014] The second input terminal u of the second operational amplifier U2 2y The common terminal s0 of the single-pole double-throw switch SW and the first terminal c1 of the integrating capacitor are electrically connected respectively, and the second terminal c2 of the integrating capacitor is electrically connected to the output terminal u1 of the second operational amplifier U2. 2z , a first input terminal m1 and a second input terminal n1 of a first multiplier M1;

[0015] The output terminal v1 of the first multiplier M1 is electrically connected to the first input terminal m1 of the second multiplier M2, and the output terminal v2 of the second multiplier M2 is electrically connected to the second terminal r2 of the second resistor R2. 22 .

[0016] Furthermore, the models of the first operational amplifier U1 and the second operational amplifier U2 are AD711.

[0017] Furthermore, the first multiplier M1 and the second multiplier M2 are four-quadrant analog multipliers AD633.

[0018] Furthermore, the model of the single-pole double-throw switch SW is TMUX1134, and the switching mode of the switch is one of manual control and programmable algorithm control.

[0019] Furthermore, the voltage U at the output terminal v1 of the first multiplier M1 is v1 , the voltage U at the first input terminal m1 m1 and the voltage U at the second input terminal n1 n1 The following relationship exists: , where g1 is the scale factor of the first multiplier M1; the voltage U at the output terminal v2 of the second multiplier M2 is v2 , the voltage U at the first input terminal m2 m2 and the voltage U at the second input terminal n2 n2 The following relationship exists: , where g2 is the scaling factor of the second multiplier M2.

[0020] A control method for a memristor simulator equivalent circuit is based on the above-mentioned memristor simulator equivalent circuit, wherein a first operational amplifier U1 and a first resistor R1 form a voltage follower, and a second operational amplifier U2 and an integrating capacitor C form an integrator;

[0021] Connect the first throw terminal s1 of the single-pole double-throw switch SW to the common terminal s0, connect the voltage follower to the integrator, and adjust the input voltage to be greater than 0. At this time, the memristor simulator is in the on mode;

[0022] Connect the first throw terminal s1 of the single-pole double-throw switch SW to the common terminal s0, connect the voltage follower to the integrator, and adjust the input voltage to 0. At this time, the memristor simulator is in reset mode;

[0023] The second throw terminal s2 of the single-pole double-throw switch SW is connected to the common terminal s0, the voltage follower is disconnected from the integrator, and the second input terminal u of the second operational amplifier U2 is connected to the common terminal s0. 2y It is grounded via the third resistor R3. At this time, the memristor simulator is in power conservation mode.

[0024] Furthermore, when the memristor simulator is in conduction mode, the conductance of the memristor simulator Specifically:

[0025]

[0026] Wherein, g1 is the scale factor of the first multiplier M1; g2 is the scale factor of the second multiplier M2; is the magnetic flux.

[0027] Furthermore, when the memristor simulator is in reset mode, the integral capacitor C is charged from 0V to the integrator saturation, and the conductance The charging time remains unchanged and is as follows:

[0028]

[0029] in, is the current passing through the first resistor R1; is the maximum voltage of the integrating capacitor C.

[0030] Furthermore, when the memristor simulator is in power conservation mode, the maximum voltage change rate of the integral capacitor C is

[0031]

[0032] Where Q is the charge of the integrating capacitor C, is the maximum input offset voltage, is the maximum value of input bias current, is the maximum leakage current.

[0033] An electronic device includes: the above-mentioned memristor simulator equivalent circuit.

[0034] Compared with the prior art, the present invention has the following positive effects:

[0035] The memristor simulator equivalent circuit provided by the present invention utilizes a combination of a multiplier and an operational amplifier to replicate the characteristics of a memristor, allowing it to be used as a memristor replacement. This not only supports long-term debugging and use, but also avoids complex hardware circuit design and high device costs, and addresses performance degradation under non-ideal conditions. By introducing an integrator consisting of a second operational amplifier and an integrating capacitor, the dynamic characteristics of the memristor can be accurately simulated, ensuring the stability of the conductance in the non-conducting state and reducing errors caused by non-ideal characteristics of the operational amplifier (such as input offset voltage and input bias current). A single-pole double-throw switch allows the circuit to flexibly switch between different operating modes, facilitating adjustment of circuit parameters according to actual application requirements, thereby optimizing simulator performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings in the specification are used to provide further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0037] Figure 1 This is the equivalent circuit diagram of the memristor simulator;

[0038] Figure 2 is the equivalent circuit diagram of the conduction mode;

[0039] Figure 3 The IV hysteresis curves of the equivalent circuit of the memristor simulator at different frequencies;

[0040] Figure 4 The IV hysteresis curves of the memristor simulator equivalent circuit at different voltage amplitudes;

[0041] Figure 5 This is the equivalent circuit diagram of the reset mode. DETAILED DESCRIPTION

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0044] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0045] In the description of the embodiments of the present invention, it should be noted that if the terms "upper," "lower," "horizontal," "inner," etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the inventive product is typically placed when in use. These terms are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0046] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0047] In the description of the embodiments of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0048] The present invention will be further described in detail below with reference to the accompanying drawings, which are intended to explain rather than limit the present invention.

[0049] See also Figure 1 , a memristor simulator equivalent circuit, including a first operational amplifier U1, a second operational amplifier U2, a first multiplier M1, a second multiplier M2, a first resistor R1, a second resistor R2, a third resistor R3, an integrating capacitor C and a single-pole double-throw switch SW;

[0050] The first input terminal u1 of the first operational amplifier 1x , the second input terminal n2 of the second multiplier M2 and the first terminal r1 of the second resistor R2 21 Both are electrically connected to the voltage input terminal a of the equivalent circuit, and the voltage output terminal b of the equivalent circuit is grounded;

[0051] The first terminal r of the first resistor R1 11are electrically connected to the second input terminal u1 of the first operational amplifier U1 1y and output u 1z , the second end r of the first resistor R1 12 electrically connected to a first throw terminal s1 of a single-pole double-throw switch SW;

[0052] The second throw terminal s2 of the single-pole double-throw switch SW is grounded via the third resistor R3, and the common terminal s0 of the single-pole double-throw switch SW is electrically connected to the second input terminal u1 of the second operational amplifier U2. 2y , the first input terminal u of the second operational amplifier U2 2x grounding;

[0053] The second input terminal u of the second operational amplifier U2 2y The common terminal s0 of the single-pole double-throw switch SW and the first terminal c1 of the integrating capacitor are electrically connected respectively, and the second terminal c2 of the integrating capacitor is electrically connected to the output terminal u1 of the second operational amplifier U2. 2z , a first input terminal m1 and a second input terminal n1 of a first multiplier M1;

[0054] The output terminal v1 of the first multiplier M1 is electrically connected to the first input terminal m1 of the second multiplier M2, and the output terminal v2 of the second multiplier M2 is electrically connected to the second terminal r2 of the second resistor R2. 22 .

[0055] In the embodiment of the present invention, the models of the first operational amplifier U1 and the second operational amplifier U2 are AD711.

[0056] In the embodiment of the present invention, the first multiplier M1 and the second multiplier M2 are four-quadrant analog multipliers AD633.

[0057] In the embodiment of the present invention, the model of the single-pole double-throw switch SW is TMUX1134, and the switching mode of the switch is one of manual control and programmable algorithm control.

[0058] In the embodiment of the present invention, the voltage U at the output terminal v1 of the first multiplier M1 is v1 , the voltage U at the first input terminal m1 m1 and the voltage U at the second input terminal n1 n1 The following relationship exists: , where g1 is the scale factor of the first multiplier M1; the voltage U at the output terminal v2 of the second multiplier M2 is v2 , the voltage U at the first input terminal m2 m2 and the voltage U at the second input terminal n2 n2 The following relationship exists: , where g2 is the scaling factor of the second multiplier M2.

[0059] The memristor simulator equivalent circuit provided by the present invention overcomes the high cost requirements and stringent usage environment requirements of commercial memristors, and can support long-term debugging and use; avoids complex hardware circuit design and device cost use; solves the problem of conductance changes of the memristor simulator affected by input offset voltage and input bias current in the non-conducting state; and supports multiple working modes, allowing the memristor simulator to operate in different working modes according to usage requirements.

[0060] The memristor simulator equivalent circuit provided by the present invention comprises a first operational amplifier U1 and a first resistor R1 forming a voltage follower, and a second operational amplifier U2 and an integrating capacitor C forming an integrator; the circuit comprises three operating modes, namely, a conduction mode, a power-saving mode, and a reset mode, and the operating modes are switched by changing the magnitude of the input voltage and switching the connection of the single-pole double-throw switch SW.

[0061] The specific control methods are as follows:

[0062] Generally speaking, the mathematical model of an ideal memristor with an 8-shaped hysteresis loop is:

[0063]

[0064] Where: is the current through the device; is the voltage across the device; is the magnetic flux of the device; is the conductance of the device; and The memristor simulator provided by the present invention is constructed according to an ideal memristor model having a similar 8-shaped hysteresis loop.

[0065] Connect the first throw terminal s1 of the single-pole double-throw switch SW to the common terminal s0, connect the voltage follower to the integrator, and adjust the input voltage to be greater than 0. At this time, the memristor simulator is in the on-mode; the memristor simulator works normally, and the IV characteristic curve is a hysteresis curve. See the equivalent circuit diagram for details. Figure 2 , where the input voltage is v(t), the current passing through is i(t), and the magnetic flux is , the conductivity is , the input voltage of the first multiplier M1

[0066]

[0067] Then the output voltage of the second multiplier M2 is for

[0068]

[0069] Wherein: g1, g2 are the scaling factors of the first multiplier M1 and the second multiplier M2 respectively.

[0070] Then we can get the current i(t) passing through the voltage input terminal a of the equivalent circuit as

[0071]

[0072] Then the conductivity for

[0073]

[0074] Compared with the mathematical model of an ideal memristor with a similar 8-shaped hysteresis loop, we can get

[0075]

[0076] Set the circuit parameters as shown in Table 1, and perform circuit simulation on the memristor simulator structure in the software Multisim. The simulation results are as follows: Figure 3 and Figure 4 shown.

[0077] Table 1 Circuit parameters

[0078]

[0079] exist Figure 3 and Figure 4 In the experiment, the external characteristics of the memristor simulator obtained through circuit simulation are similar to the 8-shaped hysteresis loop, which proves that the external characteristics of the circuit structure when the memristor simulator is turned on basically conform to the mathematical model of the ideal memristor. Only the direction of the hysteresis loop is different. Both can be used as memristor units in pulse neural networks.

[0080] Connect the first throw terminal s1 of the single-pole double-throw switch SW to the common terminal s0, connect the voltage follower to the integrator, and adjust the input voltage to 0. At this point, the memristor simulator is in reset mode and does not operate. The non-ideal characteristics of the operational amplifier will cause the conductance of the memristor simulator to change. After a period of time, the conductance of the memristor simulator returns to its initial state and remains constant. This initial state is determined by the circuit parameters and is a constant value.

[0081] The conductance of the memristor simulator is directly related to the integrator voltage formed by the second operational amplifier U2, that is, it depends on the capacitor voltage of the integrator. Therefore, the first operational amplifier M1 and the second operational amplifier M2 are mainly analyzed. After considering the offset voltage and bias current of the operational amplifier, the equivalent circuit diagram of the memristor simulator reset mode can be seen in Figure 5 , in the figure is the input offset voltage of the first operational amplifier M1, I B1+ and I B1-are the input bias currents of the non-inverting input terminal and the inverting input terminal of the first operational amplifier M1, I B1+ and I B1- The average value is called the input bias current I of the first operational amplifier M1 B1 ; Similarly, is the input offset voltage of the first operational amplifier M2, I B2+ and I B2- are the input bias currents of the non-inverting input terminal and the inverting input terminal of the first operational amplifier M2, I B2+ and I B2- The average value is called the input bias current I of the first operational amplifier M2 B2 .

[0082] Due to the existence of input offset voltage, the input voltage of the voltage follower formed by the first operational amplifier is satisfy

[0083]

[0084] Similarly, the negative input voltage of the integrator formed by the second operational amplifier is satisfy

[0085]

[0086] Then the current flowing through the first resistor R1 can be obtained satisfy:

[0087]

[0088] Considering the influence of the operational amplifier input bias current, it can be concluded that the current flowing through the integrating capacitor C is Size:

[0089]

[0090] It can be seen that when the memristor simulator is in the non-conducting state and the input voltage is 0, there is still a continuous current flowing through the integral capacitor C to charge it, causing the voltage at both ends to change, thereby causing the conductance to change. It should be noted here that although and It is a subtraction relationship, but it does not mean that the influence of the input offset voltage of the two op amps will cancel each other out or weaken each other. This is because the polarity of the input offset voltage of the op amp is not fixed and can be positive or negative. The maximum value marked in the device manual is usually the absolute value. So under extreme conditions, the current The maximum absolute value is

[0091]

[0092] According to the operational amplifier AD711 used in this embodiment and the circuit structure resistance and capacitance parameters in Table 1, we can get

[0093] A

[0094] This value is relative to the integral capacitor It cannot be ignored even under a more conservative premise. , considering AD711 in The maximum output voltage under power supply is , then is the integrating capacitor The time required to charge until the op amp output is saturated for

[0095]

[0096] Among them, Q is the charge of the integrating capacitor C, only The voltage of the integrating capacitor will be charged from 0V to the saturation of the integrator, after which the conductance will return to its initial state and remain unchanged.

[0097] If it is necessary to keep the conductance of the memristor simulator unchanged without applying the memristor input voltage, measures need to be taken to improve the impact of the non-ideal characteristics of the operational amplifier, that is, switch to the power conservation mode, specifically: connect the second throw terminal s2 of the single-pole double-throw switch SW to the common terminal s0, disconnect the voltage follower and the integrator, and the second input terminal u 2y It is grounded via the third resistor R3. At this time, the memristor simulator is in power conservation mode.

[0098] When the memristor simulator switches to power conservation mode, the memristor simulator does not work and keeps the conductance of the memristor simulator approximately constant. Since the third resistor R3 is not connected to the circuit when the memristor simulator is turned on, it can be made as large as possible to minimize the charging current. At the same time, considering that there is still a certain leakage current when the switch is turned off, If the memristor simulator is not turned on, the maximum charging current of the integral capacitor is

[0099]

[0100] For analog switch leakage current Generally speaking, the maximum value is between a few nanoamperes and a few microamperes. In order to minimize the charging capacitance of the integral capacitor C in the non-conducting state, and taking into account other indicators of the switch, such as switching speed, power supply mode, etc., the grounding resistance is selected. , the maximum charging current is

[0101]

[0102] Compared with the original state, the charging current has been greatly reduced, without changing the conductivity change rate during power on (maintaining unchanged), take , , further reducing the voltage change of the integrating capacitor C in the non-conducting state. At this time, the maximum voltage change rate of the integrating capacitor C is

[0103]

[0104] Considering that even a real memristor may dissipate its conductance and thus change when no power is applied, the conductance change caused by the voltage change of the integrating capacitor C at this time is already within an acceptable range.

[0105] In summary, the memristor simulator equivalent circuit provided by the present invention utilizes a combination of a multiplier and an operational amplifier, which not only supports long-term debugging and use but also avoids complex hardware circuit design and device costs. It effectively enhances the circuit's anti-interference capability and maintains high stability even under non-ideal conditions. By introducing an integrator consisting of a second operational amplifier and an integrating capacitor, the dynamic characteristics of the memristor can be accurately simulated, ensuring the stability of the conductance in the non-conducting state and reducing errors caused by non-ideal characteristics of the operational amplifier (such as input offset voltage and input bias current). A single-pole double-throw switch allows the circuit to flexibly switch between different operating modes, facilitating adjustment of circuit parameters according to actual application requirements, thereby optimizing circuit performance.

[0106] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including: the memristor simulator equivalent circuit as described above. The electronic device can be any of a variety of existing devices.

[0107] Finally, it should be noted that the embodiments listed above are merely one or more specific manifestations of the technical solution of the present invention. Their purpose is to clearly illustrate the concept, principles, and application of the present invention through specific examples, and is in no way intended to limit the scope of protection of the present invention to these specific embodiments. In fact, the true value of this invention lies in its technical ideas and innovations, not in its form of expression or implementation.

[0108] For ordinary technicians in the relevant technical field, after thoroughly reading and understanding the technical solutions of the present invention, they are fully capable of making various forms of changes, modifications or equivalent replacements to the specific implementation methods of the invention based on their own professional knowledge and skills. These changes may include but are not limited to: adjusting the value range of technical parameters, optimizing algorithm processes to improve efficiency, replacing some technical components to achieve better compatibility or reduce costs, etc. As long as these modified technical solutions still substantially maintain the technical features claimed for protection by the original invention, that is, they can still achieve the core functions and effects of the present invention, then these changes should be deemed to fall within the scope of protection of the pending claims of the present invention.

[0109] Furthermore, with the continuous advancement and development of technology, new technical means and methods continue to emerge, providing ample room for further improvement and perfection of the present invention. Therefore, the scope of protection of the present invention should also include reasonably foreseeable improvements and extensions based on existing technologies. As long as these improvements and extensions do not deviate from the basic principles and core concepts of the present invention, they should be considered equivalent to the present invention and equally protected by patent rights.

Claims

1. A memristor simulator equivalent circuit, characterized in that: It includes a first operational amplifier U1, a second operational amplifier U2, a first multiplier M1, a second multiplier M2, a first resistor R1, a second resistor R2, a third resistor R3, an integrating capacitor C and a single-pole double-throw switch SW; The first input terminal u1 of the first operational amplifier 1x , the second input terminal n2 of the second multiplier M2 and the first terminal r1 of the second resistor R2 21 Both are electrically connected to the voltage input terminal a of the equivalent circuit, and the voltage output terminal b of the equivalent circuit is grounded; The first terminal r of the first resistor R1 11 are electrically connected to the second input terminal u1 of the first operational amplifier U1 1y and output u 1z , the second end r of the first resistor R1 12 electrically connected to a first throw terminal s1 of a single-pole double-throw switch SW; The second throw terminal s2 of the single-pole double-throw switch SW is grounded via the third resistor R3, and the common terminal s0 of the single-pole double-throw switch SW is electrically connected to the second input terminal u1 of the second operational amplifier U2. 2y , the first input terminal u of the second operational amplifier U2 2x grounding; The second input terminal u of the second operational amplifier U2 2y The common terminal s0 of the single-pole double-throw switch SW and the first terminal c1 of the integrating capacitor are electrically connected respectively, and the second terminal c2 of the integrating capacitor is electrically connected to the output terminal u1 of the second operational amplifier U2. 2z , a first input terminal m1 and a second input terminal n1 of a first multiplier M1; The output terminal v1 of the first multiplier M1 is electrically connected to the first input terminal m1 of the second multiplier M2, and the output terminal v2 of the second multiplier M2 is electrically connected to the second terminal r2 of the second resistor R2. 22 ; The first operational amplifier U1 and the first resistor R1 form a voltage follower, and the second operational amplifier U2 and the integrating capacitor C form an integrator; the equivalent circuit of the memristor simulator includes three operating modes, namely, conduction mode, power-saving mode and reset mode, and the operating modes are switched by changing the size of the input voltage and switching the connection of the single-pole double-throw switch SW.

2. The memristor simulator equivalent circuit according to claim 1, characterized in that: The first operational amplifier U1 and the second operational amplifier U2 are both AD711.

3. The memristor simulator equivalent circuit according to claim 1, characterized in that: The first multiplier M1 and the second multiplier M2 are four-quadrant analog multipliers AD633.

4. The memristor simulator equivalent circuit according to claim 1, characterized in that: The model of the single-pole double-throw switch SW is TMUX1134, and the switching mode of the switch is one of manual control and programmable algorithm control.

5. The memristor simulator equivalent circuit according to claim 1, characterized in that: The voltage U at the output terminal v1 of the first multiplier M1 v1 , the voltage U at the first input terminal m1 m1 and the voltage U at the second input terminal n1 n1 The following relationship exists: , where g1 is the scale factor of the first multiplier M1; the voltage U at the output terminal v2 of the second multiplier M2 is v2 , the voltage U at the first input terminal m2 m2 and the voltage U at the second input terminal n2 n2 The following relationship exists: , where g2 is the scaling factor of the second multiplier M2.

6. A control method for a memristor simulator equivalent circuit, characterized in that: The memristor simulator equivalent circuit according to claim 1, wherein the first operational amplifier U1 and the first resistor R1 constitute a voltage follower, and the second operational amplifier U2 and the integrating capacitor C constitute an integrator; Connect the first throw terminal s1 of the single-pole double-throw switch SW to the common terminal s0, connect the voltage follower to the integrator, and adjust the input voltage to be greater than 0. At this time, the memristor simulator is in the on mode; Connect the first throw terminal s1 of the single-pole double-throw switch SW to the common terminal s0, connect the voltage follower to the integrator, and adjust the input voltage to 0. At this time, the memristor simulator is in reset mode; The second throw terminal s2 of the single-pole double-throw switch SW is connected to the common terminal s0, the voltage follower is disconnected from the integrator, and the second input terminal u of the second operational amplifier U2 is connected to the common terminal s0. 2y It is grounded via the third resistor R3. At this time, the memristor simulator is in power conservation mode.

7. The control method of a memristor simulator equivalent circuit according to claim 6, characterized in that: When the memristor simulator is in conduction mode, the conductance of the memristor simulator Specifically: Wherein, g1 is the scale factor of the first multiplier M1; g2 is the scale factor of the second multiplier M2; is the magnetic flux; is the resistance value of the first resistor R1; is the resistance value of the second resistor R2; is the capacitance value of the integrating capacitor C.

8. The control method of a memristor simulator equivalent circuit according to claim 6, characterized in that: When the memristor simulator is in reset mode, the integral capacitor C is charged from 0V to the integrator saturation, and the conductance The charging time remains unchanged and is as follows: in, is the current passing through the first resistor R1; is the maximum voltage of the integrating capacitor C; is the capacitance value of the integrating capacitor C.

9. The control method of a memristor simulator equivalent circuit according to claim 6, characterized in that: When the memristor simulator is in power conservation mode, the maximum voltage change rate of the integral capacitor C is in, is the maximum value of the voltage change rate of the integrating capacitor C; is the maximum value of the charging current; is the maximum input offset voltage, is the maximum value of input bias current, is the maximum leakage current; is the capacitance value of the integrating capacitor C; is the resistance value of the third resistor R3.

10. An electronic device, characterized in that: include: The memristor simulator equivalent circuit according to any one of claims 1 to 4.

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