Pixel driving circuit and display device

Abstract

The invention provides a pixel driving circuit and a display device, and relates to the technical field of display, the pixel driving circuit comprises a driving transistor, a threshold compensation module, a data write-in module, a first light-emitting control module and a first capacitor, a grid electrode of the driving transistor is connected with a first node, a first pole is connected with a first power supply voltage end, and a second pole is connected with a third node; two poles of the first capacitor are respectively connected with the first node and the second node; the first light-emitting control module is connected between the third node and a fourth node, and the fourth node is connected with a light-emitting element; the threshold compensation module is connected between a first node and a third node, the threshold compensation module comprises an N-type transistor, and the threshold compensation module is configured to provide a first power supply voltage signal provided by a first power supply voltage end to a grid electrode of the driving transistor in a threshold compensation stage so as to carry out threshold compensation on the driving transistor; the data write-in module is connected between the data signal end and the second node so as to improve the output accuracy of the pixel driving circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] In display products, pixels are usually driven to emit light through a pixel driving circuit. How to improve the accuracy of the driving signal output by the pixel driving circuit has become one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a pixel driving circuit and a display device, aiming to improve the accuracy of the output signal of the pixel driving circuit and improve the display effect.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit for electrically connecting to a light-emitting element, characterized in that it includes a driving transistor, a threshold compensation module, a data writing module, a first light-emitting control module and a first capacitor, wherein a gate of the driving transistor is connected to a first node, a first plate of the first capacitor is connected to the first node, and a second plate is connected to a second node; a first electrode of the driving transistor is connected to a first power supply voltage terminal, and a second electrode of the driving transistor is connected to a third node;

[0006] The first light-emitting control module is connected between the third node and the fourth node, the fourth node is connected to the light-emitting element, and the first light-emitting control module is configured to be turned on in the light-emitting phase and transmit the driving signal to the light-emitting element;

[0007] The threshold compensation module is connected between the first node and the third node, the threshold compensation module includes an N-type transistor, and the threshold compensation module is configured to provide a first power supply voltage signal provided by the first power supply voltage terminal to the gate of the driving transistor in the threshold compensation stage to perform threshold compensation on the driving transistor;

[0008] The data writing module is connected between the data signal terminal and the second node, and is configured to write the data signal provided by the data signal terminal into the second node during the data writing phase.

[0009] In a second aspect, based on the same inventive concept, the present disclosure further provides a display device, comprising the pixel driving circuit provided in the first aspect of the present disclosure.

[0010] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0011] In the pixel driving circuit and display device provided by the embodiment of the present disclosure, in the threshold compensation stage, the first power supply voltage signal provided by the first power supply voltage terminal is transmitted to the gate of the driving transistor, i.e., the first node, after passing through the driving transistor and the threshold compensation module, which is equivalent to using the first power supply voltage signal of the first power supply voltage signal terminal to perform threshold compensation on the driving transistor. In the data writing stage, the data signal is written to the second node through the data writing module. It can be seen that the threshold compensation stage and the data writing stage are two independent stages, and the process of threshold compensation is not affected by the duration of the data writing stage, so there will no longer be the problem of insufficient threshold compensation due to the short data writing duration. When the threshold compensation is performed on the driving transistor by the first power supply voltage signal, the duration of the threshold compensation stage can be extended according to the demand, so as to ensure the adequacy of the threshold compensation of the driving transistor, and avoid the problem of inaccurate output signal of the pixel driving circuit due to insufficient threshold compensation of the driving transistor, so as to improve the accuracy of the driving signal transmitted by the pixel driving circuit to the light-emitting element, and improve the display effect of the display product. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0014] Figure 1 Shown is a schematic diagram of a pixel driving circuit in the related art;

[0015] Figure 2 Shown Figure 1 A working timing diagram of a pixel driving circuit;

[0016] Figure 3 Shown is a module diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0017] Figure 4 Shown Figure 3 A working timing diagram of a pixel driving circuit;

[0018] Figure 5 Shown Figure 3 Another working timing diagram of the pixel driving circuit;

[0019] Figure 6 Another module diagram of a pixel driving circuit provided by an embodiment of the present disclosure is shown;

[0020] Figure 7 Another module diagram of a pixel driving circuit provided by an embodiment of the present disclosure is shown;

[0021] Figure 8 Shown Figure 6 A circuit diagram of a corresponding pixel driving circuit;

[0022] Fig. 9 Shown Figure 7 A circuit diagram of a corresponding pixel driving circuit;

[0023] Fig.10 Shown Figure 7 A circuit diagram of a corresponding pixel driving circuit;

[0024] Fig.11 Shown with Fig.10 The timing diagram corresponding to the pixel driving circuit in FIG.

[0025] Fig.12 The figure shows a timing diagram of the pixel driving circuit provided by the embodiment of the present disclosure in the holding frame;

[0026] Fig.13 FIG. 1 is a circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0027] Fig.14 Shown with Fig.13 The driving timing diagram corresponding to the pixel driving circuit in FIG.

[0028] Fig.15 Shown is a circuit schematic diagram of a pixel driving circuit provided by the disclosed embodiment;

[0029] Fig.16 Shown with Fig.15 The driving timing diagram corresponding to the pixel driving circuit in FIG.

[0030] Fig.17 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0031] Fig.18 Shown with Fig.17 The driving timing diagram corresponding to the pixel driving circuit in FIG.

[0032] Fig.19 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0033] Fig. 20 Shown with Fig.19 The driving timing diagram corresponding to the pixel driving circuit in FIG.

[0034] Fig.21 Shown Fig.17 Another working timing diagram of the pixel driving circuit;

[0035] Fig. 22 Shown Fig.19 Another working timing diagram of the pixel driving circuit;

[0036] Fig.23 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0037] Fig.24 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0038] Fig.25 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0039] Fig.26 Shown with Fig.25 The timing diagram corresponding to the pixel driving circuit in FIG.

[0040] Fig. 27 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0041] Fig.28 Shown with Fig. 27 The timing diagram corresponding to the pixel driving circuit in FIG.

[0042] Fig.29 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0043] Fig.30 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0044] Fig.31 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0045] Fig.32 Shown is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0046] Fig.33 Shown is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0048] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0049] Figure 1 FIG. 1 is a schematic diagram of a pixel driving circuit in the related art. Figure 2 Shown Figure 1 A working timing diagram of a pixel driving circuit in the embodiment of the present invention, the pixel driving circuit 100 includes 7 transistors M1 to M7 and a capacitor C. The pixel driving circuit includes three working stages, namely, the initialization stage t01, the data writing stage t02 and the light emitting stage t03. In the initialization stage t01, transistors M5 and M7 are turned on to reset the first node N1 and the anode of the light emitting element D0 respectively. In the data writing stage t02, transistors M2, M3 and M4 are turned on to write the data signal to the second node N2, and the gate of the driving transistor is threshold compensated by the data signal. At this time, the potential of the second node N2 is Vdata, and the potentials of the first node N1 and the third node N3 are Vdata-|Vth|. In the light emitting stage t03, transistors M1, M3 and M6 are turned on, at this time, the voltage of the second node N2 becomes PVDD, and the voltage of the first node N1 remains Vdata-|Vth|. At this time, the current transmitted to the light emitting element D0 is I=K×(PVDD-Vdata+|Vth|-|Vth|) 2 =K×(PVDD-Vdata) 2 It can be seen that in the data writing stage, the data signal is used to perform threshold compensation on the gate of the driving transistor. The time of threshold compensation is limited by the duration of the data writing stage. If the duration of the data writing stage is short, there may be a problem of insufficient threshold compensation, resulting in a difference between the driving signal output by the pixel driving circuit and the expected signal, affecting the display effect of the display panel.

[0050] In order to solve the above problems, the present disclosure provides a pixel driving circuit, which no longer uses a data signal to perform threshold compensation on the gate of a driving transistor, so that the threshold compensation is no longer affected by the duration of the data writing phase, and the threshold compensation process is more sufficient, thereby facilitating the improvement of the accuracy of the driving signal output by the pixel driving circuit and the improvement of the display effect. The present disclosure will be further described below in conjunction with specific embodiments.

[0051] Figure 3 FIG. 1 is a block diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Figure 3 The embodiment of the present disclosure provides a pixel driving circuit for electrically connecting to a light emitting element D0. The pixel driving circuit includes a driving transistor DT, a threshold compensation module 10, a data writing module 20, a first light emitting control module 31 and a first capacitor C1, wherein the gate of the driving transistor DT is connected to the first node N1, the first plate of the first capacitor C1 is connected to the first node N1, and the second plate is connected to the second node N2; the first electrode of the driving transistor DT is connected to the first power supply voltage terminal PVDD, and the second electrode of the driving transistor DT is connected to the third node N3. The first light emitting control module 31 is connected between the third node N3 and the fourth node N4, and the fourth node N4 is connected to the light emitting element D0. The first light emitting control module 31 is configured to be turned on in the light emitting stage and transmit the driving signal to the light emitting element D0. The threshold compensation module 10 is connected between the first node N1 and the third node N3, and the threshold compensation module 10 includes an N-type transistor. The threshold compensation module 10 is configured to provide the first power supply voltage signal provided by the first power supply voltage terminal PVDD to the gate of the driving transistor DT in the threshold compensation stage to perform threshold compensation on the driving transistor DT. The data writing module 20 is connected between the data signal terminal Vdata and the second node N2 , and the data writing module 20 is configured to write the data signal provided by the data signal terminal Vdata to the second node N2 during the data writing phase.

[0052] In the pixel driving circuit provided by the embodiment of the present disclosure, in the threshold compensation stage, the first power supply voltage signal provided by the first power supply voltage terminal PVDD is transmitted to the gate of the driving transistor DT, i.e., the first node N1, after passing through the driving transistor DT and the threshold compensation module 10, which is equivalent to using the first power supply voltage signal of the first power supply voltage signal terminal PVDD to perform threshold compensation on the driving transistor DT. In the data writing stage, the data signal is written to the second node N2 through the data writing module 20. It can be seen that the threshold compensation stage and the data writing stage are two independent stages, and the process of threshold compensation is not affected by the duration of the data writing stage, so there will no longer be the problem of insufficient threshold compensation due to the short data writing duration. When the threshold compensation is performed on the driving transistor DT by the first power supply voltage signal, the duration of the threshold compensation stage can be extended according to the demand, so as to ensure the adequacy of the threshold compensation of the driving transistor DT, and avoid the problem of inaccurate output signal of the pixel driving circuit due to insufficient threshold compensation of the driving transistor DT, so as to improve the accuracy of the driving signal transmitted by the pixel driving circuit to the light-emitting element D0, and improve the display effect of the display product.

[0053] In addition, considering that the threshold compensation module 10 is directly electrically connected to the gate of the driving transistor DT, when the threshold compensation module 10 includes an N-type transistor, since the N-type transistor has the advantage of smaller leakage current, the leakage current from the threshold compensation module 10 to the gate of the driving transistor DT can be reduced, thereby reducing the influence of the leakage current on the potential of the gate of the driving transistor DT, thereby avoiding the problem of inaccurate driving signal output by the pixel driving circuit caused by this.

[0054] Figure 4 Shown Figure 3 A working timing diagram of the pixel driving circuit in FIG. Figure 5 Shown Figure 3 Another working timing diagram of the pixel driving circuit in FIG. 1 , in an optional implementation manner of the present disclosure, the starting time of the threshold compensation phase is earlier than the starting time of the data writing phase. Figures 3 to 5 , the control signal Scan1 is a signal connected to the control end of the threshold compensation module 10. The effective level signal in the control signal Scan1 can control the threshold compensation module 10 to be turned on, so that the first power supply voltage signal can be transmitted to the first node N1 through the driving transistor DT and the threshold compensation module 10 to achieve threshold compensation for the driving transistor DT. The control signal Scan2 is a signal connected to the control end of the data writing module 20. The effective level signal in the control signal Scan2 can control the data writing module 20 to be turned on, so that the data signal at the data signal end is provided to the second node N2. Figure 4 and Figure 5 In the timing sequence shown, the moment when the control signal Scan1 jumps to a high level can be regarded as the starting moment of the threshold compensation stage, and the moment when it jumps to a low level can be regarded as the ending moment of the threshold compensation stage; the moment when the control signal Scan2 jumps to a low level can be regarded as the starting moment of the data writing stage, and the moment when it jumps to a high level can be regarded as the ending moment of the data writing stage. In the embodiment of the present disclosure, the starting moment of the threshold compensation stage is earlier than the starting moment of the data writing stage, that is, the threshold compensation can be performed on the driving transistor DT before the data is written. Compared with the method of performing threshold compensation while writing data in the related art, the scheme of the present disclosure is conducive to extending the time of threshold compensation, thereby achieving the sufficiency of the threshold compensation of the driving transistor DT, and further conducive to improving the accuracy of the driving signal output by the pixel driving circuit.

[0055] Please refer to Figure 4In an optional implementation of the present disclosure, the start time of the data writing phase is earlier than the end time of the threshold compensation phase. This embodiment discloses a scheme in which the start time of the data writing phase is earlier than the start time of the threshold compensation phase, the duration of the threshold compensation phase is longer than the duration of the data writing phase, and the data writing phase overlaps with the threshold compensation phase. This is equivalent to writing data when threshold compensation has been performed for a period of time and the threshold compensation has not yet been completed. This design method is conducive to extending the overall duration of the threshold compensation phase and ensuring the adequacy of the threshold compensation, and is also conducive to reducing the overall duration of the threshold compensation phase and the data writing phase, thereby improving the driving efficiency of the pixel driving circuit.

[0056] It should be noted that Figure 4 The illustrated embodiment shows a scheme in which the start time and the end time of the data writing phase are both within the time period of the threshold compensation phase. In some other embodiments of the present disclosure, when the start time of the data writing phase is before the end time of the threshold compensation phase, the end time of the data writing phase may also coincide with the end time of the threshold compensation phase, or the end time of the data writing phase may be after the end time of the threshold compensation phase. The present disclosure does not make specific limitations on this.

[0057] Please refer to Figure 5 In an optional embodiment of the present disclosure, the start time of the data writing phase is later than the end time of the threshold compensation phase, that is, the data writing is performed after the threshold compensation process is completed. In this embodiment, the threshold compensation phase and the data writing phase are also two independent phases. The duration of the threshold compensation phase will not be affected by the duration of the data writing phase, and thus it is also beneficial to ensure the adequacy of the threshold compensation and to improve the accuracy of the output signal of the pixel driving circuit.

[0058] Figure 6 and Figure 7 Another module diagram of the pixel driving circuit provided by the embodiment of the present disclosure is shown respectively. Figure 6 and Figure 7 In an optional embodiment of the present disclosure, the pixel driving circuit further includes a first reset module 41, the first reset module 41 is connected between the first reset signal terminal Vref1 and the second node N2, and the first reset module 41 is configured to reset the second node N2 in the first reset stage.

[0059] The first capacitor C1 in the embodiment of the present disclosure is connected between the first node N1 and the second node N2. Due to the coupling effect of the first capacitor C1, the potential change of the second node N2 will be coupled to the first node N1. When the first reset module 41 is introduced between the first reset signal terminal and the second node N2, the first reset module 41 can be turned on in the first reset stage, and the reset signal of the first reset signal terminal Vref1 can be used to reset the second node N2, thereby coupling and pulling down the potential of the first node N1, which can indirectly reset the first node N1. Figure 6 and Figure 7 The first reset stage is described in detail in the detailed structure of FIG.

[0060] Figure 8 Shown Figure 6 For a circuit diagram of the corresponding pixel driving circuit, please refer to Figure 6 and Figure 8 In an optional implementation of the present disclosure, the control end of the first reset module 41 and the control end of the first light control module 31 are connected to the same control signal end EM. Optionally, the first reset module 41 includes a first reset transistor T1, and the first light control module 31 includes a first light control transistor T4, wherein the first reset transistor T1 and the first light control transistor T4 are transistors of the same type. This embodiment is described by taking the first reset transistor T1 and the first light control transistor T4 as P-type transistors as an example. The P-type transistor is turned on in response to a low-level control signal and is turned off in response to a high-level control signal, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the first reset transistor T1 and the first light control transistor T4 may also be embodied as N-type transistors, which are turned on in response to a high-level control signal and are turned off in response to a low-level control signal.

[0061] Please continue to refer to Figure 6 and Figure 8 , and combined with Figure 4As shown in the timing, in this embodiment, the control end of the first reset module 41 and the first light control module 31 is connected to the same control signal end, and the control signal end is, for example, the light control signal end EM. In this way, there is no need to introduce different control signals for the first reset module 41 and the first light control module 31, respectively, which is conducive to simplifying the control of the circuit. Optionally, the pixel driving circuit also includes a second reset module 42, the second reset module 42 is connected between the second reset signal end Vref2 and the fourth node N4, and the second reset module 42 is configured to reset at least the fourth node N4 in the second reset stage. In this embodiment, optionally, the second reset module 42 is configured to reset the fourth node N4, the third node N3 and the first node N1 in the second reset stage. Optionally, the second reset module 42 includes a second reset transistor T5. This embodiment is described by taking the second reset transistor T5 as a P-type transistor as an example, but it is not limited to this. In some other embodiments of the present disclosure, the second reset transistor T5 can also be embodied as an N-type transistor. In order to more clearly illustrate the content of the present disclosure, the present disclosure uses the same figure mark to describe the signal end and the signal transmitted by the signal end. In the first reset stage, the control signal Scan1 is at a high level, and the threshold compensation transistor T2 in the threshold compensation module 10 is turned on; the light control signal EM is at a low level, and the first reset transistor T1 and the first light control transistor T4 are turned on; the control signal SPX is at a low level, and the second reset transistor T5 in the second reset module 42 is turned on. In the first reset stage, the reset signal of the first reset signal terminal Vref1 is transmitted to the second node N2 to reset the second node N2, and at the same time, the reset signal of the second reset signal terminal Vref2 is transmitted to the fourth node N4 through the second reset transistor T5, transmitted to the third node N3 through the first light control module 31, and further transmitted to the first node N1 through the threshold compensation module 10, thereby realizing the reset of the fourth node N4, the third node N3 and the first node N1. In this way, the reset of the first node N1, the second node N2, the third node N3 and the fourth node N4 is realized at the same time in one reset stage, which is conducive to simplifying the overall control timing of the pixel driving circuit.

[0062] The following will be combined Figure 4 The timing shown is Figure 8 The working process of the circuit structure shown is explained.

[0063] In the first stage t1, the control signal Scan1 is at a high level, the light-emitting control signal EM and the control signal SPX are at a low level, the threshold compensation transistor T2, the first reset transistor T1, the first light-emitting control transistor T4 and the second reset transistor T5 are all turned on, the reset signal of the first reset signal terminal Vref1 resets the second node N2, and the reset signal of the second reset signal terminal Vref2 resets the fourth node N4, the third node N3 and the first node N1 respectively. At this time, the potential of the second node N2 is Vref1, and the potential of the first node N1 is Vref2.

[0064] In the second stage t2, the light-emitting control signal EM becomes a high level, the first light-emitting control transistor T4 and the first reset transistor T1 are turned off, the control signal Scan1 remains at a high level, the control signal SPX remains at a low level, the threshold compensation transistor T2 and the second reset transistor T5 remain turned on, and the reset signal of the second reset signal terminal Vref2 continues to reset the fourth node N4. The first power supply voltage signal PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2 to perform threshold compensation on the driving transistor DT.

[0065] In the third stage t3, the control signal Scan1 remains at a high level, the control signal SPX remains at a low level, the fourth node N4 continues to be reset, and the driving transistor DT is threshold compensated; at the same time, the control signal Scan2 becomes a low level, and the data signal Vdata is transmitted to the second node N2 for data writing. The potential of the second node N2 is Vdata, at this time the threshold compensation transistor T2 is still in the on state, and the potential of the first node N1 is PVDD-|Vth|, so that the potential of the second node N2 can be prevented from affecting the potential of the first node N1, and the accuracy of the circuit output in the subsequent light-emitting stage is ensured. Figure 4 In the timing sequence shown, after the data writing period, i.e. the third stage t3, ends, the control signal Scan1 still maintains a high level for a period of time, and continues to perform threshold compensation on the driving transistor DT, which is beneficial to extend the threshold compensation time and ensure the adequacy of the threshold compensation. It should be noted that Figure 8 In the circuit shown, the data writing transistor T3 in the data writing module 20 is a P-type transistor as an example for explanation. When the control signal Scan2 is a low-level signal, the transistor is turned on. In some other embodiments of the present disclosure, the data writing transistor T3 can also be embodied as an N-type transistor. When the control signal Scan2 is a high-level signal, the data writing transistor T3 is turned on. Figure 4 The level of the control signal Scan2 can be adjusted based on the timing shown, and the disclosure will not elaborate on this.

[0066] In the fourth stage t4, the control signal Scan1 changes to a low level, the control signals SPX and Scan2 change to a high level, the light-emitting control signal EM changes to a low level, the threshold compensation transistor T2, the first reset transistor T1, and the second reset transistor T5 are all turned off, the first light-emitting control transistor T4 is turned on, and the signal of the first power supply voltage terminal PVDD is transmitted to the driving transistor DT, generating a driving current that is transmitted to the light-emitting element D0, driving the light-emitting element D0 to emit light. In the light-emitting stage, the first reset transistor T1 is turned on, and the potential of the second node N2 changes from Vdata to Vref1. Due to the coupling effect of the first capacitor C1, the potential of the first node N1 changes to PVDD-|Vth|+Vref1-Vdata. At this time, the current sent to the light-emitting element D0 is I=K×(PVDD-|Vth|-PVDD+|Vth|-Vref1+Vdata) 2 =K×(Vdata-Vref1) 2 .

[0067] It should be noted that the first reset stage mentioned in the above embodiment can be regarded as the stage in which the first reset transistor T1 is turned on, corresponding to the first stage t1 mentioned above. The second reset stage can be regarded as the stage in which the second reset transistor T5 is turned on, corresponding to the period when the control signal SPX is at a low level. The above threshold compensation stage can be regarded as the stage in which the threshold compensation transistor T2 is turned on, corresponding to the period in which the control signal Scan1 is at a high level. Optionally, the start time of the second reset stage coincides with the start time of the first reset stage, corresponding to Figure 4 In the timing shown, the starting time of the second reset stage and the starting time of the first reset stage are both located at the starting time of the first stage t1 mentioned above. This design method can realize the simultaneous reset of the first node N1, the second node N2, the third node N3 and the fourth node N4, which is beneficial to simplify the control process of the pixel driving circuit.

[0068] Optionally, refer to Figure 8 The pixel driving circuit further includes a second capacitor C2, two plates of which are connected to the first power supply voltage terminal PVDD and the second node N2, respectively. Since the signal of the first power supply voltage terminal PVDD is a fixed potential signal, when the first power supply voltage terminal PVDD and the second node N2 are connected through the second capacitor C2, the potential of the second node N2 can be stabilized due to the coupling effect of the second capacitor C2, so as to avoid the potential of the second node N2 drifting and affecting the potential of the first node N1, thereby facilitating the improvement of the stability of the potential of the first node N1, and further facilitating the improvement of the stability of the driving signal output by the pixel driving circuit. It should be noted that the second capacitor C2 in the subsequent embodiments has the same function, and the similarities will not be repeated.

[0069] The above embodiment is described by taking the first reset transistor T1 and the first light emitting control transistor as P-type transistors. In some other embodiments of the present disclosure, the first reset transistor T1 may also be an N-type transistor. For example, please refer to Fig. 9 , Fig. 9 Shown Figure 7 A circuit diagram of a corresponding pixel driving circuit, in an optional implementation of the present disclosure, the first reset module 41 includes an N-type transistor, and the control end of the first reset module 41 and the control end of the threshold compensation module 10 are connected to the same control signal end Scan1.

[0070] Specifically, this embodiment shows a solution of setting the first reset transistor T1 as an N-type transistor. Considering that the threshold compensation transistor T2 is also an N-type transistor, the two respond to the same signal to be turned on or off. Therefore, this embodiment connects the control ends of the first reset transistor T1 and the threshold compensation transistor T2 to the same control signal end Scan1. In this way, there is no need to introduce other control signal ends separately for the first reset module 41, which is conducive to simplifying the overall structure of the pixel driving circuit.

[0071] Please continue to refer to Fig. 9 In an optional embodiment of the present disclosure, the pixel driving circuit further includes a second reset module 42, which is connected between the second reset signal terminal Vref2 and the fourth node N4. The second reset module 42 is configured to reset at least the fourth node N4 in the second reset stage, so that the anode of the light-emitting element D0 can be restored to an initial state before each light emission, and when receiving a driving signal, the light-emitting element D0 can respond to the driving signal and emit light accurately, thereby facilitating improving the accuracy of the light-emitting brightness of the light-emitting element D0.

[0072] The following will be combined Figure 5 The timing shown is Fig. 9 The working process of the pixel driving circuit shown is explained.

[0073] In the first stage t1, the control signals Scan1, Scan2 and the light-emitting control signal EM are all high levels, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, the data writing transistor T3 is turned off, the reset signal of the first reset signal terminal Vref1 is transmitted to the second node N2, and the second node N2 is reset. The signal of the first power supply voltage terminal PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2, and the driving transistor DT is threshold compensated.

[0074] In the second stage t2, corresponding to the second reset stage, the control signal SPX is at a low level, and the fourth node N4, i.e., the anode of the light emitting element D0, is reset. The starting time of the control signal SPX is after the starting time of the control signal Scan1 and before the ending time. This embodiment is described by taking the scheme that the effective level signal of the control signal SPX overlaps with the effective level signal of the control signal Scan1 as an example. In some other embodiments of the present disclosure, the effective level signal of the control signal SPX may also be within the effective level signal range of the control signal Scan1, and the present disclosure does not specifically limit this.

[0075] In the third stage t3 , the control signal Scan1 changes to a low level, the control signal Scan2 changes to a low level, the data writing transistor T3 in the data writing module 20 is turned on, and the signal at the data signal terminal is transmitted to the second node N2 .

[0076] In the fourth stage t3, the control signal Scan1 remains at a low level, the control signals Scan2 and SPX become high levels, the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3 and the second reset transistor T5 are all turned off, the light-emitting control signal EM becomes a low level, the first light-emitting control transistor T4 is turned on, and a current path is formed between the first power supply voltage terminal PVDD and the cathode of the light-emitting element D0, driving the light-emitting element D0 to emit light.

[0077] The above embodiment is described by taking the data writing transistor T3 corresponding to the data writing module 20 as a P-type transistor as an example. In an optional implementation of the present disclosure, the data writing module 20 includes an N-type transistor. For example, please refer to Fig.10 , Fig.10 Shown Figure 7 A circuit diagram of a corresponding pixel driving circuit, and Fig. 9 The difference lies in the different types of data writing transistor T3. Fig.11 Shown with Fig.10 The timing diagram corresponding to the pixel driving circuit in Figure 5 The difference lies in the different control signal Scan2. When the data writing transistor T3 is an N-type transistor, in the aforementioned third stage t3, the control signal Scan2 becomes a high level signal, controls the data writing transistor T3 to be turned on, and writes the data signal to the second node N2. For the working process of other stages, please refer to Fig. 9 and Figure 5, this embodiment will not be described in detail. Since the N-type transistor has the advantage of small leakage current, when the data writing transistor T3 is set as an N-type transistor, it is helpful to reduce or avoid the influence of the leakage current of the data writing transistor T3 on the potential of the second node N2, and further reduce or avoid the influence of the aforementioned leakage current coupled to the first node N1 on the potential of the first node N1, thereby helping to improve the output accuracy of the pixel driving circuit.

[0078] Fig.12 FIG. 1 is a timing diagram of a pixel driving circuit provided by an embodiment of the present disclosure when maintaining a frame. Figure 4 , Figure 5 as well as Fig.11 The corresponding timing is the timing of the pixel driving circuit in the writing frame. In an optional embodiment of the present disclosure, the pixel driving circuit includes a writing frame and a holding frame. The writing frame includes the aforementioned threshold compensation stage, the data writing stage, the first reset stage and the second reset stage; the holding frame includes the third reset stage tb. Figure 8 , Fig. 9 , Fig.10 and Fig.12 The second reset module 42 is further configured to reset the fourth node N4 in a third reset stage, and the third reset stage tb is located in the cut-off period of the first light emitting control module 31.

[0079] Please combine Figure 8 , Fig. 9 , Fig.10 and Fig.12 , in the hold frame, the first reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T3 are all turned off, and the driving signal is transmitted to the light emitting element D0 when the light emitting control signal is at a low level. When the light emitting control signal is at a high level, the first light emitting control module 31 is turned off. During the period when the light emitting control signal is at a high level, the control signal SPX transmits an effective level signal to control the conduction of the second reset transistor T5, and resets the anode of the light emitting element D0, so that the light emitting element D0 is in an initial state before each light emission. It should be noted that in the hold frame, the effective level signal of the control signal SPX is within the invalid level signal range of the light emitting control signal EM, that is, the control signal SPX does not exceed the invalid level signal interval of the light emitting control signal EM. Figure 8 As for the circuit structure shown, in the holding frame, when the effective level signal of the control signal SPX overlaps with the effective level signal of the light-emitting control signal, a large current may exist between the first power supply voltage terminal PVDD and the second reset signal terminal Vref2, resulting in the risk of burning the transistors on the corresponding path. Therefore, in the holding frame, making the third reset stage in the period corresponding to the invalid level of the light-emitting control signal is conducive to avoiding the risk of burning the transistors due to the above reasons.

[0080] Considering Figure 8 and Figure 4 In the corresponding embodiment, in the first stage t1 corresponding to the write frame, the effective level signal of the control signal SPX and the effective level signal of the light-emitting control signal overlap. In order to reduce or the risk of the above-mentioned transistor burning, the time duration of the effective level signal of the control signal SPX and the effective level signal of the light-emitting control signal overlapping can be minimized. Optionally, the time duration corresponding to the first stage t1 is the time duration required to scan a row of pixels. The shorter the time duration of the first stage t1, the fewer pixels will be reset at the same time, the smaller the current from the first power supply voltage terminal PVDD to the second reset signal terminal Vref2, and the smaller the risk of transistor burning. In some other embodiments of the present disclosure, the current from the first power supply voltage terminal PVDD to the second reset signal terminal Vref2 can be reduced by widening the line width of the reset signal line connected to the second reset signal terminal Vref2. For example, the line width of the reset signal line connected to the second reset signal terminal Vref2 can be made larger than the line width of the reset signal line connected to the first reset signal terminal Vref1. When the line width of the signal line becomes larger, the transistor is less likely to be burned when the same current passes through.

[0081] Fig.13 FIG. 1 is a circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Fig.14 Shown with Fig.13 The driving timing diagram corresponding to the pixel driving circuit in is: Fig.15 FIG. 1 is a circuit diagram of a pixel driving circuit provided in a disclosed embodiment. Fig.16 Shown with Fig.15 For the driving timing diagram corresponding to the pixel driving circuit in Fig.13 and Fig.14 ,as well as Fig.15 and Fig.16 In an optional embodiment of the present disclosure, the pixel driving circuit 00 also includes a third reset module 43, the third reset module 43 is connected between the third reset signal terminal Vref0 and the first node N1, and the third reset module 43 is configured to reset the first node N1 in the first node reset stage; the first node reset stage is performed before the threshold compensation stage, and the first node reset stage does not overlap with the threshold compensation stage.

[0082] This embodiment shows that a third reset module 43 specifically for resetting the first node N1 is introduced into the pixel driving circuit. Before the threshold compensation stage, the first node N1 is reset by the third reset module 43. In the first node reset stage, no current path is formed between the first power supply voltage terminal PVDD and the second reset signal terminal Vref2. Therefore, the introduction of the third reset module 43 to reset the first node N1 alone is beneficial to avoid the formation of a large current between the first power supply voltage terminal PVDD and the second reset signal terminal to burn the transistor.

[0083] The following will be combined Fig.14 The timing shown is Fig.13 The working process of the pixel driving circuit is described, optionally, the third reset module 43 includes an N-type transistor. Since the third reset transistor T9 is directly electrically connected to the first node N1, when the third reset transistor T9 is an N-type transistor, it is beneficial to reduce the leakage current of the third reset transistor T9 to the first node N1, which is beneficial to improve the stability of the potential of the first node N1. The first reset transistor T1 in the first reset module 41 and the first light emission control transistor T4 in the first light emission control module 41 are both P-type transistors, and the control terminals of the two are connected to the same control signal terminal EM.

[0084] In the first node reset phase t11, the control signal terminal Scan0 is a high level signal, the third reset transistor T9 is turned on, and the reset signal of the third reset signal terminal is transmitted to the first node N1 to reset the first node N1.

[0085] In the fourth node reset phase t12, the control signal SPX is at a low level, the second reset transistor T5 is turned on, and the reset signal of the second reset signal terminal Vref2 is transmitted to the fourth node N4 to reset the anode of the light emitting element D0. Optionally, the first node reset phase t11 and the fourth node reset phase t12 overlap.

[0086] In the first stage t1, the control signal Scan1 becomes high level, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, the signal of the first reset signal terminal Vref1 resets the second node N2, and the signal of the first power supply voltage terminal PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2, and the driving transistor DT is threshold compensated. During the threshold compensation period, the data stage t13 is executed, the control signal Scan2 becomes low level, the data writing transistor T3 in the data writing module 20 is turned on, and the signal of the data signal terminal is transmitted to the second node N2. In other words, the data writing process is during the threshold compensation period.

[0087] In the second stage t2, the control signal Scan1 is at a low level, the control signals Scan2 and SPX become high levels, the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3 and the second reset transistor T5 are all turned off, the light-emitting control signal EM becomes a low level, the first light-emitting control transistor is turned on, and a current path is formed between the first power supply voltage terminal PVDD and the cathode of the light-emitting element D0, driving the light-emitting element D0 to emit light.

[0088] The following will be combined Fig.16 The timing shown is Fig.15 The working process of the pixel driving circuit is described below.

[0089] In the first node reset phase t11, the control signal terminal Scan0 is a high level signal, the third reset transistor T9 is turned on, and the reset signal of the third reset signal terminal Vref0 is transmitted to the first node N1 to reset the first node N1.

[0090] In the fourth node reset phase t12, the control signal SPX is at a low level, the second reset transistor T5 is turned on, and the reset signal of the second reset signal terminal is transmitted to the fourth node N4 to reset the anode of the light emitting element D0. Optionally, the fourth node reset phase t12 overlaps with the first node reset phase t11.

[0091] In the first stage t1, the control signal Scan1 becomes a high level, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, the signal at the first reset signal end resets the second node N2, and the signal at the first power supply voltage end PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2 to perform threshold compensation on the driving transistor DT.

[0092] In the second stage t2, the control signal Scan1 becomes low level, the control signal Scan2 becomes low level, the data writing transistor T3 in the data writing module 20 is turned on, and the signal at the data signal end is transmitted to the second node N2. In this embodiment, the threshold compensation process and the data writing process are separate and do not overlap.

[0093] In the third stage t3, the control signal Scan1 is at a low level, the control signals Scan2 and SPX become high levels, the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3 and the second reset transistor T5 are all turned off, the light-emitting control signal EM becomes a low level, the first light-emitting control transistor is turned on, and a current path is formed between the first power supply voltage terminal PVDD and the cathode of the light-emitting element D0, driving the light-emitting element D0 to emit light.

[0094] Optionally, Fig.13 and Fig.15In the illustrated embodiment, the third reset module 43 includes an N-type transistor. Since the third reset transistor T9 is directly electrically connected to the first node N1, when the third reset transistor T9 is an N-type transistor, it is beneficial to reduce the leakage current of the third reset transistor T9 to the first node N1, which is beneficial to improve the stability of the potential of the first node N1.

[0095] Fig.17 FIG. 2 is another circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Fig.18 Shown with Fig.17 The driving timing diagram corresponding to the pixel driving circuit in is: Fig.19 FIG. 1 is another circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Fig. 20 Shown with Fig.19 The driving timing diagram corresponding to the pixel driving circuit in is: Fig.17 and Fig.13 The difference is that the signal connected to the control end of the third reset module 43 is different, and the type of the third reset transistor T9 is different. Fig.19 and Fig.15 The difference lies in that the signal connected to the control end of the third reset module 43 is different, and the type of the third reset transistor T9 is different. Fig.17 and Fig.19 The third reset transistor T9 in the illustrated embodiment is a P-type transistor. Fig.17 and Fig.18 ,as well as Fig.19 and Fig. 20 In an optional embodiment of the present disclosure, the pixel driving circuit includes a third reset module 43 and a second reset module 42. The third reset module 43 is connected between the third reset signal terminal Vref0 and the first node N1. The third reset module 43 is configured to reset the first node N1 in the first node reset phase; the first node reset phase is performed before the threshold compensation phase, and the first node reset phase does not overlap with the threshold compensation phase. The second reset module 42 is connected between the second reset signal terminal and the fourth node N4; the control terminal of the third reset module 43 and the control terminal of the second reset module 42 are connected to the same control signal terminal.

[0096] In the present embodiment, the third reset transistor T9 and the second reset transistor T5 are both used as the embodiment. When the third reset module 43 is introduced into the pixel driving circuit to reset the first node N1, the control end of the third reset module 43 and the control end of the second reset module 42 for resetting the fourth node N4 are connected to the same control end SPX. That is to say, the process of resetting the first node N1 and the process of resetting the anode of the light-emitting element D0 are carried out simultaneously. In this way, there is no need to introduce a control signal separately for the third reset module 43, which is conducive to simplifying the overall design of the pixel driving circuit.

[0097] The following will be combined Fig.17 and Fig.18 right Fig.17 The working process of the pixel driving circuit is explained below.

[0098] In the reset stage t21, the control signal terminal Scan0 is at a low level, the third reset transistor T9 is turned on, and the reset signal of the third reset signal terminal Vref0 is transmitted to the first node N1 to reset the first node N1; the control signal SPX is at a low level, the second reset transistor T5 is turned on, and the reset signal of the second reset signal terminal Vref2 is transmitted to the fourth node N4 to reset the anode of the light-emitting element D0.

[0099] In the first stage t1, the control signal Scan1 becomes high level, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, the signal at the first reset signal terminal resets the second node N2, and the signal at the first power supply voltage terminal PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2, and the driving transistor DT is threshold compensated. During the threshold compensation period, the control signal Scan2 becomes low level, the data writing transistor T3 in the data writing module 20 is turned on, and the signal at the data signal terminal is transmitted to the second node N2.

[0100] In the second stage t2, the control signal Scan1 is at a low level, the control signals Scan2 and SPX become high levels, the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3 and the second reset transistor T5 are all turned off, the light-emitting control signal EM becomes a low level, the first light-emitting control transistor is turned on, and a current path is formed between the first power supply voltage terminal PVDD and the cathode of the light-emitting element D0, driving the light-emitting element D0 to emit light.

[0101] The following will be combined Fig.19 and Fig. 20 right Fig.19 The working process of the pixel driving circuit is explained below.

[0102] In the reset stage t21, the control signal terminal Scan0 is at a low level, the third reset transistor T9 is turned on, and the reset signal of the third reset signal terminal Vref0 is transmitted to the first node N1 to reset the first node N1; the control signal SPX is at a low level, the second reset transistor T5 is turned on, and the reset signal of the second reset signal terminal is transmitted to the fourth node N4 to reset the anode of the light-emitting element D0.

[0103] In the first stage t1, the control signal Scan1 becomes a high level, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, the signal at the first reset signal end resets the second node N2, and the signal at the first power supply voltage end PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2 to perform threshold compensation on the driving transistor DT.

[0104] In the second stage t2, the control signal Scan1 changes to a low level, the control signal Scan2 changes to a low level, the data writing transistor T3 in the data writing module 20 is turned on, and the signal at the data signal end is transmitted to the second node N2.

[0105] In the third stage t3, the control signal Scan1 is at a low level, the control signals Scan2 and SPX become high levels, the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3 and the second reset transistor T5 are all turned off, the light-emitting control signal EM becomes a low level, the first light-emitting control transistor T4 is turned on, and a current path is formed between the first power supply voltage terminal PVDD and the cathode of the light-emitting element D0, driving the light-emitting element D0 to emit light.

[0106] Fig.21 Shown Fig.17 Another working timing diagram of the pixel driving circuit in Fig.17 The difference in timing is that the control signal of the third reset module 43 does not reuse the control signal of the second reset module 42. Fig. 22 Shown Fig.19 Another working timing diagram of the pixel driving circuit in Fig.19 The difference in timing is that the control signal of the third reset module 43 does not reuse the control signal of the second reset module 42. Fig.21 and Fig. 22 In an optional embodiment of the present disclosure, the pixel driving circuit is connected to a cascade-arranged shift register, the control end of the third reset module 43 in the pixel driving circuit of the Nth row is connected to the output end of the shift register of the Nth stage, and the output end of the shift register of the Nth stage is connected to the control end of the data writing module 20 in the pixel driving circuit of the Nmth row, wherein N and m are both integers, and 1≤m<N, N≥2.

[0107] This embodiment is explained by taking the third reset transistor T9 in the third reset module 43 and the data write transistor T3 in the data write module 20 as the same type of transistor as an example, and specifically taking both of them as P-type transistors as an example. In this embodiment, the signals at each control signal end of the pixel driving circuit are provided by a shift register. For example, in a set of cascaded shift registers, a one-bit register at the first level is connected to the control end of the data write transistor in the first row of pixel driving circuits, and a one-bit register at the second level is connected to the control end of the data write transistor in the second row of pixel driving circuits, and so on. The control signal output by the aforementioned shift register is the control signal Scan2 mentioned in the embodiment of the present disclosure, and the control signal Scan2 includes multiple valid pulse signals, for example, the pixel driving circuit of the first row corresponds to the first valid pulse signal, the pixel driving circuit of the second row corresponds to the second valid pulse signal, and so on. It should be noted that the specific structure of the shift register can refer to the relevant technology, and the present disclosure does not specifically limit this. In this embodiment, the control signal received by the third reset transistor T9 multiplexes the valid pulse signals of the first several levels in the control signal Scan2 corresponding to the data write transistor T3. When m=1, the control signal of the third reset transistor T9 of the current row corresponds to the same valid pulse as the control signal of the data write transistor T3 of the previous row. That is to say, while writing data to the pixel drive circuit of the previous row, the first node in the pixel drive circuit of the current row is reset by the third reset module 43. In this way, the control ends of the third reset transistor T9 and the data write transistor T3 can be connected to the same set of gate drive circuits, which is conducive to simplifying the overall design of the display product including the pixel drive circuit in the embodiment of the present disclosure.

[0108] Fig.23 FIG. 1 is another circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Fig.13 The difference is that the bias module 60 is added. Fig.24 FIG. 1 is another circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Fig.15 The difference is that the bias module 60 is added, please refer to Fig.23 and Fig.24 In an optional embodiment of the present disclosure, the pixel driving circuit 00 further includes a bias module 60, the bias module 60 is connected between the bias signal terminal and the first electrode of the driving transistor DT, or the bias module 60 is connected between the bias signal terminal and the second electrode of the driving transistor DT. Fig.23 The embodiment shown is described by taking the bias module 60 connected to the third node N3, i.e., the second electrode of the driving transistor DT, as an example. Fig.24The embodiment shown is described by taking the bias module 60 connected to the first electrode of the driving transistor D as an example, but the computer is not limited thereto. The bias module 60 is configured to adjust the bias state of the driving transistor DT in the bias adjustment stage; the control end of the bias module 60 and the control end of the third reset module 43 are connected to the same control signal end Scan0, and the bias adjustment stage coincides with the first node reset stage.

[0109] When the bias module 60 and the third reset module 43 exist in the pixel driving circuit at the same time, optionally, the bias transistor T8 in the bias module 60 and the third reset transistor T9 in the third reset module 43 are transistors of the same type. In this case, the control end of the third reset transistor T9 and the control end of the bias transistor T8 can be connected to the same control signal end Scan0, and there is no need to introduce a separate control signal end for the third reset transistor T9, which is conducive to simplifying the overall structure of the pixel driving circuit. When the control end of the third reset transistor T9 and the control end of the bias transistor T8 are connected to the same control signal end Scan0, the process of resetting the first node N1 and the stage of adjusting the bias state of the driving transistor DT overlap, and both can be performed before the threshold compensation stage. For the specific processes of the threshold compensation stage, the data writing stage and the light emitting stage, please refer to Fig.14 or Fig.16 The embodiment shown is not described in detail in this embodiment.

[0110] It should be noted that when the pixel driving circuit includes a third reset module 43, a second reset module 42 and a bias module 60 at the same time, the types of transistors in the three modules can be set to be the same, and the control ends of the three can be connected to the same control signal end, so that the process of resetting the first node N1, the process of resetting the fourth node N4 and the process of adjusting the bias voltage overlap, which is also conducive to simplifying the overall control and timing of the pixel driving circuit.

[0111] Fig.25 FIG. 2 is another circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Fig.26 Shown with Fig.25 The timing diagram corresponding to the pixel driving circuit in Fig.23 The difference lies in the different types of data writing transistor T3. Fig.25 In the description, the data writing transistor T3 is taken as an N-type transistor as an example. Fig. 27 FIG. 2 is another circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Fig.28 Shown with Fig. 27 The timing diagram corresponding to the pixel driving circuit in FIG. 24 is different from that in FIG. 24 in that the type of the data writing transistor T3 is different. Fig. 27In the example, the data writing transistor T3 is an N-type transistor. When the data writing transistor T3 is an N-type transistor, the data writing transistor T3 is turned on when the control signal Scan2 is at a high level, and the other working processes are respectively the same as Fig.23 and Fig.24 When the data writing transistor T3 is an N-type transistor, it is beneficial to reduce the leakage current of the data writing transistor T3 to the second node N2, thereby reducing the influence of the leakage current of the second node N2 on the potential of the first node N1, so it is beneficial to improve the overall output accuracy of the pixel driving circuit. Fig.25 The working process of the pixel driving circuit can be referred to Fig.23 The embodiment shown, Fig. 27 The working process of the pixel driving circuit can be referred to Fig.24 The same aspects of the embodiments shown will not be described in detail.

[0112] Please continue to refer to Fig.13 and Fig.15 In an optional embodiment of the present disclosure, the pixel driving circuit also includes a second light-emitting control module 32 and a first switch control module 50, the second light-emitting control module 32 is connected between the first power supply voltage terminal PVDD and the first electrode of the driving transistor DT, and the first switch control module 50 is connected between the first power supply voltage terminal PVDD and the first electrode of the driving transistor DT; the control end of the second light-emitting control module 32 and the control end of the first light-emitting control module 31 are connected to the same control signal terminal EM, and the control end of the first switch control module 50 and the control end of the threshold compensation module 10 are connected to the same control signal terminal Scan1; the first switch control module 50 is configured to be turned on in the threshold compensation stage, and the second light-emitting control module 32 is configured to be turned on in the light-emitting stage.

[0113] In this embodiment, the type of the second light-emitting control transistor T6 included in the second light-emitting control module 32 is the same as the type of the first light-emitting control transistor T4 included in the first light-emitting control module 31, and the control terminals of the two are connected to the same light-emitting control signal terminal EM. In this embodiment, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are both P-type transistors for illustration. The type of the switch control transistor T7 included in the first switch control module 50 is different from the type of the second light-emitting control transistor T6. In this embodiment, the type of the switch control transistor T7 is the same as the type of the threshold compensation transistor T2 for illustration. In this embodiment, both are N-type transistors, and the control terminals of both are connected to the control signal Scan1. In the threshold compensation stage, the control signal Scan1 controls the switch control transistor T7 and the threshold compensation transistor T2 to turn on, while the second switch control transistor T6 is turned off. In this way, the first power supply voltage signal PVDD can also be used to perform threshold compensation on the driving transistor DT. In the light-emitting stage, the light-emitting control signal EM controls the first light-emitting control transistor T4 and the second light-emitting control transistor T6 to be turned on, and the switch control transistor T7 to be turned off, so that a current path can be formed between the first power supply voltage terminal PVDD and the cathode of the light-emitting element D0, driving the light-emitting element D0 to emit light. By introducing the second light-emitting control module 32 and the first switch control module 50, the time-sharing utilization of the first power supply voltage signal is realized.

[0114] In addition, when the second light emitting control module 32 and the first switch control module 50 are introduced into the pixel driving circuit, a bias module 60 may also be included at the same time. Fig.23 and Fig.24 The bias module 60 is used to transmit the bias signal to the first electrode or the second electrode of the driving transistor DT in the bias adjustment stage. The bias adjustment stage does not overlap with the threshold compensation stage and the light-emitting stage. In this way, in the bias adjustment stage, the second light-emitting control transistor T6 and the switch control transistor T7 are in the cut-off state, and a large current path will not be formed between the first power supply voltage terminal PVDD and the bias signal terminal, which is conducive to avoiding the phenomenon of forming a large current path and burning the driving transistor DT.

[0115] Fig.29 and Fig.30 Another circuit diagram of the pixel driving circuit provided by the embodiment of the present disclosure is shown respectively. Figure 8 and Fig. 9 The bias module 60 is added on the basis of the embodiment shown, that is, even if the pixel driving circuit does not include the third reset module, the bias module 60 may be included. Fig.29 and Fig.30In an optional embodiment of the present disclosure, the pixel driving circuit further includes a bias module 60, the bias module 60 is connected between the bias signal terminal and the first electrode of the driving transistor DT, or the bias module 60 is connected between the bias signal terminal and the second electrode of the driving transistor DT; the bias module 60 is configured to adjust the bias state of the driving transistor DT in the bias adjustment stage. By introducing the bias module 60 to adjust the bias state of the driving transistor DT, the afterimage and the first frame brightness can be effectively improved, and the overall display effect can be improved.

[0116] Fig.31 and Fig.32 Another circuit diagram of the pixel driving circuit provided by the embodiment of the present disclosure is shown respectively. Fig.31 and Fig.29 The difference is that the control signal connected to the control end of the bias module is different. Fig.32 and Fig.30 The difference is that the control signal connected to the control end of the bias module is different, please refer to Fig.31 In an optional embodiment of the present disclosure, the pixel driving circuit further includes a second reset module 42, and the second reset module 42 is connected between the second reset signal terminal and the fourth node N4; the control terminal of the bias module 60 and the control terminal of the second reset module 42 are connected to the same control signal terminal SPX, that is, the control terminal of the bias module 60 and the control terminal of the second reset module 42 are connected to the same control signal, and there is no need to introduce a new control signal for the bias module 60 separately, which is conducive to simplifying the overall design of the pixel driving circuit. In this embodiment, the bias adjustment stage and the process of resetting the fourth node N4 can be carried out simultaneously. In an optional embodiment of the present disclosure, the pixel driving circuit includes a writing frame and a holding frame, and the holding frame includes a bias adjustment stage. It should be noted that when the control terminal of the bias module 60 and the control terminal of the second reset module 42 are connected to the same control signal segment SPX, the reset process of the fourth node N4 and the bias state adjustment process can also be carried out in the holding frame, which is also conducive to improving the display effect. It should also be noted that in some other embodiments of the present disclosure, a new control signal can be introduced separately for the bias module 60. In this case, the bias state can also be adjusted in both the writing frame and the holding frame, which is beneficial to improving the overall display effect.

[0117] Of course, in some other embodiments of the present disclosure, please refer to Fig.32 The control end of the bias module 60 can also be connected to the same control signal end Scan2 as the control end of the data writing module 20. The bias transistor T8 in the bias module 60 and the data writing transistor T3 in the data writing module 20 are of the same type. In this way, the bias state adjustment process and the data writing process are carried out simultaneously. There is no need to introduce a new control signal for the bias module 60 separately, which is conducive to simplifying the overall design of the pixel driving circuit.

[0118] Based on the same inventive concept, the present disclosure also provides a display device, Fig.33 FIG. 1 is a schematic diagram of a structure of a display device provided in an embodiment of the present disclosure. Please refer to FIG. Fig.33 , the display device 200 includes the pixel driving circuit 00 in any of the above embodiments. The display device 200 provided in the embodiment of the present disclosure may be any electronic device with a display function, such as a tablet computer with a display function, a display cabinet display product, a television, or a vehicle-mounted display device. The display device 200 provided in the embodiment of the present disclosure has the beneficial effects of the pixel driving circuit 00 provided in the embodiment of the present disclosure. For details, please refer to the specific description of the pixel driving circuit 00 in the above embodiments, which will not be repeated in this embodiment.

[0119] Understandably, Fig.33 Only a rectangular structure is used to illustrate the display device. In some other embodiments of the present disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and the present disclosure does not specifically limit this.

[0120] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0121] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pixel driving circuit, for electrically connecting to a light emitting element, characterized in that: It includes a driving transistor, a threshold compensation module, a data writing module, a first light-emitting control module and a first capacitor, wherein the gate of the driving transistor is connected to a first node, the first plate of the first capacitor is connected to the first node, and the second plate is connected to a second node; the first electrode of the driving transistor is connected to a first power supply voltage terminal, and the second electrode of the driving transistor is connected to a third node; The first light-emitting control module is connected between the third node and the fourth node, the fourth node is connected to the light-emitting element, and the first light-emitting control module is configured to be turned on in the light-emitting stage and transmit the driving signal to the light-emitting element; The threshold compensation module is connected between the first node and the third node, the threshold compensation module includes an N-type transistor, and the threshold compensation module is configured to provide the first power supply voltage signal provided by the first power supply voltage terminal to the gate of the driving transistor in the threshold compensation stage to perform threshold compensation on the driving transistor; The data writing module is connected between the data signal terminal and the second node, and is configured to write the data signal provided by the data signal terminal to the second node during a data writing phase.

2. The pixel driving circuit according to claim 1, characterized in that: The starting time of the threshold compensation phase is earlier than the starting time of the data writing phase.

3. The pixel driving circuit according to claim 2, characterized in that: The start time of the data writing phase is earlier than the end time of the threshold compensation phase.

4. The pixel driving circuit according to claim 2, characterized in that: The start time of the data writing phase is later than the end time of the threshold compensation phase.

5. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes a first reset module, which is connected between the first reset signal terminal and the second node, and is configured to reset the second node in a first reset phase.

6. The pixel driving circuit according to claim 5, characterized in that: The control end of the first reset module and the control end of the first light emitting control module are connected to the same control signal end.

7. The pixel driving circuit according to claim 5, characterized in that: The first reset module includes an N-type transistor, and a control terminal of the first reset module and a control terminal of the threshold compensation module are connected to the same control signal terminal.

8. The pixel driving circuit according to claim 5, characterized in that: The pixel driving circuit further includes a second reset module, which is connected between the second reset signal terminal and the fourth node, and is configured to reset at least the fourth node in a second reset phase.

9. The pixel driving circuit according to claim 8, characterized in that: The second reset module is configured to reset the fourth node, the third node and the first node in a second reset phase.

10. The pixel driving circuit according to claim 8, characterized in that: The start time of the second reset phase coincides with the start time of the first reset phase.

11. The pixel driving circuit according to claim 8, characterized in that: The pixel driving circuit includes a writing frame and a holding frame, the writing frame includes the threshold compensation stage, the data writing stage, the first reset stage and the second reset stage; the holding frame includes a third reset stage, and the second reset module is further configured to reset the fourth node in the third reset stage, and the third reset stage is located in the cut-off period of the first light-emitting control module.

12. The pixel driving circuit according to claim 1, characterized in that: The data writing module includes an N-type transistor.

13. The pixel driving circuit according to claim 1, characterized in that: Also includes a third reset module, the third reset module is connected between the third reset signal terminal and the first node, the third reset module is configured to reset the first node in the first node reset phase; The first node reset phase is performed before the threshold compensation phase, and the first node reset phase does not overlap with the threshold compensation phase.

14. The pixel driving circuit according to claim 13, characterized in that: Also includes a second reset module, the second reset module is connected between the second reset signal terminal and the fourth node; The control end of the third reset module and the control end of the second reset module are connected to the same control signal end.

15. The pixel driving circuit according to claim 13, characterized in that: It also includes a bias module, the bias module is connected between the bias signal terminal and the first electrode of the driving transistor, or the bias module is connected between the bias signal terminal and the second electrode of the driving transistor; The bias module is configured to adjust the bias state of the driving transistor in a bias adjustment phase; The control end of the bias module and the control end of the third reset module are connected to the same control signal end, and the bias adjustment phase overlaps with the first node reset phase.

16. The pixel driving circuit according to claim 13, characterized in that: The pixel driving circuit is connected to a cascaded shift register; the control end of the third reset module in the pixel driving circuit of the Nth row is connected to the output end of the Nth stage shift register, and the output end of the Nth stage shift register is connected to the control end of the data writing module in the pixel driving circuit of the Nmth row, wherein N and m are both integers, and 1≤m<N, N≥2.

17. The pixel driving circuit according to claim 13, characterized in that: The third reset module includes an N-type transistor.

18. The pixel driving circuit according to claim 1, characterized in that: It also includes a second light-emitting control module and a first switch control module, wherein the second light-emitting control module is connected between the first power supply voltage terminal and the first electrode of the driving transistor, and the first switch control module is connected between the first power supply voltage terminal and the first electrode of the driving transistor; The control end of the second light-emitting control module and the control end of the first light-emitting control module are connected to the same control signal end, and the control end of the first switch control module and the control end of the threshold compensation module are connected to the same control signal end; the first switch control module is configured to be turned on during the threshold compensation stage, and the second light-emitting control module is configured to be turned on during the light-emitting stage.

19. The pixel driving circuit according to claim 1, characterized in that: Also includes a bias module, the bias module is connected between the bias signal terminal and the first electrode of the driving transistor, or the bias module is connected between the bias signal terminal and the second electrode of the driving transistor; The bias module is configured to adjust the bias state of the driving transistor in a bias adjustment phase.

20. The pixel driving circuit according to claim 19, characterized in that: Also includes a second reset module, the second reset module is connected between the second reset signal terminal and the fourth node; The control end of the bias module and the control end of the second reset module are connected to the same control signal end; or, the control end of the bias module and the control end of the data writing module are connected to the same control signal end.

21. The pixel driving circuit according to claim 19, characterized in that: The pixel driving circuit includes a writing frame and a holding frame, and the holding frame includes the bias adjustment stage.

22. A display device, characterized in that: The pixel driving circuit comprises any one of claims 1 to 21.

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