Power supply generating circuit and display driving circuit

Abstract

The invention discloses a power supply generating circuit and a display driving circuit. The power supply generating circuit comprises a first circuit, a second circuit coupled with the first circuit, and a voltage regulating circuit, the first circuit is used for generating a first voltage and outputting the first voltage to the first end of the second circuit; and the voltage regulation circuit is used for regulating the first voltage according to the second voltage of the second end of the second circuit, so that the voltage difference between the first end and the second end of the second circuit is within a preset voltage range. By adding the voltage regulating circuit, the voltage at the two ends of the digital circuit can be dynamically regulated, so that the normal work of the digital circuit is ensured.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to a power generation circuit and a display driving circuit. Background Art

[0002] In recent years, with the rapid development of mobile devices and the advancement of integrated circuit production technology, the characteristic size of transistors has been continuously reduced, and the integration of a single chip has been continuously improved. At the same time, digital circuits require higher and higher clock operating frequencies to complete large amounts of data processing and realize complex functions. Although technological advances can reduce the operating voltage of digital circuits, high clock frequencies and complex chip functions still generate large power consumption, posing challenges to power stability.

[0003] For example, in the field of liquid crystal display driver chips (LCD), the internal system on chip (System On Chip, SOC), high-speed signal processing module, static random access memory (Static Random-Access Memory, SRAM), image algorithm, etc. are usually integrated with complex functions, making the power consumption of digital modules reach the order of hundreds of milliamperes. Such a large power consumption will cause great interference to the power supply and ground. At the same time, because the display effect of LCD is extremely sensitive to the noise of analog signals, multiple ground lines are usually planned inside the chip. They are not short-circuited inside the chip, but connected through the external pins (PIN) of the integrated circuit (IC) to achieve the purpose of isolating signal noise. However, there must be a certain resistance between different grounds through the external PIN pins, including routing, IC pressing, etc. When currents of different sizes flow through these resistors, voltage differences will be generated between different grounds. When the voltage difference is too large, it will affect the normal operation of the chip. Summary of the invention

[0004] Based on the problems existing in the prior art, the present invention provides a power supply generating circuit, comprising: a first circuit, a second circuit coupled to the first circuit, and a voltage regulating circuit; the first circuit is used to generate a first voltage output to a first end of the second circuit; the voltage regulating circuit is used to adjust the first voltage according to a second voltage at the second end of the second circuit, so that the voltage difference between the first end and the second end of the second circuit is within a preset voltage range.

[0005] In some embodiments, the first circuit includes: a reference voltage generating circuit; the output end of the reference voltage generating circuit outputs the reference voltage; a low voltage dropout linear regulator; the low voltage dropout linear regulator includes a first input end, a second input end and an output end; the first input end of the low voltage dropout linear regulator is coupled to the output end of the reference voltage generating circuit; the first end of the voltage regulating circuit is coupled to the second input end of the low voltage dropout linear regulator; the second end of the voltage regulating circuit is coupled to the output end of the low voltage dropout linear regulator; the third end of the voltage regulating circuit is coupled to the second end of the digital circuit module.

[0006] In some embodiments, the second end of the second circuit is coupled to the ground; the voltage regulation circuit includes at least a first resistance unit, a second resistance unit and an adjustment unit connected in series; the first end of the first resistance unit is coupled to the ground; the second end of the first resistance unit is coupled to the second input end of the low-voltage difference linear regulator and the first end of the second resistance unit; the second end of the second resistance unit is coupled to the output end of the low-voltage difference linear regulator; based on the second voltage at the second end of the second circuit, the adjustment unit adjusts the third voltage at the second end of the first resistance unit, thereby adjusting the first voltage.

[0007] In some embodiments, the adjustment unit includes a first N-type MOS transistor; the first end of the first N-type MOS transistor is coupled to the first end of the first resistance unit; the second end of the first N-type MOS transistor is coupled to the second end of the first resistance unit; and the gate of the first N-type MOS transistor is coupled to the second end of the second circuit.

[0008] In some embodiments, the adjustment unit includes a first P-type MOS transistor; the first end of the first P-type MOS transistor is coupled to the first end of the second resistance unit; the second end of the first P-type MOS transistor is coupled to the second end of the second resistance unit; and the gate of the first P-type MOS transistor is coupled to the second end of the second circuit.

[0009] In some embodiments, the adjustment unit includes multiple groups of second N-type MOS transistors and third resistors connected in series; the second N-type MOS transistors and third resistors of each group are connected in parallel; the second N-type MOS transistors and third resistors of each group are coupled to the first end of the first resistance unit; the second end of the second N-type MOS transistors and third resistors of each group are coupled to the second end of the first resistance unit; the closing and opening of the second N-type MOS transistor are controlled by the second voltage of the second end of the second circuit.

[0010] In some embodiments, the adjustment unit includes multiple groups of second P-type MOS transistors and third resistors connected in series; the second P-type MOS transistors and third resistors of each group are connected in parallel; the second P-type MOS transistors and third resistors of each group are coupled to the first end of the second resistance unit; the second end of the second P-type MOS transistors and third resistors of each group are coupled to the second end of the second resistance unit; the closing and opening of the second P-type MOS transistor are controlled by the second voltage of the second end of the second circuit.

[0011] In some embodiments, the adjustment unit includes a detection unit; one end of the detection unit is coupled to the second end of the second circuit for detecting a second voltage at the second end of the second circuit; the detection unit adjusts the resistance value of the first resistance unit and the resistance value of the second resistance unit based on the second voltage, thereby adjusting the first voltage so that the voltage difference between the first end and the second end of the second circuit is within a preset voltage range.

[0012] In some embodiments, impedance exists in a wiring between the second end of the second circuit and the ground end.

[0013] In some embodiments, the first circuit is an analog circuit; and the second circuit is a digital circuit.

[0014] The present invention also provides a display driving circuit comprising the power generation circuit.

[0015] Compared with the prior art, the power generation circuit in the display driving circuit of the present invention can adjust the voltage at both ends of the digital circuit by adding a voltage regulating circuit, thereby ensuring the normal operation of the digital circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a module diagram of an LCD (Liquid Crystal Display) display.

[0017] Figure 2 The figure is a schematic diagram of a power generation circuit of a digital power supply according to an embodiment of the present invention.

[0018] Figure 3 FIG. 4 is a schematic diagram of a power generation circuit of another digital power supply according to an embodiment of the present invention.

[0019] Figure 4 FIG. 4 is a schematic diagram of a power generation circuit of another digital power supply according to an embodiment of the present invention.

[0020] Figure 5 FIG. 4 is a schematic diagram of a power generation circuit of another digital power supply according to an embodiment of the present invention.

[0021] Figure 6FIG. 4 is a schematic diagram of a power generation circuit of another digital power supply according to an embodiment of the present invention.

[0022] Figure 7 FIG. 4 is a schematic diagram of a power generation circuit of another digital power supply according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present invention. For ordinary technicians in this field, the present invention can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0024] Figure 1 Figure 1 is a schematic diagram of the LCD display module. Figure 1 As shown, 104 is a glass panel (Panel). 105 is a flexible printed circuit board (Flexible Printed Circuit, FPC), which is used to interconnect signals, external power supply and other external electronic components. 103 is the display driver chip (DriverIC) of the LCD. 101 is an analog circuit (AnalogCircuit), and the main modules include power supply, reference voltage, Gamma voltage and liquid crystal display source drive voltage. 102 is a digital circuit (DigitalCircuit), and the main modules include clock, logic control, image algorithm and display data control. Among them, PAD1 and PAD2 are two ground pins of the display driver chip 103, and their voltages are AVSS and VSS respectively. Among them, AVSS is the ground voltage of the analog circuit 101 inside the LCD; VSS is the ground voltage of the digital circuit 102.

[0025] The pins of the display driver chip 103 are pressed together with the transparent conductive pads of indium tin oxide (ITO) on the glass through anisotropic conductive adhesive (ACF), connected to the FPC 105 also pressed on the glass panel 104 through the ITO wiring on the glass panel 104, and then connected to the mainboard through the metal wire on the FPC 105. As can be seen from the schematic diagram, the ground end (voltage is VSS) of the digital circuit 102 of the display driver chip 103 needs to pass through the following resistors: the wiring resistor R5 in the display driver chip 103 is connected to PAD2, the PAD2 and the glass panel 104 are pressed together with the resistor R6, the ITO wiring resistor R7, the FPC 105 is pressed together with the wiring resistor R8, and then connected to the GND of the mainboard. The total resistance of R5~R8 resistors is usually around 1~2ohm. Due to differences in materials, processes and wiring, some impedances can even reach 5ohm. The resistors R1 to R4 from AVSS of the analog circuit 101 to GND of the mainboard can be obtained in the same way.

[0026] The display driver chip 103 includes a power generation circuit 100 . Figure 2 FIG. 1 is a schematic diagram of a power generation circuit 100 of a digital power source DVDD.

[0027] The power generation circuit 100 may include an analog circuit portion, which includes a reference voltage generation circuit 113 (BGR) and a low dropout regulator (LDO) 112. The BGR 113 is used to generate a reference voltage VREF, which is input to a first input terminal ( Figure 2 The power generation circuit 100 further includes a first resistor unit Rx and a second resistor Ry. The first end ( Figure 2 The G in the figure is connected to GND; the second end of the first resistor unit Rx ( Figure 2 D) and the first end of the second resistor unit Ry ( Figure 2 The second end of the first resistor unit Rx is coupled to the second input end ( Figure 2 B) in the coupling; the second end of the second resistor unit Ry ( Figure 2 C) is coupled to the output terminal of LDO 112 ( Figure 2 The circuit 100 further includes a digital circuit (Digital) 102. The output terminal of the LDO 112 is connected to the first terminal ( Figure 2 E) is coupled; the second end of the digital circuit 102 ( Figure 2 F in FIG. 1 is coupled to GND through an equivalent resistor Rd.

[0028] Since the power consumption of the analog circuit is relatively small, usually a few mA, the voltage drop on AVSS is about a few millivolts, assuming the resistance between AVSS and GND is 1 ohm, so AVSS = GND = 0 V is set. According to the working principle of LDO, the output voltage of DVDD is: DVDD = REF × (1 + Ry / Rx).

[0029] Figure 2 In the example, DVDD supplies power to the digital circuit 102, and Rd is the equivalent resistance from the ground terminal VSS to GND of the digital circuit 102. Figure 1 The equivalent resistance from VSS to GND is calculated as Rd=R5+R6+R7+R8. IL is the maximum average current of the digital circuit 102. Therefore, the VSS voltage is Rd*IL, and the actual operating voltage of the digital circuit 102 is DVDD_L= DVDD-Rd*IL.

[0030] For example, in a 55nm process size, the working voltage DVDD of the digital circuit 102 is 1.2V. In order to ensure the normal operation of the digital circuit 102, it is usually necessary to meet the power supply fluctuation range of less than 10% DVDD, that is, 1.08~1.32V.

[0031] When Rd=1ohm, IL=100mA, VSS rises by 100mV, DVDD_L=1.2V-100mV=1.1V. At this time, the anti-interference capability of the digital circuit 102 is reduced.

[0032] When Rd=2ohm, IL=100mA, VSS rises by 200mV, DVDD_L=1.2V-200mV=1.0V, which is less than the minimum voltage 1.08V required for the digital circuit 102 to work normally, causing the digital circuit 102 to fail to work normally.

[0033] Usually, in order to avoid this situation, it is necessary to raise the DVDD voltage value, for example, to 1.3V or even higher, to meet the working voltage requirement of the digital circuit 102 under heavy load. However, this will bring additional power consumption under light load, especially the standby power consumption of the chip (as the transistor channel size decreases, its static leakage current is larger and proportional to the voltage value). At the same time, the increase in the DVDD voltage value may cause the risk that DVDD_L exceeds the device withstand voltage under light load. In addition, the ground impedance of the display driver chip 103 will vary greatly according to different application environments and different modules. At the same time, the load current of the digital circuit in different states fluctuates greatly, so the VSS variation range is large and dynamic, and it is difficult to set DVDD to a fixed voltage value.

[0034] Based on the impedance of the wiring between the second end of the second circuit and the ground end in the above-mentioned power generation circuit 100, the present invention proposes a power generation circuit 200 that can dynamically adjust the output voltage value. The power generation circuit 200 may include a first circuit, a second circuit coupled to the first circuit, and a voltage regulation circuit. The first circuit is used to generate a first voltage and output it to the first end of the second circuit; the voltage regulation circuit is used to adjust the first voltage according to the second voltage of the second end of the second circuit, so that the voltage difference between the first end and the second end of the second circuit is within a preset voltage range, so that the second circuit works normally.

[0035] Different embodiments are described below with reference to the accompanying drawings.

[0036] Specifically, in one embodiment, if Figure 3 As shown, the power generation circuit 200 includes a first circuit, a second circuit and a voltage regulating circuit 114. The first circuit may be an analog circuit part, which includes a BGR 113 and an LDO 112. The second circuit may include a digital circuit (Digital) 102. The LDO 113 includes a first input terminal ( Figure 3 A in the second input ( Figure 3 B) and the output terminal ( Figure 3 The output of BGR 113 ( Figure 3 A) in the output reference voltage VREF. The first input terminal of the LDO is coupled to the output terminal of the BGR 113. The first terminal of the voltage regulating circuit 114 is coupled to the second input terminal of the LDO ( Figure 3 The second terminal of the voltage regulating circuit 114 is coupled to the output terminal of the LDO ( Figure 3 The third terminal of the voltage regulating circuit 114 is coupled to the second terminal ( Figure 3 Specifically, the voltage regulating circuit 114 includes a first resistance unit Rx, a second resistance unit Ry and a regulating unit.

[0037] The first end of the first resistor unit Rx is coupled to GND. The second end of the first resistor unit Rx ( Figure 3 D) and the second input terminal of the LDO ( Figure 3 The second end of the first resistor unit Rx ( Figure 3 D) and the first end of the second resistor unit Ry ( Figure 3 The second end ( Figure 3 D) is coupled to the output of the LDO ( Figure 3 The regulating unit is an N-type MOS transistor M1. The first end of M1 is coupled to the first end of the first resistor unit Rx; the second end of M1 is coupled to the second end of the first resistor unit Rx ( Figure 3The gate of M1 is coupled to the second end of the digital circuit 102. Based on the second end of the digital circuit 102 ( Figure 3 The MOS tube M1 can adjust the second end of the first resistor unit Rx ( Figure 3 The voltage difference between the first terminal and the second terminal of the digital circuit 102 is within a preset voltage range, so that the digital circuit 102 works normally.

[0038] Specifically, through the N-type MOS tube M1, which has a lower threshold voltage VTN (about 100-200mV). The source of M1 is connected to AVSS, and the drain is coupled to the second end of the first resistor unit Rx ( Figure 3 The gate is connected to the second terminal of the digital circuit 102 ( Figure 3 F in.

[0039] When the digital power consumption is small, IL is small, VSS is much smaller than VTN, M1 is turned off, DVDD_L≈1.2V, and the power generation circuit 200 is not affected.

[0040] When the digital power consumption is large and IL increases, when VSS>VTN, M1 starts to conduct, and its on-resistance is set to Rn, then the DVDD output voltage is: DVDD=REF × [1+Ry / (Rx')]; where Rx'=Rx / / Rn (i.e., the parallel resistance of Rx and Rn). Rx'< Rx, that is, DVDD increases. Therefore, while VSS is raised, the DVDD output voltage is also increased accordingly. And the on-resistance Rx' of M decreases with the increase of VSS, that is, the larger the load current IL, the higher the VSS rises, the smaller Rx', and the higher the increase of DVDD. By reasonably designing the size of NMOS, the voltage difference DVDD_L between the first end and the second section of the digital circuit 102 can be maintained unchanged. Therefore, when the digital power consumption is small, DVDD maintains the original voltage, and when the digital power consumption is large, the DVDD output voltage value can be dynamically adjusted, thereby avoiding the undervoltage risk of the digital circuit 102 caused by the VSS rise.

[0041] In another embodiment, Figure 3 The embodiment is similar to Figure 4 As shown, the adjustment unit includes a P-type MOS transistor M2; the first end of M2 is coupled to the first end of the second resistor unit Ry; the second end of M2 is coupled to the second end of the second resistor unit Ry; the gate of M2 is coupled to the second end of the digital circuit 102. The size of the resistor Ry' is controlled by M1 to dynamically adjust the DVDD output voltage value; Ry'=Rx / / Rn (i.e., the parallel resistance of Ry and Rn), and Rn is the impedance of M1.

[0042] In another embodiment, the regulating unit includes multiple sets of second N-type MOS transistors and third resistors connected in series. Each set of the second N-type MOS transistors and the third resistors are connected in parallel; each set of the second N-type MOS transistors and the third resistors are coupled to the first end of the first resistor Rx unit; the second ends of each set of the second N-type MOS transistors and the third resistors are coupled to the second end of the first resistor unit Rx; the closing and opening of the second N-type MOS transistors are controlled by the second voltage at the second end of the digital circuit 102.

[0043] Specifically, as Figure 5 shown, the second N-type transistor Ma and the third resistor Ra are connected in series; the second N-type transistor Mb and the third resistor Rb are connected in series; the second N-type transistor Mc and the third resistor Rc are connected in series; the series connection of the second N-type transistor Ma and the third resistor Ra, the series connection of the second N-type transistor Mb and the third resistor Rb, and the second N-type transistor Mc and the third resistor Rc are connected in parallel. The gates of Ma, Mb, and Mc are connected to VSS. For example, the threshold voltages of Ma, Mb, and Mc are selected as VTN1 = 100 mV, VTN2 = 200 mV, and VTN3 = 300 mV.

[0044] When the digital power consumption is small, IL is small, and VSS < 100 mV, Ma, Mb, and Mc are turned off. DVDD_L ≈ 1.2 V. The power generation circuit 200 is not affected.

[0045] When the digital power consumption gradually increases and 100 mV < VSS < 200 mV, M1 is turned on, and M2 and M3 are turned off. At this time, Ra is connected in parallel with Rx, and the DVDD output voltage is: DVDD = REF × [1 + Ry / (Rx / / Ra)].

[0046] And so on. When 200 mV < VSS < 300 mV, DVDD = REF × [1 + Ry / (Rx / / Ra / / Rb)]; when 300 mV < VSS < 400 mV, DVDD = REF × [1 + Ry / (Rx / / Ra / / Rb / / Rc)]. The voltage of DVDD at high power consumption can be adjusted by designing the resistance values of the resistors Ra, Rb, and Rc.

[0047] In another embodiment, in Figure 5The embodiment is similar to that of the embodiment. Similarly, the same effect can be achieved by using a P-type MOS transistor instead of an N-type MOS transistor. The regulating unit includes a plurality of groups of second P-type MOS transistors and third resistors connected in series; the second P-type MOS transistors and the third resistors of each group are connected in parallel; the second P-type MOS transistors and the third resistors of each group are coupled to the first end of the second resistor unit Ry; the second end of the second P-type MOS transistors and the third resistors of each group are coupled to the second end of the second resistor unit Ry; the closing and opening of the second P-type MOS transistors are controlled by the second voltage of the second end of the digital circuit 102.

[0048] Specifically, Figure 6 As shown, the second P-type MOS transistor Mu and the third resistor Ru are connected in series; the second P-type MOS transistor Mv and the third resistor Rv are connected in series; the second P-type MOS transistor Mw and the third resistor Rw are connected in series; the gates of Mu, Mv and Mw are connected to VSS.

[0049] In another embodiment, if Figure 7 As shown, the regulating unit includes a detection unit (VSS_DET) 115; one end of the detection unit 115 is connected to the second end of the digital circuit 102 ( Figure 7 F) is coupled to detect the second voltage VSS of the second end of the digital circuit 102; the detection unit 115 may include common functions such as voltage detection and digital-to-analog conversion to improve the detection accuracy of VSS. The detection unit 115 adjusts the resistance value of the first resistance unit Rx and the resistance value of the second resistance unit Ry based on the second voltage VSS, thereby adjusting the first voltage DVDD so that the first end ( Figure 7 The detection unit 115 can generate a plurality of adjustment signals to more finely control the resistance value or voltage division ratio of the first resistance unit Rx and the second resistance unit Ry, thereby more accurately and dynamically adjusting the DVDD.

[0050] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although it is not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention. It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as an example and not a limitation, the alternative configurations of the embodiments of the present invention may be considered to be consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A power generation circuit, characterized in that: include: A first circuit, a second circuit coupled to the first circuit, and a voltage regulating circuit; The first circuit is used to generate a first voltage and output it to a first end of the second circuit; The voltage regulating circuit is used to regulate the first voltage according to a second voltage at the second end of the second circuit so that the voltage difference between the first end and the second end of the second circuit is within a preset voltage range.

2. The power generation circuit according to claim 1, wherein: The first circuit comprises: A reference voltage generating circuit; the output end of the reference voltage generating circuit outputs a reference voltage; A low voltage dropout linear regulator; the low voltage dropout linear regulator comprises a first input terminal, a second input terminal and an output terminal; The first input terminal of the low voltage drop linear regulator is coupled to the output terminal of the reference voltage generating circuit; The first terminal of the voltage regulating circuit is coupled to the second input terminal of the low voltage drop linear regulator; The second terminal of the voltage regulating circuit is coupled to the output terminal of the low voltage drop linear regulator; The third terminal of the voltage regulating circuit is coupled to the second terminal of the digital circuit module.

3. The power generation circuit according to claim 2, characterized in that: The second terminal of the second circuit is coupled to the ground; The voltage regulating circuit at least comprises a first resistance unit, a second resistance unit and a regulating unit connected in series; The first end of the first resistor unit is coupled to the ground end; The second end of the first resistance unit is coupled to the second input end of the low voltage difference linear regulator and the first end of the second resistance unit; The second end of the second resistor unit is coupled to the output end of the low voltage drop linear regulator; Based on the second voltage at the second end of the second circuit, the adjusting unit adjusts the third voltage at the second end of the first resistance unit, thereby adjusting the first voltage.

4. The power generation circuit according to claim 3, characterized in that: The regulating unit comprises a first N-type MOS transistor; A first terminal of the first N-type MOS transistor is coupled to a first terminal of the first resistance unit; The second end of the first N-type MOS transistor is coupled to the second end of the first resistance unit; A gate of the first N-type MOS transistor is coupled to a second end of the second circuit.

5. The power generation circuit according to claim 3, characterized in that: The regulating unit comprises a first P-type MOS transistor; A first end of the first P-type MOS transistor is coupled to a first end of the second resistance unit; The second end of the first P-type MOS transistor is coupled to the second end of the second resistance unit; A gate of the first P-type MOS transistor is coupled to a second end of the second circuit.

6. The power generation circuit according to claim 3, characterized in that: The regulating unit includes a plurality of sets of second N-type MOS transistors and third resistors connected in series; The second N-type MOS transistor and the third resistor of each group are connected in parallel; The second N-type MOS transistor and the third resistor of each group are coupled to the first end of the first resistor unit; The second end of each group of the second N-type MOS transistor and the third resistor is coupled to the second end of the first resistor unit; The closing and opening of the second N-type MOS transistor is controlled by a second voltage at the second end of the second circuit.

7. The power generation circuit according to claim 3, characterized in that: The regulating unit includes a plurality of sets of second P-type MOS transistors and third resistors connected in series; The second P-type MOS transistor and the third resistor of each group are connected in parallel; The second P-type MOS transistor and the third resistor of each group are coupled to the first end of the second resistor unit; The second end of each group of the second P-type MOS transistor and the third resistor is coupled to the second end of the second resistor unit; The closing and opening of the second P-type MOS transistor is controlled by a second voltage at the second end of the second circuit.

8. The power generation circuit according to claim 3, characterized in that: The regulating unit includes a detecting unit; One end of the detection unit is coupled to the second end of the second circuit, and is used to detect a second voltage at the second end of the second circuit; The detection unit adjusts the resistance values ​​of the first resistance unit and the second resistance unit based on the second voltage, thereby adjusting the first voltage so that the voltage difference between the first end and the second end of the second circuit is within a preset voltage range.

9. The power generation circuit according to claim 3, characterized in that: There is impedance in the wiring between the second end of the second circuit and the ground end.

10. The power generation circuit according to claim 1, wherein: The first circuit is an analog circuit; the second circuit is a digital circuit.

11. A display driving circuit, characterized in that: The method comprises a power generation circuit as claimed in any one of claims 1 to 10.

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