Semiconductor device

Abstract

One embodiment of the present disclosure relates to a device. The device includes a memory macro having a front side and a back side in a vertical direction. The memory macro includes edge band regions extending longitudinally in a first direction at an edge of the memory macro, a memory cell region having a plurality of memory cells, and an intermediate band region extending lengthwise in the first direction and disposed between the edge band regions in a second direction, wherein the memory cell region is arranged between the edge band regions in a second direction perpendicular to the first direction, and the intermediate band region divides the memory cell region into two memory cell domains. The intermediate band region includes a feed-through circuit routing a power supply signal line of one of the plurality of memory cells to a back surface of the memory macro.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to semiconductor devices. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more increasingly complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power ICs. To date, these goals have been achieved in large part by reducing IC size (e.g., minimum IC feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of IC manufacturing processes. Therefore, achieving continued advancements in IC devices and their performance requires similar advances in IC manufacturing processes and technologies.

[0003] As technology nodes become smaller, power signals may be routed to the back side of semiconductor devices to optimize power and chip space. For example, a memory device such as a static random access memory (SRAM) device can have its bit cell active area connected to a back side via, which is then routed to a corresponding back side metal line electrically connected to a high voltage power supply Vdd or a low voltage power supply Vss (or ground). However, for high-density memory cells with smaller active areas, the back side vias may be blocked or not properly formed due to process limitations. This is because the back side vias are limited by the critical dimensions of the active area. In this case, power signals such as Vdd and Vss cannot be provided from the back side. Instead, the power signal is provided from the front side to the back side only from the edge band area of ​​the memory macro. However, the long wiring starting from the edge of the memory macro produces high resistance and reduces the Vmax of the power supply voltage (e.g., write voltage).

[0004] Thus, while existing structures for providing power routing from edge strap regions (ie, the edges of memory macros) are generally adequate for their intended purposes, they are not completely satisfactory in every respect. Summary of the invention

[0005] An embodiment of the present invention provides a semiconductor device, comprising: a memory macro having a front side and a back side along a vertical direction, wherein the memory macro comprises: an edge band region extending longitudinally along a first direction at an edge of the memory macro, a memory cell region having a plurality of memory cells, wherein the memory cell region is arranged between the edge band regions along a second direction perpendicular to the first direction, and an intermediate band region extending longitudinally along the first direction and arranged between the edge band regions along the second direction, wherein the intermediate band region divides the memory cell region into two memory cell domains, and the intermediate band region comprises a feed-through circuit, wherein the feed-through circuit routes a power signal line of one of the plurality of memory cells to the back side of the memory macro.

[0006] Another embodiment of the present invention provides a semiconductor device, comprising: a memory macro having a front side and a back side along a vertical direction, wherein the memory macro comprises: a memory cell region having a plurality of memory cells, an edge band region adjacent to a first side of the memory cell region, the edge band region extending longitudinally along a first direction at an edge of the memory macro, and an intermediate band region within the memory cell region, the intermediate band region extending longitudinally along the first direction, wherein the intermediate band region divides the memory cell region into two memory cell domains, wherein the intermediate band region comprises a feed-through circuit, the feed-through circuit routing a power signal line of one of a plurality of memory cells to the back side of the memory macro, wherein the intermediate band region spans a first width along a second direction perpendicular to the first direction, and the edge band region spans a second width along the second direction, the first width being the distance between the two memory cell domains, and the first width is greater than the second width.

[0007] Another embodiment of the present invention provides a semiconductor device, comprising: a memory macro having a plurality of memory cells, the memory macro having a front side and a back side; an intermediate band region arranged between two of the plurality of memory cells, the intermediate band region comprising a vertical metal wiring, the vertical metal wiring being electrically connected to a power signal line of one of the plurality of memory cells on the back side of the memory macro; an edge band region located on an edge of the memory macro, wherein the intermediate band region is located between the edge band regions, wherein the edge band region further comprises a vertical metal wiring, the vertical metal wiring electrically connects the power signal line of the one of the plurality of memory cells to the back side of the memory macro; and a logic circuit region adjacent to the memory macro, the logic circuit region having a plurality of logic cells adjacent to the edge band region, wherein the logic cells and the memory cells have active regions with different configurations. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the present invention and therefore should not be considered as limiting the scope, as the present invention is equally applicable to other embodiments. In addition, the accompanying drawings may implicitly describe components that are not explicitly described in the detailed description.

[0009] Figure 1 A device having an SRAM circuit region (or memory macro) with an intermediate band region between edge band regions is shown according to one embodiment of the present disclosure.

[0010] Figure 2 An embodiment according to the present disclosure is shown as Figure 1 Circuit diagram of the SRAM array in the memory macro section.

[0011] Figures 3 to 7 A top view device layout of an SRAM array according to one embodiment of the present disclosure is shown. Figure 1 The SRAM circuit area is part of Figure 2 The circuit diagram corresponds to .

[0012] Figure 8 A top view and a cross-sectional view of an SRAM circuit region having an intermediate band region between edge band regions according to one embodiment of the present disclosure are shown.

[0013] 9A to 9C A top view of an SRAM circuit region with an even number of domains between strap regions is shown according to one embodiment of the present disclosure.

[0014] Fig.9D A graph is shown showing the improvement in voltage drop according to the number of domains in the SRAM circuit area.

[0015] FIG. 10A to FIG. 10B A top view of an SRAM circuit region with an odd number of domains between strap regions is shown according to one embodiment of the present disclosure.

[0016] Fig.11A A top view of an IC structure (or device) having an SRAM circuit region with two edge band regions according to an embodiment of the present disclosure is shown.

[0017] Fig. 11B A top view of an IC structure (or device) having an SRAM circuit region with one edge band region according to an embodiment of the present disclosure is shown.

[0018] Fig. 12A A top view of an IC structure (or device) having an SRAM circuit region with a plurality of intermediate band regions between edge band regions according to one embodiment of the present disclosure is shown.

[0019] Fig. 12B The embodiment according to the present disclosure is shown Fig. 12A A magnified top view of the middle band area between the SRAM arrays of the SRAM circuit area.

[0020] Fig. 12C The embodiment according to the present disclosure is shown Fig. 12A A magnified top view of the edge band area between the SRAM circuit area and the logic device circuit area.

[0021] Fig.13A A top view of a mid-band region in a SRAM circuit region according to an embodiment of the present disclosure is shown.

[0022] Fig. 13B The embodiment according to the present disclosure is shown Fig.13A A cross-sectional view of the feed-through circuit region of the mid-band region. DETAILED DESCRIPTION

[0023] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0025] In addition, when "approximately," "approximately," "substantially," etc. are used to describe a number or a series of numbers, the term is intended to include numbers within a reasonable range including the number, such as within + / -10% of the number, or other values ​​understood by a person skilled in the art. For example, the term "about 5nm" may include a size range of 4.5nm to 5.5nm, where the manufacturing tolerance associated with the deposited material layer is known to a person of ordinary skill in the art as + / -10%. When comparing the size or size of a component to another component, the phrases "substantially the same," "essentially the same," "similar in size," etc. may be understood to be within + / -10% between the compared components. In addition, the disclosed dimensions of different components may implicitly disclose the size ratios between the different components.

[0026] The present disclosure relates to semiconductor devices, and more particularly to memory devices, such as static random access memory (SRAM) devices having intermediate band regions between edge band regions. The edge band region defines the edge boundary of a memory macro. The memory macro includes a plurality of memory cells, such as an SRAM cell array, each of which has a plurality of metal wirings, including a power line connection connected to a power source or ground. These power line connections are electrically connected to source / drain (S / D) components in the SRAM cell and provide wiring for power pull-up and pull-down transistors of the memory macro. For back power wiring, the power can be routed from the back of the memory macro through the edge band region, or from one or more intermediate band regions embedded in the memory macro. Note that the edge band and intermediate band regions do not contain any SRAM cells. Instead, they include vertical metal wiring to route power signals from the front of the memory device to the back of the memory device. The advantages of combining the intermediate band region (in addition to the existing edge band region) include high-density current discharge and an increased write voltage (Vmax) due to shorter power signal wiring. Compared with no intermediate band region, the Vmax improvement can be greater than 200mV.

[0027] As explained in more detail with reference to the accompanying drawings, the intermediate band area can divide the memory macro into multiple domains. In one embodiment, each domain can include 32, 62, 128 or 256 bit cells according to the number of intermediate band areas of a 512-bit memory macro. Each intermediate band area includes a feed-through circuit that routes the power signal line from the front of the memory macro to the back of the memory macro. The power signal line includes a front metal part that electrically connects the source / drain component of the memory cell to the front metal line. The front metal line is then electrically connected to the back metal line under the memory macro through the feed-through circuit in the intermediate band area. Then, the back metal line can be electrically connected to the high voltage power supply Vdd or the low voltage power supply Vss (or ground). In various embodiments, the memory macro can be divided into an even number of domains by an odd number of intermediate band areas, or the memory macro can be divided into an odd number of domains by an even number of intermediate band areas. In various embodiments, the memory macro can be sandwiched between each logic circuit area, wherein the edge band area separates the memory cell in the memory macro from the logic cell in the logic circuit area. In various embodiments, one side of the memory macro may have only one edge band region, while on the other side of the memory macro, the memory cells in the memory macro directly abut the logic cells in the logic circuit region without an intermediate edge band region.

[0028] The present disclosure also contemplates having backside vias that connect the source / drain components in the memory cell directly to the backside metal lines. The backside metal lines are then routed to Vdd or Vss. However, for high-density memory cells with smaller active areas (e.g., active areas with a width of 10nm or less), some backside vias may be blocked or not formed correctly due to process limitations caused by overlay offset or insufficient penetration. In this case, power signals such as Vdd and Vss cannot be provided through the backside vias. Instead, the power signal is provided from the front to the back only from the edge band area of ​​the memory macro. However, the long wiring starting from the edge of the memory macro produces high resistance and reduces the Vmax of the power supply voltage (e.g., write voltage). By adding an intermediate band area to the memory macro, the wiring can be shortened, thereby reducing resistance and increasing Vmax.

[0029] The focus of this disclosure is to provide power routing to the back of the memory device to improve the process window and power performance. However, in addition to providing power line connections to the back of the memory device, power line connections can also be provided from the front of the memory device for double-sided power routing. In some cases, double-sided power routing can reduce power consumption by more than 30% for better power performance.

[0030] Figure 1A device 100 is shown with an SRAM circuit region 200, which is also referred to as a memory macro 200. The device 100 may be a memory device integrated with a logic component. Alternatively, the device 100 may be part of a microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a digital signal processor (DSP). The exact functionality of the device 100 is not limited to what is provided. The memory macro 200 may be a single-port SRAM macro, a dual-port SRAM macro, or other types of memory macros. The memory macro 200 includes a memory cell region 102 having an array memory cell 104 storing memory bits (e.g., 512 SRAM cells for storing 512 bits). In this embodiment, a single memory bit is stored in a single memory cell 104. The memory cell region 102 contains all memory bits (implemented as transistors) of the memory macro 200. The device 100 may also include a peripheral logic circuit 300 (along the x direction) adjacent to the memory macro 200 for implementing various functions such as write and / or read address decoders, word / bit selectors, data drivers, memory self-tests, and the like. The logic circuit 300 includes a logic cell area 103 that may include a standard logic cell array for implementing input / output (I / O) blocks. Each memory bit and logic circuit may be implemented with various PMOS and NMOS transistors, such as planar transistors, FinFETs, gate-all-around (GAA) nanosheet transistors, GAA nanowire transistors, or other types of transistors. In addition, the memory macro 200 and logic circuit 300 may include various contact features (or contacts), vias, and metal lines for connecting the source, drain, and gate electrodes (or terminals) of the transistors to form an integrated circuit.

[0031] Still refer to Figure 1 , the memory macro 200 includes two edge band regions 400. The edge band regions 400 are located at the edges of the memory macro in the x direction and extend longitudinally in the y direction. The memory macro 200 also includes one or more intermediate band regions 500 arranged laterally between the edge band regions 400 in the x direction. For simplicity, only one intermediate band region 500 is shown. The edge band regions 400 and the intermediate band regions 500 do not contain storage bits and are used to route power signal lines from the front side of the device 100 to the back side. Therefore, the edge band regions 400 and the intermediate band regions 500 do not contain any transistors associated with implementing any memory cell 104.

[0032] Still refer to Figure 1, the middle band region 500 may have a first width x1 along the x-direction, the edge band region 400 may have a second width x2 along the x-direction, and the first width x1 is greater than the second width x2. This is because the middle band region 500 requires a larger (or more) buffer than the edge band region 400. The buffer refers to the idle area at the edge of the middle band region 400 and the edge band region 500 (not shown). The buffer provides metal wiring and is also isolated from the active transistors in the memory cell region 102 and the logic cell region 103. The buffer disposed near the memory cell region 102 may require a larger spacing than the buffer disposed near the logic cell region 103. This is because memory cell wiring and isolation may be more sensitive than logic cell wiring and insulation. In some embodiments, for the edge band region 400, there is no buffer adjacent to the logic cell region 103. Therefore, since one side of the edge zone region 400 is adjacent to the logic cell region 103 and both sides of the middle zone region 500 are adjacent to the memory cell region 102 , the span of the middle zone region 500 in the x direction may be wider than that of the edge zone region 400 .

[0033] Still refer to Figure 1 , the edge band region 400 and the middle band region 500 do not include any well taps or well pick-up structures for providing voltage (or bias) to the N-well and P-well in the memory macro 200. Well taps are not required because the device 100 is a back-side power device with back-side interconnect components. Therefore, when forming the device 100, the back side of the device 100 is ground so that the N-well and P-well are discontinuous and fully isolated from each other. As described herein, the edge band region 400 and the middle band 500 include a feed-through circuit structure electrically connected between the front and back sides of the device 100, rather than having a well tap structure.

[0034] Figure 2 Shown as Figure 1 1 is a circuit diagram of a portion of an SRAM array of a memory macro 200 in FIG. More specifically, the circuit diagram corresponds to an SRAM array of four memory cells 104 (or SRAM cells 104) in a memory cell region 102 of the memory macro 200. The SRAM array includes SRAM cells 104a, 104a', 104b, and 104b'. Each of the SRAM cells 104a, 104a', 104b, and 104b' is formed by six transistors (two pull-down transistors, two pull-up transistors, and two pass-gate transistors). Each transistor is defined by a source, a drain, and a gate. Each SRAM cell 104 stores one bit of storage data through a pull-down and pull-up transistor, and the SRAM cell is addressed by a word line and a bit line through a pass-gate transistor.

[0035] The SRAM cell 104a includes pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and pass-gate transistors PG1 and PG2. The sources of PU1 and PU2 are coupled together and connected to a high voltage Vdd. The sources of PD1 and PD2 are coupled together and connected to a low source voltage Vss or ground. The gates of PU1 and PD1 are coupled together and connected to a common drain of PU2, PD2, and PG2. The gates of PU2 and PD2 are coupled together and connected to a common drain of PU1, PD1, and PG1. PU1, PU2, PD1, and PD2 form a first set of cross-coupled inverters to store data bits. The source of PG1 is connected to a first bit line BL1, and the source of PG2 is connected to a first inverted bit line BLB1. The gates of PG1 and PG2 are connected to a first word line WL_A.

[0036] The SRAM cell 104b includes pull-up transistors PU3 and PU4, pull-down transistors PD3 and PD4, and transfer gate transistors PG3 and PG4. The sources of PU3 and PU4 are coupled together and connected to a high voltage Vdd. The sources of PD3 and PD4 are coupled together and connected to a low voltage Vss or ground. The gates of PU3 and PD3 are coupled together and connected to a common drain of PU4, PD4, and PG4. The gates of PU4 and PD4 are coupled together and connected to a common drain of PU3, PD3, and PG3. PU3, PU4, PD3, and PD4 form a second set of cross-coupled inverters to store data bits. The source of PG3 is connected to the same first bit line BL1, and the source of PG4 is connected to the same first inverted bit line BLB1. The gates of PG3 and PG4 are connected to a second word line WL_B.

[0037] The configuration of SRAM cells 104a' and 104b' is similar to that of corresponding SRAM cells 104a and 104b. SRAM cell 104a' includes pull-up transistors PU1' and PU2', pull-down transistors PD1' and PD2', and transfer gate transistors PG1' and PG2'. SRAM cell 104b' includes pull-up transistors PU3' and PU4', pull-down transistors PD3' and PD4', and transfer gate transistors PG3' and PG4'. For the sake of brevity, similar configurations and connections will not be repeated. SRAM cells 104a' and 104b' include third and fourth groups of cross-coupled inverters, each group of inverters storing one data bit. The sources of PG1' and PG3' are connected to the second bit line BL2. The sources of PG2' and PG4' are connected to the second inverted bit line BLB2. SRAM cell 104a' shares the same first word line WL_A with SRAM cell 104a, and SRAM cell 104b' shares the same second word line WL_B with SRAM module 104b. That is, the gates of pass gate transistors PG1' and PG2' are also connected to the first word line WL_A, and the gates of pass gate transistors PG3' and PG4' are also connected to the second word line WL_B.

[0038] Notice, Figure 2 An example embodiment of an SRAM array is shown, but other configurations are also possible. For example, in other embodiments, the source and drain nodes of different pull-up and pull-down transistors can be exchanged. In addition, Vdd and Vss nodes can also be exchanged. In other words, in some embodiments, a high voltage Vdd can be connected to a source or drain in any one of the pull-up and pull-down transistors of the SRAM array. In other embodiments, a low voltage Vss or ground can be connected to a source or drain in any one of the pull-up and pull-down transistors of the SRAM array. Therefore, the electrical connector to Vdd and to Vss is referred to as a power line, a power signal line, or a power line connector in this article, which provides the wiring of the power pull-up and pull-down transistors of the memory macro 200 in the device 100.

[0039] Figure 3 Shown as Figure 1 2 is a top-view device layout 202 of an SRAM array of a portion of a memory macro 200 in FIG. 2. More specifically, the top-view device layout 202 corresponds to an SRAM array of eight memory cells 104 (or SRAM cells 104) in the memory cell region 102 of the memory macro 200. The device layout 202 includes SRAM cells 104a, 104a', 104b, and 104b' defined by dashed cell boundaries. The SRAM cells 104a, 104a', 104b, and 104b' may correspond to Figure 22. The SRAM cells 104a, 104b, 104a' and 104b' in the device layout 202. The SRAM cells 104a and 104a' are adjacent to each other in the y-direction and are mirror images of each other at the horizontal cell boundary between them. The SRAM cells 104b and 104b' are adjacent to each other in the y-direction and are mirror images of each other at the horizontal cell boundary between them. The SRAM cells 104a and 104b are adjacent to each other in the x-direction and are mirror images of each other at the vertical cell boundary between them. The SRAM cells 104a' and 104b' are adjacent to each other in the x-direction and are mirror images of each other at the vertical cell boundary between them. As shown, the device layout 202 may include additional SRAM cells 104 adjacent to and mirror images of the SRAM cells 104a, 104a', 104b and 104b'.

[0040] Figure 3 The location of each transistor PU1, PU1', PU2, PU2', PU3, PU3', PU4, PU4', PD1, PD1', PD2, PD3, PD3', PD4, PD4', PG1, PG1', PG2, PG2', PG3, PG3', PG4 and PG4' is shown (marked on the gate 108 of each transistor). How each transistor is connected to each other has been referred to. Figure 2 has been described and will not be repeated here for the sake of brevity.

[0041] The device layout 202 includes a plurality of active regions 106 extending along the x-direction on the front side of the device 100. The active region 106 may be configured as a planar, fin, or all-around gate semiconductor structure. In one embodiment, the active region 106 is a fin structure protruding from the substrate along the positive z-direction. Some active regions 106 may extend longitudinally across the vertical cell boundary, thereby sharing the same active region between the SRAM cells 104. The active region 106 may include an n-type active region 106a for forming a pull-down and transfer gate transistor and a p-type active region 106b for forming a pull-up transistor. The length of the p-type active region 106b extending along the x-direction is shorter than that of the n-type active region 106a. As shown, the p-type active region 106b is discontinuous and spans a length less than the width of two SRAM cells 104 at most along the x-direction. On the other hand, the n-type active region 106a may continuously span the entire memory cell region 102 (shown here as spanning the entire device layout 202) in the x-direction. A plurality of gates 108 are disposed over the channel region of the active region 106. The channel region (or transistor channel) refers to the portion of the active region 106 directly below the gate 108. The gates 108 extend longitudinally in the y-direction. Some gates 108 may extend across horizontal cell boundaries to span the active regions 106 of different SRAM cells.

[0042] The device layout 202 also shows several backside vias 115 that penetrate from the backside of the memory macro 200 and land on the source / drain (S / D) region of the active area 106. The S / D region is the region adjacent to the channel region below the gate 108. The S / D region may refer to the source or drain individually or collectively, depending on the context. For the n-type active region 106a, the S / D region may include an epitaxial component doped with an n-type dopant, such as phosphorus or arsenic. For the p-type active region 106b, the S / D region may include an epitaxial component doped with a p-type dopant, such as boron. The epitaxial component may be grown from a semiconductor material using a suitable epitaxial growth technique.

[0043] The backside via 115 electrically connects the source (or drain in other embodiments) of the active area 106 to the backside power line, which is then routed to Vss or Vdd. The backside via 115 includes a suitable metal, such as tungsten. In the illustrated embodiment, the backside via 115 falls on the backside of the source epitaxial component of the pull-down transistor (e.g., PD1 to PD4 and PD1' to PD4'), which is then routed to Vss. Alternatively or in addition, the backside via 115 falls on the backside of the source epitaxial component of the pull-up transistor (e.g., PU1-PU4 and PU1'-PU4'), which is then routed to Vdd. However, for high-density memory cells, the active area 106 may be too small to uniformly form the backside vias 115. For example, when the active region 106 has a width of 10 nm or less along the y-direction, some backside vias 115 may be blocked or improperly formed due to missing the S / D regions or not passing through the S / D regions (as indicated by the X symbol). Therefore, in addition to or in lieu of the backside vias 115, the present disclosure also contemplates providing backside power connections through feedthrough circuits in the edge strips 400 and the middle strip regions 500.

[0044] Figure 4 A top view device layout 202 is shown, which shows the Figure 1 The S / D contacts 112 and S / D vias 116 of a portion of the memory macro 200 (specifically, the memory cell region 102) are shown. Figure 4 Corresponds to Figure 3 , for the sake of brevity, similar parts will not be repeated. The difference is that Figure 4 S / D contacts 112 and S / D vias 116 are shown, and Figure 3The backside vias 115 in the memory macro 200 are omitted (for simplicity). The S / D contacts 112 are disposed above and fall on the S / D regions of the active region 106, some of which are slot contacts extending in the y direction to couple the S / D regions of different transistors together (for example, a single S / D contact 122 wires the S / D regions of transistors PD1, PD1', PD3, and PD3' together). The S / D vias 116 are disposed above and fall on the S / D contacts 112. The S / D vias 116 may also be referred to as front side vias 116 because they are vias formed on the front side of the memory macro 200. The S / D vias 116 (or front side vias 116) allow the S / D contacts 112 to be electrically coupled to a material layer higher in the z direction.

[0045] Figure 5 A top view device layout 202 is shown, which shows the Figure 1 The first metal line M1 of a portion of the memory macro 200 (specifically, the memory cell region 102) in FIG. Figure 5 Corresponds to Figure 4 , for the sake of brevity, similar parts will not be repeated. The difference is that Figure 5 A first metal line M1 extending longitudinally along the x direction is shown. The first metal line M1 is disposed above and falls on the front through hole 116. As shown, some of the first metal lines M1 extend across multiple front through holes 116 to wire across the same node connection of multiple SRAM cells 104. These metal lines M1 can wire together the S / D components of several pull-up transistors, or wire together the S / D components of several pass gate transistors. Some of the metal lines M1 extend only through a single front through hole 116 to wire only connections from a single front through hole 116. Since the narrow S / D contact 112 below couples multiple S / D regions together, these metal lines M1 can still wire together the S / D components of several pull-down transistors. Note that the width of the metal line M1 that only extends across a single front through hole 116 in the y direction can be less than the width of the metal line M2 that extends across multiple front through holes 16. As shown, there can also be other metal lines M1 that fall on the gate 108 and / or are coupled to the gate 108.

[0046] Figure 6 A top view device layout 202 is shown, which shows the Figure 1 The first interconnection via V1 and the second metal line M2 of a portion of the memory macro 200 (specifically, the memory cell region 102) are shown in FIG. Figure 6 Corresponds to Figure 5 , for the sake of brevity, similar parts will not be repeated. The difference is that Figure 6A first interconnection line via V1 falling on the first metal line M1 and a second metal line M2 falling on the first interconnection line via V1 are shown. In addition, for simplicity, components under the first metal line M1 (e.g., front via 116, S / D contact 112, etc.) are omitted. The first interconnection via V1 may have a size similar to the front via 116. The first interconnection via V1 allows the first metal line M1 to be electrically coupled to a higher material and metal layer (i.e., the second metal line M2). The second metal line M2 extends longitudinally in the y direction above the first interconnection via V1. As shown, some of the second metal lines M2 extend through multiple first interconnection vias V1 to connect wiring across the same node of multiple SRAM cells 104 (e.g., connecting different gates 108 together to the same node). Some of the second metal lines M2 extend only across a single first interconnection via V1 to connect wiring only from a single first interconnection via V1. In the present embodiment, the second metal line M2 extending only across a single first interconnection via V1 corresponds to a metal line wired to a low voltage Vss or ground node. Although not shown, there may also be a second metal line M2 corresponding to a metal line routed to a high voltage Vdd node. The width of the second metal line M2 extending across only a single first interconnection via V1 in the x direction may be smaller than the width of the third metal line M2 extending across multiple first interconnection vias V1.

[0047] Figure 7 A top view device layout 202 is shown, which shows the Figure 1 The second interconnection via V2 and the third metal line M3 of the portion of the memory macro 200 (specifically, the memory cell region 102) in FIG. Figure 7 Corresponds to Figure 6 , for the sake of brevity, similar parts will not be repeated. The difference is that Figure 7A second interconnection through hole V2 falling on the second metal line M2 and a third metal line M3 falling on the second interconnection through hole V2 are shown. In addition, for simplicity, the components under the second metal line M2 (e.g., the first interconnection through hole V2, the first metal line M1, etc.) are omitted. The second interconnection through hole V2 may have a size similar to that of the first interconnection through hole V1. The second interconnection through hole V2 allows the second metal line M2 to be electrically coupled to a higher material and metal layer (i.e., the third metal line M3). The third metal line M3 extends longitudinally in the x direction above the second interconnection through hole V2. As shown, the third metal line M3 may extend across a plurality of second interconnection through holes V2 to connect wiring for the same node across a plurality of SRAM cells 104. The present embodiment only shows the third metal line M3 corresponding to the metal line wired to the low voltage Vss or the ground node. However, although not shown, there may also be a third metal line M3 corresponding to the metal line wired to the high voltage Vdd node. The third metal line M3 may continuously extend in the x direction from the memory cell region 102 to the edge band region 400 and the middle band region 500 of the memory macro 200. In other words, the third metal line M3 is a conductive wire connecting the memory cell region 102 with the edge band region 400 and the middle band region 500.

[0048] Figure 8 A top view 200a and a cross-sectional view 200b of an SRAM circuit region 200 (or memory macro 200) are shown. The top view 200a and the cross-sectional view 200b are aligned along the x-direction, as shown by the aligned positions of the corresponding edge band 400 and middle band regions 500. Figure 8 A middle band region 500 is shown between the two edge band regions 400. The middle band region 500 divides the memory macro 200 into two memory cell regions 102, each memory cell region having N / 2 cells for storing N / 2 bits. N is equal to the total number of memory cells 104 or memory bits in the memory macro 200. As shown, the middle band region 500 creates a shorter Vss (or Vdd) path to the backside power line (e.g., backside metal line BM1) for the memory cells 104 closer to the middle of the memory macro 200.

[0049] Referring to top view 200a, the middle memory cell 104 has a cell current Icell that travels to the middle band region 500 and the edge band region 400 for the backside Vss (or Vdd) power supply connection. The cell current Icell is improved by the additional and closer wiring provided by the middle band region 500. In this embodiment, the cell current Icell can be obtained from the second interconnect via V2 (e.g. Figure 7The third metal line M3 (shown in the figure) flows to the third metal line M3, wherein the third metal line M3 extends to the edge band area 400 and the middle band area 500 in the x-direction. The third metal line M3 is then electrically coupled to the feedthrough circuit 450 in the edge band area 400 and the feedthrough circuit 550 in the middle band area 500. The feedthrough circuits 450 and 550 then fall on the back metal line BM1 for back power wiring. The back metal line BM1 is disposed on the back side of the memory macro 200. The top view 200a also shows metal lines M4 and M5 above the metal line M3. The metal line M4 extends longitudinally along the y-direction and is connected to the metal line M3 through the third interconnection via V3 between the metal lines M3 and M4. The metal line M5 extends longitudinally along the x-direction and is connected to the metal line M4 through the fourth interconnection via V4 between the metal lines M5 and M4. The metal lines M4 and M5 can also route power signals to higher-level interconnects, and even to higher-level redistribution layers and pads on the front side of the memory macro 200.

[0050] Referring to the cross-sectional view 200b, the memory macro 200 includes a device layer DL in which the device-level components of the memory cell 104 are formed. The device layer DL includes an active region 106, a gate 108, an S / D contact 112, and a front via 116. The device layer DL also includes and embeds feedthrough circuits 450 and 550, which penetrate the device layer DL and are directly connected to the back metal, such as the back metal line BM1. The back metal line BM1 can be electrically connected to Vss as shown, or to Vdd in other embodiments. The first metal line M1 is arranged above the device layer (DL), for example, falling on the front via 116 and the feedthrough circuit 550 in the memory cell 104. The first interconnection via V1 falls on the first metal line M1. The second metal line M2 falls on the first interconnection via V1. The second interconnection via V2 falls on the second metal line M2. The third metal line M3 falls on the second interconnection via V2. The third metal line M3 is electrically connected to the feed-through circuits 450 and 550 at the edge band region 400 and the intermediate band region 500 through the second interconnection via V2, the second metal line M2, the first interconnection via V1, and the first metal line M1. The third interconnection via V3 falls on the third metal line M3. The fourth metal line M4 falls on the third interconnection via V3. The fourth interconnection via V4 falls on the fourth metal line M4. The fifth metal line M5 falls on the fourth interconnection via V4. Additional front metal lines and interconnection vias may be formed above the fifth metal line M5 (not shown) to form a front interconnection structure. A passivation structure (not shown) having a redistribution layer and a bonding pad may be formed above the front interconnection structure.

[0051] 9A to 9C A top view 200a of an SRAM circuit region 200 (or memory macro 200) is shown, including edge and / or middle band regions 400 and 500 with an even number of domains between band regions. Fig.9A In the embodiment of the present invention, the memory macro 200 has N bits, where N is 512. In this case, there is a middle band region 500 every N / 2 bits (i.e., 256 bits), thereby forming the middle band region 500 between the edge band regions 400. As shown in the figure, the memory macro 200 is divided into two domains of storage cell regions 102. Each storage cell region 102 has 256 storage bits, which are arranged between the edge band region 400 and the middle band region 500. Referring to Fig. 9B In the embodiment of the present invention, the memory macro 200 also has N bits, where N is 512. In this case, there is an intermediate band region 500 for every N / 4 bits (i.e., 128 bits), resulting in three intermediate band regions 500 between the edge band regions 400. As shown in the figure, the memory macro 200 is divided into four domains of storage cell regions 102. Each storage cell region 102 is arranged between an edge band region 400 and an intermediate band region 500, or between two intermediate band regions 500. Referring to Fig. 9C In the embodiment of the present invention, the memory macro 200 also has N bits, where N is 512. In this case, there is an intermediate band region 500 every N / 8 bits (i.e., 64 bits), resulting in seven intermediate band regions 500 between the edge band regions 400. As shown in the figure, the memory macro 200 is divided into eight domains of storage cell regions 102. Each storage cell region 102 is arranged between an edge band region 400 and an intermediate band region 500, or between two intermediate band regions 500. It should be noted that the present embodiment limits the memory macro 200 to having N bits, where N is 512. However, according to design requirements, N can be any other number (e.g., 256, 1024).

[0052] Fig.9D Graphs showing improvements in voltage drop according to the number of domains in the SRAM circuit region 200 (or memory macro 200) are shown. FIG. 9A to FIG. 9BAs shown, as the number of domains is increased by adding more intermediate band regions 500, the storage bits in each domain are reduced (e.g., from 512 to 64). As the storage bits in each domain are reduced, the resistance is also reduced due to the shorter current path to Vss and / or Vdd. As the resistance is reduced, the voltage drop in the Vss and / or Vdd current path is minimized, thereby maximizing Vmax to improve the unit current performance. For example, in the case where N=512 and there is no intermediate band region 500: there is only one domain with 512 bits. In this case, the resistance is the highest, resulting in the worst Vmax. In the case where N=512 and there is one intermediate band region 500: there are two domains, each with 256 bits. In this case, the resistance is lower and Vmax is higher than the single domain case. In the case where N=512 and there are three intermediate band regions 500: there are four domains, each with 128 bits. In this case, the resistance is lower and Vmax is higher than the case of two domains. In the case where N=512 and there are seven intermediate band regions 500: there are eight domains, each with 64 bits. In this case, the resistance is lower and Vmax is higher than the four domain case. At a certain point, adding more mid-band regions 500 has diminishing returns as Vmax approaches the ideal Vdd.

[0053] FIG. 10A to FIG. 10B A top view 200a of an SRAM circuit region 200 (or memory macro 200) is shown having an odd number of domains between band regions including edge band regions 400 and / or middle band regions 500. Fig. 10A In the embodiment of FIG. 1 , the memory macro 200 has N bits, and a middle band region 500 is provided every N / 3 bits, thereby generating three domains and two middle band regions 500 between the edge band regions 400. Note that, depending on the number N, each of the three domains may not have exactly the same number of bits. Fig. 10B In the embodiment of FIG. 4 , the memory macro 200 has N bits, and every N / 5 bits has a middle band region 500, resulting in five domains and four middle band regions 500 between the edge band regions 400. Note that, depending on the number N, each of the five domains may not have exactly the same number of bits. For any given N bits, other odd numbers of domains are possible, where the number of middle band regions 500 will be one less than the number of domains. For example, given Q domains that evenly (or substantially evenly) divide the N bits, there are (Q-1) middle band regions 500.

[0054] Fig.11AA top view 200a of an IC structure (or device 100) having an SRAM circuit region 200 (or memory macro 200) including two edge band regions 400 is shown. The memory macro 200 includes N bits implemented by N memory cells 104. And the memory macro 200 includes Q domains implemented by Q memory cell regions 102. The Q memory cell regions 102 are separated from each other by the middle band region 500. Each domain may include N / Q bits. In the illustrated embodiment, there are two edge band regions 400. One edge of each edge band region 400 is directly adjacent to the memory cell region 102 along the x direction. The other edge of each edge band region 400 is directly adjacent to the logic cell region 103 of the logic circuit 300 along the x direction. Therefore, each logic cell region 103 is isolated from the memory cell region 102 by the edge band region 400. In the present embodiment, each edge band region 400 spans the width along the x-axis direction from the memory cell region 102 to the logic cell region 103, and each middle band region 500 spans the width along the x-axis direction between the memory cell regions 102. As described above, both the edge band region 400 and the middle band region 500 provide backside power wiring for the memory cells 104 in the memory cell region 102. However, the edge band region 400 may additionally provide backside power wiring for the logic cells in the logic cell region 103.

[0055] Fig. 11B A top view 200 a of an IC structure (or device 100 ) having an SRAM circuit region 200 (or memory macro 200 ) including one edge band region 400 is shown. Fig. 11B Similar to Fig.11A , similar components will not be described again for the sake of brevity. The difference is that there is only one edge band region 400 instead of two. As shown in the figure, there is an edge band region 400 at one end of the memory macro 200, and there is no edge band region 400 at the other end of the memory macro 100. In this configuration, at one end of the memory macro 200, the storage cell region 102 is directly adjacent to the logic cell region 103, and there is no edge band region 400 in between. In addition to the domain directly adjacent to the logic circuit 300, each domain can include 2*N / (2Q-1) bits, and the domain directly adjacent to the logic circuit 300 can include N / (2-Q-1) bits. In other words, the size of the domain directly adjacent to the logic circuit 300 can be half the size of the domain that is not directly adjacent to the logic circuit 300.

[0056] Still refer to Fig. 11B, the middle band region 500 at the end of one side of the memory macro 200 provides backside power routing to the memory cell region 102 that is directly adjacent to the logic cell region 103. As an edge band of the logic cell region 103, the same middle band region 500 can also provide backside power routing to the logic cell region 103 itself. Therefore, at this end of the memory macro, the edge band region 400 is not needed. However, if the domain directly adjacent to the logic circuit 300 is too large (i.e., close to the size of other domains), a separate edge band region 400 may be needed to ensure that power routing is adequately provided. This is why the domain directly adjacent to the logic circuit 300 should be smaller than the other domains, for example half the size of the domain not directly adjacent to the logic circuit 300 or even less than half.

[0057] Fig. 12A A top view 200 a of an IC structure (or device 100 ) having an SRAM circuit region 200 (or memory macro 200 ) having a plurality of intermediate band regions 500 between edge band regions 400 is shown. Fig. 12A Also shown is a logic circuit 300 adjacent to the memory macro 200 . Fig. 12A Similar to Fig.11A For the sake of brevity, similar components will not be described again. The difference is that Fig. 12A The first interface region 250 and the second interface region 350 indicated by respective dashed boxes are shown. The first interface region 250 includes an intermediate band region 500 between the memory cell regions 102. The second interface region 350 includes an edge band region 400 between the memory cell region 102 and the logic cell region 103.

[0058] Fig. 12B Shows Fig. 12A FIG. 2 is an enlarged top view of the first interface region 250. Fig. 12B As shown, the intermediate band region 500 spans between the SRAM memory cell regions 102. Each of the SRAM memory cell regions 102 includes an n-type active region 106a, which extends longitudinally and continuously along the x-direction through the entire area of ​​the corresponding memory cell region. Each of the SRAM memory cell regions 102 includes a p-type active region 106b, which extends discontinuously along the x-direction through the memory cell region 102 (that is, each p-type active region 106b is isolated from each other along the x-direction passing through the memory cell region 102). In addition, the width of the n-type active region 106a along the y-direction can be greater than that of the p-type active region 106b. It should be noted that some of the n-type active regions 106a and the p-type active regions 106b extend into the buffer region of the intermediate band region 500. These n-type and p-type active regions 106a and 106b do not form transistor devices, but act as dummy extensions 503.

[0059] Still refer to Fig. 12B , the middle band region 500 may also include pseudo n-type active regions 506 that also do not form transistor devices. These pseudo n-type active regions 506 are aligned with the pseudo extensions 503 in the x-direction. However, the pseudo n-type active regions 406 are separated from the pseudo extensions 503 to form isolated active regions. In addition, the middle band region 500 includes a feed-through circuit 550 between the pseudo n-type active regions 506 along the y-direction. The feed-through circuit 550 provides vertical metal wiring to the back of the memory macro 200. The feed-through circuit 550 is also arranged between the buffers of the middle band region 500 along the x-direction. The buffer includes the above-mentioned pseudo extension 503.

[0060] Fig. 12C Shows Fig. 12A An enlarged top view of the second interface region 350 in FIG. Fig. 12C Included with Fig. 12B Similar components, for the sake of brevity, similar components will not be described again. The difference is the edge band region 400 between the SRAM storage cell region 102 and the logic cell region 103. The logic cell region 103 may include input / output (IO) and / or standard cell (STD) transistors for performing logic functions. The logic cell region 103 includes a logic cell active area 606, which is all longitudinally and continuously extended along the x direction over the entire logic cell region 104. The logic cell active area 606 can be a combination of n-type, p-type or n-type and p-type to form a logic transistor. The edge band region 400 includes components similar to the intermediate band region 500. For example, the edge band region 400 includes a feed-through circuit 450 between the pseudo n-type active regions 406 along the y direction. The feed-through circuit 450 provides a vertical metal wiring to the back of the memory macro 200. The feed-through circuit 450 is arranged between the buffers of the edge band region 400 along the x direction. The buffer includes a pseudo extension 403 extending from the storage cell region 102. In some embodiments (as shown), there is only one buffer along the side of the memory cell region 102. In this case, there is no buffer along the side of the logic cell region 103.

[0061] Still refer to Fig. 12CAs previously described, the width of the edge strip region 400 along the x-direction may be smaller than that of the middle strip region 500. For example, although the sizes of the feedthrough circuits 450 and 550 may be similar, the buffer zone around the feedthrough circuit 550 in the middle strip region 500 may be larger than the buffer zone around the feedthrough circuit 450 in the edge strip region 400. This may be due to the smaller buffer zone between the feedthrough circuit 450 and the logic cell region 103 compared to the buffer zone between the feedthrough circuit 450 and the memory cell region 102. However, in the case of the middle strip region 500, both sides of the middle strip region 500 have a larger buffer zone between the feedthrough circuit 550 and the memory cell region 102. In some embodiments (as shown), for the edge strip region 400, there is no buffer zone on the side of the edge strip region 40 adjacent to the logic cell region 103.

[0062] Fig.13A A top view of an intermediate band region 500 in an SRAM circuit region 200 (or a memory macro 200) is shown. In the illustrated embodiment, the intermediate band region 500 includes a feedthrough circuit region 500a sandwiched between buffer regions 500b along the x-direction. The feedthrough circuit region 500a includes a feedthrough circuit 550 disposed between dummy n-type active regions 506 along the y-direction. The buffer region 500b includes a dummy extension 503 extending from an n-type active region 106a and a p-type active region 106b in a memory cell region 102. Fig.13A Other device-level features are also shown, such as the gate 108 extending longitudinally in the y-direction, the S / D contacts 112 disposed over the S / D regions of the dummy extension 503, and the front side vias 116 that fall over some of the S / D contacts 122 at the edge of the intermediate band region 500. Fig.13A As shown, the front side vias 116 define the edge boundaries of the middle band region 500. This is because these front side vias 116 define the starting position of the memory cell region 102.

[0063] Still refer to Fig.13A , the middle band region 500 may span a width of 13 gate pitches, where the gate pitch is the distance between the gates 108 along the x-direction. The feedthrough circuit region 500a may span 7 gate pitches, and each of the buffer zones 500b may span 3 gate pitches, for a total of 13 gate pitches. The edge band region 400 (not shown) may only span a width of 10 gate pitches. The edge band region 400 may be configured similarly to the middle band region 500, but instead of having two buffer zones, only one. For example, the edge band region 400 may have a feedthrough circuit region spanning 7 gate pitches and a single buffer zone spanning 3 gate pitches, for a total of 10 gate pitches. In this case, the edge band region 400 has only a buffer zone bordering the memory cell region 102, and no buffer zone bordering the logic cell region 103.

[0064] Fig. 13B Shows Fig.13A A cross-sectional view of a feed-through circuit 550 in the mid-band region 500 . Fig. 13B A device layer DL having various interlayer dielectric (ILD) layers 130, 140, and 160, etch stop layers 111, 113, and 117, and / or a backside hard mask layer 117 with embedded metal features is shown. The metal features constitute a feedthrough circuit 550, and the metal features may include a feedthrough via 150f passing through a first portion of the device layer DL from the backside of the memory macro 200, a feedthrough contact 112f passing through a second portion of the device layer DL from the frontside of the memory macro 200, and a frontside feedthrough via 116f passing through a third portion of the device layer DL from the frontside of the memory macro 200. In the illustrated embodiment, the feedthrough via 150f may penetrate one or more backside hard mask layers 117 and portions of the ILD layer 130. The feedthrough via 150f lands on a backside metal line BM1 disposed on the backside of the device layer DL. The back metal line BM1 may be part of a back metal interconnect structure (not shown) that includes additional stacked back metals vertically connected by additional back interconnect vias for back power signal routing (e.g., Vss or Vdd). The feed-through contact 112f may penetrate the ILD layer 140, the etch stop layer 111, and a portion of the ILD layer 130 to land on the top surface of the feed-through hole 150f. The front feed-through hole 116f may penetrate the ILD layer 160 and the etch stop layer 113 to land on the top surface of the feed-through contact 112f.

[0065] The etch stop layers 111, 113 and the hard mask layer 117 may include a dielectric material different from the ILD layers 130, 140 and 160 to achieve selectivity of the etchant. For example, the etch stop layers 111, 113 and the hard mask layer 117 include a nitride-based dielectric, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride or a combination thereof. The first ILD layer 130, the second ILD layer 140 and the third ILD layer 160 include silicon oxide or an oxide-based dielectric formed of tetraethyl orthosilicate, undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silica glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials or a combination thereof.

[0066] Still reference Fig. 13B , the device layer DL may correspond to Figure 8106. Thus, components in the feedthrough circuit 550 may be compared to components in other regions, such as the memory cell region 102. In the illustrated embodiment, the top surface of the feedthrough contact 112f may be substantially coplanar with the top surface of the previously described S / D contact 112. The etch stop layer 111 may fall on the top surface of the previously described gate 108. The top surface of the front feedthrough hole 116f may be substantially coplanar with the top surface of the previously described front through hole 116. The ILD layer 130 may be embedded in and disposed above the previously described active region 106.

[0067] Although not limiting, the present disclosure provides advantages for backside power routing of semiconductor devices such as SRAM devices. One example advantage is integrating the middle band region within the memory macro region to route power lines directly to the backside of the SRAM device. Another example advantage is utilizing backside vias and the middle band region for double-sided power routing. Another example advantage is eliminating the edge band region in the memory macro and allowing the middle band region to provide necessary power routing for memory and logic cells.

[0068] One aspect of the present invention relates to a device. The device includes a memory macro having a front side and a back side in a vertical direction. The memory macro includes an edge band region extending longitudinally along a first direction at an edge of the memory macro, a memory cell region having a plurality of memory cells, and an intermediate band region extending in length along the first direction and arranged between the edge band regions along a second direction, wherein the memory cell regions are arranged between the edge band regions along a second direction perpendicular to the first direction, wherein the intermediate band region divides the memory cell region into two memory cell domains. The intermediate band region includes a feed-through circuit that routes a power signal line of one of the plurality of memory cells to the back side of the memory macro.

[0069] In one embodiment, the power signal line is connected to a high voltage power source Vdd or a low voltage power source Vss.

[0070] In one embodiment, the edge band region further includes a feed-through circuit that routes a power supply signal line of one of the plurality of memory cells to a back side of the memory macro.

[0071] In one embodiment, the device further comprises a logic circuit region adjacent to the memory macro, wherein the logic circuit region is isolated from the memory cell region by one of the edge band regions. In another embodiment, one of the edge band regions spans between the memory macro and the logic circuit region, and the width of the middle band region spanning along the second direction is greater than that of the edge band region.

[0072] In one embodiment, the device further includes a back side metal line disposed on a back side of the memory macro, wherein a feed-through hole of the feed-through circuit falls on the back side metal line.

[0073] In one embodiment, the power signal line of one of the multiple memory cells includes: a source / drain (S / D) contact that lands on the S / D component of the one memory cell; a front through hole located on the S / D contact; a first metal line that lands on the front through hole; a first interconnection through hole that lands on the first metal line; a second metal line that lands on the first interconnection through hole; a second interconnection through hole that lands on the second metal line; and a third metal line that lands on the second interconnection through hole, wherein the third metal line lands on the metal component of the feed-through circuit in the middle strip area.

[0074] In another embodiment, the device also includes a back metal line disposed on the back side of the memory macro, wherein the metal components of the feedthrough circuit include: a feedthrough hole located on the back metal line; a feedthrough contact that lands on the feedthrough hole; a front feedthrough hole on the feedthrough contact; a first feedthrough metal line that lands on the front feedthrough hole; a first feedthrough interconnection via that lands on the first feedthrough metal line; a second feedthrough metal line that lands on the first feedthrough interconnection via; and a second feedthrough interconnection via located on the second feedthrough metal line, wherein the third metal line is located on the second feedthrough interconnection via.

[0075] In another embodiment, the power signal line of one of the multiple memory cells further includes: a third interconnect via pad on a third metal line; and a fourth metal line that lands on the third interconnect via, wherein the fourth metal line also routes the power signal line to a higher-level metal line above the front side of the memory macro.

[0076] In one embodiment, the memory cell region has 512 SRAM cells, and each of the two memory cell regions has 256 SRAM cells.

[0077] In one embodiment, the middle band region is a first middle band region, and the memory macro further includes an additional middle band region extending longitudinally along the first direction and disposed between the edge band regions along the second direction. The additional middle band portion divides the memory cell region into additional memory cell domains, wherein each additional middle band region includes a feed-through circuit that routes a power signal line of one of the plurality of memory cells to the back side of the memory macro.

[0078] Another aspect of the present disclosure relates to a device. The device includes a memory macro having a front side and a back side along a vertical direction, wherein the memory macro includes: a memory cell region having a plurality of memory cells, an edge band region adjacent to a first side of the memory cell region, an edge band region extending longitudinally along a first direction at an edge of the memory macro, and an intermediate band region within the memory cell region, wherein the intermediate band region extends longitudinally along the first direction. The intermediate band region divides the memory cell region into two memory cell domains. The intermediate band region includes a feed-through circuit that routes a power signal line of one of the plurality of memory cells to the back side of the memory macro. The intermediate band region spans a first width along a second direction perpendicular to the first direction, and the edge band region spans a second width along the second direction, wherein the first width is the distance between the two memory cell domains, and the first width is greater than the second width.

[0079] In another embodiment, the device further includes a first logic circuit region adjacent to a first side of the memory macro, wherein the first logic circuit region is isolated from the memory cell region by an edge band region; and a second logic circuit adjacent to a second side of the memory macro, wherein the second logic circuit directly adjoins the memory cell region without an intermediate edge band region.

[0080] In another embodiment, the edge band region is a first edge band region, and the device further includes: a second edge band region adjacent to a second side of the memory cell region; a first logic circuit region adjacent to a first side of the memory macro, wherein the first logic circuit region is isolated from the memory cell region by the first edge band region; and a second logic circuit region adjacent to a second side of the memory macro, wherein the second logic circuit region is isolated from the memory cell region by the second edge band region.

[0081] In one embodiment, the power signal line is connected to a high voltage power source VDD or a low voltage power source VSS. In one embodiment, the middle and edge band regions do not include memory cells.

[0082] Another aspect of the present disclosure relates to a device. The device includes a memory macro having a plurality of memory cells, the memory macro having a front side and a back side; an intermediate band region disposed between two memory cells among the plurality of memory cells, the intermediate band region including a vertical metal wiring electrically connected to a power signal line of one of the plurality of memory cells on the back side of the memory macro; an edge band region on an edge of the memory macro, wherein the intermediate band region is located between the edge band regions, wherein the edge band region also includes a vertical metal wiring electrically connecting a power signal line of one of the plurality of memory cells to the back side of the memory macro; and a logic circuit region adjacent to the memory macro, the logic circuit region having a plurality of logic cells adjacent to the edge band region, wherein the logic cells and the memory cells have active regions with different configurations.

[0083] In one embodiment, in the memory cell, active regions for p-type transistors and n-type transistors extend longitudinally along the first direction with different lengths, and in the logic cell, active regions for p-type transistors and n-type transistors extend longitudinally along the first direction with the same length.

[0084] In one embodiment, the edge band region spans between the memory macro and the logic circuit region, and the width of the middle band region along the second direction is greater than that of the edge band region.

[0085] In one embodiment, the middle band region is a first middle band region, and the memory macro further includes additional middle band regions extending longitudinally along the first direction and disposed between the edge band regions. Each additional middle band region is disposed between additional two memory cells of the plurality of memory cells, and each middle band region includes a vertical metal wiring that electrically connects a power signal line of one of the plurality of memory cells to the back side of the memory macro.

[0086] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A memory macro having a front side and a back side in a vertical direction, wherein the memory macro comprises: an edge band region extending longitudinally in a first direction at an edge of the memory macro, a memory cell region having a plurality of memory cells, wherein the memory cell region is arranged between the edge band regions along a second direction perpendicular to the first direction, and A middle band region extends longitudinally along the first direction and is arranged between the edge band regions along the second direction, wherein the middle band region divides the memory cell region into two memory cell domains, and the middle band region includes a feed-through circuit, which routes a power signal line of one of the multiple memory cells to the back side of the memory macro.

2. The device according to claim 1, wherein The power signal line is connected to a high voltage power source Vdd or a low voltage power source Vss.

3. The device according to claim 1, wherein The edge band region further includes a feed-through circuit that routes the power signal line of the one of the plurality of memory cells to a back side of the memory macro.

4. The device according to claim 1, further comprising: A logic circuit region is adjacent to the memory macro, wherein the logic circuit region is isolated from the memory cell region by one of the edge band regions.

5. The device according to claim 4, wherein The one of the edge band regions spans between the memory macro and the logic circuit region, and the middle band region spans a greater width along the second direction than the edge band region.

6. A semiconductor device comprising: A memory macro having a front side and a back side in a vertical direction, wherein the memory macro comprises: A storage unit area having a plurality of storage units, an edge band region adjacent to a first side of the memory cell region, the edge band region extending longitudinally in a first direction at an edge of the memory macro, and an intermediate zone region within the memory cell region, the intermediate zone region extending longitudinally along the first direction, wherein the intermediate zone region divides the memory cell region into two memory cell domains, wherein the intermediate zone region includes a feed-through circuit, the feed-through circuit routing a power signal line of one of the plurality of memory cells to a back side of the memory macro, The middle band region spans a first width along a second direction perpendicular to the first direction, and the edge band region spans a second width along the second direction. The first width is the distance between the two storage cell domains, and the first width is greater than the second width.

7. The device according to claim 6, further comprising: a first logic circuit region adjacent to a first side of the memory macro, wherein the first logic circuit region is isolated from the memory cell region by the edge band region; and A second logic circuit is adjacent to a second side of the memory macro, wherein the second logic circuit directly adjoins the memory cell region without an intermediate edge band region.

8. A semiconductor device comprising: A memory macro having a plurality of memory cells, the memory macro having a front side and a back side; an intermediate band region disposed between two of the plurality of memory cells, the intermediate band region comprising a vertical metal wiring electrically connected to a power signal line of one of the plurality of memory cells on the back side of the memory macro; an edge band region located on an edge of the memory macro, wherein the middle band region is located between the edge band regions, wherein the edge band region further comprises a vertical metal wiring that electrically connects a power signal line of the one of the plurality of memory cells to a back side of the memory macro; and A logic circuit region is adjacent to the memory macro, the logic circuit region having a plurality of logic cells adjacent to the edge band region, wherein the logic cells and the memory cells have active regions with different configurations.

9. The device according to claim 8, in, In the memory cell, active regions for p-type transistors and n-type transistors extend longitudinally in a first direction with different lengths, Wherein, in the logic unit, active regions for p-type transistors and n-type transistors extend longitudinally along the first direction with the same length.

10. The device according to claim 8, wherein The edge band region spans between the memory macro and the logic circuit region, and the width of the middle band region spanned along the second direction is greater than that of the edge band region.

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