Memory

Abstract

The embodiment of the invention discloses a memory. The memory comprises a memory cell array and a peripheral circuit coupled with the memory cell array, the memory cell array comprises a plurality of bit lines, a plurality of word lines and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the peripheral circuit is configured to: in response to a write command, apply a first voltage to a selected word line coupled to a target memory cell, apply a second voltage to a selected bit line coupled to the target memory cell, and apply a third voltage to an unselected bit line; performing a sensing operation on the target memory cell in response to the write command; determining whether to apply a fourth voltage to the selected word line and determining whether to apply a fifth voltage to the unselected bit line based on a comparison result of a voltage on the selected bit line and a reference voltage after the sensing operation is performed on the target memory cell; the fourth voltage is greater than the first voltage and the fifth voltage is greater than the third voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, for example, to a memory. Background Art

[0002] Semiconductor memories can be roughly divided into two categories, depending on whether they retain stored data when power is off; the two categories of semiconductor memories are: volatile memory, which loses stored data when power is off, and non-volatile memory, which retains stored data when power is off.

[0003] As an emerging non-volatile memory device, phase change memory has great advantages over flash memory in many aspects such as read and write speed, read and write times, data retention time, unit area, and multi-value realization. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a memory is provided, comprising a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the peripheral circuit is configured to: in response to a write command, apply a first voltage to a selected word line coupled to a target memory cell, apply a second voltage to a selected bit line coupled to a target memory cell, and apply a third voltage to an unselected bit line; in response to the write command, perform a sensing operation on the target memory cell; determine whether to apply a fourth voltage to the selected word line and determine whether to apply a fifth voltage to the unselected bit line based on a comparison result of the voltage on the selected bit line with a reference voltage after the sensing operation is performed on the target memory cell; the fourth voltage is greater than the first voltage, and the fifth voltage is greater than the third voltage.

[0005] In some optional embodiments, the peripheral circuit is configured to: apply the fourth voltage to the selected word line and apply the fifth voltage to the unselected bit line based on the voltage on the selected bit line being less than the reference voltage after a sensing operation is performed on the target memory cell; perform a set operation or a reset operation on the target memory cell; or, based on the voltage on the selected bit line being greater than the reference voltage after a sensing operation is performed on the target memory cell, not apply the fourth voltage to the selected word line and not apply the fifth voltage to the unselected bit line; perform a set operation or a reset operation on the target memory cell.

[0006] In some optional embodiments, the plurality of memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; and the first voltage is less than the minimum voltage of the first threshold voltage distribution.

[0007] In some optional embodiments, a difference between the first voltage and the second voltage is greater than a minimum voltage of the second threshold voltage distribution and less than a maximum voltage of the second threshold voltage distribution.

[0008] In some optional embodiments, the peripheral circuit is configured to: apply a ground voltage to an unselected word line in response to the write command; and an absolute value of the second voltage is smaller than a minimum voltage of the first threshold voltage distribution.

[0009] In some optional embodiments, the first voltage is greater than 0, and the second voltage is less than 0.

[0010] In some optional embodiments, a difference between the fourth voltage and the second voltage is greater than a maximum voltage of the second threshold voltage distribution, and a difference between the fourth voltage and the fifth voltage is less than a minimum voltage of the first threshold voltage distribution.

[0011] In some optional embodiments, the first voltage ranges from 3V to 4V; the second voltage ranges from -4V to -3V; the third voltage is a ground voltage; the fourth voltage ranges from 4V to 5V; and the fifth voltage ranges from 0.6V to 1.2V.

[0012] In some optional embodiments, the peripheral circuit includes a current mirror circuit; the selected bit line is connected to the current mirror circuit; the current mirror circuit is configured to: provide a current pulse in response to a write command, thereby performing a sensing operation on the target storage unit.

[0013] In some alternative embodiments, the memory comprises a phase change memory or a selector-only memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure of an exemplary system provided in an embodiment of the present disclosure;

[0015] Figure 2 A schematic diagram of the structure of a memory including a memory cell array and a peripheral circuit provided in an embodiment of the present disclosure;

[0016] Figure 3 A schematic diagram of a storage unit provided in an embodiment of the present disclosure Figure 1 ;

[0017] Figure 4 A schematic diagram of a storage unit provided in an embodiment of the present disclosure Figure 2 ;

[0018] Figure 5 A schematic diagram of pulses for performing a set operation and a reset operation on a phase change memory cell is shown;

[0019] Figure 6 A schematic diagram of the threshold voltage distribution of a memory cell in a memory provided by an embodiment of the present disclosure;

[0020] Figure 7 The relationship between the threshold voltage distribution and the applied voltage provided in the embodiment of the present disclosure is shown in FIG. Figure 1 ;

[0021] Figure 8 The voltage applied waveform provided in the embodiment of the present disclosure is shown as follows: Figure 1 ;

[0022] Fig. 9 Schematic diagram of voltage application to each storage unit provided in the embodiment of the present disclosure Figure 1 ;

[0023] Fig.10 The voltage applied waveform provided in the embodiment of the present disclosure is shown as follows: Figure 2 ;

[0024] Fig.11 Schematic diagram of voltage application to each storage unit provided in the embodiment of the present disclosure Figure 2 ;

[0025] Fig.12 The relationship between the threshold voltage distribution and the applied voltage provided in the embodiment of the present disclosure is shown in FIG. Figure 2 . DETAILED DESCRIPTION

[0026] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0027] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0028] In the drawings, like reference numerals refer to like elements throughout.

[0029] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0030] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0031] like Figure 1As shown, an embodiment of the present disclosure shows an exemplary system 10, which may include a host 20 and a memory system 30. The exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 34 therein; the host 20 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. The memory system 30 includes a memory controller 32 and a memory 34 coupled to the memory controller 32.

[0032] Exemplarily, the memory controller 32 can communicate with an external host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI high-speed (Peripheral Component Interconnect Express, PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire, ONFI, DDR, LPDDR protocol, etc.

[0033] The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array may include a plurality of memory cells. The memory cell array may be integrated on the same die as the peripheral circuit, which allows a wider bus and a higher operating speed. In some embodiments, the memory cell array and the peripheral circuit may be formed in different regions on the same plane; or the memory cell array and the peripheral circuit may form a stacked structure, i.e., the two are formed on different planes.

[0034] Figure 2FIG. 1 shows a schematic diagram of the structure of a memory including a memory cell array and a peripheral circuit. Figure 2 As shown, the memory 304 includes a memory cell array 401 and a peripheral circuit 402 coupled to the memory cell array 401. The memory cell array 401 may include a plurality of memory cells 4013 arranged in rows and columns. The plurality of memory cells 4013 arranged in rows are coupled to the same word line (WL) 4011, and the plurality of memory cells arranged in columns are coupled to the same bit line (BL) 4012.

[0035] In the embodiments of the present disclosure, the memory includes but is not limited to a variety of memory types such as phase change memory (PCM) and selector only memory (SOM). It should be understood that the present disclosure is not limited thereto. In some embodiments, the storage unit is a phase change memory unit, such as Figure 3 As shown, the phase change memory cell 130 includes a gating element 110 and a phase change element 120 connected in series. In some embodiments, the memory cell is a select-only memory cell, such as Figure 4 As shown, only the selected memory cell 140 includes the gating element 110 .

[0036] The following is an explanation using a phase change memory as an example. The basic storage principle of phase change memory is to apply voltage or current pulse signals of different widths and heights to the phase change memory unit to change the physical phase of the phase change material in the phase change element of the phase change memory unit, for example, to achieve reversible mutual conversion between the crystalline state (low resistance state) and the amorphous state (high resistance state) of the phase change material, thereby realizing data storage. When the memory unit is in the crystalline state and the amorphous state, it has different threshold voltages, wherein the threshold voltage of the crystalline state (defined as 1) is lower, and the threshold voltage of the amorphous state (defined as 0) is higher. The operation that can complete the crystalline conversion of the memory unit is defined as a set operation, and the operation that can complete the amorphous conversion of the memory unit is defined as a reset operation.

[0037] In some embodiments, in order to realize the conversion of the phase change material in the phase change memory between the crystalline state and the amorphous state, different pulses (eg, light pulses, electrical pulses) may be used to control the heating of the phase change material. Figure 5 FIG. 4 shows a schematic diagram of pulses for performing a set operation and a reset operation on a phase change memory cell. Figure 5As shown, the set operation includes: by applying a long and medium-intensity set pulse to raise the temperature of the phase change material of the phase change memory unit to below the melting temperature Tm and above the crystallization temperature Tx, and maintaining it for a period of time and promoting the growth of the crystal nucleus, the phase change material of the phase change memory unit can be transformed from the amorphous state (corresponding to the high resistance state) to the crystalline state (corresponding to the low resistance state). The reset operation includes: by applying a short and strong reset pulse to raise the temperature of the phase change material of the phase change memory unit to above the melting temperature Tm, and then rapidly cooling it, the phase change material of the phase change memory unit can be transformed from the crystalline state to the amorphous state. Among them, the set process and the reset process are mutually reversible processes, so that the phase change memory unit can use the crystalline state to represent the unit binary data "1", and use the amorphous state to represent the binary data "0".

[0038] Figure 6 A schematic diagram of the threshold voltage distribution of a storage unit in a memory provided by an embodiment of the present disclosure. Figure 6 As shown, a plurality of memory cells in the memory have a set state (crystalline state) and a reset state (amorphous state). The memory cells with the set state correspond to a first threshold voltage distribution, and the memory cells with the reset state correspond to a second threshold voltage distribution, wherein the minimum voltage of the second threshold voltage distribution is greater than the maximum voltage of the first threshold voltage distribution.

[0039] In order to implement the write operation, that is, to complete the above-mentioned set operation or reset operation, such as Figure 7 As shown, a maximum voltage higher than the threshold voltage distribution (second threshold voltage distribution) corresponding to the memory cell in the reset state needs to be applied to both ends of the target memory cell to ensure that the target memory cell is in the on state. The voltage Vwrite higher than the maximum voltage of the threshold voltage distribution corresponding to the memory cell in the reset state is generally higher.

[0040] In some embodiments, the higher Vwrite is applied to the selected word line or the selected bit line coupled to the target memory cell through a single-rail power supply. Non-target memory cells in the memory cell array that are in common with the selected word line or the selected bit line will also be subjected to a higher voltage, which will accelerate the threshold voltage drift of the storage data of the non-target memory cells, and may eventually cause errors in reading data from these non-target memory cells; in addition, the single-rail power supply solution requires the use of a high-voltage resistant process, and the power consumption is relatively large.

[0041] An embodiment of the present disclosure provides a memory, which includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines; the peripheral circuit is configured to: in response to a write command, apply a first voltage to a selected word line coupled to a target memory cell, apply a second voltage to a selected bit line coupled to the target memory cell, and apply a third voltage to an unselected bit line; in response to the write command, perform a sensing operation on the target memory cell; based on a comparison result of the voltage on the selected bit line with a reference voltage after the sensing operation is performed on the target memory cell, determine whether to apply a fourth voltage to the selected word line and determine whether to apply a fifth voltage to the unselected bit line; the fourth voltage is greater than the first voltage, and the fifth voltage is greater than the third voltage.

[0042] like Figure 8 as well as Fig.10 As shown, in the embodiment of the present disclosure, after receiving a write command, a first voltage (VL) is applied to a selected word line coupled to the target memory cell, a second voltage (VN) is applied to a selected bit line coupled to the target memory cell, a third voltage (V1) is applied to an unselected bit line, and a sensing operation is performed on the target memory cell to determine whether the target memory cell is in a conductive state, and then determine whether to apply a larger fourth voltage (VH) to the selected word line and determine whether to apply a fifth voltage (VB) greater than the third voltage to the unselected bit line.

[0043] In the embodiment of the present disclosure, applying a first voltage to a selected word line coupled to a target memory cell, applying a second voltage to a selected bit line coupled to the target memory cell, applying a third voltage to an unselected bit line, performing a sensing operation on the target memory cell, and determining whether to apply a fourth voltage and a fifth voltage based on a comparison result of the voltage on the selected bit line with a reference voltage are all performed after the peripheral circuit receives a write command.

[0044] In the embodiment of the present disclosure, a lower voltage is first applied to the selected word line, and it is determined whether to apply a fourth voltage to the selected word line and whether to apply a fifth voltage to the unselected bit line according to the comparison result between the voltage on the selected bit line after the sensing operation and the reference voltage. In the embodiment of the present disclosure, in the first aspect, a dual-rail power supply is used to apply voltages to the selected word line and the selected bit line at the same time, which can improve the problem that a high-voltage-resistant process is required in a single-rail power supply solution, the power consumption is large, and the higher voltage will accelerate the threshold voltage drift of the storage data of the non-target storage cell; in the second aspect, by first applying a lower voltage to the selected word line, and according to the comparison result between the voltage on the selected bit line after the sensing operation and the reference voltage, it is determined whether the target storage cell is in the on state when the first voltage is applied to the selected word line and the second voltage is applied to the selected bit line, if the target storage cell is in the on state, a reset operation or a set operation can be directly performed, and if the target storage cell is not turned on, a larger fourth voltage can be applied to the selected word line, so that the target storage cell is in the on state, and a fifth voltage larger than the third voltage is applied to the unselected bit line, so that the target storage cell is in the on state. The non-target memory cells coupled to the selected bit line and the selected word line are in a non-conducting state, thereby ensuring that the target memory cells are in a conducting state and ensuring that the non-target memory cells are in a non-conducting state, avoiding the problem that the non-target memory cells are mistakenly opened and the data of the non-target memory cells are mistakenly rewritten; on the third aspect, since a smaller first voltage is first applied to the selected word line in the embodiment of the present disclosure, a smaller voltage is correspondingly applied to the selected bit line to ensure that the non-target memory cells are in a non-conducting state. After the sensing operation, if it is determined that the target memory cell is in a non-conducting state, a higher fourth voltage is further applied to the selected word line, and a fifth voltage higher than the third voltage is applied to the unselected bit line to ensure that the non-target memory cells are in a non-conducting state. This can improve the problem of high power consumption caused by applying a higher fifth voltage to the unselected bit lines at the beginning.

[0045] In some embodiments, the peripheral circuit includes a current mirror circuit; the selected bit line is connected to the current mirror circuit; and the current mirror circuit is configured to: provide a current pulse in response to a write command, thereby performing a sensing operation on the target memory cell.

[0046] In the embodiment of the present disclosure, after receiving a write command, in response to the write command, a smaller first voltage is applied to the selected word line coupled to the target memory cell, and a sensing operation is performed on the target memory cell to determine whether the target memory cell is in a conducting state. If the target memory cell is in a conducting state, a current pulse provided by a current mirror circuit connected to the selected bit line will flow through a path consisting of the selected bit line, the target memory cell, and the selected word line, and the voltage on the selected bit line will be charged high; if the target memory cell is in a non-conducting state, a current pulse provided by a current mirror circuit connected to the selected bit line will not flow through a path consisting of the selected bit line, the target memory cell, and the selected word line, and the voltage on the selected bit line will not be charged high, and the voltage on the selected bit line maintains a second voltage. By comparing the voltage on the bit line with a reference voltage (Vref), it can be determined whether the voltage on the bit line is charged high, and then it can be determined whether the target memory cell is in a conducting state.

[0047] like Fig. 9 as well as Fig.11 As shown, the non-target memory cells can be divided into three types according to the voltages at both ends of the non-target memory cells: the first type, non-target memory cell cell1, non-target memory cell cell1 is coupled to the selected word line and the unselected bit line; the second type, non-target memory cell cell2, non-target memory cell cell2 is coupled to the unselected word line and the selected bit line; the third type, non-target memory cell cell3, non-target memory cell cell3 is coupled to the unselected word line and the unselected bit line. In addition, cell0 is a target memory cell, which is coupled to the selected bit line and the selected word line.

[0048] In some embodiments, the peripheral circuit is configured to: based on the voltage on the selected bit line being greater than the reference voltage after a sensing operation is performed on the target memory cell, not apply the fourth voltage to the selected word line and not apply the fifth voltage to the unselected bit line; perform a set operation or a reset operation on the target memory cell.

[0049] like Fig. 9 As shown, the voltage across non-target memory cell cell1 is (VL-V1); the voltage across non-target memory cell cell2 is (VSS-VN); the voltage across non-target memory cell cell3 is (VSS-V1). In addition, the voltage across target memory cell cell0 is (VL-VN).

[0050] In the above embodiment, if Figure 8 as well as Fig. 9As shown, when the voltage on the selected bit line is greater than the reference voltage (Vref) after the target memory cell performs a sensing operation, it means that when the first voltage is applied to the selected word line and the second voltage is applied to the selected bit line, the voltage on the bit line is charged high, which further indicates that the target memory cell is in a conductive state, and the voltage on the selected word line can be maintained at the first voltage (VL) to directly perform a reset operation or a set operation on the target memory cell. Since the value of the first voltage is relatively small, the surge current can be reduced. And the voltage across the non-target memory cell cell1 coupled to the selected word line is (VL-V1), (VL-V1) is small, and the non-target memory cell cell1 coupled to the selected word line will not be mistakenly opened, so the voltage on the unselected bit line can be maintained at a smaller third voltage (V1), and the voltage on the unselected bit line does not need to be charged to a higher fifth voltage, which will greatly reduce the power consumption of the power domain that generates the fifth voltage.

[0051] In some embodiments, the peripheral circuit is configured to: apply the fourth voltage to the selected word line and apply the fifth voltage to the unselected bit line based on the voltage on the selected bit line being less than the reference voltage after a sensing operation is performed on the target memory cell; and perform a set operation or a reset operation on the target memory cell.

[0052] like Fig.10 As shown, the voltage across the non-target memory cell cell1 is (VH-VB); the voltage across the non-target memory cell cell2 is (VSS-VN); the voltage across the non-target memory cell cell3 is (VSS-VB). In addition, the voltage across the target memory cell cell0 is (VH-VN), and (VH-VN) is equal to Vwrite.

[0053] In the above embodiment, if Figure 10 to Figure 11 As shown, when the voltage on the selected bit line is less than the reference voltage after the target memory cell performs a sensing operation, it means that when the first voltage is applied to the selected word line and the second voltage is applied to the selected bit line, the voltage on the selected bit line is not charged high, which further indicates that the target memory cell is in a non-conducting state, and thus a fourth voltage (VH) greater than the first voltage needs to be applied to the selected word line, and a fifth voltage (VB) greater than the second voltage needs to be applied to the unselected bit line, so that the target memory cell is in a conducting state while the non-target memory cell cell1 coupled to the selected word line and the unselected bit line is in a non-conducting state.

[0054] It can be understood that if a high voltage (VH-VN) is directly used to open a target memory cell with a lower threshold voltage, there will be a large surge current at the moment the target memory cell is opened. In the embodiment of the present disclosure, when a lower voltage (VL-VN) is first used to open a target memory cell with a lower threshold voltage, the lower voltage will have a suppressive effect on the surge current. When the target memory cell is not turned on, the high voltage (VH-VN) is used to open the target memory cell, thereby effectively reducing the surge current and reducing write interference.

[0055] In the embodiment of the present disclosure, on the basis of making the target memory cell in a conducting state in response to the write command, a set operation or a reset operation is performed on the target memory cell, thereby realizing writing "0" or writing "1".

[0056] In some embodiments, multiple memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; and the first voltage is less than the minimum voltage of the first threshold voltage distribution.

[0057] In some embodiments, the first voltage is greater than 0, and the second voltage is less than 0.

[0058] In the present disclosure, Fig.12 As shown, the first voltage (VL) is less than the minimum voltage of the first threshold voltage distribution. When the voltage across the non-target memory cell cell1 is (VL-V1), since the first voltage (VL) is less than the minimum voltage of the first threshold voltage distribution, and V1 is greater than or equal to 0, the voltage across the non-target memory cell cell1 (VL-V1) is less than the minimum voltage of the first threshold voltage distribution, thereby ensuring that the non-target memory cell cell1 is in a non-conducting state. In the disclosed embodiment, the specific voltage of the first voltage can be comprehensively determined based on the bias drift index of the non-target memory cell cell1. The bias drift here can be understood as a phenomenon in which the threshold voltage of the non-target memory cell coupled to the selected word line or the selected bit line is offset by applying pressure to the selected word line and the selected bit line.

[0059] In some embodiments, Fig.12 As shown, the difference (VL-VN) between the first voltage and the second voltage is greater than the minimum voltage of the second threshold voltage distribution and less than the maximum voltage of the second threshold voltage distribution.

[0060] When the first voltage is applied to the selected word line and the second voltage is applied to the selected bit line, the voltage across the target memory cell cell0 is (VL-VN). Since (VL-VN) can open all memory cells in the set state and more than half of the memory cells in the reset state, only some memory cells in the reset state with higher threshold voltages need to be opened using (VH-VN). Assuming that multiple memory cells in the memory cell array store data evenly, half of the memory cells in the memory cell array store 0 and half of the memory cells store 1, when performing a write operation, more than 75% of the memory cells can be opened. By opening the lower voltage group (VL-VN), only less than 25% of the memory cells need to charge the unselected bit lines to the fifth voltage (VB) to compensate for the pressure caused by the fourth voltage (VH); compared with opening the target memory cells with a higher voltage (VH-VN) and charging the unselected bit lines to the fifth voltage (VB) to compensate for the pressure caused by the fourth voltage (VH), the embodiment of the present disclosure significantly optimizes the power consumption of the power supply where the fifth voltage (VB) is located, and can improve the problem of accelerated bias drift caused by long-term application of the fifth voltage (VB) to the unselected bit lines.

[0061] In some embodiments, Figure 8 as well as Fig.10 As shown, the peripheral circuit is configured to: apply a ground voltage (VSS) to unselected word lines in response to the write command; and an absolute value of the second voltage is smaller than a minimum voltage of the first threshold voltage distribution.

[0062] A ground voltage is applied to the unselected word line, and the voltage across the non-target memory cell cell2 is (VSS-VN). Since the absolute value of the second voltage (VN) is less than the minimum voltage of the first threshold voltage distribution, the voltage across the non-target memory cell cell2 (VSS-VN) is less than the minimum voltage of the first threshold voltage distribution, which ensures that the non-target memory cell cell2 is in a non-conducting state.

[0063] In some embodiments, a difference between the fourth voltage and the second voltage is greater than a maximum voltage of the second threshold voltage distribution, and a difference between the fourth voltage and the fifth voltage is less than a minimum voltage of the first threshold voltage distribution.

[0064] like Fig.12As shown, the difference (VH-VN) between the fourth voltage and the second voltage is greater than the maximum voltage of the second threshold voltage distribution, so that when the fourth voltage is applied to the selected word line and the second voltage is applied to the selected bit line, the target memory cell cell0 can be ensured to be in the on state. In the disclosed embodiment, the fourth voltage (VH) is greater than the absolute value of the second voltage (VN), (VH-VN) is equal to Vwrite, so VH is greater than Vwrite / 2. When the voltage applied to the selected word line is increased to the fourth voltage (VH), if the unselected bit line is still applied with a lower third voltage such as the ground voltage (VSS), the voltage across the non-target memory cell cell1 is (VH-VSS), and since VH is greater than Vwrite / 2, the voltage across the non-target memory cell cell1 (VH-VSS) is greater than Vwrite / 2, which causes the non-target memory cell cell1 to be in the on state. In the disclosed embodiment, while increasing the voltage applied to the selected word line from the first voltage to the fourth voltage, the voltage applied to the unselected bit line is synchronously adjusted to the fifth voltage (VB), and the voltage (VH-VB) across the non-target memory cell cell1 is less than the minimum voltage of the first threshold voltage distribution, thereby ensuring that the non-target memory cell cell1 is in a non-conducting state when the voltage applied to the selected word line is increased to the fourth voltage (VH).

[0065] In some embodiments, the first voltage ranges from 3V to 4V; the second voltage ranges from -4V to -3V; the third voltage is a ground voltage; the fourth voltage ranges from 4V to 5V; and the fifth voltage ranges from 0.6V to 1.2V.

[0066] It should be noted that the ranges of the first voltage, the second voltage, the third voltage, the fourth voltage, and the fifth voltage given in the above embodiments are only examples and are not used to limit the ranges of the first voltage, the second voltage, the third voltage, the fourth voltage, and the fifth voltage in the embodiments of the present disclosure. In some specific examples, corresponding adjustments can be made according to actual needs.

[0067] In some embodiments, the memory comprises phase change memory or selector-only memory.

[0068] In some embodiments, the memory cell comprises a phase change memory cell; the phase change memory cell comprises a phase change element and a gating element connected in series with the phase change element.

[0069] In some specific examples, the phase change element may include a chalcogenide component, such as a binary compound such as GaSb, InSb, InSe, SbTe, and GeTe, a ternary compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, and InSbGe, and a quaternary compound such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and TeGeSbS. The gating element may include a material having an Ovonic Threshold Switch (OTS) property, and the material having the OTS property may include at least one element of oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as ZnxTey, GexTey, NbxOy, SixAsyTez, etc.

[0070] In some embodiments, the memory cell comprises a select-only memory cell; the select-only memory cell comprises a gating element.

[0071] In the disclosed embodiment, the voltage application method on the selected word line is adjusted, and the voltage is first increased to a slightly lower first voltage, and a sensing operation is added to this voltage to determine whether the target memory cell is in the on state. If the target memory cell is in the on state, the first voltage is maintained to complete the write operation. At this time, since the first voltage is relatively low, the non-target memory cell coupled to the selected word line will not be opened, so there is no need to charge the unselected bit line to a higher fifth voltage, thereby saving power consumption. If it is determined after the sensing operation that the target memory cell is not opened, the voltage applied to the selected word line is increased to a higher fourth voltage to open the target memory cell to complete the write operation. At this time, the unselected bit line needs to be charged to the fifth voltage to prevent the non-target memory cell coupled to the selected word line from being opened by mistake.

[0072] Based on the above memory, an embodiment of the present disclosure further provides a memory system, which includes the memory described in any of the above embodiments and a memory controller coupled to the memory, and the memory controller is configured to control the memory.

[0073] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0074] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0075] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A memory, characterized in that: The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the peripheral circuit is configured as follows: In response to a write command, applying a first voltage to a selected word line coupled to a target memory cell, applying a second voltage to a selected bit line coupled to the target memory cell, and applying a third voltage to unselected bit lines; In response to the write command, performing a sensing operation on the target memory cell; Based on the comparison result of the voltage on the selected bit line and the reference voltage after performing a sensing operation on the target memory cell, determine whether to apply a fourth voltage to the selected word line and determine whether to apply a fifth voltage to the unselected bit line; the fourth voltage is greater than the first voltage, and the fifth voltage is greater than the third voltage.

2. The memory according to claim 1, characterized in that: The peripheral circuit is configured as: Based on the voltage on the selected bit line being less than the reference voltage after the sensing operation is performed on the target memory cell, applying the fourth voltage to the selected word line and applying the fifth voltage to the unselected bit line; Performing a set operation or a reset operation on the target storage unit; or, Based on the voltage on the selected bit line being greater than the reference voltage after the sensing operation is performed on the target memory cell, not applying the fourth voltage to the selected word line, and not applying the fifth voltage to the unselected bit line; A set operation or a reset operation is performed on the target storage unit.

3. The memory according to claim 1 or 2, characterized in that: The multiple memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; and the first voltage is less than the minimum voltage of the first threshold voltage distribution.

4. The memory according to claim 3, characterized in that: A difference between the first voltage and the second voltage is greater than a minimum voltage of the second threshold voltage distribution and less than a maximum voltage of the second threshold voltage distribution.

5. The memory according to claim 3, characterized in that: The peripheral circuit is configured as: In response to the write command, a ground voltage is applied to unselected word lines; and an absolute value of the second voltage is smaller than a minimum voltage of the first threshold voltage distribution.

6. The memory according to claim 3, characterized in that: The first voltage is greater than 0, and the second voltage is less than 0.

7. The memory according to claim 3, characterized in that: A difference between the fourth voltage and the second voltage is greater than a maximum voltage of the second threshold voltage distribution, and a difference between the fourth voltage and the fifth voltage is less than a minimum voltage of the first threshold voltage distribution.

8. The memory according to claim 1 or 2, characterized in that: The first voltage ranges from 3V to 4V; the second voltage ranges from -4V to -3V; the third voltage is a ground voltage; the fourth voltage ranges from 4V to 5V; and the fifth voltage ranges from 0.6V to 1.2V.

9. The memory according to claim 1, characterized in that: The peripheral circuit includes a current mirror circuit; the selected bit line is connected to the current mirror circuit; the current mirror circuit is configured as follows: In response to a write command, a current pulse is provided so that a sensing operation is performed on the target memory cell.

10. The memory according to claim 1, characterized in that: The memory includes a phase change memory or a selector-only memory.

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