Control method, parameter calculation method, memory and storage system

Abstract

The invention provides a control method, a parameter calculation method, a memory and a storage system. The memory comprises a plurality of memory cells and a plurality of first transistors; the plurality of storage units correspond to the plurality of first transistors; the control method comprises the following steps: reading a plurality of first transistors based on a first verification read voltage, and obtaining a first read failure number; the value of the first reading failure number corresponds to different product stages of the memory. A first voltage is stored in the plurality of first transistors. The first voltage is equal to the first verification read voltage in voltage value. The product stage is related to the number of data processing times of the plurality of storage units. And selecting a target table item from the plurality of table items according to the value of the first reading failure number. The table items are used for recording processing parameters for performing data processing on the plurality of storage units. The processing parameter includes an offset voltage value. Based on the operation, the processing rate of the memory is improved, the reading reliability of the memory is improved, and the waste of the storage space is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of chip storage technology, and in particular to a control method, a parameter calculation method, a memory, and a storage system. Background Art

[0002] The storage system includes a memory. The memory may be a flash memory (NAND). The storage unit in the flash memory may be used to store data. The performance and life of the storage unit may change due to the number of data processing times. The number of data processing times includes the number of data writing times, the number of data erasing times, etc. When the performance of the storage unit changes, the processing parameters based on which the data processing is performed on the storage unit will also change.

[0003] In order to ensure the reliability of the flash memory, during the data processing process of the memory, it is necessary to record each data processing operation and store the data processing times of the relevant storage unit, so as to adjust the processing parameters of the data processing according to the corresponding data processing times. However, in this implementation, the recording operation of the data processing times will occupy the processing time of the program and reduce the processing performance of the memory. In addition, recording these data processing times will also occupy a certain storage space of the memory. Summary of the invention

[0004] The embodiments of the present disclosure provide a control method, a parameter calculation method, a memory, and a storage system, which reduce the program processing time and storage space occupied while improving the reliability and service life of the flash memory.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present disclosure provides a control method, which is based on storage. The memory includes multiple storage cells and multiple first transistors. The multiple storage cells correspond to the multiple first transistors. The control method includes: reading the multiple first transistors based on a first verification read voltage to obtain a first read failure number. The value of the first read failure number corresponds to different product stages of the memory. A first voltage is stored in the multiple first transistors. The first voltage is equal to the voltage value of the first verification read voltage. The product stage is related to the number of data processing times of the multiple storage cells. According to the value of the first read failure number, a destination table entry is selected from multiple table entries. The table entry is used to record processing parameters for data processing of multiple storage cells. The processing parameters include an offset voltage value.

[0007] In the embodiment of the present disclosure, the confirmation of the product stage of the storage unit M can be realized through a verification read operation. By selecting corresponding table entries for different product stages. The data processing performance can be improved in the early stage of the life of the memory (for example, the processing speed of the loop programming is accelerated), and the reliability of data processing (for example, the reliability of reading data) can be improved in the late stage of the life. The first verification read voltage is used to verify and read multiple first transistors to obtain a first read failure number. The value of the first read failure number is related to the number of data processing times of multiple storage units. Therefore, different product stages can be divided into multiple storage units by the value of the first read failure number, and corresponding table entries can be designed. Different table entries carry processing parameters for data processing operations on storage units under different product stages. In the subsequent work of the memory, it is only necessary to perform a read verification operation on the first transistor to confirm the current product stage of multiple storage units. The embodiment of the present disclosure does not need to record the number of data processing after each data processing operation, and store the number of data processing times, which can improve the processing performance of the memory, reduce the processing time of the memory, and avoid the occupation of storage space by recording the number of data processing times.

[0008] In some possible implementations, the above-mentioned selecting a target table item from a plurality of table items according to the value of the first read failure number includes: if the first read failure number is less than or equal to the first value, selecting the first target table item from the plurality of table items. The first target table item corresponds to the first product stage of the plurality of storage units. If the first read failure number is greater than the first value, selecting the second target table item from the plurality of table items. The second target table item corresponds to the second product stage of the plurality of storage units. In an embodiment of the present disclosure, a first value may be set, and the first value is a reference value for judging the read failure number. In the case where the first verification read voltage is the same, the first product stage and the second product stage are divided by the read failure number. The corresponding table items are respectively designed according to the first product stage and the second product stage. In actual programming, a read verification operation is performed by the first verification read voltage, and the corresponding first read failure number is obtained, and the first read failure number is compared with the preset first value. When the first read failure number is less than or equal to the first value, it means that the memory is in the first product stage at this time, and the first target table item corresponding to the first product stage can be obtained. When the first read failure number is greater than the first value, it means that the memory is currently in the second product stage, and the second target table entry corresponding to the second product stage can be obtained.

[0009] In some possible implementations, the first verification read voltage is a voltage value obtained according to the first voltage set; the first voltage set includes multiple threshold voltages; the multiple threshold voltages are: threshold voltages corresponding to multiple first transistors under multiple different programming times. In an embodiment of the present disclosure, the performance change of the first transistor is positively correlated with the number of data processing times of the storage unit. The first verification voltage is used to: perform read verification on multiple storage units after data processing on multiple storage units. The performance change of the first transistor is positively correlated with the number of data processing times of the storage unit. Therefore, the first verification voltage can be obtained according to the performance change of the first transistor of the non-storage unit when the storage unit is under different data processing times. Based on the first verification voltage to verify the reading of the storage unit, the value of the first read failure number obtained can also indicate the number of data processing times of the storage unit.

[0010] In some possible implementations, the voltage magnitude of the first verification read voltage is between the first threshold voltage and the second threshold voltage. The first threshold voltage is the threshold voltage corresponding to the first transistor at the first programming number. The first programming number belongs to the programming number corresponding to the first product stage. The second threshold voltage is the threshold voltage corresponding to the first transistor at the second programming number. The second programming number belongs to the programming number corresponding to the second product stage. In an embodiment of the present disclosure, a plurality of first transistors are read by the first verification read voltage to divide the first product stage and the second product stage, and the first verification read voltage can be selected as a voltage between the first threshold voltage and the second threshold voltage. Among them, the first threshold voltage is the threshold voltage at a first programming number corresponding to the first product stage. The second threshold voltage is the threshold voltage at a second programming number corresponding to the second product stage.

[0011] In some possible implementations, the first programming number is one tenth of the second programming number. In the embodiment of the present disclosure, the starting programming number of the first product stage can be set to one tenth of the starting programming number of the second product stage. When the starting programming number of the first product stage is used as the first programming number, and the starting programming number of the second product stage is used as the second programming number, the first verification voltage obtained by combining the first programming number and the second programming number, when the first verification voltage is used to verify the reading of multiple first transistors, the first read failure number that can be obtained can more accurately divide the first product stage and the second product stage.

[0012] In some possible implementations, the first transistor is a programming selection transistor or a dummy storage transistor. In an embodiment of the present disclosure, the performance of the first transistor is affected by the increase in the number of data processing times. In an actual memory, the performance of the programming selection transistor or the dummy storage transistor will be affected by the increase in the number of data processing times. Therefore, the programming selection transistor or the dummy storage transistor can be used as the first transistor. In some examples, the programming selection transistor can be a TSG transistor, a BSG transistor, etc.

[0013] In some possible implementations, the offset voltage value includes a programming offset voltage value and / or a reading offset voltage value. The processing parameters also include a programming start voltage value and / or a verification start voltage value. The control method also includes: outputting multiple programming voltages and / or multiple verification read voltages. The lowest voltage value of the multiple programming voltages is the programming start voltage value. The multiple verification read voltages control the lowest voltage value of the multiple verification read voltages in a step unit with the read offset voltage value as the verification start voltage value. In the embodiment of the present disclosure, the threshold voltage of the storage unit will also change with the increase of the number of data processing times. When the threshold voltage of the storage unit changes, the parameters of its data processing will also change. For example, in the method of loop programming, the programming start voltage value for programming and the verification start voltage value after programming need to be adaptively adjusted. At the same time, the programming offset voltage value between multiple programming operations in the loop programming and the reading offset voltage value between multiple verification operations need to be adaptively adjusted. By determining the product stage, selecting an adaptive target table entry for loop programming can improve the processing speed of programming and improve the reliability of reading.

[0014] In a second aspect, an embodiment of the present disclosure provides a parameter calculation method, which is based on at least one memory. Each memory includes multiple storage cells and multiple first transistors. Multiple storage cells correspond to multiple first transistors. The parameter calculation method includes: obtaining a first verification read voltage based on multiple first transistors. A first voltage is stored in multiple first transistors; the first voltage is equal to the voltage value of the first verification read voltage. Based on the first verification read voltage, multiple first transistors are read to obtain a first read failure number. According to the value of the first read failure number, different product stages are divided for multiple storage cells of at least one memory and corresponding multiple table entries are obtained. The table entries are used to record processing parameters for data processing of multiple storage cells. The processing parameters include offset voltage values.

[0015] In some possible implementations, the above-mentioned dividing the storage units of at least one memory into different product stages and obtaining corresponding multiple table entries according to the value of the first read failure number includes: if the first read failure number is less than or equal to the first value, the corresponding multiple storage units are in the first product stage. A first destination table entry is obtained according to the first product stage. If the first read failure number is greater than the first value, the corresponding storage unit is in the second product stage. A second destination table entry is obtained according to the second product stage.

[0016] In some possible implementations, obtaining the first verification read voltage according to the first transistor includes: obtaining a first voltage set according to a plurality of first transistors. The first voltage set includes a plurality of threshold voltages. The plurality of threshold voltages are: threshold voltages corresponding to the plurality of first transistors under a plurality of different programming times. The first verification read voltage is obtained according to the first voltage set.

[0017] In some possible implementations, the voltage magnitude of the first verification read voltage is between a first threshold voltage and a second threshold voltage. The first threshold voltage is a threshold voltage corresponding to the plurality of first transistors at a first programming number. The first programming number belongs to a programming number corresponding to a first product stage. The second threshold voltage is a threshold voltage corresponding to the plurality of first transistors at a second programming number. The second programming number belongs to a programming number corresponding to a second product stage.

[0018] In some possible implementations, the first programming number is one tenth of the second programming number.

[0019] In some possible implementations, the plurality of first transistors are programming selection transistors or dummy storage transistors.

[0020] In some possible implementations, the offset voltage value includes a programming offset voltage value and / or a reading offset voltage value. The processing parameter also includes a programming start voltage value and / or a verification start voltage value.

[0021] In a third aspect, an embodiment of the present disclosure further provides a memory, which includes a control circuit, a register, a driving circuit, a read verification circuit, a plurality of storage units, and a plurality of first transistors. The plurality of first transistors correspond to the plurality of first transistors. A plurality of table entries are stored in the register. The driving circuit is used to: output a first verification read voltage to the plurality of first transistors. The first verification read voltage is used to turn on and read the plurality of first transistors. The read verification circuit is used to: output a plurality of first indication signals to the control circuit. The plurality of first indication signals are used to indicate the first read failure number corresponding to the plurality of first transistors. The value of the first read failure number corresponds to the different product stages of the plurality of storage units. The product stage is related to the number of data processing times of the plurality of storage units. The control circuit is used to: select a destination table entry from the plurality of table entries in the register according to the value of the first read failure number. The table entry is used to record processing parameters for data processing of the plurality of storage units. The processing parameters include an offset voltage value.

[0022] In some possible implementations, the control circuit is further configured to: if the first read failure number is less than or equal to the first value, select a first destination table entry from the plurality of table entries. The first destination table entry corresponds to a first product stage of the plurality of storage units. If the first read failure number is greater than the first value, select a second destination table entry from the plurality of table entries. The second destination table entry corresponds to a second product stage of the plurality of storage units.

[0023] In some possible implementations, the offset voltage value includes a programming offset voltage value and / or a reading offset voltage value. The processing parameters also include a programming start voltage value and / or a verification start voltage value. The control circuit is also used to: control the drive circuit to output multiple programming voltages and / or multiple verification read voltages. The lowest voltage value of the multiple programming voltages is the programming start voltage value. The multiple verification read voltages control the lowest voltage value of the multiple verification read voltages as the verification start voltage value in step units with the read offset voltage value.

[0024] In a fourth aspect, an embodiment of the present application further provides a storage system, the storage system comprising a controller and the memory as described in the third aspect. The controller is coupled to the memory.

[0025] In a fifth aspect, an embodiment of the present application further provides an electronic device, the electronic device comprising a processor and the storage system as described in the fourth aspect. The processor is coupled to the storage system.

[0026] It can be understood that the beneficial effects that can be achieved by the parameter calculation method, memory, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the control method described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0028] Figure 1 is a schematic diagram of a module of a memory according to some embodiments;

[0029] Figure 2 is a schematic diagram of a module of a storage array according to some embodiments;

[0030] Figure 3 A flow chart of a parameter calculation method according to some embodiments Figure 1 ;

[0031] Figure 4 A flow chart of a parameter calculation method according to some embodiments Figure 2 ;

[0032] Figure 5 is a schematic diagram of distribution of threshold voltages of a first voltage set as a function of data processing times according to some embodiments;

[0033] Figure 6 A flow chart of another parameter calculation method according to some embodiments is shown in FIG. Figure 3 ;

[0034] Figure 7 A control method according to some embodiments is shown in FIG. Figure 1 ;

[0035] Figure 8 FIG. 1 is a flow chart of another control method according to some embodiments. Figure 2 ;

[0036] Fig. 9 A module diagram of a storage system according to some embodiments Figure 1 ;

[0037] Fig.10 A schematic diagram of another module of a storage system according to some embodiments Figure 2 ;

[0038] Fig.11 A schematic diagram of a module of an electronic device according to some embodiments. DETAILED DESCRIPTION

[0039] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0040] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0043] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0044] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0045] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0046] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0047] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0048] The embodiment of the present disclosure provides a memory, such as Figure 1 As shown, the memory 100 includes a peripheral circuit 10 and a memory array 20. The peripheral circuit 10 includes a control circuit 1, a register 2, a drive circuit 3, a page buffer circuit 4, a row decoding circuit 5, a column decoding circuit 6 and a first interface circuit 7. The page buffer circuit 4 also includes a read verification circuit 41. Figure 1 and Figure 2 As shown, the memory array 20 includes a plurality of memory cells M. Among them: the control circuit 1 is coupled to the register 2, the driving circuit 3, the page buffer circuit 4, the row decoding circuit 5, the column decoding circuit 6, the memory array 20 and the first interface circuit 7 respectively. The driving circuit 3 is also coupled to the page buffer circuit 4, the row decoding circuit 5 and the column decoding circuit 6 respectively. The column decoding circuit 6 is also coupled to the first interface circuit 7. The memory 100 is coupled to the peripheral device through the first interface circuit 7.

[0049] For example, Figure 2As shown, in the memory array 20 of the memory 100, a plurality of memory cell strings are included, each of which includes a top select gatecut (TSG) transistor, a spare dummy storage transistor, a memory cell M, a bottom select gatecut (BSG) transistor, and the like. The TSG transistor, the dummy storage transistor, and the BSG transistor in each memory cell string are connected to a plurality of memory cells M via a bit line (BL). The TSG transistor and the BSG transistor are used to assist in the selection of different bit lines BL, and the like. The gates of each TSG transistor, the BSG transistor, the dummy storage transistor, and the memory cell M are coupled to corresponding different word lines (WL). By charging and discharging the selected bit line BL and the selected WL, the selected transistor can be read and processed. The dummy storage transistor can provide a stable working environment for the memory cell M at the edge of the memory array 20 (i.e., the same working environment as other non-edge memory cells M). At the same time, in some examples, the dummy storage transistor can also store relevant operation data of some functions of the memory 100, and the like.

[0050] In some possible implementations, the read verification circuit 41 may be a sense latch in the page buffer circuit 4 .

[0051] In some possible implementations, the memory 100 may be a flash memory (NAND). In some examples, the memory cell M in the memory array 20 may be a single level memory cell (SLC), a double level memory cell (MLC), a triple level memory cell (TLC), a quadruple level cell (QLC), a penta level cell (PLC), etc. In a memory cell M based on SLC, MLC, TLC, etc., as the number of levels increases, the number of data bits that can be stored in each memory cell M will also increase. Parameter table entries are stored in register 2. The parameter table entries are used to record the processing parameters of the memory 100 performing data processing operations.

[0052] The data processing operation of the memory 100 includes programming operation, data reading operation and erasing operation, etc. The programming operation of the memory 100 can be divided into single pressure programming and step programming. Single pressure programming refers to programming the selected storage cell M with a larger threshold voltage. The programming speed of single pressure programming is faster, but it is easy to have the problem of over-programming, resulting in reduced reliability of the memory 100. Step programming refers to implementing programming operations through multiple loop programming. Each loop programming includes a programming stage and a read verification (Program Verify, PV) stage. Among them, multiple loop programming will apply multiple programming voltages with different voltage values ​​in a certain step to the selected storage cell M to perform multiple loop programming stages and verification stage processing operations. The number of programming stages and verification stages is related to the number of erased states and programming states of the storage cell M. The erased state corresponds to a data value of 0. The programming state corresponds to a data value of 1 and above. Usually, multiple loop programming includes at least one previous rough programming and the last fine programming. In rough programming, the processing operations of the programming stage and the verification stage are implemented with smaller steps. In the last fine programming, the processing operations of the programming phase and the verification phase are implemented in relatively large steps.

[0053] Taking the storage cell M as SLC as an example, the SLC has a data bit number, including data values ​​0 and 1, that is, corresponding to 1 erase state and 1 programming state. For SLC, the programming operation of multiple storage cells M in a certain storage area (for example, a storage block or a storage page) can be realized by two cycles of programming in a loop programming manner. When programming multiple storage cells M: in the initial programming stage, the control circuit 1 selects multiple storage cells M in the storage area based on the driving circuit 3, the row decoding circuit 5 and the column decoding circuit 6, and firstly, the selected multiple storage cells M need to be programmed with the program start voltage as the starting threshold voltage. In the read verification stage after the initial programming stage, the selected multiple storage cells M are verified and read based on the verification start voltage (verify start loop), and multiple first indication signals are output to the control circuit 1 through the read verification circuit 41 in the page cache circuit 4. The multiple first indication signals are used to indicate the verification reading results of the corresponding multiple storage cells M. When a certain storage cell M passes the verification, it means that the storage cell M has been programmed to the target programming state, and the subsequent programming stage stops programming it. When a certain storage cell M fails to pass the verification, it means that the storage cell M has not been programmed to the target programming state, and the subsequent programming stage continues to program it. The control circuit 1 can determine the number of failed bits (Fail Bit Count, FBC) according to multiple first indication signals. FBC is used to indicate the number of storage cells M that have not passed the verification. In the programming stage of the second fine programming, the value of the programming start voltage is increased stepwise with a certain programming offset voltage value, and the storage cells M that have not passed the verification are programmed. Similarly, when in the application scenarios of MLC, TLC, etc., there are more programming states compared to the application scenarios of SLC. More number of loop programming is also required. In each loop programming, compared with the previous loop programming, the size of the verification read voltage in the verification stage is increased stepwise with a certain read offset voltage value. Exemplarily, the size of the read offset voltage value in two adjacent loop programming stages can be the same or different. The size of the programming offset voltage value in two adjacent loop programming stages can be the same or different.

[0054] Because the performance of each storage unit M in NAND is affected by the number of data processing operations, such as programming operations, erasing operations, etc., will cause wear of the storage unit M and reduce the life of the storage unit M. Depending on the type of storage unit M, the number of times the storage unit M can perform data processing operations is also different. Generally, as the number of data bits of the storage unit M increases, the number of data processing operations that can be performed decreases accordingly. For example, some SLC-based memories 100 can perform data processing operations up to hundreds of thousands of times, while some TLC, QLC or PLC-based memories 100 can perform data processing operations only hundreds of thousands of times. As the number of programming times of the storage unit M increases, the performance of the storage unit M changes, and the processing parameters for the data processing operations on it also need to be adjusted. In order to ensure the reliability of the memory 100, different table entries need to be set for storage units M with different data processing times, and each table entry records the processing parameters required for the storage unit M corresponding to different data processing times to perform data processing operations. In actual applications, the number of data processing times of multiple storage units M in the relevant storage area is recorded after each data processing. When the data of the multiple storage units M in the storage area are processed subsequently, the corresponding table entry is selected to perform the current data processing operation according to the recorded data processing times. PROG ) is an important indicator to measure its performance. However, under this implementation, the recording operation of the number of data processing times will occupy the processing time of the program and reduce the processing performance of the memory. In addition, recording these data processing times will also occupy a certain storage space of the memory.

[0055] In order to improve the processing performance of the memory 100 while ensuring the reliability of the memory 100 at different product stages, the embodiment of the present disclosure provides a parameter calculation method based on the following steps: Figure 1 and Figure 2 The memory 100 of the structure shown in the figure executes the parameter calculation method. Figure 3 As shown, the parameter calculation method includes the following steps S110 to S130:

[0056] S110 , obtaining a first verification voltage according to the first transistor M1 .

[0057] In some possible implementations, the performance change of the first transistor is positively correlated with the number of data processing times of the memory cell M. The first verification voltage is used to: after data processing is performed on the multiple memory cells M, read verification is performed on the multiple memory cells M. In the embodiment of the present disclosure, the performance change of the first transistor M1 is positively correlated with the number of data processing times of the memory cell M. Therefore, the first verification voltage can be obtained according to the performance change of the first transistor M1 of the non-memory cell M when the memory cell M is under different data processing times. Based on the first verification voltage, the value of the first read failure number obtained to verify the reading of the memory cell M can also indicate the number of data processing times of the memory cell M.

[0058] For example, Figure 2 As shown, the first verification voltage can be obtained based on one or more memories 100. One or more memories 100 are memories that have been subjected to data processing operations. In actual data processing operations, the performance of TSG transistors, BSG transistors, dummy storage transistors, etc. will change with the increase in the number of data processing times. Therefore, at least one of the TSG transistors, BSG transistors, dummy storage transistors, etc. can be used as the first transistor M1 to obtain the first verification read voltage.

[0059] In some possible implementations, such as Figure 4 As shown, step S110 specifically includes the following operations of step S111 to step S112:

[0060] S111 . Obtain a first voltage set according to the first transistor M1 .

[0061] Exemplarily, when the number of data processing times of the memory cell M in the memory array 20 of the memory 100 increases, the performance of the first transistor M1 of the non-memory cell M will also change, and as the performance changes, the threshold voltage of the first transistor M1 will also change. The change of the threshold voltage of the first transistor M1 under different data processing times is obtained to obtain multiple threshold voltages. The multiple threshold voltages are: the threshold voltages corresponding to the first transistor M1 under multiple different programming times. The first voltage set is obtained by merging the multiple threshold voltages.

[0062] S112 , obtaining a first verification voltage according to the first voltage set.

[0063] In some possible implementations, the change of the multiple threshold voltages in the first voltage set is related to the number of data processing times. According to the distribution of the multiple threshold voltages in the first voltage set at different product stages, a corresponding threshold voltage is selected as the first verification voltage.

[0064] Exemplarily, the voltage magnitude of the first verification voltage is between a first threshold voltage and a second threshold voltage. The first threshold voltage is a threshold voltage corresponding to the first transistor M1 at a first programming number; the first programming number belongs to a programming number corresponding to a first product stage; the second threshold voltage is a threshold voltage corresponding to the first transistor M1 at a second programming number; the second programming number belongs to a programming number corresponding to a second product stage.

[0065] For example, Figure 5 As shown, a schematic diagram of the change of the first voltage set obtained by the dummy storage transistor of a certain model of memory 100 and the number of data processing times of the memory 100 is shown. According to the number of data processing times of the storage unit M, the memory 100 can be divided into two or more product stages according to the number of data processing times. In the interval of 0-100 for the number of data processing times, the threshold voltage Vth of the first transistor M1 varies greatly, and this part can be used for purposes such as factory testing of the memory 100. In the interval of 100-1000 for the number of data processing times, the threshold voltage Vth of the first transistor M1 still varies, but the variation range gradually becomes flat, and this stage can be used as the first product stage of the memory 100, and the first product stage is the factory stage of the memory 100, that is, the beginning of life (BOL) stage. When the number of data processing times is above 1000, the change of the threshold voltage Vth is small, but the memory 100 may have problems such as device aging, such as transistor aging caused by hot carrier injection in the transistors in the memory 100. This stage can be classified as the second product stage of the memory 100, namely, end of life (EOL). Similarly, the threshold voltage of the memory cell M will also change with the number of data processing times.

[0066] Exemplarily, the first programming number is one tenth of the second programming number. In the embodiment of the present disclosure, when the memory 100 is generally divided into EOL and BOL, the starting programming number of BOL is one tenth of the starting programming number of EOL. Exemplarily, the starting programming number of BOL (i.e., 100 times) can be selected as the first programming number. The starting programming number of EOL (i.e., 1000 times) is selected as the second programming number. Figure 5 As shown, the threshold voltage corresponding to the first programming number is 1400mv, i.e., 1.4V. The threshold voltage corresponding to the second programming number is 1600mv, i.e., 1.6V. A threshold voltage between 1.4V and 1.6V can be selected as the first verification read voltage. In some examples, an average value of 1.5V can be taken as the first verification read voltage. In some examples, the mode can be taken to obtain the first verification read voltage. In some examples, a threshold voltage can also be calculated based on other methods as the first verification read voltage.

[0067] S120 , reading a plurality of first transistors M1 based on a first verification read voltage to obtain a first read failure number.

[0068] In the embodiment of the present disclosure, after the value of the first verification read voltage is determined, the first verification read voltage is used to read the plurality of first transistors M1 to obtain the first read failure numbers corresponding to the plurality of first transistors M1.

[0069] S130 . According to the value of the first read failure number, multiple storage units M of at least one memory 100 are divided into different product stages and a corresponding plurality of table entries are obtained.

[0070] In some possible implementations, such as Figure 6 As shown, step S130 includes the following operations of step S131A to step S132A, and the operations of step S131B to step S132B:

[0071] S131A: If the first read failure number is less than or equal to the first value, determine that the corresponding plurality of storage units are in the first product stage.

[0072] S132A. Obtain a first destination table entry according to the first product stage design.

[0073] S131B: If the first read failure number is greater than the first value, determine that the corresponding storage unit is in the second product stage.

[0074] S132B. Obtain a second destination table entry according to the second product stage design.

[0075] In an embodiment of the present disclosure, a first value may be set, which is a reference value for determining the number of read failures. In the case where the first verification read voltage is the same, the first product stage and the second product stage are divided by the number of read failures.

[0076] In this disclosure Figure 3 , Figure 4 and Figure 6 In the illustrated embodiment, a first voltage set is obtained by acquiring the threshold voltages of a plurality of first transistors M1. The memory 100 is divided into a plurality of product stages based on the different data processing times of the plurality of storage units M, and a first verification voltage is obtained according to the threshold voltages under the plurality of product stages. The first verification voltage is used as the verification read voltage of the plurality of first transistors M1 to perform verification reading on the plurality of first transistors M1, and obtain a first read failure number. According to the first read failure number and the data processing times, the plurality of storage units M are re-divided into product stages, and corresponding processing parameters are designed for the re-divided product stages, and the plurality of processing parameters are carried on a plurality of table entries.

[0077] The embodiment of the present disclosure also provides a control method, based on the following Figure 1 and Figure 2 The memory 100 of the structure shown in FIG. Figure 7 As shown, the control method includes the following steps S210-S230:

[0078] S210 , reading a plurality of first transistors based on a first verification read voltage to obtain a first read failure number.

[0079] Exemplarily, the value of the first read failure number corresponds to different product stages of the memory. Multiple memory cells correspond to multiple first transistors. A first voltage is stored in the multiple first transistors; the first voltage is equal to the voltage value of the first verification read voltage. The product stage is related to the number of data processing times of the multiple memory cells. In an embodiment of the present disclosure, a first voltage is stored in the first transistor M1, and the voltage value of the first voltage is equal to the voltage value of the first verification read voltage. The first verification read voltage is used to verify the reading of multiple first transistors M1, and the first read failure number is obtained by verification reading. According to the size of the first read failure number, the product stage corresponding to the multiple memory cells M is determined.

[0080] For example, Figure 1 and Figure 2 As shown, the driving circuit 3 is used to: output a first verification read voltage to the plurality of first transistors M. The first verification read voltage is used to turn on the plurality of first transistors M1 for verification reading. The read verification circuit 41 is used to: output a plurality of first indication signals to the control circuit 1. The plurality of first indication signals are used to indicate the number of first read failures after the verification reading of the plurality of first transistors M1. The value of the first read failure number corresponds to different product stages of the plurality of storage cells M. The product stage is related to the number of data processing times of the plurality of storage cells M.

[0081] In some examples, the first verification read voltage is a voltage value obtained according to the first voltage set. The first voltage set includes multiple threshold voltages. The multiple threshold voltages are: threshold voltages corresponding to multiple first transistors M1 under multiple different data processing times. In some examples, the voltage magnitude of the first verification read voltage is between the first threshold voltage and the second threshold voltage. The first threshold voltage is the threshold voltage corresponding to the first transistor under the first programming number. The first programming number belongs to the programming number corresponding to the first product stage. The second threshold voltage is the threshold voltage corresponding to the first transistor under the second programming number. The second programming number belongs to the programming number corresponding to the second product stage. In some examples, the first programming number is one tenth of the second programming number. In the embodiments of the present disclosure, for the description of the specific technical principles and technical effects of the voltage value obtained by the first verification read voltage being the first voltage set, reference can be made to the relevant description in the embodiment of the aforementioned parameter calculation method, which will not be repeated here.

[0082] In some examples, the processing parameters also include a program start voltage value and / or a verify start voltage value.

[0083] In some examples, the first transistor M1 is a program selection transistor or a dummy memory transistor.

[0084] S220: Select a target entry from multiple entries according to the value of the first read failure number.

[0085] In some possible implementations, such as Figure 1 and Figure 2 As shown, the control circuit 1 is used to select a destination table entry from a plurality of table entries in the register 2 according to the value of the first read failure number. The plurality of table entries are used to record processing parameters for data processing of the plurality of storage units M. The processing parameters include an offset voltage value. In the embodiment of the present disclosure, after inputting a plurality of first indication signals, the control circuit 1 can determine the first read failure number after verification reading of the plurality of first transistors M1 based on the first verification read voltage. The product stage corresponding to the current plurality of storage units M can be determined according to the first read failure number, and the destination table entry is selected from the plurality of table entries in the register 2 according to the determined product stage. The destination table entry is the table entry corresponding to the determined product stage. Compared with the scheme of recording the number of data processing times and storing the data number results multiple times in the operation of loop programming, and then selecting the destination table entry by reading the result of the number of data processing times during data processing, in the embodiment of the present disclosure, by setting the first verification read voltage for the memory 100, the first read failure number corresponding to the plurality of storage units M in the memory 100 is obtained based on the first verification read voltage, and the plurality of storage units M corresponding to a certain product stage of the memory 100 is directly determined according to the value of the first read failure number. And the corresponding target table entry is selected for subsequent data processing operations. In the embodiment of the present disclosure, the operation of performing the corresponding number of records after each data processing operation is avoided. Taking the storage unit M as SLC as an example, only one read operation based on the first verification read voltage is required to confirm the product stage corresponding to the multiple storage units M. The embodiment of the present disclosure omits the program operation of the memory 100 to record the number of data processing operations, reduces the processing time of the memory 100, and improves the processing speed of the data processing operation. In addition, the memory 100 does not need to perform additional continuous storage records of the processing times, which reduces the storage resource occupation of the memory 100.

[0086] In some possible implementations, such as Figure 8 As shown, step S220 may include the following operations of step S220A or step S220B:

[0087] S220A: If the first read failure number is less than or equal to the first value, select a first destination entry from the multiple entries.

[0088] S220B: If the first read failure number is greater than the first value, select a second destination entry from the multiple entries.

[0089] For example, Figure 1 As shown, the control circuit 1 is also used for: if the first read failure number is less than or equal to the first value, then selecting a first destination table item from a plurality of table items; the first destination table item corresponds to the first product stage of the plurality of storage units M. If the first read failure number is greater than the first value, then selecting a second destination table item from a plurality of table items; the second destination table item corresponds to the second product stage of the plurality of storage units M. In the embodiment of the present disclosure, the corresponding table items are respectively designed according to the first product stage and the second product stage. In actual programming, a read verification operation is performed by a first verification read voltage, and the corresponding first read failure number is obtained, and the first read failure number is compared with the preset first value. When the first read failure number is less than or equal to the first value, it means that the memory 100 is in the first product stage at this time, and the first destination table item corresponding to the first product stage can be obtained. When the first read failure number is greater than the first value, it means that the memory 100 is in the second product stage at this time, and the second destination table item corresponding to the second product stage can be obtained.

[0090] S230, output multiple voltages with the offset voltage value as a step unit.

[0091] In some possible implementations, as the number of data processing times increases, the performance of the memory cell M will change. For example: the offset of the threshold voltage of the turned-on memory cell M, etc. Therefore, in order to ensure the reliability of the data processing operation of the memory 100, the memory 100 can be divided into different product stages according to the number of data processing times of the memory cell M. Different processing parameters are configured for different product stages, and these processing parameters are stored in the register 2 in the form of multiple table entries. The offset voltage value can be recorded in each table entry. The offset voltage value can be the offset voltage value related to different parameters related to the threshold voltage Vth. For example, the programming offset voltage value corresponding to the programming voltage during different times of loop programming under loop programming; or, the read offset voltage value corresponding to the verification read voltage during different times of loop programming; or, other offset voltage values ​​of voltages related to the threshold voltage Vth of the memory cell M.

[0092] Exemplarily, the multiple voltages may be programming voltages required for loop programming. The offset voltage value includes a programming offset voltage value between multiple programming voltages in loop programming. The processing parameters may also include a programming start voltage value. The control circuit 1 obtains a programming start voltage value and a programming offset voltage value according to the target table entry, and controls the drive circuit 3 to generate multiple programming voltages according to the programming start voltage value and the programming offset voltage value, so as to perform multiple programming operations on multiple storage cells M.

[0093] Exemplarily, the multiple voltages may be verification read voltages required for loop programming. The offset voltage value includes a read offset voltage value between multiple verification read voltages in loop programming. The processing parameters may also include a verification start voltage value. The control circuit 1 obtains a verification start voltage value and a read offset voltage value according to the target table entry, and controls the drive circuit 3 to generate multiple verification read voltages according to the programming start voltage value and the programming offset voltage value, so as to perform verification operations on multiple programming operations of multiple storage cells M.

[0094] The present disclosure Figure 7 and Figure 8 In the embodiment shown, the product stage of the storage unit M can be confirmed by a verification read operation. By selecting corresponding table entries for different product stages, the data processing performance can be improved in the BOL stage of the product of the memory 100 (for example, the processing speed of loop programming can be accelerated), and the reliability of data processing (for example, the reliability of reading data) can be improved in the EOL stage.

[0095] The embodiments of the present disclosure provide a control method, a parameter calculation method, a memory and a storage system. In the storage array of the memory, a plurality of storage units and a plurality of first transistors are included. The performance change of the first transistor is related to the number of data processing times of the corresponding plurality of storage units. Therefore, a first verification read voltage can be obtained based on the threshold voltage of the first transistor. The plurality of first transistors are verified and read by the first verification read voltage to obtain a first read failure number. The value of the first read failure number is also related to the number of data processing times of the plurality of storage units. Therefore, the value of the first read failure number can be used to divide the plurality of storage units into different product stages, and the corresponding table entries can be designed. The processing parameters for performing data processing operations on the storage units under different product stages are carried by different table entries. In the subsequent work of the memory, it is only necessary to perform a read verification operation on the first transistor to confirm the product stage in which the plurality of storage units are currently located. The embodiments of the present disclosure do not need to record the number of data processing times after each data processing operation, and store the number of data processing times, which can improve the processing performance of the memory, reduce the processing time of the memory, and avoid the occupation of storage space by recording the number of data processing times.

[0096] The embodiment of the present disclosure also provides a storage system, such as Fig. 9 , Fig.10 As shown, Fig. 9 is a block diagram of a storage system according to some embodiments. Fig.10 is a block diagram of a storage system according to some other embodiments.

[0097] See also Fig. 9 and Fig.10 Some embodiments of the present disclosure further provide a storage system 1000, which includes a controller 200 and the memory 100 of some embodiments as described above, wherein the controller 200 is coupled to the memory 100 to control the memory 100 to store data.

[0098] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0099] In some embodiments, see Fig. 9 , the storage system 1000 includes a controller 200 and a memory 100, and the storage system 1000 can be integrated into a memory card.

[0100] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0101] In other embodiments, see Fig.10 The storage system 1000 includes a controller 200 and a plurality of memories 100, and the storage system 1000 is integrated into a solid state drive (SSD).

[0102] In the storage system 1000, in some embodiments, the controller 200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0103] In other embodiments, the controller 200 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0104] In some embodiments, the controller 200 may be configured to manage data stored in the memory 100 and communicate with an external device (e.g., a host). In some embodiments, the controller 200 may also be configured to control operations of the memory 100, such as programming operations such as reading and erasing. In some embodiments, the controller 200 may also be configured to manage various functions regarding data stored or to be stored in the memory 100, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 200 is also configured to process error correction codes regarding data read from or written to the memory 100.

[0105] Of course, the controller 200 may also perform any other suitable functions, such as formatting the memory 100; for example, the controller 200 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0106] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0107] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0108] like Fig.11As shown, the electronic device 10000 may include the storage system 1000 described above, and may also include at least one of a processor 2000 and a cache.

[0109] Exemplarily, the processor 2000 may be a chip, specifically a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processing circuit (DSP), a microcontroller (MCU), a programmable logic device (PLD), or other integrated chips.

[0110] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A control method, characterized in that: Memory based; The memory comprises a plurality of memory cells and a plurality of first transistors; The plurality of storage cells correspond to the plurality of first transistors; The control method comprises: The first transistors are read based on a first verification read voltage to obtain a first read failure number; the value of the first read failure number corresponds to different product stages of the memory; a first voltage is stored in the first transistors; the first voltage is equal to the voltage value of the first verification read voltage; the product stage is related to the number of data processing times of the multiple storage units; According to the value of the first read failure number, a target table entry is selected from a plurality of table entries; the table entry is used to record processing parameters for data processing of the plurality of storage units; the processing parameters include an offset voltage value.

2. The control method according to claim 1, characterized in that: According to the value of the first read failure number, a destination entry is selected from a plurality of entries, including: If the first read failure number is less than or equal to a first value, selecting a first destination table entry from a plurality of table entries; the first destination table entry corresponds to a first product stage of the plurality of storage units; If the first read failure number is greater than the first value, a second destination table entry is selected from the plurality of table entries; the second destination table entry corresponds to the second product stage of the plurality of storage units.

3. The parameter calculation method according to claim 2, characterized in that: The first verification read voltage is a voltage value obtained according to a first voltage set; the first voltage set includes a plurality of threshold voltages; the plurality of threshold voltages are: threshold voltages corresponding to the plurality of first transistors under a plurality of different programming times.

4. The control method according to claim 3, characterized in that: The voltage magnitude of the first verification read voltage is between a first threshold voltage and a second threshold voltage; the first threshold voltage is a threshold voltage corresponding to the first transistor at a first programming number; the first programming number belongs to a programming number corresponding to the first product stage; The second threshold voltage is a threshold voltage corresponding to the first transistor under a second programming number; the second programming number belongs to a programming number corresponding to the second product stage.

5. The control method according to claim 4, characterized in that: The first programming number is one tenth of the second programming number.

6. The control method according to claim 3, characterized in that: The first transistor is a programming selection transistor or a dummy storage transistor.

7. The control method according to any one of claims 1 to 6, characterized in that: The offset voltage value includes a programming offset voltage value and / or a reading offset voltage value; the processing parameter also includes a programming start voltage value and / or a verification start voltage value; The control method further comprises: outputting a plurality of programming voltages and / or a plurality of verification read voltages; The lowest voltage value of the plurality of programming voltages is the programming start voltage value; and the plurality of verification read voltages are controlled in step units with the read offset voltage value, and the lowest voltage value of the plurality of verification read voltages is the verification start voltage value.

8. A parameter calculation method, characterized in that: Based on at least one memory; each of the memories comprises a plurality of memory cells and a plurality of first transistors; The plurality of storage cells correspond to the plurality of first transistors; The parameter calculation method comprises: A first verification read voltage is obtained according to the plurality of first transistors; a first voltage is stored in the plurality of first transistors; the first voltage is equal to a voltage value of the first verification read voltage; Reading the plurality of first transistors based on the first verification read voltage to obtain a first read failure number; According to the value of the first read failure number, the multiple storage units of the at least one memory are divided into different product stages and corresponding multiple table entries are obtained; the table entries are used to record processing parameters for data processing of the multiple storage units; the processing parameters include offset voltage values.

9. The parameter calculation method according to claim 8, characterized in that: The dividing the storage unit of the at least one memory into different product stages according to the value of the first read failure number and obtaining a corresponding plurality of table entries includes: If the first read failure number is less than or equal to a first value, the corresponding plurality of storage units are in a first product stage; a first destination table entry is obtained according to the first product stage; If the first read failure number is greater than the first value, the corresponding storage unit is in the second product stage; and a second destination table entry is obtained according to the second product stage.

10. The parameter calculation method according to claim 9, characterized in that: The obtaining a first verification read voltage according to the first transistor includes: A first voltage set is obtained according to the plurality of first transistors; the first voltage set includes a plurality of threshold voltages; the plurality of threshold voltages are: threshold voltages corresponding to the plurality of first transistors under a plurality of different programming times; The first verification read voltage is obtained according to the first voltage set.

11. The parameter calculation method according to claim 10, characterized in that: The voltage magnitude of the first verification read voltage is between a first threshold voltage and a second threshold voltage; the first threshold voltage is the threshold voltage corresponding to the plurality of first transistors at a first programming number; the first programming number belongs to the programming number corresponding to the first product stage; The second threshold voltage is a threshold voltage corresponding to the plurality of first transistors at a second programming number; the second programming number belongs to a programming number corresponding to the second product stage.

12. The parameter calculation method according to any one of claims 8 to 11, characterized in that: The plurality of first transistors are program selection transistors or dummy storage transistors.

13. A memory, characterized in that: It includes a control circuit, a register, a driving circuit, a read verification circuit, a plurality of storage units and a plurality of first transistors; the plurality of first transistors correspond to the plurality of first transistors; the register stores a plurality of table entries; The driving circuit is used to: output a first verification read voltage to the plurality of first transistors; the first verification read voltage is used to turn on and read the plurality of first transistors; The read verification circuit is used to: output a plurality of first indication signals to the control circuit; the plurality of first indication signals are used to indicate a first read failure number corresponding to the plurality of first transistors; the value of the first read failure number corresponds to a different product stage of the plurality of storage units; the product stage is related to the number of data processing times of the plurality of storage units; The control circuit is used for: According to the value of the first read failure number, a target table entry is selected from multiple table entries in the register; the table entry is used to record processing parameters for data processing of the multiple storage units; the processing parameters include an offset voltage value.

14. The memory according to claim 13, characterized in that: The control circuit is also used for: If the first read failure number is less than or equal to a first value, selecting a first destination table entry from a plurality of table entries; the first destination table entry corresponds to a first product stage of the plurality of storage units; If the first read failure number is greater than the first value, a second destination table entry is selected from the plurality of table entries; the second destination table entry corresponds to the second product stage of the plurality of storage units.

15. The memory according to claim 13, characterized in that: The offset voltage value includes a programming offset voltage value and / or a reading offset voltage value; the processing parameter also includes a programming start voltage value and / or a verification start voltage value; the control circuit is further used for: Controlling the driving circuit to output a plurality of programming voltages and / or a plurality of verification read voltages; The lowest voltage value of the plurality of programming voltages is the programming start voltage value; and the plurality of verification read voltages are controlled in step units with the read offset voltage value, and the lowest voltage value of the plurality of verification read voltages is the verification start voltage value.

16. A storage system, characterized in that: The storage system comprises a controller and the memory according to any one of claims 13 to 15; the controller is coupled to the memory.

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