Memory device

Abstract

The invention relates to a memory device. An example memory device includes a memory cell region including a memory cell array configured to store data and an anti-fuse cell array including a plurality of anti-fuse bit lines, a plurality of anti-fuse word lines, a plurality of program transistors, the plurality of programming transistors are electrically coupled to a first antifuse bit line of the plurality of antifuse bit lines and coupled in parallel with each other. The memory device includes a peripheral circuit region including an anti-fuse sense amplifier configured to output one-time programmable (OTP) data stored in a plurality of program transistors.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0103603 filed in the Korean Intellectual Property Office on August 8, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to memory devices. Background Art

[0004] Volatile memory generally cannot store data when power is off. For this reason, in some areas of volatile memory devices, one-time programmable (OTP) elements may be provided. By performing electrical fuse and anti-fuse operations on the OTP element, the information that needs to be stored is stored in the OTP element as fuse information.

[0005] A method of disposing an anti-fuse cell array in a memory device and storing fuse information in an anti-fuse manner using oxide breakdown characteristics of the anti-fuse cells in consideration of a manufacturing method, a degree of integration, etc. is being used. Summary of the invention

[0006] The present disclosure relates to memory devices, including memory devices that can store more fuse information and in which an anti-fuse cell array occupies a small area, memory devices with smaller chip sizes, memory devices with improved operational reliability for anti-fuse cells, and memory devices with improved operational speed for anti-fuse cells.

[0007] In some embodiments, a memory device includes a memory cell region and a peripheral circuit region, the memory cell region including a memory cell array configured to store data and an antifuse cell array including an antifuse cell, the peripheral circuit region including at least a portion overlapping the memory cell region in a planar manner, and including an antifuse sense amplifier configured to output one-time programmable (OTP) data stored in the antifuse cell.

[0008] In some embodiments, a memory device includes a memory cell region and a peripheral circuit region, the memory cell region including a memory cell array configured to store data and an antifuse cell array, the antifuse cell array including a plurality of antifuse bit lines, a plurality of antifuse word lines, and a plurality of programming transistors electrically coupled to a first antifuse bit line among the plurality of antifuse bit lines and coupled in parallel to each other, the peripheral circuit region including an antifuse sense amplifier configured to output one-time programmable (OTP) data stored in the plurality of programming transistors.

[0009] In some embodiments, a memory device includes a memory cell region and a peripheral circuit region, the memory cell region including a plurality of bit lines, a plurality of word lines and an antifuse cell array, the memory cell array including a memory vertical channel layer extending perpendicular to a direction in which the plurality of word lines extend on an upper surface of the plurality of bit lines, the antifuse cell array including antifuse cells, the peripheral circuit region including at least a portion overlapping the memory cell region in a planar manner, and including an antifuse sense amplifier configured to output one-time programmable (OTP) data stored in the antifuse cell.

[0010] In some embodiments, a memory device includes: a memory cell region including a memory cell array configured to store data and an anti-fuse cell array that does not overlap with the memory cell array in a planar manner, the anti-fuse cell array including anti-fuse cells; a peripheral circuit region including an anti-fuse sense amplifier configured to output one-time programmable (OTP) data stored in the anti-fuse cells; and a contact plug extending from an external pad disposed on an upper surface of the memory cell region, passing through at least a portion of the memory cell region, and electrically coupled to a circuit element of the peripheral circuit region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram illustrating a configuration of an example of a memory device.

[0012] Figure 2 is a view for explaining an example of an antifuse cell array.

[0013] Figure 3 is a circuit diagram showing an example of an anti-fuse unit.

[0014] Figure 4 is an example perspective view showing a memory device.

[0015] Figure 5 is a plan view showing an example of a memory cell region.

[0016] Figure 6 is a plan view showing an example of a peripheral circuit region.

[0017] Figure 7 is along Figure 5 Example cross-sectional views taken along lines AA and BB in FIG.

[0018] Figure 8 is along Figure 4 Example cross-sectional view taken along line CC' in FIG.

[0019] Fig. 9 is a circuit diagram showing another example of an anti-fuse unit.

[0020] Fig.10 and Fig.11 is an exemplary diagram for explaining the operation of a memory device.

[0021] Fig.12 is another exemplary diagram for explaining the operation of the memory device.

[0022] Fig.13 is a circuit diagram showing another example of an anti-fuse unit.

[0023] Fig.14 is another exemplary diagram for explaining the operation of the memory device.

[0024] Fig.15 and Fig.16 is an exemplary diagram for explaining an anti-fuse cell array.

[0025] Fig.17 is another exemplary diagram for explaining the operation of the memory device.

[0026] Fig.18 is a circuit diagram showing another example of an anti-fuse unit.

[0027] Fig.19 is another exemplary diagram for explaining the operation of the memory device.

[0028] Fig. 20 is an example diagram for explaining a memory device.

[0029] Fig.21 is another exemplary diagram for explaining a memory device.

[0030] Fig. 22 is a block diagram illustrating an example of a computing device. DETAILED DESCRIPTION

[0031] In the following detailed description, only certain embodiments of the present disclosure are shown and described by way of illustration. The present disclosure can be implemented in various ways and is not limited to the following implementations.

[0032] The drawings and description are to be regarded as illustrative in nature and not restrictive.Throughout the specification, like reference numerals refer to like elements.

[0033] In addition, for the sake of understanding and ease of description, the size and thickness of each configuration shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. In the drawings, for the sake of clarity, the thickness of layers, films, panels, regions, etc. are exaggerated. In addition, in the drawings, for the sake of understanding and ease of description, the thickness of some layers and regions is exaggerated.

[0034] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0035] Figure 1 is a block diagram illustrating a configuration of an example of a memory device.

[0036] The memory device 10 may include a memory cell array 210, an anti-fuse cell array 220, a sense amplifier 110, an anti-fuse sense amplifier 120, a row decoder 130, a column decoder 140, a control logic circuit 191, an address register 192, a bank control logic 193, a refresh counter 194, a column address (CA) latch 195, a row address multiplexer 196, an I / O gate circuit 197 and a data I / O buffer 198.

[0037] The memory cell array 210 may include a predetermined number of memory groups including memory channels. In some embodiments, the memory groups may include Figure 5 A plurality of sub-memory cell arrays 210_1 to 210_4 are shown in FIG.

[0038] Furthermore, in some implementations, the sense amplifier 110 , the row decoder 130 , and the column decoder 140 may include a plurality of sets of sense amplifiers, a plurality of sets of row decoders, and a plurality of sets of column decoders respectively coupled to the memory banks; however, they are not limited thereto.

[0039] The memory cell array 210 may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC located at intersections of the word lines WL and the bit lines BL. The memory device 10 may perform an operation of reading or writing data DQ on the plurality of memory cells MC.

[0040] The sense amplifier 110 may include a plurality of bit line sense amplifiers coupled to a plurality of bit lines BL of the memory cell array 210. The plurality of bit line sense amplifiers may detect data input or output through the bit lines BL and input or output the detected data. In some embodiments, the plurality of bit line sense amplifiers may be Figure 6 The bit line sense amplifier 111 in the description Figure 6 When , the arrangement of multiple bit line sense amplifiers will be described below.

[0041] The control logic circuit 191 may control the operation of the memory device 10. For example, the control logic circuit 191 may generate a control signal so that the memory device 10 performs a write operation or a read operation. Although not shown in the figure, the control logic circuit 191 may include a command decoder for decoding a received command CMD and a mode register for setting an operation mode of the memory device 10.

[0042] The address register 192 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 192. The address register 192 may provide the received bank address BANK_ADDR to the bank control logic 193 and provide the received row address ROW_ADDR to the row address multiplexer 196.

[0043] The bank control logic 193 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, the row decoder 130 and the column decoder 140 may activate the corresponding bank.

[0044] The row address multiplexer 196 may receive the row address ROW_ADDR from the address register 192 and the refresh row address REF_ADDR from the control logic circuit 191. The row address multiplexer 196 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 196 may be applied to the row decoder 130.

[0045] The row decoder 130 may decode the row address RA output from the row address multiplexer 196, thereby activating the word line corresponding to the row address RA. For example, the row decoder 130 may include a plurality of word line drivers for applying a word line driving voltage to the word line corresponding to the row address RA. In some embodiments, the plurality of word line drivers may include Figure 6 The sub-word line driver 131 in the embodiment of the present invention will be described below. Figure 6 The arrangement of multiple word line drivers is described.

[0046] In addition, the row decoder 130 may include a first repair unit RU1. The first repair unit RU1 may receive fuse information FI from the anti-fuse cell array 220 and perform a repair operation on the defective cell based on the fuse information FI. After the repair operation, when the row address RA associated with the defective cell is input, the first repair unit RU1 activates the redundant decoder in the row decoder 130. The activated redundant decoder may disable the decoder associated with the defective cell so that the defective cell is replaced by a redundant cell in the redundant memory cell array. The fuse information FI may include address information about the defective cell in the memory cell array 210. In some embodiments, the redundant decoder may be implemented as a separate external device.

[0047] The column address latch 195 may receive the column address COL_ADDR from the address register 192 and temporarily store the received column address COL_ADDR. In addition, the column address latch 195 may gradually increase the received column address COL_ADDR in a burst mode. The column address latch 195 may apply the temporarily stored or gradually increased column address to the column decoder 140.

[0048] Regarding the bank activated by the bank control logic 193 , the column decoder 140 may activate a bit line sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR among the sense amplifiers 110 through the I / O gating circuit 197 .

[0049] In addition, the column decoder 140 may include a second repair unit RU2. The second repair unit RU2 may receive fuse information FI from the anti-fuse cell array 220 and perform a repair operation on the defective cell based on the fuse information FI. After the repair operation, when the column address COL_ADDR associated with the defective cell is input, the second repair unit RU2 activates the redundant decoder in the column decoder 140. The activated redundant decoder may disable the decoder associated with the defective cell so that the defective cell is replaced by a redundant cell in the redundant memory cell array. In some embodiments, the redundant decoder may be implemented as a separate external device.

[0050] The I / O gating circuit 197 may include a circuit for gating I / O data, an input data mask logic, a data latch for storing data output from the memory cell array 210 , and a write driver for writing data into the memory cell array 210 .

[0051] The data I / O buffer 198 may provide data DQ to the I / O strobe circuit 197 based on the clock signal during a write operation. The data I / O buffer 198 may provide data DQ to the memory controller based on the clock signal during a read operation.

[0052] The anti-fuse sense amplifier 120 can detect the fuse information FI stored in the anti-fuse cell array 220 and output the fuse information FI. In the drawings, the fuse information FI looks like it is input only to the row decoder 130 and the column decoder 140; however, the fuse information can be provided to the components of the memory device 10 that need option signals for adjusting parameters (e.g., reference voltage, reference current, etc.).

[0053] In some embodiments, the anti-fuse sense amplifier 120 may include a plurality of anti-fuse sense amplifiers and a majority voting circuit; however, it is not limited thereto. Any one of the plurality of anti-fuse sense amplifiers may be Figure 3 The 0th anti-fuse sense amplifier 121_0a in FIG. A plurality of anti-fuse sense amplifiers may be included in Figure 6 In the anti-fuse sense amplifier 120 in.

[0054] When describing Figure 2 and Figure 3 When the anti-fuse cell array 220 and the anti-fuse sense amplifier 120 are described in detail below.

[0055] Figure 2 is a view for explaining an example of an antifuse cell array. Figure 3 is a circuit diagram showing an example of an anti-fuse unit.

[0056] refer to Figures 1 to 3 , the anti-fuse cell array 220a may include a plurality of anti-fuse cells Fuse_00a to Fuse_nma arranged in (n+1) rows and (m+1) columns, a plurality of anti-fuse word lines aWL, and a plurality of anti-fuse bit lines aBL.

[0057] The plurality of anti-fuse units Fuse_00a to Fuse_nma may be arranged in a matrix form with respect to the plurality of anti-fuse word lines aWL and the plurality of anti-fuse bit lines aBL. The plurality of anti-fuse word lines aWL may include a plurality of programming word lines WLP <0> To WLP <n>and multiple read word lines WLR <0> To WLR <n>In some embodiments, a plurality of programming word lines WLP <0> To WLP <n>and multiple read word lines WLR <0> To WLR <n>For example, multiple programming word lines WLP <0> To WLP <n>and multiple read word lines WLR <0> To WLR <n>It can be arranged in the order of one programming word line, one reading word line, one programming word line, one reading word line, and so on.

[0058] In some embodiments, among the plurality of antifuse word lines aWL, a pair of a program word line and a read word line adjacent to each other and activated together may be a row, and among the plurality of antifuse bit lines aBL, one antifuse bit line may correspond to a column.

[0059] Among the plurality of anti-fuse cells Fuse_00a to Fuse_nma, the anti-fuse cells arranged in the same column may share one of the plurality of anti-fuse bit lines aBL with each other.

[0060] Hereinafter, since the plurality of anti-fuse cells Fuse_00a to Fuse_nma have the same configuration, a specific description of the plurality of anti-fuse cells Fuse_00a to Fuse_nma may be replaced by a description of the (0,0)th anti-fuse cell Fuse_00a.

[0061] The (0,0)th anti-fuse cell Fuse_00a may store 1-bit data of 0 or 1. In other words, in the present disclosure, one anti-fuse cell may store 1-bit fuse data FD. Figure 1 The fuse information FI in may include fuse data FD stored in a plurality of anti-fuse units Fuse_00a to Fuse_nma. In the present disclosure, the fuse data FD may be stored in an OTP (one-time programmable) element in an electric fuse or anti-fuse manner. In addition, the fuse data FD may be OTP data programmable once.

[0062] The (0,0)th anti-fuse unit Fuse_00a can be connected to the 0th anti-fuse bit line aBL <0> The 0th anti-fuse sense amplifier 121_0a is coupled to the 0th anti-fuse sense amplifier 121_0a. The 0th anti-fuse sense amplifier 121_0a can be connected to the 0th anti-fuse bit line aBL through the 0th anti-fuse bit line aBL. <0> The 0th anti-fuse sense amplifier 121_0a receives an electrical signal from the (0,0)th anti-fuse cell Fuse_00a. The 0th anti-fuse sense amplifier 121_0a may generate a voltage based on the received electrical signal and compare the generated voltage with a reference voltage Vref, thereby detecting and outputting fuse data FD.

[0063] The (0,0)th anti-fuse unit Fuse_00a includes a read transistor RTr and a program transistor PTr. The gate terminal of the read transistor RTr may be coupled to the 0th read word line WLR. <0> , and the gate terminal of the programming transistor PTr can be coupled to the 0th programming word line WLP <0> The read transistor RTr can be connected to the 0th read word line WLR <0> operation, and the programming transistor PTr can be operated by the 0th programming word line WLP <0> operate.

[0064] The other terminal of the read transistor RTr may be coupled to the 0th anti-fuse bit line aBL <0> , and the other terminal of the read transistor RTr can be coupled to the other terminal of the programming transistor PTr. For example, the source terminal of the read transistor RTr can be coupled to the 0th anti-fuse bit line aBL <0> , and the drain terminal of the read transistor RTr can be coupled to the source terminal of the programming transistor PTr.

[0065] The other terminal of the programming transistor PTr may be coupled to the reading transistor RTr so that the programming transistor PTr is electrically coupled to the 0th anti-fuse bit line aBL through the reading transistor RTr. <0> The other terminal of the programming transistor PTr may be floating. For example, the source terminal of the programming transistor PTr may be coupled to the 0th anti-fuse bit line aBL. <0> , and the drain terminal of the programming transistor PTr may be floated. Since the drain terminal of the programming transistor PTr is floated, the programming transistor PTr may be used as a two-terminal element having a gate terminal and a source terminal. In other words, in the present disclosure, the read transistor RTr and the programming transistor PTr may be coupled in series.

[0066] When a programming or rupture operation is performed on the programming transistor PTr, the 0th programming word line WLP <0> A breakdown voltage is applied to the programming transistor PTr. The breakdown voltage may be in the range of about 5 V to about 8 V. As an example, the breakdown voltage may be in the range of about 5.5 V to about 6 V. For example, the breakdown voltage may be 5.5 V at the beginning of a programming operation on the programming transistor PTr, but may gradually rise to a voltage level of 6 V or higher over time.

[0067] The programming transistor PTr is a device that is turned on before rupture so that current does not flow between the two terminals, and in which the source terminal (or both the source terminal and the drain terminal) is short-circuited with the gate terminal after rupture so that current can flow. In other words, the programming transistor PTr can be a device that has a resistance value close to infinity before rupture and has a predetermined resistance value after rupture.

[0068] Before the rupture operation, when the read voltage is applied to the 0th programming word line WLP <0> When a read operation is performed on the programming transistor PTr, a current may not flow between the gate terminal and the source terminal of the programming transistor PTr, or a cut-off current at a leakage current level may flow. After the rupture operation, the read transistor RTr and the programming transistor PTr may be coupled in series to the 0th anti-fuse bit line aBL. <0> WLP <0> After the rupture operation, when the 0th programming word line WLP <0> When performing a read operation on the programming transistor PTr, a programming current of a predetermined magnitude may flow between the gate terminal and the source terminal of the programming transistor PTr. In some embodiments, the read voltage may be in a range of about 2V to about 4V, which is lower than the breakdown voltage. As an example, the read voltage may be about 3V.

[0069] According to whether a programming current of a predetermined magnitude flows in the programming transistor PTr, it can be determined whether the programming transistor PTr has been programmed (ruptured). Using this, fuse data FD of 0 or 1 can be stored or programmed in the programming transistor PTr. Since the programming transistor PTr cannot be restored to the state before rupture, it can be an OTP element that can only be programmed once.

[0070] The read transistor RTr can be connected to the 0th read word line WLR <0> operation, and when the read transistor RTr is turned on, the 0th programming word line WLP <0> and the 0th anti-fuse bit line aBL <0> During a read operation, the programming transistor PTr may operate as a resistor, thereby providing a current signal corresponding to the programming current to the 0th anti-fuse sense amplifier 121_0a.

[0071] Below, in Figure 7 and Figure 8 When describing, the structures of the read transistor RTr and the programming transistor PTr are described.

[0072] In the following, reference will be made to Figures 4 to 6 The arrangement of constituent elements in a memory device is described.

[0073] Figure 4 is an example stereogram of a memory device, Figure 5 is a plan view of an example of a memory cell region, Figure 6 is a plan view of an example of a peripheral circuit region.

[0074] refer to Figures 4 to 6 , the memory device 10 may include a peripheral circuit region PS and a memory cell region CS. The memory device 10 may have a COP (chip-peripheral) structure, and the peripheral circuit region PS and the memory cell region CS may be three-dimensionally stacked in a third direction D3.

[0075] At least a portion of the peripheral circuit region PS may overlap the memory cell region CS on a plane along the third direction D3. In some embodiments, the peripheral circuit region PS may include some of the external pads or wiring members disposed on the memory cell region CS.

[0076] The memory cell region CS may include a memory cell array 210 and an anti-fuse cell array 220. The memory cell array 210 and the anti-fuse cell array 220 may be disposed so as not to overlap each other on a plane along a third direction D3. In some embodiments, the memory cell array 210 and the anti-fuse cell array 220 may be disposed in the same plane.

[0077] The memory cell array 210 may include a plurality of sub-memory cell arrays 210_1 to 210_4. The plurality of sub-memory cell arrays 210_1 to 210_4 may be arranged to be spaced apart from each other in the first direction D1 and the second direction D2. The plurality of sub-memory cell arrays 210_1 to 210_4 are arranged not to overlap each other on a plane along the third direction D3. In some embodiments, the middle region 210D may be located between the plurality of sub-memory cell arrays 210_1 to 210_4, so that the plurality of sub-memory cell arrays 210_1 to 210_4 are spaced apart from each other around the middle region 210D.

[0078] The anti-fuse cell array 220 may be Figure 2 The anti-fuse cell array 220 in the embodiment of the present invention. The anti-fuse cell array 220 may include a plurality of sub-anti-fuse cell arrays 220_1 to 220_4. The plurality of sub-anti-fuse cell arrays 220_1 to 220_4 may be disposed in a middle region 210D, which is a region between the plurality of sub-memory cell arrays 210_1 to 210_4. In some embodiments, the plurality of sub-anti-fuse cell arrays 220_1 to 220_4 may be disposed to be aligned in a first direction D1 and a second direction D2. The plurality of sub-anti-fuse cell arrays 220_1 to 220_4 are disposed not to overlap each other on a plane along a third direction D3.

[0079] In the drawings, it is shown that each of the number of sub-memory cell arrays 210_1 to 210_4 and the number of sub-anti-fuse cell arrays 220_1 to 220_4 is four; however, this is merely an example, and the technical concept of the present disclosure is not limited to the number of sub-memory cell arrays and sub-anti-fuse cell arrays.

[0080] The peripheral circuit region PS may include a sub word line driver region SWDA, a row decoder region 130A, a sense amplifier region SAA, and an anti-fuse peripheral circuit region AFA.

[0081] In the sub word line driver area SWDA, a plurality of sub word line drivers 131 may be provided. The plurality of sub word line drivers 131 may be included in Figure 1 The word line driver in the row decoder 130 in.

[0082] The sub word line driver 131 may be coupled to word lines provided in the plurality of sub memory cell arrays 210_1 to 210_4 and may activate the coupled word lines to drive the plurality of sub memory cell arrays 210_1 to 210_4. Figure 6 , a plurality of sub-word line drivers 131 are shown to be arranged in a line along the second direction D2; however, Figure 6 The arrangement of the plurality of sub-word line drivers 131 in is merely an example, and the technical concept of the present disclosure is not limited to the above-mentioned arrangement example.

[0083] In the row decoder area 130A, it is possible to set Figure 1 The circuits in the row decoder region 130A may be electrically coupled to the multiple sub word line drivers 131 or the word lines in the multiple sub memory cell arrays 210_1 to 210_4.

[0084] The sense amplifier area SAA may include a plurality of bit line sense amplifiers 111. The plurality of bit line sense amplifiers 111 may be coupled to bit lines and complementary bit lines coupled to the plurality of sub memory cell arrays 210_1 to 210_4 so as to be able to detect and amplify data input to or output from the plurality of sub memory cell arrays 210_1 to 210_4 through the bit lines and complementary bit lines coupled thereto. Figure 6 , a plurality of bit line sense amplifiers 111 are shown to be arranged in a row along the second direction D2; however, Figure 6 The arrangement of the plurality of bit line sense amplifiers 111 in FIG. 1 is merely an example, and the technical concept of the present disclosure is not limited to the above-described arrangement example.

[0085] Although not shown in the drawings, in the sense amplifier area SAA, in addition to the plurality of bit line sense amplifiers 111 , a data sense amplifier, a write driver circuit, and the like may be provided.

[0086] In the anti-fuse peripheral circuit area AFA, an anti-fuse sense amplifier 120 may be provided. The anti-fuse sense amplifier 120 may be Figure 1 The anti-fuse sense amplifier 120 in the anti-fuse circuit area AFA may include a plurality of anti-fuse sense amplifiers coupled to the anti-fuse bit lines. In some embodiments, the anti-fuse sense amplifier 120 may include a majority voting circuit. Although not shown in the figure, an anti-fuse word line driver, a multiplexer for selecting an anti-fuse bit line, etc. may be provided in the anti-fuse peripheral circuit area AFA.

[0087] exist Figure 6 In the embodiment, the sub word line driver area SWDA, the row decoder area 130A, the sense amplifier area SAA, and the anti-fuse peripheral circuit area AFA extend along the second direction D2 and are spaced apart in the first direction D1. Figure 6 The arrangement of components in the peripheral circuit region PS in FIG. 1 is merely an example, and the above-mentioned arrangement example does not limit the technical concept of the present disclosure.

[0088] The anti-fuse cell array 220 of the present disclosure may not be disposed in the peripheral circuit region PS, and may be disposed in at least one of the intermediate regions 210D between the plurality of sub-memory cell arrays 210_1 to 210_4. By such an arrangement of the anti-fuse cell array 220, the area of ​​the peripheral circuit region PS may be reduced, and the chip size overhead of the entire memory device 10 may be reduced. In addition, in the COP structure, the intermediate region 210D between the plurality of sub-memory cell arrays 210_1 to 210_4 may have a sufficient area, and the anti-fuse cell array 220 may be disposed in the intermediate region 210D. By the above arrangement of the anti-fuse cell array 220, the operational performance of the anti-fuse cells in the anti-fuse cell array 220 may be improved.

[0089] Figure 7 is along Figure 5 Example cross-sectional views taken along lines AA and BB in FIG. Figure 8 is along Figure 4 Example cross-sectional view taken along line CC' in FIG.

[0090] refer to Figure 4 , Figure 5 , Figure 7 and Figure 8 , the memory cell array 210 may include a second substrate SUB2, a bit line BL, a memory vertical channel layer CH, a plurality of first gate electrodes 211, a first gate insulating layer 212, and a capacitor structure Cap. The anti-fuse cell array 220 may include a second substrate SUB2, an anti-fuse bit line aBL, a first vertical channel layer CHr and a second vertical channel layer CHp, a plurality of second gate electrodes 221, a second gate insulating layer 222, and a coupling conductor 227.

[0091] In some embodiments, the memory cell array 210 and the anti-fuse cell array 220 may include a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the memory vertical channel layer CH, the first vertical channel layer CHr, and the second vertical channel layer CHp extend along a third direction D3, which is a vertical direction from the second substrate SUB2. The third direction D3 is perpendicular to the first direction D1 in which the bit line BL extends and the second direction D2 in which the first gate electrode 211 extends.

[0092] On the second substrate SUB2, the bit line BL may extend in the first direction D1. Although not shown in the figure, in the memory cell array 210, a plurality of bit lines BL may be provided, and an insulating pattern may be provided in a region between the plurality of bit lines BL. The insulating pattern may extend in the first direction D1, and an upper surface of the insulating pattern may be provided at the same level as an upper surface of the bit line BL.

[0093] As an example, the bit line BL may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit line BL may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof; but not limited thereto. The bit line BL may include a single layer or multiple layers formed of the above materials. In some embodiments, the bit line BL may include a two-dimensional semiconductor material, and examples of the two-dimensional semiconductor material may include graphene, carbon nanotubes, and a combination thereof.

[0094] The memory vertical channel layers CH may be arranged to be spaced apart from each other along the first direction D1 on the bit lines BL. Although not shown in the figure, the memory vertical channel layers may be arranged in a matrix form on a plurality of bit lines, wherein they are spaced apart from each other in the first direction D1 and the second direction D2. The bottom portion of the memory vertical channel layer CH may be used as a first source / drain region, and the upper portion of the memory vertical channel layer CH may be used as a second source / drain region, and a portion of the memory vertical channel layer CH between the first source / drain region and the second source / drain region may be used as a channel region.

[0095] As an example, the memory vertical channel layer CH may include silicon, an oxide semiconductor, or a combination thereof, and for example, the oxide semiconductor may include In x Ga y Zn z O(IGZO), In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga y O or a combination thereof. The memory vertical channel layer CH may include a single layer or multiple layers formed of the above-mentioned oxide semiconductor. In some embodiments, the memory vertical channel layer CH may have a band gap energy greater than the band gap energy of silicon. For example, the memory vertical channel layer CH may have a band gap energy in the range of about 1.5eV to 5.6eV. For example, when having a band gap energy in the range of about 2.0eV to 4.0eV, the memory vertical channel layer CH may have optimal channel performance. For example, the memory vertical channel layer CH may be polycrystalline or amorphous, but is not limited thereto. In an embodiment, the memory vertical channel layer CH may include a two-dimensional semiconductor material, and examples of two-dimensional semiconductor materials may include graphene, carbon nanotubes, and combinations thereof.

[0096] The first gate electrode 211 may extend along the second direction D2 on both sidewalls of each memory vertical channel layer CH. The first gate electrode 211 may include a first sub-gate electrode 211g facing a first sidewall of the memory vertical channel layer CH and a first back-gate electrode 211bg facing a second sidewall of the memory vertical channel layer CH opposite to the first sidewall. Each first sub-gate electrode 211g may be used as Figure 1 The first back gate electrode 211bg may be one word line among the plurality of word lines WL in the memory, and the first back gate electrode 211bg may perform a function of forming a bottom potential of a vertical channel transistor including the memory vertical channel layer CH.

[0097] The first gate electrode 211 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the first gate electrode 211 may be formed of doped silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof; but is not limited thereto.

[0098] The first gate insulating layer 212 may be disposed to surround the first gate electrode 211, and at least some portions of the first gate insulating layer 212 may be interposed between the first gate electrode 211 and the memory vertical channel layer CH. Figure 7 In the embodiment, the first gate insulating layer 212 is disposed to surround the first gate electrode 211 ; however, in some embodiments, the first gate electrode 211 may be disposed along at least some portions of the sidewalls of the first gate insulating layer 212 .

[0099] In some embodiments, the first gate insulating layer 212 may be composed of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a dielectric constant greater than that of the silicon oxide film, or a combination thereof. The high dielectric film may be formed of a metal oxide or a metal oxynitride. For example, the high dielectric film that may be used as the first gate insulating layer 212 may be formed of HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 or a combination thereof, but not limited thereto.

[0100] In a region between the first gate electrode 211 on the bit line BL and the memory vertical channel layer CH, a first interlayer insulating layer 213 may be disposed. Figure 7 In FIG. 1 , the first interlayer insulating layer 213 is shown as one continuous material layer; however, in some embodiments, the first interlayer insulating layer 213 may be formed in the form of a plurality of insulating patterns.

[0101] On the memory vertical channel layer CH, a capacitor contact 215 may be provided. The capacitor contact 215 may be provided to vertically overlap the memory vertical channel layer CH in the third direction D3. The capacitor contact 215 may be formed of doped silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto. The first upper insulating layer 214 may surround the sidewall of the capacitor contact 215 on the first interlayer insulating layer 213.

[0102] On the first upper insulating layer 214 , a first etch stop layer 216 may be disposed, and on the first etch stop layer 216 , a capacitor structure Cap may be disposed. The capacitor structure Cap may include a lower electrode 217 , a capacitor dielectric layer 218 , and an upper electrode 219 .

[0103] The lower electrode 217 may pass through the first etch stop layer 216 and be electrically coupled to the upper surface of the capacitor contact 215. The lower electrode 217 may be formed in the form of a column extending in the third direction D3, but is not limited thereto. In some embodiments, the lower electrode 217 may be disposed so as not to overlap with the capacitor contact 215 on a plane along the third direction D3. Alternatively, a landing pad may be further disposed between the capacitor contact 215 and the lower electrode 217, and the lower electrode 217 may be arranged in a hexagonal shape.

[0104] The first gate electrode 211, the memory vertical channel layer CH, and the capacitor structure Cap may function as one memory cell MC, and may correspond to Figure 1 One of the multiple memory cells MC.

[0105] The second substrate SUB2, the anti-fuse bit line aBL, the first vertical channel layer CHr and the second vertical channel layer CHp, the plurality of second gate electrodes 221 and the second gate insulating layer 222 in the anti-fuse cell array 220 may respectively correspond to the second substrate SUB2, the bit line BL, the memory vertical channel layer CH, the plurality of first gate electrodes 211 and the first gate insulating layer 212 in the memory cell array 210.

[0106] Hereinafter, for convenience of explanation, components in the antifuse cell array 220 will be described focusing on differences from components in the memory cell array 210 corresponding to components in the antifuse cell array 220, and common matters will not be described.

[0107] The upper portion of the first vertical channel layer CHr may be used as Figure 3 The drain terminal of the read transistor RTr in the first vertical channel layer CHr can be used as Figure 3 The source terminal of the read transistor RTr in.

[0108] The lower surface of the second vertical channel layer CHp may be spaced apart from the upper surface of the antifuse bit line aBL by a floating distance d and the second vertical channel layer CHp may extend in the third direction D3. The second interlayer insulating layer 223 may be disposed in a region between the lower surface of the second vertical channel layer CHp and the upper surface of the antifuse bit line aBL.

[0109] In some embodiments, an upper surface of the first vertical channel layer CHr and an upper surface of the second vertical channel layer CHp may be disposed on a level having an upper surface of the memory vertical channel layer CH.

[0110] The bottom of the second vertical channel layer CHp may correspond to the source / drain region, but due to the arrangement between the anti-fuse bit line aBL and the second vertical channel layer CHp, the bottom of the second vertical channel layer CHp may be in a floating state. The upper portion of the second vertical channel layer CHp may be used as Figure 3 The source terminal of the programming transistor PTr in the second vertical channel layer CHp can be used as Figure 3 The drain terminal of the programming transistor PTr in.

[0111] The second gate electrode 221 may include a read gate electrode 221gr facing a first sidewall of the first vertical channel layer CHr, a second back gate electrode 221bg facing a second sidewall of the first vertical channel layer CHr opposite to the first sidewall, and a programming gate electrode 221gp, each of which faces one sidewall of the second vertical channel layer CHp. The programming gate electrode 221gp may be disposed on a side of the second vertical channel layer CHp opposite to the second back gate electrode 221bg. The read gate electrode 221gr may be used as a gate electrode coupled to the read transistor RTr. Figure 3 The 0th read word line WLR <0> , and the programming gate electrode 221gp can be used as a coupling to the programming transistor PTr Figure 3 WLP <0> The second back gate electrode 221bg may also play a function of forming a bottom potential of the vertical channel transistor including the first vertical channel layer CHr and the second vertical channel layer CHp.

[0112] The coupling contact 225 may be disposed on the first vertical channel layer CHr and the second vertical channel layer CHp. The coupling contact 225 may be disposed to overlap the memory vertical channel layer CH on a plane along the third direction D3. The second upper insulating layer 224 may surround the sidewall of the coupling contact 225 on the second interlayer insulating layer 223.

[0113] On the second upper insulating layer 224, a second etch stop layer 226 may be disposed, and coupling conductors 227 may be disposed on a horizontal plane having the second etch stop layer 226. Each coupling conductor 227 may contact two coupling contacts 225, thereby electrically coupling the upper portions of the first vertical channel layer CHr and the second vertical channel layer CHp.

[0114] As an example, the coupling conductor 227 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0115] A covering pattern 228 may be disposed on the coupling conductor 227 and the second upper insulating layer 224 so as to cover the antifuse cell array 220. Figure 7 , the insulating pattern, the upper insulating layer, the lower insulating layer, and the interlayer insulating layer are illustrated as being separated from each other; however, in some embodiments, the insulating pattern, the upper insulating layer, the lower insulating layer, and the interlayer insulating layer may be formed as one insulating layer.

[0116] The second gate electrode 221, the first vertical channel layer CHr, the second vertical channel layer CHp, and the coupling conductor 227 may function as an anti-fuse unit (Fuse), and may correspond to Figure 3 The (0,0) anti-fuse unit Fuse_00a in.

[0117] refer to Figure 8 , the memory device 10a may be a C2C (chip-to-chip) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a memory cell region CS on a first wafer, manufacturing a lower chip including a peripheral circuit region PS on a second wafer different from the first wafer, and coupling the upper chip and the lower chip together by a bonding method. For example, the bonding method may refer to a method of electrically coupling a bonding metal formed in the uppermost metal layer of the upper chip and a bonding metal formed in the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the above bonding method may be a Cu-Cu bonding method, and the bonding metal may be formed of aluminum or tungsten.

[0118] In the memory device 10 a , each of the peripheral circuit region PS and the memory cell region CS may include an external pad bonding region PA, an anti-fuse bonding region AFBA, and a memory cell bonding region MCBA.

[0119] The peripheral circuit region PS may include a first substrate SUB1, a first interlayer insulating layer 102, a plurality of circuit elements 150a, 150b, and 150c formed on the first substrate SUB1, first metal layers 160a, 160b, and 160c respectively coupled to the plurality of circuit elements 150a, 150b, and 150c, and second metal layers 170a, 170b, and 170c formed on the first metal layers 160a, 160b, and 160c. In some implementations, the first metal layers 160a, 160b, and 160c may be formed of tungsten having a relatively high resistance, and the second metal layers 170a, 170b, and 170c may be formed of copper having a relatively low resistance.

[0120] In the present specification, only the first metal layers 160a, 160b, and 160c and the second metal layers 170a, 170b, and 170c are shown in the drawings; however, the present disclosure is not limited thereto, and at least one metal layer may be further formed on the second metal layers 170a, 170b, and 170c. At least some of the one or more metal layers formed on the second metal layers 170a, 170b, and 170c may be formed of a material having a lower resistance than that of copper forming the second metal layers 170a, 170b, and 170c, such as aluminum, etc.

[0121] The first interlayer insulating layer 102 may be disposed on the first substrate SUB1 to cover the plurality of circuit elements 150a, 150b, and 150c, the first metal layers 160a, 160b, and 160c, and the second metal layers 170a, 170b, and 170c, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0122] The memory cell region CS may provide at least one of a plurality of memory cells MC and an anti-fuse cell (Fuse). The memory cell region CS may include a second substrate SUB2, a bit line BL, an anti-fuse bit line aBL, first metal layers 260b and 260c coupled to the anti-fuse bit line aBL and the bit line BL, respectively, and second metal layers 270b and 270c formed on the first metal layers 260b and 260c. In some implementations, the first metal layers 260b and 260c may be formed of tungsten having a relatively high resistance, and the second metal layers 270b and 270c may be formed of copper having a relatively low resistance. The bit line BL and the anti-fuse bit line aBL may be arranged to extend in parallel with the lower surface of the second substrate SUB2 in the first direction D1.

[0123] exist Figure 8 In the illustrated embodiment, a region in which a plurality of memory cells MC, a bit line BL, and the like are disposed may be defined as a memory cell bonding area MCBA.

[0124] In the memory cell bonding area MCBA, a plurality of memory cells MC may extend in a direction perpendicular to the upper surface of the second substrate SUB2. The plurality of memory cells MC may be electrically coupled to the first metal layer 260c and the second metal layer 270c. For example, the first metal layer 260c may be a bit line contact.

[0125] On the second metal layer 170c in the memory cell bonding area MCBA, lower bonding metals 181c and 182c may be formed. In the memory cell bonding area MCBA, the lower bonding metals 181c and 182c in the peripheral circuit area PS may be electrically coupled to the upper bonding metals 281c and 282c in the memory cell area CS by a bonding method, and the lower bonding metals 181c and 182c and the upper bonding metals 281c and 282c may be formed of aluminum, copper, tungsten, or the like.

[0126] The bit line BL may be electrically coupled to a circuit element 150c that provides a sense amplifier 110 in a peripheral circuit region PS in a memory cell bonding region MCBA. For example, the bit line BL may be coupled to upper bonding metals 281c and 282c in a memory cell region CS, and the upper bonding metals 281c and 282c may be coupled to lower bonding metals 181c and 182c that are coupled to the circuit element 150c of the sense amplifier 110. At least some components of the sense amplifier 110 may overlap with a plurality of memory cells MC and the bit line BL on a plane along a third direction D3.

[0127] In the anti-fuse bonding area AFBA, the anti-fuse bit line aBL may extend in parallel with the lower surface of the second substrate SUB2 along the first direction D1. The anti-fuse bit line aBL may be electrically coupled to the first metal layer 260b and the second metal layer 270b. For example, the first metal layer 260b may be an anti-fuse bit line contact. In the anti-fuse bonding area AFBA, the first metal layer 260b and the second metal layer 270b may be coupled to the peripheral circuit region PS through the upper bonding metals 281b and 282b of the memory cell region CS and the lower bonding metals 181b and 182b of the peripheral circuit region PS.

[0128] On the second metal layer 170b of the anti-fuse bonding area AFBA, lower bonding metals 181b and 182b may be formed. In the anti-fuse bonding area AFBA, the lower bonding metals 181b and 182b of the peripheral circuit area PS may be electrically coupled to the upper bonding metals 281b and 282b of the memory cell area CS by a bonding method, and the lower bonding metals 181b and 182b and the upper bonding metals 281b and 282b may be formed of aluminum, copper, tungsten, or the like.

[0129] The anti-fuse bit line aBL may be electrically coupled to a circuit element 150b that provides an anti-fuse sense amplifier 120 in the peripheral circuit region PS. In some embodiments, the anti-fuse sense amplifier 120 may be connected in a plane to an anti-fuse cell array ( ) including an anti-fuse cell (Fuse) along a third direction D3. Figure 2 overlaps with at least a portion of the reference numeral "220" in the figure.

[0130] Meanwhile, the external pad landing region PA may include a first external pad 107 disposed on the peripheral circuit region PS and a second external pad 104 disposed on the memory cell region CS. Figure 8 , on the lower surface of the first substrate SUB1, a lower insulating layer 103 may be formed so as to cover the lower surface of the first substrate SUB1, and on the lower insulating layer 103, first external pads 107 may be formed. Each of the first external pads 107 may be coupled to at least one of the plurality of circuit elements 150a, 150b, and 150c provided in the peripheral circuit region PS through the first external contact plug 108, and may be separated from the first substrate SUB1 by the lower insulating layer 103. Although not shown in the drawings, a side surface insulating layer may be provided between the first external contact plug 108 and the first substrate SUB1 so as to electrically separate the first external contact plug 108 from the first substrate SUB1.

[0131] On the upper surface of the second substrate SUB2, an upper insulating layer 203 may be formed to cover the upper surface of the second substrate SUB2, and on the upper insulating layer 203, second external pads 104 may be formed. Each second external pad 104 may be electrically coupled to at least one of a plurality of circuit elements 150a, 150b, and 150c provided in the peripheral circuit region PS through a second external contact plug 105 extending in a third direction D3 and passing through the second interlayer insulating layer 202 of the memory cell region CS. The second external pads 104 may be separated from the second substrate SUB2 by the upper insulating layer 203. The second external contact plugs 105 may be coupled to the upper bonding metals 281a and 282a through bonding, and the upper bonding metals 281a and 282a may be coupled to the lower bonding metals 181a and 182a, and the lower bonding metals 181a and 182a are coupled to the circuit element 150a of the peripheral circuit region PS. The lower bonding metals 181 a and 182 a and the upper bonding metals 281 a and 282 a may be formed of aluminum, copper, tungsten, or the like.

[0132] In addition, in the anti-fuse bonding area AFBA, an upper metal pattern 283b may be formed in the uppermost metal layer of the memory cell region CS in the same form as the lower metal pattern 183b formed in the uppermost metal layer of the peripheral circuit region PS so as to correspond to the lower metal pattern 183b. No contact may be formed on the upper metal pattern 283b formed in the uppermost metal layer of the memory cell region CS.

[0133] Similarly, in the memory cell bonding area MCBA, an upper metal pattern 283c may be formed in the uppermost metal layer of the memory cell area CS in the same form as the lower metal pattern 183c formed in the uppermost metal layer of the peripheral circuit area PS so as to correspond to the lower metal pattern 183c. No contact may be formed on the upper metal pattern 283c formed in the uppermost metal layer of the memory cell area CS.

[0134] Fig. 9 is a circuit diagram showing another example of an anti-fuse unit. Fig. 9 The (0,0) anti-fuse unit Fuse_00b in may correspond to Figure 3 For ease of explanation, we will focus on the (0,0) antifuse unit Fuse_00a. Fig. 9 The (0,0) anti-fuse unit Fuse_00b in Figure 3 The following description is made based on the difference between the (0,0)th anti-fuse unit Fuse_00a in FIG.

[0135] Reference together Figure 3 and Fig. 9 , the (0,0)th anti-fuse unit Fuse_00b may include a programming transistor PTr, and the programming transistor PTr includes a first programming transistor PTr1 to an xth programming transistor PTrx. Each of the first programming transistor PTr1 to the xth programming transistor PTrx may correspond to Figure 3 The first programming transistor PTr1 to the xth programming transistor PTrx can be connected to the 0th programming word line WLP. <0> operate.

[0136] One terminal of each of the first to xth programming transistors PTr1 to PTrx may be coupled to the read transistor RTr. The first to xth programming transistors PTr1 to PTrx may be electrically coupled to the anti-fuse bit line aBL through the read transistor RTr. <0> The other terminal of each of the first to xth programming transistors PTr1 to PTrx may be floated so that the first to xth programming transistors PTr1 to PTrx are coupled to each other in parallel at the 0th programming word line WLP. <0> Between the read transistor RTr.

[0137] The (0,0) anti-fuse unit Fuse_00b can be set in the COP structure Figure 5 In the middle area 210D in the middle area 210D, the area occupied by one anti-fuse unit in the present disclosure is larger. Therefore, the (0,0)th anti-fuse unit Fuse_00b may include at least two programming transistors PTr1 to PTrx, and at least three transistors PTr1 to PTrx and RTr to improve the performance of the read operation of the anti-fuse unit.

[0138] Fig.10 and Fig.11 is an exemplary diagram for explaining the operation of a memory device.

[0139] refer to Figures 9 to 11 , by the 0th programming word line WLP <0> After performing a programming or interrupt operation on the (0,0)th anti-fuse unit Fuse_00b, the 0th programming word line WLP <0> and read word line 0 WLR <0> A read operation is performed on the (0,0)th anti-fuse unit Fuse_00b.

[0140] When the 0th programming word line WLP <0> When a read voltage is applied, each of the first to xth programming transistors PTr1 to PTrx may output a programming current Ion to the read transistor RTr.

[0141] The read transistor RTr may output a parallel programming current xIon to the 0th anti-fuse sense amplifier 121_0b based on the programming currents Ion output from the x programming transistors PTr1 to PTrx.

[0142] During a read operation, the 0th anti-fuse sense amplifier 121_0b may generate a parallel generation voltage Vx based on the parallel programming current xIon associated with the first to xth programming transistors PTr1 to PTrx. The 0th anti-fuse sense amplifier 121_0b may compare the parallel generation voltage Vx with a reference voltage Vref, and when the parallel generation voltage Vx is greater than the reference voltage Vref, determine that the (0,0)th anti-fuse cell Fuse_00b has been programmed. The 0th anti-fuse sense amplifier 121_0b may detect and output fuse data FD based on whether the anti-fuse cell has been programmed.

[0143] When the anti-fuse sense amplifier detects the fuse data FD based on the programming current Ion, the fuse data FD may be detected in the programming detection time Ts_1. The 0th anti-fuse sense amplifier 121_0b may detect the fuse data FD based on the parallel programming current xIon, thereby detecting the fuse data FD in the parallel detection time Ts_x.

[0144] The (0,0)th anti-fuse unit Fuse_00b of the present disclosure may be a parallel arrangement of the first to xth programming transistors PTr1 to PTrx to improve the speed of a read operation.

[0145] The 0th anti-fuse sense amplifier 121_0b cannot detect fuse data FD indicating that the (0,0)th anti-fuse cell Fuse_00b has been programmed based on the off-generation voltage Voff generated by the off-current Ioff.

[0146] Fig.12 is another exemplary diagram for explaining the operation of the memory device.

[0147] refer to Fig. 9 and Fig.12 , by the 0th programming word line WLP <0> After performing a programming or interrupt operation on the (0,0)th anti-fuse unit Fuse_00b, the 0th programming word line WLP <0> and read word line 0 WLR <0> A read operation is performed on the (0,0)th anti-fuse unit Fuse_00b.

[0148] Although the breakdown voltage is applied to the first to xth programming transistors PTr1 to PTrx, some of the first to xth programming transistors PTr1 to PTrx may not be broken due to operation errors. Some programming transistors that have not been broken may output an off current Ioff during a read operation.

[0149] In some implementations, some of the first through xth programming transistors PTr1 through PTrx may output a programming current Ion during a read operation, and others of the first through xth programming transistors PTr1 through PTrx may output an off current Ioff.

[0150] For example, refer to Fig.12 , through the 0th programming word line WLP <0> After applying the breakdown voltage to the first to x-th programming transistors PTr1 to PTrx, the first programming transistor PTr1 may not be ruptured, and the remaining portions of the first to x-th programming transistors PTr1 to PTrx except the first programming transistor PTr1 may be ruptured. Thereafter, during a read operation on the (0,0)th anti-fuse unit Fuse_00b, the first programming transistor PTr1 may output an off current Ioff, and the remaining programming transistors except the first programming transistor PTr1 may output a programming current Ion.

[0151] The read transistor RTr may provide some programming current Ion to the 0th anti-fuse sense amplifier 121_0b based on the programming current Ion of the remaining programming transistors except the first programming transistor PTr1.

[0152] The 0th anti-fuse sense amplifier 121_0b can generally detect and output the fuse data FD of the (0,0)th anti-fuse unit Fuse_00b based on the programming current Ion of the remaining programming transistors except the failed first programming transistor PTr1. The (0,0)th anti-fuse unit Fuse_00b of the present disclosure can be a parallel arrangement of the first programming transistor PTr1 to the xth programming transistor PTrx to improve the reliability of the read operation on the (0,0)th anti-fuse unit Fuse_00b.

[0153] Fig.13 is a circuit diagram showing another example of an anti-fuse unit. Fig.13 The (0,0) anti-fuse unit Fuse_00c in may correspond to Figure 2 For ease of explanation, the following description will focus on the (0,0) anti-fuse unit Fuse_00a. Fig.13 The (0,0) anti-fuse unit Fuse_00c in Figure 2 The difference between the (0,0) antifuse unit Fuse_00a in.

[0154] The (0,0)th anti-fuse unit Fuse_00c may include a read transistor RTr including first to xth read transistors RTr1 to RTrx and a programming transistor PTr including first to xth programming transistors PTr1 to PTrx.

[0155] Each of the first to xth read transistors RTr1 to RTrx may correspond to Figure 2 The first read transistor RTr1 to the xth read transistor RTrx can be connected to the 0th read word line WLR. <0> One terminal of each of the first to xth read transistors RTr1 to RTrx may be coupled to the 0th anti-fuse bit line aBL. <0> .

[0156] Each of the first to xth programming transistors PTr1 to PTrx may correspond to Figure 2 The first programming transistor PTr1 to the xth programming transistor PTrx can be connected to the 0th programming word line WLP. <0> One terminal of each of the first to xth programming transistors PTr1 to PTrx may be coupled to the other terminal of a corresponding one of the first to xth reading transistors RTr1 to RTrx.

[0157] Therefore, after performing a rupture operation on the first programming transistor PTr1, the first programming transistor PTr1 and the first reading transistor RTr1 may be coupled in series on the 0th anti-fuse bit line aBL. <0> and the 0th programming word line WLP <0> Similarly, after the rupture operation is performed on the second programming transistor PTr2, the second programming transistor PTr2 and the second reading transistor RTr2 may be coupled in series to the 0th anti-fuse bit line aBL. <0> and the 0th programming word line WLP <0> The series connection relationship between the remaining programming transistors and the remaining reading transistors after the rupture operation may correspond to Fig.13 The series connection relationship between the first programming transistor PTr1 and the first reading transistor RTr1 is shown.

[0158] After performing the rupture operation on the first to xth programming transistors PTr1 to PTrx, the first programming transistor PTr1 and the first reading transistor RTr1 may be connected to the 0th anti-fuse bit line aBL. <0> and the 0th programming word line WLP <0> Similarly, after the rupture operation is performed on the first to xth programming transistors PTr1 to PTrx, the first programming transistor PTr1 and the first reading transistor RTr1 may be connected to the 0th anti-fuse bit line aBL. <0> and the 0th programming word line WLP <0> After the rupture operation is performed on the first to xth programming transistors PTr1 to PTrx, the parallel connection relationship between the remaining programming transistors and the remaining reading transistors may correspond to the following: Fig.13 The parallel connection relationship between the first programming transistor PTr1 and the first reading transistor RTr1 and the second programming transistor PTr2 and the second reading transistor RTr2 is shown.

[0159] Fig.14 is another exemplary diagram for explaining the operation of the memory device.

[0160] refer to Fig.14 , through the 0th programming word line WLP <0> After performing a programming or interrupt operation on the (0,0)th anti-fuse unit FUSE_0C, the 0th programming word line WLP <0> and the 0th read word line WLR <0> A read operation is performed on the (0,0)th anti-fuse unit FUSE_0C.

[0161] When the 0th programming word line WLP <0> When a read voltage is applied, the first to xth programming transistors PTr1 to PTrx may output programming currents Ion to the first to xth read transistors RTr1 to RTrx, respectively.

[0162] The first to xth read transistors RTr1 to RTrx may output the programming current Ion output by the programming transistors PTr1 to PTrx to the 0th anti-fuse sense amplifier 121_0c. The 0th anti-fuse sense amplifier 121_0c may receive a parallel programming current xIon based on the programming current Ion output from the first to xth read transistors RTr1 to RTrx.

[0163] During a read operation, the 0th anti-fuse sense amplifier 121_0c may detect and output fuse data FD based on the parallel programming current xIon associated with the first to xth read transistors RTr1 to RTrx.

[0164] Fig.15 and Fig.16 is an exemplary diagram for explaining an anti-fuse cell array. Fig.15 and Fig.16 The (0,0)th anti-fuse unit Fuse_00d and the anti-fuse unit array 220d in may correspond to Figure 2 and Figure 3 For ease of explanation, the following description will focus on the difference between the (0,0)th antifuse cell Fuse_00d and the antifuse cell array 220d, and the difference between the (0,0)th antifuse cell Fuse_00a and the antifuse cell array 220a.

[0165] The antifuse cell array 220d may include a plurality of antifuse cells Fuse_00d to Fuse_nm-2d arranged in (n+1) rows and (m+1) / 3 columns. In some embodiments, m may be 3L-1, where l may be an integer equal to or greater than 2.

[0166] In the anti-fuse cell array 220d, among the plurality of anti-fuse bit lines aBL, three anti-fuse bit lines that are adjacent and activated together may function as one column. <0> To the second anti-fuse bit line aBL <2> It can be operated as a column in burst mode, so that the 0th antifuse bit line aBL <0> To the second anti-fuse bit line aBL <2> Coupled to the (0,0)th anti-fuse unit Fuse_00d.

[0167] Hereinafter, the plurality of antifuse cells Fuse_00d to Fuse_nm-2d will be described as having the same configuration, and a specific description of the plurality of antifuse cells Fuse_00d to Fuse_nm-2d may be replaced by a description of the (0,0)th antifuse cell Fuse_00d.

[0168] The (0,0)th anti-fuse unit Fuse_00d may include (0,0)th to (0,2)th read transistors RTr00 to RTr02 and (0,0)th to (0,2)th programming transistors PTr00 to PTr02.

[0169] Gate terminals of the (0,0)th to (0,2)th read transistors RTr00 to RTr02 may be coupled to a 0th read word line WLR. <0> , and the gate terminals of the (0,0)th programming transistor PTr00 to the (0,2)th programming transistor PTr02 may be coupled to the 0th programming word line WLP <0> The (0,0)th read transistor RTr00 to the (0,2)th read transistor RTr02 can be connected to the 0th read word line WLR. <0> operation, and the (0,0)th programming transistor PTr00 to the (0,2)th programming transistor PTr02 can be connected to the 0th programming word line WLP <0> operate.

[0170] One terminal of the (0,0)th read transistor RTr00 may be coupled to the 0th anti-fuse bit line aBL. <0> The other terminal of the (0,0)th read transistor RTr00 may be coupled to one terminal of the (0,0)th programming transistor PTr00, so that the (0,0)th programming transistor PTr00 is electrically coupled to the 0th anti-fuse bit line aBL through the (0,0)th read transistor RTr00. <0> The other terminal of the (0,0)th programming transistor PTr00 may be floated so that the (0,0)th programming transistor PTr00 may be used as a two-terminal element having a gate terminal and a source terminal. In other words, after the rupture operation is performed on the (0,0)th programming transistor PTr00, the (0,0)th read transistor RTr00 and the (0,0)th programming transistor PTr00 may be coupled in series on the 0th anti-fuse bit line aBL. <0> WLP <0> between.

[0171] One terminal of the (0,1)th read transistor RTr01 may be coupled to the first anti-fuse bit line aBL <1> The other terminal of the (0,1)th read transistor RTr01 may be coupled to one terminal of the (0,1)th programming transistor PTr01, so that the (0,1)th programming transistor PTr01 is electrically coupled to the first anti-fuse bit line aBL through the (0,1)th read transistor RTr01. <1> The other terminal of the (0,1)th programming transistor PTr01 may be floated, so that the (0,1)th programming transistor PTr01 may be used as a two-terminal element having a gate terminal and a source terminal. In other words, after the rupture operation is performed on the (0,1)th programming transistor PTr01, the (0,1)th read transistor RTr01 and the (0,1)th programming transistor PTr01 may be coupled in series on the first anti-fuse bit line aBL. <1> With the first programming word line WLP <1> between.

[0172] One terminal of the (0,2)th read transistor RTr02 may be coupled to the second anti-fuse bit line aBL <2> The other terminal of the (0,2)th read transistor RTr02 may be coupled to one terminal of the (0,2)th programming transistor PTr02, so that the (0,2)th programming transistor PTr02 is electrically coupled to the second anti-fuse bit line aBL through the (0,2)th read transistor RTr02. <2> The other terminal of the (0,2)th programming transistor PTr02 may be floated, so that the (0,2)th programming transistor PTr02 may be used as a two-terminal element having a gate terminal and a source terminal. In other words, after the rupture operation is performed on the (0,2)th programming transistor PTr02, the (0,2)th read transistor RTr02 and the (0,2)th programming transistor PTr02 may be coupled in series on the second anti-fuse bit line aBL. <2> With the second programming word line WLP <2> between.

[0173] The (0,0)th anti-fuse unit Fuse_00d can be connected to the 0th anti-fuse bit line aBL <0> The 0th anti-fuse sense amplifier 121_0d is coupled to the 0th anti-fuse sense amplifier 121_0d. The 0th anti-fuse sense amplifier 121_0d can be connected to the 0th anti-fuse bit line aBL through the 0th anti-fuse bit line aBL. <0> The 0th anti-fuse sense amplifier 121_0d may generate a voltage based on the received electrical signal and compare the generated voltage with the reference voltage Vref, thereby detecting and outputting the 0th output data OutD0. The 0th anti-fuse sense amplifier 121_0d may provide the 0th output data OutD0 to the majority voting circuit 122.

[0174] The (0,0)th anti-fuse unit Fuse_00d can be connected to the first anti-fuse bit line aBL. <1> The first anti-fuse sense amplifier 121_1d can be coupled to the first anti-fuse sense amplifier 121_1d through the first anti-fuse bit line aBL. <1> The first anti-fuse sense amplifier 121_1d receives an electrical signal from the (0,1)th read transistor RTr01 of the (0,0)th anti-fuse unit Fuse_00d. The first anti-fuse sense amplifier 121_1d may generate a voltage based on the received electrical signal and compare the generated voltage with the reference voltage Vref, thereby detecting and outputting the first output data OutD1. The first anti-fuse sense amplifier 121_1d may provide the first output data OutD1 to the majority voting circuit 122.

[0175] The (0,0)th anti-fuse unit Fuse_00d can be connected to the second anti-fuse bit line aBL. <2> The second anti-fuse sense amplifier 121_2d can be coupled to the second anti-fuse sense amplifier 121_2d through the second anti-fuse bit line aBL. <2> The second anti-fuse sense amplifier 121_2d receives an electrical signal from the (0, 2)th read transistor RTr02 of the (0, 0)th anti-fuse unit Fuse_00d. The second anti-fuse sense amplifier 121_2d may generate a voltage based on the received electrical signal and compare the generated voltage with the reference voltage Vref, thereby detecting and outputting the second output data OutD2. The second anti-fuse sense amplifier 121_2d may provide the second output data OutD2 to the majority voting circuit 122.

[0176] The majority voting circuit 122 may include Figure 1 The anti-fuse sense amplifier 120 in FIG. 1 can receive an odd number of output data consisting of at least three output data and output fuse data FD corresponding to the majority of the received output data. The output data can be 0 or 1. Fig.16 , it is shown that the majority voting circuit 122 receives three output data OutD0 to OutD2; however, Fig.16 The number of output data in is only an example, and the technical concept of the present disclosure is not limited thereto.

[0177] Fig.17 is another exemplary diagram for explaining the operation of the memory device.

[0178] refer to Fig.16 and Fig.17 , by the 0th programming word line WLP <0> After performing a programming or interrupt operation on the (0,0)th anti-fuse unit Fuse_00d, the 0th programming word line WLP <0> and read word line 0 WLR <0> A read operation is performed on the (0,0)th anti-fuse unit Fuse_00d.

[0179] Although the breakdown voltage is applied to the (0,0)th programming transistors PTr00 to (0,2)th programming transistors PTr02, some of the (0,0)th programming transistors PTr00 to (0,2)th programming transistors PTr02 may not be broken due to operation errors. Some programming transistors that have not been broken may output an off current Ioff during a read operation.

[0180] In some implementations, some of the (0,0)th to (0,2)th programming transistors PTr00 to PTr02 may output a programming current Ion during a read operation, and other programming transistors of the (0,0)th to (0,2)th programming transistors PTr02 may output an off current Ioff.

[0181] For example, refer to Fig.17 , through the 0th programming word line WLP <0> After applying the breakdown voltage to the (0,0)th programming transistor PTr00 to the (0,2)th programming transistor PTr02, the (0,0)th programming transistor PTr00 may not be ruptured, and the (0,1)th programming transistor PTr01 and the (0,2)th programming transistor PTr02 other than the (0,0)th programming transistor PTr00 may be ruptured. Thereafter, during a read operation on the (0,0)th anti-fuse unit Fuse_00d, the (0,0)th programming transistor PTr00 may output an off current Ioff, and the (0,1)th programming transistor PTr01 and the (0,2)th programming transistor PTr02 may output a programming current Ion.

[0182] The (0,0)th read transistor RTr00 may provide an off current Ioff to the 0th anti-fuse sense amplifier 121_0d. In some embodiments, the 0th anti-fuse sense amplifier 121_0d may output a value of 0 (a low level signal) to the majority voting circuit 122 based on the off current Ioff.

[0183] The (0,1)th read transistor RTr01 may provide the programming current Ion to the first anti-fuse sense amplifier 121_1d. In some embodiments, the first anti-fuse sense amplifier 121_1d may output a value of 1 (a high level signal) to the majority voting circuit 122 based on the programming current Ion.

[0184] The (0,2)th read transistor RTr02 can provide the programming current Ion to the second anti-fuse sense amplifier 121_2d. In some embodiments, the second anti-fuse sense amplifier 121_2d can output a value of 1 (a high level signal) to the majority voting circuit 122 based on the programming current Ion.

[0185] The majority voting circuit 122 may output a value of 1 as the fuse data FD based on the value 1 (high level signal) output from the first anti-fuse sense amplifier 121_1 d and the second anti-fuse sense amplifier 121_2 d .

[0186] The majority voting circuit 122 may normally output the fuse data FD of the (0,0)th anti-fuse cell Fuse_00d based on the programming current Ion outputted from the (0,1)th programming transistor PTr01 and the (0,2)th programming transistor PTr02 except for the failed (0,0)th programming transistor PTr00. In the present disclosure, the anti-fuse cell array 220d may be arranged at Figure 5 In the memory cell region CS in the embodiment, the majority voting circuit 122 may be arranged Figure 6 By means of the majority voting circuit 122, the reliability of the read operation on the (0,0)th anti-fuse unit Fuse_00d can be improved.

[0187] Fig.18 is a circuit diagram showing another example of an anti-fuse unit.

[0188] Fig.18 The (0,0) anti-fuse unit Fuse_00e in may correspond to Fig.16 For ease of explanation, the following description will focus on the difference between the (0,0)th anti-fuse unit Fuse_00e and the (0,0)th anti-fuse unit Fuse_00d.

[0189] Reference together Fig.16 and Fig.18 , compared to Fig.16 The (0,0)th anti-fuse unit Fuse_00d and the (0,0)th anti-fuse unit Fuse_00e may further include the (1,0)th programming transistor PTr10 to the (1,2)th programming transistor PTr12 and the (1,0)th reading transistor RTr10 to the (1,2)th reading transistor RTr12.

[0190] The (1,0)th read transistor RTr10 to the (1,2)th read transistor RTr12 may correspond to Fig.16 The (0,0)th read transistor RTr00 to the (0,2)th read transistor RTr02 in the 0th read word line WLR. The (1,0)th read transistor RTr10 to the (1,2)th read transistor RTr12 can be connected to the 0th read word line WLR. <0> One terminal of each of the (1,0)th read transistor RTr10 to the (1,2)th read transistor RTr12 may be coupled to the 0th to the second anti-fuse bit lines aBL. <0> To aBL <2> The corresponding anti-fuse bit line in .

[0191] The (1,0)th programming transistor PTr10 to the (1,2)th programming transistor PTr12 may correspond to Fig.16 The (0,0)th programming transistor PTr00 to the (0,2)th programming transistor PTr02 in the 0th programming word line WLP. The (1,0)th programming transistor PTr10 to the (1,2)th programming transistor PTr12 can be connected to the 0th programming word line WLP. <0> One terminal of each of the (1,0)th programming transistor PTr10 to the (1,2)th programming transistor PTr12 may be coupled to the other terminal of a corresponding one of the (1,0)th reading transistor RTr10 to the (1,2)th reading transistor RTr12.

[0192] Therefore, after the rupture operation is performed on the (0,0)th programming transistor PTr00 and the (1,0)th programming transistor PTr10, the (1,0)th programming transistor PTr10 and the (1,0)th reading transistor RTr10 can be connected to the 0th anti-fuse bit line aBL. <0> and the 0th programming word line WLP <0> The first anti-fuse bit line aBL is connected to the (0,0)th programming transistor PTr00 and the (0,0)th reading transistor RTr00 in parallel. Similarly, after the rupture operation is performed on the (0,1)th programming transistor PTr01 and the (1,1)th programming transistor PTr11, the (1,1)th programming transistor PTr11 and the (1,1)th reading transistor RTr11 can be connected to the first anti-fuse bit line aBL. <1> and the 0th programming word line WLP <0> The (0,1)th programming transistor PTr01 and the (0,1)th reading transistor RTr01 are coupled in parallel therebetween. After the rupture operation is performed on the (0,2)th programming transistor RTr02 and the (1,2)th programming transistor PTr12, the (1,2)th programming transistor PTr12 and the (1,2)th reading transistor RTr12 can be connected to the second anti-fuse bit line aBL. <2> and the 0th programming word line WLP <0> The transistors are coupled in parallel to the (0, 2)th programming transistor PTr02 and the (0, 2)th reading transistor RTr02.

[0193] Fig.19 is another exemplary diagram for explaining the operation of the memory device.

[0194] refer to Fig.18 and Fig.19 , by the 0th programming word line WLP <0> After performing a programming or interrupt operation on the (0,0)th anti-fuse unit Fuse_00e, the 0th programming word line WLP <0> and read word line 0 WLR <0> A read operation is performed on the (0,0)th anti-fuse unit Fuse_00e.

[0195] When the 0th programming word line WLP <0> When a read voltage is applied, the (0,0)th programming transistor PTr00 to the (0,2)th programming transistor PTr02 and the (1,0)th programming transistor PTr10 to the (1,2)th programming transistor PTr12 can output programming current Ion to the (0,0)th read transistor RTr00 to the (0,2)th read transistor RTr02 and the (1,0)th read transistor RTr10 to the (1,2)th read transistor RTr12, respectively.

[0196] The (0,0)th read transistor RTr00 and the (1,0)th read transistor RTr10 may provide the programming current Ion output from the (0,0)th programming transistor PTr00 and the (1,0)th programming transistor PTr10 to the 0th anti-fuse sense amplifier 121_0e. The 0th anti-fuse sense amplifier 121_0e may receive the parallel programming current Ion based on the programming current Ion output from the (0,0)th read transistor RTr00 and the (1,0)th read transistor RTr10. During a read operation, the 0th anti-fuse sense amplifier 121_0e may detect and output the 0th output data OutD0 based on the parallel programming current Ion associated with the (0,0)th read transistor RTr00 and the (1,0)th read transistor RTr10.

[0197] The (0, 1)th read transistor RTr01 and the (1, 1)th read transistor RTr11 may provide the programming current Ion output from the (0, 1)th programming transistor PTr01 and the (1, 1)th programming transistor PTr11 to the first anti-fuse sense amplifier 121_1e. The first anti-fuse sense amplifier 121_1e may receive the parallel programming current Ion based on the programming current Ion output from the (0, 1)th read transistor RTr01 and the (1, 1)th read transistor RTr11. The first anti-fuse sense amplifier 121_1e may detect and output the first output data OutD1 based on the parallel programming current Ion associated with the (0, 1)th read transistor RTr01 and the (1, 1)th read transistor RTr11 during a read operation.

[0198] The (0, 2)th read transistor RTr02 and the (1, 2)th read transistor RTr12 may provide the programming current Ion outputted from the (0, 2)th programming transistor PTr02 and the (1, 2)th programming transistor PTr12 to the second anti-fuse sense amplifier 121_2e. The second anti-fuse sense amplifier 121_2e may receive the parallel programming current Ion based on the programming current Ion outputted from the (0, 2)th read transistor RTr02 and the (1, 2)th read transistor RTr12. The second anti-fuse sense amplifier 121_2e may detect and output the second output data OutD2 based on the parallel programming current Ion associated with the (0, 2)th read transistor RTr02 and the (1, 2)th read transistor RTr12 during the read operation.

[0199] The 0th to 2nd anti-fuse sense amplifiers 121_0e to 121_2e can detect the 0th to 2nd output data OutD0 to OutD2 based on the parallel programming current Ion through the parallel arrangement of the programming transistor and the reading transistor. Through the above parallel arrangement, the speed of the read operation on the (0,0)th anti-fuse unit Fuse_00e can be increased.

[0200] Fig. 20 is an example diagram for explaining a memory device. Fig. 20 is along Figure 5 A cross-sectional view taken along line AA and line BB. Fig. 20 The memory device 10f and Figure 7 The memory devices 10a in the embodiment may correspond to each other. For ease of explanation, the following description will be made focusing on the difference between the memory device 10f and the memory device 10a.

[0201] The anti-fuse cell array 220 may include a second substrate SUB2 , a first gate electrode G1 , a second gate electrode G2 , a bit line contact BC, and an anti-fuse bit line aBL.

[0202] In some embodiments, the anti-fuse cell array 220 may include a metal oxide semiconductor (MOS) transistor. The read transistor RTr and the programming transistor PTr may be implemented as a metal oxide semiconductor (MOS) transistor. Each metal oxide semiconductor (MOS) transistor may include gate insulating layers GI1 and GI2 stacked on a second substrate SUB2 and gate electrodes G1 and G2, and source / drain regions SD1 to SD3 disposed adjacent to a channel layer on both sides of its gate.

[0203] The first gate electrode G1 and the second gate electrode G2 may extend in the second direction D2 on the second substrate SUB2 in parallel with the second substrate SUB2. The first gate electrode G1 and the second gate electrode G2 may be disposed to extend in the second direction D2 and be spaced apart from each other in the first direction D1.

[0204] The first gate electrode G1 and the second gate electrode G2 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the first gate electrode G1 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof; but is not limited thereto.

[0205] In a region of the second substrate SUB2 overlapping the first gate electrode G1 and the second gate electrode G2 on a plane along the third direction D3 , a channel layer may be formed.

[0206] Source / drain regions SD1 to SD3 may be formed on both sides of the channel layer and between the channel layers. The source / drain regions SD1 to SD3 are impurity-doped regions, and the first source / drain region SD1 and the second source / drain region SD2 may be formed on both sides of the first gate electrode G1, and the second source / drain region SD2 and the third source / drain region SD3 may be formed on both sides of the second gate electrode G2. Between the first gate electrode G1 and the second gate electrode G2, the second source / drain region SD2 may be formed as one source / drain region.

[0207] Some portions of the first gate insulating layer GI1 and the second gate insulating layer GI2 may be inserted between the first gate electrode G1 and the second substrate SUB2 and between the second gate electrode G2 and the second substrate SUB2. For example, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be composed of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a dielectric constant greater than that of the silicon oxide film, or a combination thereof. The high dielectric film may be formed of a metal oxide or a metal oxynitride. For example, the high dielectric film that may be used as the first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO2, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0208] An interlayer insulating layer ILD may be disposed on a region between the first gate electrode G1 and the second gate electrode G2 of the second substrate SUB2.

[0209] The anti-fuse bit line aBL may extend along the first direction D1 on the interlayer insulating layer ILD. Fig. 20 The anti-fuse bit line aBL shown is one of a plurality of anti-fuse bit lines aBL. Although not shown in the figure, in the memory device 10f, a plurality of anti-fuse bit lines aBL are arranged to be spaced apart from each other in the second direction D2. A covering pattern CP may be arranged on the anti-fuse bit line aBL and the interlayer insulating layer ILD so as to cover the anti-fuse cell array 220.

[0210] The bit line contact BC may extend in the third direction D3 while passing through the interlayer insulating layer ILD so as to make contact with the anti-fuse bit line aBL and the first source / drain region SD1 .

[0211] The first source / drain region SD1, the first gate electrode G1, and the second source / drain region SD2 may be used as Figure 3 The read transistor RTr in the second source / drain region SD2, the second gate electrode G2 and the third source / drain region SD3 may be used as Figure 3 The second source / drain region SD2 may be Figure 3 The connection node of the read transistor RTr and the programming transistor PTr in , and can be a shared area.

[0212] A wiring structure or the like in the anti-fuse cell array may be disposed so as to be spaced apart from the third source / drain region SD3 so that the third source / drain region SD3 is in a floating state.

[0213] Fig.21 is another exemplary diagram for explaining a memory device. Fig.21 is along Figure 4 For ease of explanation, we will focus on Fig.21 The memory device 10g in Figure 8 The following description will be made based on the differences between the memory devices 10a in FIG.

[0214] Also refer to Figure 8 and Fig.21 ,and Figure 8 Compared with the memory device 10a in FIG. 1 , in the memory device 10g, the lower bonding metals 181a to 181c and 182a to 182c and the lower metal patterns 183b and 183c in the peripheral circuit area PS and the upper bonding metals 281a to 281c and 282a to 282c and the upper metal patterns 283b and 283c in the memory cell area CS are not set.

[0215] Furthermore, between the second metal layers 170a, 170b, and 170c of the peripheral circuit region PS and the second metal layers 270b and 270c of the memory cell region CS, an anti-fuse bit line aBL, a bit line BL, and an anti-fuse unit (Fuse) may be disposed.

[0216] Therefore, the second metal layers 270 b and 270 c of the memory cell region CS may be disposed over the anti-fuse bit line aBL, the bit line BL, and the anti-fuse unit (Fuse) in the third direction D3 .

[0217] and Figure 8 Compared with the memory device 10a in FIG. 1 , the memory device 10g may include a horizontal semiconductor layer 201 disposed below the anti-fuse bit line aBL and the bit line BL, instead of a second substrate SUB2 disposed on the anti-fuse bit line aBL and the bit line BL.

[0218] The horizontal semiconductor layer 201 may include a lower supporting semiconductor layer and a common source plate on the lower supporting semiconductor layer. The horizontal semiconductor layer 201 may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaA), indium gallium arsenide (InGaA), aluminum gallium arsenide (AlGaA), or a mixture thereof. The horizontal semiconductor layer 201 may have a crystal structure including at least one selected from a single crystal, an amorphous, and a polycrystalline structure.

[0219] In some embodiments, the horizontal semiconductor layer 201 may have an opening OP. In some embodiments, the first interlayer insulating layer 102 and the second interlayer insulating layer 202 may contact each other through the opening OP. The second external contact plug 105 may extend through the opening OP and through some portions of the second interlayer insulating layer 202 and the first interlayer insulating layer 102 in the third direction D3, thereby being electrically coupled to the second metal layer 170c of the external pad bonding area PA. In some embodiments, the second external contact plug 105 may be electrically coupled to the circuit element 150a in the external pad bonding area PA.

[0220] In addition, an upper insulating layer 203 may be disposed over the second metal layers 260 b and 260 c so as to cover the second metal layers 260 b and 260 c and the second interlayer insulating layer 202 .

[0221] exist Fig.21 In the embodiment, the second metal layers 170a, 170b and 170c of the peripheral circuit region PS and the second metal layers 270b and 270c of the memory cell region CS are not coupled to each other; however, the second metal layers 170a, 170b and 170c of the peripheral circuit region PS can be electrically coupled to the second metal layers 270b and 270c of the memory cell region CS, respectively.

[0222] Therefore, although not shown in the figure, the circuit element 150b of the anti-fuse sense amplifier 120 can be electrically coupled to the multiple anti-fuse bit lines aBL through the first metal layer 160b and the second metal layer 170b of the peripheral circuit region PS and the first metal layer 260b and the second metal layer 270b of the memory cell region CS.

[0223] Similarly, the circuit element 150c of the sense amplifier 110 may be electrically coupled to the bit line BL through the first and second metal layers 160c and 170c of the peripheral circuit region PS and the first and second metal layers 260c and 270c of the memory cell region CS.

[0224] Fig. 22 is a block diagram illustrating an example of a computing device.

[0225] refer to Fig. 22 , the computing device 1000 includes a processor 1030, a memory 1010, a memory controller 1020, a storage device 1040, a communication interface 1050, and a bus 1060. Although not shown in the drawings, the computing device 1000 may also include other general components.

[0226] The processor 1030 controls the overall operation of each component of the computing device 1000. The processor 1030 may be implemented using at least one of various processing units such as a CPU (Central Processing Unit), an AP (Application Processor), a GPU (Graphics Processing Unit), and the like.

[0227] The memory 1010 stores various data and commands. The memory 1010 can be used as a reference Figures 1 to 21 The memory device described above can be implemented in the form of a COP structure, and an anti-fuse cell array for storing fuse information can be arranged in a memory cell region.

[0228] The memory controller 1020 controls the transfer of data or commands to and from the memory 1010. In some implementations, the memory controller 1020 may be provided as a separate chip from the processor 1030. In some implementations, the memory controller 1020 may be provided as an internal component of the processor 1030.

[0229] The storage device 1040 stores programs and data in a non-volatile manner. In some embodiments, the storage device 1040 can be implemented with a non-volatile memory. The communication interface 1050 supports wired / wireless Internet communication of the computing device 1000. In addition, the communication interface 1050 can support various communication systems other than Internet communication. The bus 1060 provides a communication function between the components of the computing device 1000. The bus 1060 may include at least one type of bus according to the communication protocol between the components.

[0230] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope that can be claimed, but rather as descriptions of features that can be specific to a particular implementation of a particular invention. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiples individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0231] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it is to be understood that the present disclosure is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A memory device, comprising: A memory cell region, the memory cell region comprising: a memory cell array configured to store data, and an anti-fuse cell array, comprising anti-fuse cells; and A peripheral circuit region at least a portion of which overlaps the memory cell region in a planar manner, and the peripheral circuit region includes an anti-fuse sense amplifier configured to output one-time programmable (OTP) data stored in the anti-fuse cell.

2. The memory device of claim 1, wherein The OTP data stored in the anti-fuse unit corresponds to one bit, and The anti-fuse unit includes at least three transistors.

3. The memory device of claim 2, wherein The antifuse cell array includes a plurality of programming word lines, and The anti-fuse unit includes at least two programming transistors operated by a programming word line among the plurality of programming word lines.

4. The memory device of claim 2, wherein The anti-fuse cell array includes a plurality of anti-fuse bit lines, the plurality of anti-fuse bit lines include a first anti-fuse bit line, a second anti-fuse bit line, and a third anti-fuse bit line. The anti-fuse sense amplifier includes a first anti-fuse sense amplifier configured to output first output data based on a signal input from the first anti-fuse bit line, a second anti-fuse sense amplifier configured to output second output data based on a signal input from the second anti-fuse bit line, and a third anti-fuse sense amplifier configured to output third output data based on a signal input from the third anti-fuse bit line, and The peripheral circuit region includes a majority voting circuit configured to receive the first output data, the second output data, and the third output data.

5. The memory device of claim 4, wherein The majority voting circuit is configured to output data corresponding to a majority of the first output data, the second output data, and the third output data as the OTP data.

6. The memory device of claim 1, wherein The anti-fuse sense amplifier overlaps at least a portion of the anti-fuse cell array in a planar manner.

7. The memory device of claim 1, wherein The peripheral circuit region includes a substrate, and The antifuse unit includes a vertical channel layer extending in a vertical direction of the substrate.

8. The memory device of claim 7, wherein The vertical channel layer includes at least one of silicon or indium gallium zinc oxide (IGZO).

9. A memory device comprising: Memory cell area, including: a memory cell array configured to store data, and an antifuse cell array comprising (i) a plurality of antifuse bit lines, (ii) a plurality of antifuse word lines, and (iii) a plurality of programming transistors electrically coupled to a first antifuse bit line of the plurality of antifuse bit lines and coupled in parallel to each other; and A peripheral circuit region includes an anti-fuse sense amplifier configured to output one-time programmable (OTP) data stored in the plurality of programming transistors.

10. The memory device of claim 9, wherein The anti-fuse cell array includes a read transistor disposed between the first anti-fuse bit line and the plurality of program transistors.

11. The memory device of claim 9, wherein The plurality of programming transistors include a first programming transistor and a second programming transistor, and The anti-fuse cell array includes a first read transistor disposed between the first anti-fuse bit line and the first programming transistor, and a second read transistor disposed between the first anti-fuse bit line and the second programming transistor.

12. The memory device of claim 9, wherein The plurality of programming transistors include a first programming transistor and a second programming transistor operated by a first programming word line of the plurality of anti-fuse word lines, and The second programming transistor is configured to operate the first programming transistor to output a programming current and a cutoff current based on the first programming word line.

13. The memory device of claim 9, wherein The plurality of programming transistors include a first programming transistor and a second programming transistor operated by a first programming word line of the plurality of anti-fuse word lines, and The first programming transistor and the second programming transistor are configured to output a programming current operated by the first programming word line.

14. A memory device comprising: a memory cell region including (i) a plurality of bit lines, (ii) a plurality of word lines, (iii) a memory cell array, and (iv) an anti-fuse cell array, the memory cell array including a memory vertical channel layer extending perpendicularly to a direction in which the plurality of word lines extend on upper surfaces of the plurality of bit lines, and the anti-fuse cell array including anti-fuse cells; as well as A peripheral circuit region at least a portion of which overlaps the memory cell region in a planar manner and includes an anti-fuse sense amplifier configured to output one-time programmable (OTP) data stored in the anti-fuse cell.

15. The memory device of claim 14, wherein The antifuse cell array includes a plurality of antifuse bit lines, a plurality of antifuse word lines, and a first vertical channel layer and a second vertical channel layer extending perpendicularly to a direction in which the plurality of antifuse word lines extend over the plurality of antifuse bit lines.

16. The memory device of claim 15, wherein For the plurality of anti-fuse bit lines, a height of an upper surface of the first vertical channel layer and a height of an upper surface of the second vertical channel layer are the same as a height of an upper surface of the memory vertical channel layer.

17. The memory device of claim 16, wherein: The anti-fuse cell array comprises: a first contact disposed on the upper surface of the first vertical channel layer; a second contact disposed on the upper surface of the second vertical channel layer; and A coupling conductor contacts the first contact and the second contact.

18. The memory device of claim 16, wherein The memory cell array includes a capacitor structure disposed on the memory vertical channel layer.

19. The memory device of claim 15, wherein The anti-fuse unit includes the first vertical channel layer and the second vertical channel layer, and The first vertical channel layer contacts the plurality of anti-fuse bit lines, and The second vertical channel layer is disposed to be spaced apart from the plurality of antifuse bit lines.

20. The memory device of claim 14, wherein The anti-fuse unit includes a source / drain region in contact with a bit line contact extending in an extension direction of the memory vertical channel layer among the plurality of bit lines.

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