Wafer testing method and wafer testing apparatus

Abstract

Embodiments of the present disclosure provide a wafer testing method and a wafer testing apparatus. The method comprises: providing a wafer having a wafer device area and a wafer edge area, the wafer edge area surrounding the wafer device area; providing a wafer testing apparatus having a testing chuck, the testing chuck comprising a main body supporting portion and an edge supporting portion, the edge supporting portion surrounding the main body supporting portion and comprising a vacuum suction passage and an isolation vent passage; placing the wafer on the testing chuck, wherein the wafer device area is located on the main body supporting portion and the wafer edge area is located on the edge supporting portion; extracting gas in the vacuum suction passage and between the wafer edge area and the edge supporting portion through the vacuum suction passage to fix the wafer on the testing chuck, the isolation vent passage being in communication with ambient air pressure and isolating a space between the wafer device area and the main body supporting portion from the vacuum suction passage; and testing the wafer using a probe. The wafer testing method and apparatus of the present disclosure can improve the accuracy of wafer testing.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of semiconductor technology, and in particular to a wafer testing method and wafer testing equipment. Background Technology

[0002] Chip testing is a crucial step in semiconductor manufacturing. After the main manufacturing steps of a semiconductor wafer are completed, the chips on the wafer are tested to screen out defective or failed chips, ensuring that only qualified chips proceed to subsequent processes. However, conventional testing methods may suffer from inaccuracies or the inability to effectively test all chips, leading to inaccurate judgments about chip quality and potentially impacting subsequent processes. Improving testing accuracy is a significant research topic in this field. Summary of the Invention

[0003] A wafer testing method is provided according to at least one embodiment of the present disclosure, comprising: providing a wafer having a wafer device region and a wafer edge region, the wafer device region including semiconductor devices, and the wafer edge region surrounding the wafer device region; providing a wafer testing apparatus having a test tray, the test tray including a main support portion and an edge support portion, the edge support portion surrounding the main support portion and including spaced-apart vacuum adsorption channels and isolation venting channels; placing the wafer on the test tray of the wafer testing apparatus, wherein the wafer device region is located on the main support portion; the wafer edge region... The wafer edge region is located on the edge support portion, and the vacuum adsorption channel and the isolation venting channel each have an opening facing the wafer edge region; the vacuum adsorption channel extracts gas from the vacuum adsorption channel and between the wafer edge region and the edge support portion, making the gas pressure between the wafer edge region and the edge support portion lower than the ambient gas pressure, thereby adsorbing and fixing the wafer onto the test platform, wherein the isolation venting channel is connected to the ambient gas pressure and separates the space between the wafer device area and the main support portion from the vacuum adsorption channel; and the wafer is tested using a probe.

[0004] In a wafer testing method provided according to at least one embodiment of the present disclosure, the semiconductor device has a cavity and a diaphragm, and the cavity is located between the diaphragm and the main support portion. The space between the wafer device region and the main support portion includes the cavity and the space at the contact interface between the wafer device region and the main support portion. During the test, the air pressure in the cavity is the same as the air pressure on the side of the diaphragm away from the cavity.

[0005] In a wafer testing method provided according to at least one embodiment of the present disclosure, the orthogonal projection of the isolation venting channel on a reference plane parallel to the main surface of the wafer is located between the orthogonal projection of the cavity on the reference plane and the orthogonal projection of the vacuum adsorption channel on the reference plane.

[0006] In the wafer testing method provided according to at least one embodiment of the present disclosure, the air pressure on the side of the diaphragm away from the cavity is the ambient air pressure, and the space between the wafer device area and the main support portion is connected to the ambient air pressure through the isolation venting channel.

[0007] According to at least one embodiment of the wafer testing method provided in this disclosure, the test platform has a first surface and a second surface opposite to each other in a direction perpendicular to the main surface of the wafer, the first surface is in contact with the wafer, and the vacuum adsorption channel includes: a first trench recessed from the first surface of the test platform toward the second surface; and a first connecting channel communicating with the first trench and connected to a vacuum pump.

[0008] In a wafer testing method provided according to at least one embodiment of the present disclosure, the first connection channel extends from the first trench to the sidewall of the test platform.

[0009] In a wafer testing method provided according to at least one embodiment of the present disclosure, the first trench is annular, or the first trench includes a plurality of first holes.

[0010] According to at least one embodiment of the wafer testing method provided in this disclosure, the isolation venting channel includes: a second trench recessed from a first surface of the test tray that contacts the wafer toward a second surface of the test tray opposite to the first surface; and a second connecting channel communicating with the second trench and the ambient air pressure.

[0011] In a wafer testing method provided according to at least one embodiment of the present disclosure, the second trench is located in the upper portion of the test platform, and the second connection channel extends from the bottom of the second trench to the second surface of the test platform.

[0012] In a wafer testing method provided according to at least one embodiment of the present disclosure, the second trench is annular, or the second trench includes a plurality of second holes.

[0013] According to at least one embodiment of the wafer testing method provided in this disclosure, the wafer testing equipment includes a probe assembly, the probe assembly includes the probe and an elastic probe fixing bracket, the elastic probe fixing bracket includes a fixing part and an elastic extension part connected to each other, the elastic extension part is elastically movable in a direction perpendicular to the main surface of the wafer, and the probe is fixed on the elastic extension part.

[0014] In a wafer testing method provided according to at least one embodiment of the present disclosure, the fixing portion extends along a direction perpendicular to the main surface of the wafer, the initial included angle between the elastic extension portion and the fixing portion is an obtuse angle, and the included angle between the probe and the wafer is an acute angle.

[0015] According to at least one embodiment of the wafer testing method provided in this disclosure, testing the wafer using the probe includes: contacting the wafer with the probe, in response to the reaction force of the wafer on the probe, fixing the elastic extension of the probe to undergo elastic displacement, and the probe sliding on the wafer from a first position to a second position, wherein the sliding distance between the first position and the second position is in the range of 10 micrometers to 30 micrometers.

[0016] At least one embodiment of this disclosure provides a wafer testing apparatus, comprising: a test tray configured to carry a wafer during wafer testing, wherein the test tray includes a main support portion and an edge support portion, the edge support portion surrounding the main support portion and including a spaced-apart vacuum adsorption channel and an isolation venting channel, the vacuum adsorption channel being configured to be connected to a vacuum pump, and the isolation venting channel being configured to communicate with ambient air pressure and disposed on a side of the vacuum adsorption channel away from the sidewall of the test tray; and a probe assembly including probes configured to test the wafer during wafer testing.

[0017] In a wafer testing apparatus provided according to at least one embodiment of the present disclosure, the probe assembly further includes: an elastic probe fixing bracket, the elastic probe fixing bracket including a fixing part and an elastic extension part, the elastic extension part being configured to fix the probe and be elastically movable in a direction perpendicular to the main surface of the test tray.

[0018] According to at least one embodiment of the wafer testing method and wafer testing equipment provided in this disclosure, during wafer testing, while the wafer is stably fixed on the test tray, the device structure of semiconductor devices in the wafer device area is prevented from being affected by vacuum adsorption during the testing process. This avoids the impact of vacuum adsorption on the accuracy of wafer testing, thereby improving the accuracy of wafer testing. Moreover, it can perform comprehensive, effective and accurate testing on all semiconductor devices in the wafer device area, ensuring that the chips entering subsequent processes are suitable chips, thereby improving process yield. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0020] Figure 1 A schematic diagram of a wafer testing apparatus and a wafer according to some embodiments of the present disclosure is shown.

[0021] Figure 2 A schematic cross-sectional view of a wafer testing apparatus according to some embodiments of the present disclosure is shown, including a test tray and a wafer carried on the test tray.

[0022] Figure 3 A schematic plan view of a test bench of a wafer testing apparatus according to some embodiments of the present disclosure is shown.

[0023] Figure 4 A schematic cross-sectional view of a test bench of a wafer testing apparatus according to some embodiments of the present disclosure is shown.

[0024] Figure 5 Another schematic cross-sectional view of the test bench of a wafer testing apparatus according to some embodiments of the present disclosure is shown.

[0025] Figure 6 A schematic plan view of a wafer according to some embodiments of the present disclosure is shown.

[0026] Figure 7 A schematic cross-sectional view of a wafer according to some embodiments of the present disclosure is shown.

[0027] Figure 8 This diagram illustrates the displacement of the elastic probe holder and the probe during wafer testing using a wafer testing device according to some embodiments of the present disclosure.

[0028] Figure 9 A schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0029] Figure 10 A schematic flowchart illustrating a wafer testing method according to some embodiments of the present disclosure is shown.

[0030] Symbol explanation:

[0031] 11: First surface; 12: Second surface; 30: Substrate; 31: First dielectric layer; 32: Second dielectric layer; 33: Backplate; 34: Additional cavity; 35: First conductive pad; 36: Second conductive pad; 50: Wafer testing equipment; 100: Test platform; 101: Main support portion; 102: Edge support portion; 103: Vacuum adsorption channel; 103a: First trench; 103b: First connection channel; 105: Isolation and venting channel; 105a: Second trench; 105b: Second connection channel; 120: Probe base; 121: Extended cantilever; 122: Fixing portion; 123: Elastic extension portion; 1 24: Elastic probe holder; 125: Probe; 150: Probe assembly; 200: Wafer; 201: Wafer device area; 202: Wafer edge area; 204: Semiconductor device; 205: Cavity; 206: Diaphragm; α: Initial angle; β: First angle; θ: Second angle; D1: First direction; D2: Second direction; w1: First width; w2: Second width; d1: First distance; d2: Second distance; d3: Third distance; P1: First position; P2: Second position; S1: Sliding distance; S10: First step; S20: Second step; S30: Third step; S40: Fourth step. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0034] Semiconductor wafers typically consist of multiple dies, each containing one or more semiconductor devices. After the main manufacturing processes of a semiconductor wafer are completed, wafer testing can be performed, such as testing the electrical and other performance characteristics of the semiconductor devices within the dies on the wafer. For example, during wafer testing, the semiconductor wafer can be placed on a test platform of a testing apparatus, for instance, by vacuum adsorption, and probes can be used to perform probing on the wafer. In some examples, a die may also be referred to as a chip.

[0035] Generally, vacuum adsorption fixes the entire wafer onto the test platform; however, for some semiconductor devices with special structures, vacuum adsorption may affect the device structure of the semiconductor device in the wafer, which may affect the accuracy of the test results and lead to inaccurate test results.

[0036] For example, in some cases, the wafer may include semiconductor devices with special structures such as cavities and diaphragms. For testing such products, due to the influence of these special structures, conventional testing methods may be difficult to meet the special requirements of these products, resulting in inaccurate test results or the inability to test all the devices on the die.

[0037] For example, in devices with cavities and diaphragms, when using vacuum adsorption to fix the wafer, the gas inside the cavity is also removed, causing the gas pressure inside the cavity to be lower than the ambient gas pressure. This results in a pressure difference across the diaphragm, leading to diaphragm movement and deformation. However, this movement and deformation of the diaphragm affects the accuracy of the test results, causing the test results to fail to accurately reflect the true characteristics of the device.

[0038] In some examples, test chips with dedicated test patterns can be embedded in the wafer. These test chips have vent holes on their diaphragms to maintain pressure balance across the diaphragm during testing, preventing displacement due to vacuum adhesion. However, other device chips do not have vent holes on their diaphragms and are not directly used for testing. This testing method only allows for sampling of devices on the wafer, inferring parameters of other chips from the test chips, but it cannot accurately test the true parameters of all chips, thus failing to guarantee the accuracy of testing all chips.

[0039] In some examples, the chip is tested after the back of the wafer is coated with a film and diced. However, the sealing pressure in the cavity between the film and the chip can affect the pressure deformation of the diaphragm during the test, thus affecting the accuracy of the test.

[0040] To address the aforementioned issue of inaccurate testing, this disclosure provides a wafer testing method and wafer testing equipment, which can improve the accuracy of wafer testing, achieve comprehensive and effective initial screening of chip performance in wafers, ensure that chips entering subsequent processes (e.g., packaging processes) are all qualified chips, thereby improving product yield.

[0041] For example, this disclosure provides a wafer testing method, comprising: providing a wafer having a wafer device region and a wafer edge region, the wafer device region including semiconductor devices, and the wafer edge region surrounding the wafer device region; providing a wafer testing apparatus having a test tray, the test tray including a main support portion and an edge support portion, the edge support portion surrounding the main support portion and including spaced-apart vacuum adsorption channels and isolation venting channels; placing the wafer on the test tray of the wafer testing apparatus, wherein the wafer device region is located on the main support portion; and the wafer edge region is placed... The edge support portion has an opening facing the wafer edge region, and the vacuum adsorption channel and the isolation venting channel each have an opening facing the wafer edge region. Gas is extracted from the vacuum adsorption channel and from the space between the wafer edge region and the edge support portion, making the gas pressure between the wafer edge region and the edge support portion lower than the ambient gas pressure, thereby adsorbing and fixing the wafer onto the test platform. The isolation venting channel is connected to the ambient gas pressure and separates the space between the wafer device area and the main support portion from the vacuum adsorption channel. The wafer is then tested using a probe.

[0042] This disclosure provides a wafer testing apparatus, comprising: a test tray configured to carry a wafer during wafer testing, wherein the test tray includes a main support portion and an edge support portion, the edge support portion surrounding the main support portion and including a spaced-apart vacuum adsorption channel and an isolation venting channel, the vacuum adsorption channel being configured to be connected to a vacuum pump, and the isolation venting channel being configured to communicate with ambient air pressure and disposed on a side of the vacuum adsorption channel away from the sidewall of the test tray; and a probe assembly including probes configured to test the wafer during wafer testing.

[0043] In the wafer testing method of this disclosure, a wafer adsorption channel and an isolation venting channel are provided in the test tray of the wafer testing equipment. The wafer adsorption channel ensures that the air pressure between the wafer edge region and the edge support portion is lower than the ambient air pressure, thereby adsorbing and fixing the wafer onto the test tray. Simultaneously, the isolation venting channel is connected to the ambient air pressure and separates the space between the wafer device area and the main support portion from the vacuum adsorption channel. This avoids the adverse effects of vacuum adsorption on the device structure of semiconductor devices in the wafer device area during testing, thus preventing the accuracy of wafer testing from being affected by vacuum adsorption. Therefore, the accuracy of wafer testing is improved, and all semiconductor devices in the wafer device area can be comprehensively, effectively, and accurately tested, ensuring that the chips entering subsequent processes are suitable chips, thereby improving process yield. The wafer testing equipment of this disclosure has the same technical effects as the above-described wafer testing method, and will not be described again here.

[0044] In some embodiments, the semiconductor device has a cavity and a diaphragm, and the cavity is located between the diaphragm and the main support portion. The space between the wafer device region and the main support portion includes the cavity and the space at the contact interface between the wafer device region and the main support portion. During the test, the air pressure in the cavity is the same as the air pressure on the side of the diaphragm away from the cavity.

[0045] Therefore, for semiconductor devices with special structures such as cavities and diaphragms, the wafer testing method disclosed herein, through the above-mentioned settings, ensures that while the wafer is fixed by vacuum adsorption, the air pressure in the cavity located in the wafer device area is the same as the air pressure on the side of the diaphragm away from the cavity. This avoids displacement of the diaphragm due to vacuum adsorption, thereby preventing the diaphragm displacement from affecting the accuracy of the test and improving the accuracy of wafer testing.

[0046] Figure 1 A schematic diagram of a wafer testing apparatus and a wafer according to some embodiments of the present disclosure is shown. Figure 2 A schematic cross-sectional view is shown of a test tray and a wafer supported on the test tray in a wafer testing apparatus according to some embodiments of the present disclosure. It should be understood that, for the sake of brevity, Figure 1 The specific structure of the test platform and wafer is not shown in the document.

[0047] refer to Figure 1 In some embodiments, the wafer testing apparatus 50 includes a test tray 100 and a probe assembly 150. The test tray 100 is configured to hold and hold a wafer under test, such as wafer 200, during wafer testing. The probe assembly 150 is configured to perform tests on the wafer, such as electrical tests, using probes 125 during wafer testing.

[0048] refer to Figure 2In some embodiments, the test platform 100 includes a main support portion 101 and an edge support portion 102, the edge support portion 102 being close to the edge (i.e., its sidewall) of the test platform 100 and surrounding the main support portion 101. In some embodiments, the edge support portion 102 includes a vacuum adsorption channel 103 and an isolation venting channel 105 spaced apart.

[0049] Wafer 200 has a wafer device region 201 and a wafer edge region 202; wafer device region 201 includes a semiconductor device having a cavity 205 and a diaphragm 206; wafer edge region 202 is the region of wafer 200 outside the region having cavity 205, and may surround wafer device region 201. No cavity or diaphragm is provided in wafer edge region 202.

[0050] In some embodiments, during wafer testing, a wafer 200 is placed on a test tray 100, wherein the wafer device region 201 is located on the main support portion 101 of the test tray 100, and a cavity 205 is located between the diaphragm 206 and the main support portion 101. That is, a portion of the surface of the main support portion 101 is exposed to the cavity 205 of the wafer 200.

[0051] The wafer edge region 202 is placed on the edge support portion 102 of the test stage 100, and both the vacuum adsorption channel 103 and the isolation venting channel 105 have openings facing the wafer edge region 202. That is, a portion of the surface of the wafer edge region 202 (i.e., Figure 2 The bottom surface shown is exposed to the openings of the vacuum adsorption channel 103 and the isolation venting channel 105. In this document, the opening of the channel refers to the opening of the channel exposed on the surface of the tray.

[0052] It should be understood that the wafer and the test stage have matching dimensions in a direction parallel to the main surface of the wafer, and the dimensions of the two can be the same or different, as long as the device area with cavities on the wafer can be correspondingly set with the main support part, and the edge area of ​​the wafer can be correspondingly set with the vacuum adsorption channel and isolation venting channel of the edge support part.

[0053] In some embodiments, the vacuum adsorption channel 103 is configured to be connected to a vacuum pump (not shown) and is used to adsorb and fix the wafer 200 during wafer testing. An isolation venting channel 105 is configured to be in communication with ambient air pressure and is configured to isolate the space between the wafer device area 201 and the main support portion 101 from the vacuum adsorption channel 103 during wafer testing; the space between the wafer device area 201 and the main support portion 101 includes a cavity 205. In this way, when the wafer 200 is vacuum adsorbed and fixed, gas in the space between the wafer device area 201 and the main support portion 101 (e.g., cavity 205) is prevented from being drawn away by the vacuum pump. In this document, "channel or space in communication with ambient air pressure" means that the channel or space is directly or indirectly connected to the ambient space in the wafer testing equipment (e.g., the environment in the testing equipment, or the ambient atmosphere), and the air pressure in the channel or space is approximately the same as the ambient air pressure.

[0054] In some embodiments, at least a portion of the isolation venting channel 105 surrounds the main support portion 101, and the vacuum adsorption channel 103 is located on the side of the isolation venting channel 105 away from the main support portion 101. The orthographic projection of the cavity 205 on a reference plane parallel to the main surface of the wafer may lie within the orthographic projection of the main support portion 101 on the reference plane. For example, the orthographic projection of the isolation venting channel 105 on a reference plane parallel to the main surface of the wafer may lie between the orthographic projection of the cavity 205 on the reference plane and the orthographic projection of the vacuum adsorption channel 103 on the reference plane, thereby effectively isolating the cavity and the vacuum adsorption channel. In some embodiments, the orthographic projections of at least the openings of the isolation venting channel 105 and the vacuum adsorption channel 103 near the wafer on the aforementioned reference plane may lie within the orthographic projection of the wafer edge region on the reference plane; for example, the orthographic projections of the isolation venting channel 105 and the vacuum adsorption channel 103 on a reference plane parallel to the main surface of the wafer may both lie entirely within the orthographic projection of the wafer edge region (i.e., the region without a cavity) on the reference plane.

[0055] It should be understood that after the wafer 200 is placed on the test tray 100, the wafer 200 and the test tray 100 are in contact with each other, but the contact interface between the wafer 200 and the test tray 100 is not a completely enclosed space. For example, there is a tiny space (or gap) between the wafer 200 and the test tray 100 (i.e., at the contact interface). Under normal conditions, the air pressure in this space is the same as the ambient air pressure; under vacuum conditions, the gas in this space can be removed, thereby making the air pressure in this space lower than the ambient air pressure, for example, a vacuum state. In this document, ambient air pressure refers to the ambient air pressure in the wafer testing equipment, such as normal pressure or atmospheric pressure; a vacuum state can include an absolute vacuum state with zero gas pressure or a negative pressure state with air pressure lower than the ambient air pressure.

[0056] In some embodiments, during wafer testing, a vacuum pump is used to extract gas from the vacuum adsorption channel 103 and the space between the wafer edge region 202 and the edge support portion 102 (i.e., at their contact interface) through the vacuum adsorption channel 103, making the gas pressure between the wafer edge region 202 and the edge support portion 102 lower than the ambient gas pressure, thereby adsorbing and fixing the wafer 200 onto the test platform 100. Specifically, during the vacuum pumping process, in addition to the gas being extracted from the vacuum adsorption channel directly connected to the vacuum pump, the gas in the space between the edge support portion 102 and the wafer edge region 202 (i.e., at their contact interface) is also extracted because it is connected to the vacuum adsorption channel 103. This makes the gas pressure between the edge support portion 102 and the wafer edge region 202 lower than the ambient gas pressure, thus allowing the wafer edge region 202 to be adsorbed and fixed onto the edge support portion of the test platform 100, thereby fixing the wafer 200 onto the test platform 100.

[0057] The isolation venting channel 105 is connected to the ambient air pressure and separates the space between the wafer device area 201 and the main support portion 101 from the vacuum adsorption channel 103. The space between the wafer device area 201 and the main support portion 101 includes the cavity 205 and also includes the space at the contact interface between the wafer device area 201 and the main support portion 101. In this way, the gas in the cavity 205 and at the contact interface between the wafer device area 201 and the main support portion 101 can be prevented from being drawn away by the vacuum pump.

[0058] For example, the isolation venting channel 105 is connected to the ambient air pressure, the vacuum adsorption channel 103 is located outside the isolation venting channel, and the main support portion 101 is located inside the isolation venting channel 105 to be separated from the vacuum adsorption channel. For example, the isolation venting channel 105 may surround the main support portion 101. Therefore, the space between the main support portion 101 and the wafer device region 201 can be separated from the vacuum adsorption channel 103 by the isolation venting channel 105, so that the gas in the cavity 205 of the wafer device region 201 and the gas in the space at the contact interface between the main support portion 101 and the wafer device region 201 will not be pumped away by the vacuum pump. For example, the cavity 205 and the space at the contact interface between the wafer device region 201 and the main support portion 101 are connected to the isolation venting channel 105 and the ambient air pressure.

[0059] In some embodiments, the cavity 205 communicates with the isolation venting channel 105 through the space at the contact interface between the wafer device region 201 and the main support portion 101. For example, the opening of the isolation venting channel 105 near the wafer side does not directly communicate with the cavity 205, that is, the opening of the isolation venting channel 105 and the cavity 205 do not overlap in a direction perpendicular to the main surface of the wafer or test tray. In other words, at least the orthographic projection of the opening of the isolation venting channel 105 on a reference plane parallel to the main surface of the wafer or test tray does not overlap with the orthographic projection of the cavity 205 on the reference plane (i.e., they are offset). For example, the entire orthographic projection of the isolation venting channel 105 on the reference plane may not overlap with the orthographic projection of the cavity 205 on the reference plane. For example, a portion of the contact interface between the wafer device region 201 and the main support portion 101 is located between the opening of the isolation venting channel 105 and the cavity 205 in a direction parallel to the main surface of the wafer. This further ensures that cavity 205 is isolated from the vacuum adsorption channel, preventing the gas in the cavity from being drawn away during the vacuum adsorption process.

[0060] In some embodiments, the air pressure on the side of the diaphragm away from the cavity is the ambient air pressure, and the space between the wafer device area and the main support portion is connected to the ambient air pressure through the isolation venting channel. In this way, the air pressure on both sides of the diaphragm is approximately the same, thereby preventing the diaphragm from shifting due to the pressure difference between its two sides.

[0061] For example, a probe can be used to test the wafer, and during the test, while the air pressure between the edge support and the wafer edge region is less than the ambient air pressure to fix the wafer, the air pressure in the cavity 205 of the wafer device region and the air pressure on the side of the diaphragm 206 away from the cavity can be approximately equal to each other, for example, both equal to the ambient air pressure.

[0062] It should be understood that since the wafer edge region and the wafer device region are connected as a whole, and the main support part and the edge support part of the test platform are also connected as a whole, and the wafer edge region surrounds the wafer device region, and the edge support part surrounds the main support part, a vacuum is formed between the wafer edge region and the edge support part, so that the wafer edge region can be adsorbed onto the main support part, thus the entire wafer can be stably fixed on the test platform.

[0063] For example, during wafer testing, the vacuum pump can operate continuously, and its power can be adjusted as needed. This allows the gas in the space between the edge support portion 102 and the wafer edge region 202 to be continuously evacuated, maintaining the gas pressure in this space at a vacuum level. This ensures the wafer is stably fixed on the test platform. Therefore, although the space between the edge support portion and the wafer edge region is connected to the isolation venting channel, the vacuum pump can be continuously operated to extract the gas between them. For instance, the rate at which the gas is removed from this space can be greater than the rate at which gas enters the space from the isolation venting channel. This maintains the gas pressure between the wafer edge and the edge support portion at a vacuum level (e.g., negative pressure) throughout the wafer testing process, allowing the wafer edge to be continuously adhered and fixed to the edge support portion, thus securing the entire wafer on the test platform.

[0064] In this embodiment, the wafer edge region and the edge support portion are in a vacuum state, while the space between the wafer device region and the main support portion is separated from the vacuum adsorption channel, for example, in an ambient air pressure state. Thus, during wafer testing, while keeping the wafer stably fixed on the test tray, the device structure of the semiconductor device in the wafer device region is largely unaffected by vacuum adsorption. For example, when the semiconductor device has special structures such as cavities and diaphragms, pressure differences on both sides of the diaphragm of the semiconductor device can be avoided to prevent deformation, thereby improving the accuracy of wafer testing.

[0065] In some embodiments, in the wafer testing apparatus, the test platform has a first surface and a second surface opposite each other in a direction perpendicular to the main surface of the wafer, the first surface being configured to contact the wafer during wafer testing, and the vacuum adsorption channel comprising: a first trench recessed from the first surface of the test platform toward the second surface; and a first connecting channel communicating with the first trench and connected to a vacuum pump. For example, the first connecting channel extends from the first trench to a sidewall of the test platform. For example, the first trench is annular, or the first trench includes a plurality of first holes.

[0066] In some embodiments, the isolation venting channel of the test bench includes: a second groove recessed from the first surface of the test bench toward the second surface; and a second connecting channel communicating with the second groove and ambient air pressure. For example, the second groove is located in the upper portion of the test bench, and the second connecting channel extends from the bottom of the second groove to the second surface of the test bench. For example, the second groove is annular, or the second groove includes a plurality of second holes.

[0067] Figure 3A schematic plan view of a test bench of a wafer testing apparatus according to some embodiments of the present disclosure is shown; Figure 4 A schematic cross-sectional view of a test bench of a wafer testing apparatus according to some embodiments of the present disclosure is shown; Figure 5 Another schematic cross-sectional view of a test bench of a wafer testing apparatus according to some embodiments of the present disclosure is shown. For example, Figure 4 and Figure 5 They are along Figure 3 A cross-sectional view taken from lines AB and AC; Figure 3 It is along Figure 4 The planar view intercepted by line I-I'.

[0068] refer to Figures 3 to 5 For example, the test tray 100 may have a circular planar shape. The test tray 100 is used to hold the wafer under test and has a first surface 11 and a second surface 12 opposite each other in a direction perpendicular to the main surface of the wafer (or the main surface of the test tray). The first surface 11 of the test tray 100 is configured to contact the wafer during wafer testing. The vacuum adsorption channel 103 and the isolation venting channel 105 have openings exposed at the first surface 11. The first surface 11 or the second surface 12 may also be referred to as the main surface of the test tray. The main surface of the test tray is substantially parallel to the main surface of the wafer.

[0069] In some embodiments, the vacuum adsorption channel 103 of the test platform 100 includes a first groove 103a and a first connecting channel 103b. For example, the first groove 103a is recessed from the first surface 11 of the test platform 100 toward the second surface 12; the first connecting channel 103b communicates with the first groove 103a and is connected to a vacuum pump (not shown). In some embodiments, the first connecting channel 103b extends from the first groove 103a to the sidewall of the test platform 100.

[0070] like Figure 4 and Figure 5 As shown, for example, the first trench 103a may extend from the first surface 11 of the test platform 100 into the test platform 100 in a direction perpendicular to the main surface of the wafer, without penetrating the test platform 100; that is, the depth of the first trench 103a in the direction perpendicular to the main surface of the wafer is less than the thickness of the test platform 100. For example, the extension direction of the first connection channel 103b may be different from the extension direction of the first trench 103a (i.e., intersecting, for example, substantially perpendicular). For example, the first connection channel 103b may extend in a direction substantially parallel to the main surface of the wafer and may extend from the bottom of the first trench 103a to the sidewall of the edge of the test platform 100.

[0071] For example, such as Figure 3As shown, the first groove 103a may be annular, for example, circular; one or more first connecting channels 103b may be connected to the first groove 103a, for example, they may be set on the side of the annular groove and extend to the side wall of the edge of the test platform to connect with the vacuum pump.

[0072] In other embodiments, the first trench may include a plurality of first holes, which may be spaced apart from each other and connected to a vacuum pump via one or more first connecting channels. In other embodiments, the first connecting channels may also extend from the first trench to a second surface of the test platform to connect to the vacuum pump at the second surface; this disclosure is not limiting. It should be understood that the shape of the vacuum adsorption channel shown in the figures is merely illustrative and is not intended to limit the scope of the disclosure. The vacuum adsorption channel may have any suitable shape or structure, as long as a vacuum pump can be used to extract gas between the edge support portion of the test platform and the wafer edge region through the channel, thereby maintaining a vacuum between the edge support portion and the wafer edge region to fix the wafer on the test platform.

[0073] refer to Figures 3 to 5 In some embodiments, the isolation venting channel 105 includes a second groove 105a and a second connecting channel 105b. For example, the second groove 105a is recessed from the first surface 11 of the test bench 100 toward the second surface 12; the second connecting channel 105b communicates with the second groove 105a and the ambient air pressure. For example, as... Figure 5 As shown, the second groove 105a is located in the upper portion of the test platform 100, that is, the depth of the second groove is less than the thickness of the test platform, and the second connecting channel 105b extends from the bottom of the second groove 105a to the second surface of the test platform 100. In other words, the second groove 105a and the second connecting channel 105b can overlap in a direction perpendicular to the main surface of the test platform and are spatially connected to each other. Figure 4 The cross-sectional view shows the structure at the intersection of a portion of the second groove 105a and the second connecting channel 105b, where the second groove 105a and the second connecting channel 105b are spatially connected in a direction perpendicular to the main surface of the test platform, such that the isolation venting channel 105 penetrates the test platform 100 at this location, that is, extends from the first surface 11 of the test platform 100 to the second surface 12. Figure 5 The cross-sectional view shows that the first portion of the second groove 105a overlaps with the second connecting channel 105b, and the second portion of the second groove 105a does not overlap with the second connecting channel 105b. At the second portion of the second groove 105a, the isolation venting channel 105 extends from the first surface 11 of the test tray 100 into the test tray 100, but does not penetrate the test tray 100.

[0074] like Figure 3As shown, in some embodiments, the second groove 105a is annular, for example, circular. One or more second connecting channels 105b are disposed at the bottom of the annular second groove to communicate with ambient air pressure. It should be understood that, in order to clearly show the positional relationship between the second groove and the second connecting channels in the plan view, Figure 2 The dimensions (e.g., width) of the second connecting channel are shown to be larger than the corresponding dimensions of the second trench, but this disclosure is not limited thereto. In a direction parallel to the main surface of the test platform, the dimensions of the second trench 105a and the second connecting channel 105b may be the same or different from each other, as long as the second trench can be connected to the ambient air pressure through the second connecting channel.

[0075] In other embodiments, the second trench may also be a perforated structure including multiple second holes, which are connected to the ambient air pressure through one or more second connecting channels. It should be understood that the shape and structure of the isolation venting channel shown in the figures are merely illustrative examples, and this disclosure is not limited thereto. As long as the space between the wafer device area and the main support portion can be separated from the vacuum adsorption channel during wafer testing, preventing the space from being evacuated and / or ensuring that the air pressure in the space is approximately the same as the ambient air pressure, it is acceptable.

[0076] Continue to refer to Figures 3 to 5 In some embodiments, the isolation venting channel 105 (e.g., its second groove) surrounds the main support portion 101. The vacuum adsorption channel 103 is located near the edge of the test platform 100 and on the side of the isolation venting channel 105 away from the main support portion 101. That is, the isolation venting channel 105 is located between the vacuum adsorption channel 103 and the main support portion 101. For example, the vacuum adsorption channel 103 (e.g., its first groove) may surround the isolation venting channel 105 and be spaced apart from the isolation venting channel 105.

[0077] In some embodiments, the openings of the first connecting channel 103b of the vacuum adsorption channel 103 and the second connecting channel 105b of the isolation and venting channel 105 are respectively located on the side wall and the second surface of the test platform. This facilitates the connection of the first connecting channel to the vacuum pump without affecting the opening of the isolation and venting channel 105, but this disclosure is not limited thereto. The openings of the vacuum adsorption channel and the isolation and venting channel may also both be located on the second surface of the test platform, as long as they are spaced at a suitable distance, allowing the isolation and venting channel to communicate with the ambient air pressure and the vacuum adsorption channel to connect to the vacuum pump. In this document, the opening of each channel refers to the portion of the channel exposed on the surface (first surface, second surface, or side wall surface) of the test platform.

[0078] refer to Figure 3In some embodiments, the vacuum adsorption channel 103 is located near the edge of the test tray (i.e., its sidewall). For example, the first distance d1 of the vacuum adsorption channel 103 from the edge of the test tray 100 can range from about 1 mm to 8 mm. In some embodiments, the first width w1 of the vacuum adsorption channel 103 can be set in the range of 0.5 mm to 5 mm. The above-mentioned size ranges of the vacuum adsorption channel are all size ranges of its main body portion (i.e., the first groove). The above-mentioned first distance d1 and first width w1 are corresponding dimensions in a direction parallel to the main surface of the test tray, and corresponding dimensions in a direction perpendicular to the extension direction of the vacuum adsorption channel, for example, corresponding dimensions in a direction perpendicular to the circumferential direction of the test tray.

[0079] In some embodiments, setting the corresponding size of the vacuum adsorption channel within the above-mentioned range can facilitate the alignment of the vacuum adsorption channel with the wafer edge region, and enable the wafer to be adsorbed and fixed on the test tray through the vacuum adsorption channel.

[0080] Continue to refer to Figure 3 In some embodiments, the isolation venting channel 105 is disposed on the side of the vacuum adsorption channel 103 away from the edge of the test tray and is spaced apart from the vacuum adsorption channel 103. For example, the second distance d2 of the isolation venting channel 105 from the edge (i.e., its sidewall) of the test tray 100 can range from about 4 mm to 10 mm or 3 mm to 10 mm. In some embodiments, the second width w2 of the isolation venting channel 105 can be set in the range of 0.5 mm to 2 mm. The above-mentioned size ranges of the isolation venting channel are all size ranges of its main body portion (e.g., the second groove). The above-mentioned second distance d2 and second width w2 are both corresponding dimensions in a direction parallel to the main surface of the test tray and corresponding dimensions in a direction perpendicular to the extension direction of the isolation venting channel, for example, corresponding dimensions in a direction perpendicular to the circumferential direction of the test tray.

[0081] In some embodiments, setting the corresponding size of the isolation venting channel 105 within the above-mentioned range can help to isolate the vacuum adsorption channel and the wafer device area during wafer testing, prevent the space between the wafer device area and the main support from being evacuated, and help to maintain the space between the wafer device area and the main support at a pressure approximately the same as the ambient air pressure.

[0082] Figure 6 A schematic plan view of a wafer according to some embodiments of the present disclosure is shown. Figure 7 A schematic cross-sectional view of a wafer according to some embodiments of the present disclosure is shown.

[0083] refer to Figure 6 and Figure 7In some embodiments, wafer 200 may include a wafer device region 201 and a wafer edge region 202. For example, the wafer edge region 202 may be annular and surround the wafer device region 201 in a direction parallel to the main surface of the wafer. A semiconductor device 204 having a cavity 205 and a diaphragm 206 is disposed within the wafer device region 201. In some embodiments, wafer 200 includes a substrate and a device material layer formed on the substrate. For example, wafer 200 may be a semiconductor wafer and include a semiconductor substrate; for example, wafer 200 may be a silicon wafer including a silicon substrate.

[0084] For example, wafer 200 includes multiple dies, which can be arranged in an array and spaced apart from each other by dicing regions, and each die may include one or more semiconductor devices. Figure 6 and Figure 7 In the example shown, each die corresponds to a semiconductor device 204. In some embodiments, at least some of the devices of the multiple dies may be devices including cavities and diaphragms, such as micro-electro-mechanical system (MEMS) devices. For example, the product formed by dicing dies including MEMS devices may also be called a MEMS chip.

[0085] In some embodiments, multiple dies on a wafer have similar structures, i.e., each die may include a MEMS device with a cavity and a diaphragm. For the sake of simplicity in the illustrations, Figure 6 The diagram only schematically illustrates the cavity 205 and diaphragm 206 included in a semiconductor device corresponding to one die. It should be understood that semiconductor devices corresponding to other dies also have similar structures. The number and arrangement of multiple dies in this diagram are merely illustrative and are not intended to limit the scope of this disclosure.

[0086] In some embodiments, the cavities and diaphragm structures of the semiconductor devices of multiple dies are all located within the wafer device area, while no cavities or diaphragm structures are located in the wafer edge area. This allows the wafer edge area to correspond to the vacuum adsorption channel of the test tray, preventing the cavities and diaphragm structures from being adversely affected by vacuum adsorption. In other words, the wafer manufacturing process does not involve cavity processing in its edge area.

[0087] In some embodiments, such as Figure 7As shown, the third distance d3 between the edge of the outermost cavity of the wafer and the edge of the wafer's sidewall can range from 4 mm to 10 mm or from 3 mm to 10 mm. That is, no cavity structure is provided in the region 3 or 4 mm to 10 mm away from the edge of the wafer's sidewall (e.g., it may be or include the wafer edge region). By ensuring that no cavity is provided in this region and that it has the above-mentioned size range, this region has sufficient size to allow the entire wafer to be fixed on the test stage by vacuum adsorption.

[0088] It should be understood that Figure 6 The boundary between the wafer device area and the wafer edge area is schematically shown as a dashed circle, but this is only for illustrative purposes. The wafer edge area refers to the area of ​​the wafer outside the cavity area, which may include all areas except the outermost device cavity. The wafer device area and the wafer edge area may also partially overlap, as long as there is no cavity in the wafer edge area.

[0089] In some embodiments, the wafer testing equipment includes a probe assembly, which includes the probe and a flexible probe holder. The flexible probe holder includes a fixed portion and a flexible extension portion connected to each other. The flexible extension portion is elastically movable in a direction perpendicular to the main surface of the wafer or the main surface of the test tray, and the probe is fixed to the flexible extension portion.

[0090] In some embodiments, the fixing portion extends in a direction perpendicular to the main surface of the wafer, and the initial angle between the elastic extension portion and the fixing portion is an obtuse angle, while the angle between the probe and the wafer is an acute angle. For example, the angle between the probe and the wafer ranges from 30° to 80°.

[0091] In some embodiments, during the testing of a wafer using a probe, the probe contacts the wafer, and in response to the reaction force of the wafer on the probe, the elastic extension of the probe is fixed to undergo elastic displacement, and the probe slides on the wafer from a first position to a second position, wherein the sliding distance between the first position and the second position ranges from 10 micrometers to 30 micrometers.

[0092] Return to reference Figure 1 In some embodiments, the probe assembly 150 of the wafer testing equipment 50 may include a probe base 120, an extension cantilever 121, a flexible probe holder 124, and a probe 125. The extension cantilever 121 is connected to the probe base 120, for example, extending outward from the sidewall of the probe base 120. The extension cantilever 121 and the probe base 120 may be integrally formed, or they may be fixedly connected to each other using connecting members.

[0093] The elastic probe fixing bracket 124 is fixed to the extension cantilever 121. For example, the extension cantilever 121 may be provided with fixing holes, and the elastic probe fixing bracket 124 is fixed to the extension cantilever 121 through the fixing holes.

[0094] In some embodiments, the resilient probe holder 124 includes a fixing portion 122 and a resilient extension 123 connected to each other. The fixing portion 122 is fixedly connected to the extension cantilever 121 and does not undergo significant displacement during wafer testing. The resilient extension 123 is used to fix the probe 125, for example, extending from the fixing portion 122 above the test tray to facilitate the probe 125 testing the wafer on the test tray. The resilient extension 123 is elastic, for example, it can move elastically in a direction perpendicular to the main surface of the wafer (e.g., a first direction D1), for example, it can be displaced vertically in said direction under force. In some embodiments, the fixing portion 122 and the resilient extension 123 may be an integrally formed structure.

[0095] In some embodiments, the probe 125 is fixed to the elastic extension 123 of the elastic probe fixing bracket 124, for example, at a position near the edge of the elastic extension 123. Here, the edge of the elastic extension 123 refers to the edge away from the fixing portion 122. For example, the elastic extension 123 and the probe 125 can be fixedly connected together using a screw or other connector.

[0096] In some embodiments, suitable materials and structural configurations, such as dimensions, can be selected to make the elastic probe holder 124 both structurally stable and elastic. Structural stability refers to the elastic probe holder 124's ability to effectively fix the probe, enabling effective contact between the probe and the wafer for testing. Elasticity refers to the elastic probe holder 124's ability to undergo elastic displacement under stress.

[0097] For example, the elastic modulus of the material of the elastic probe fixing bracket 124 can be set in the range of about 100 GPa to about 300 GPa, for example, about 190 GPa to 210 GPa, or about 200 GPa. For example, the elastic probe fixing bracket 124 may include materials such as stainless steel.

[0098] In some embodiments, the initial included angle α between the fixing portion 122 and the elastic extension portion 123 is set to an obtuse angle, i.e., 90° < α < 180°. The diameter of the elastic extension portion 123 can range from about 2 mm to 5 mm, and the length of the elastic extension portion can range from about 10 cm to 30 cm, 10 cm to 20 cm, or 10 cm to 15 cm. Here, the initial included angle refers to the angle between the fixing portion and the elastic extension portion when the elastic extension portion has not undergone elastic displacement; the length of the elastic extension portion refers to its length in its extension direction, and the diameter of the elastic extension portion generally refers to its width in the direction perpendicular to its extension direction. In some embodiments, while maintaining the elasticity of the elastic extension portion, the length of the elastic extension portion can be matched with the size of the wafer to be tested to facilitate the testing of the wafer by the probe assembly; the above-mentioned length range of the elastic extension portion is only illustrative and is not limited thereto, and the length can be adjusted according to the size of the wafer to be tested.

[0099] In some embodiments, setting the included angle between the fixing portion and the elastic extension portion to an obtuse angle, setting the diameter of the elastic extension portion to a small size, and / or setting the length of the elastic extension portion to a long size can all help to give the elastic extension portion a certain degree of elasticity. Moreover, while being elastic, the probe fixing bracket can effectively provide probe pressure, that is, enable the probe fixed thereon to apply appropriate pressure to the wafer and contact the wafer, thereby enabling the probe to effectively test the wafer.

[0100] In some embodiments, the probe 125 is obliquely fixed to the elastic extension 123, for example, at a position near the edge of the elastic extension 123. For example, the distance between the position where the probe 125 is fixed on the elastic extension 123 and the edge of the elastic extension 123 can range from about 0.5 cm to 3 cm. In some embodiments, the first included angle β between the probe 125 and the wafer 200 is set to an acute angle, for example, in the range of 30° to 80°. The included angle between the probe and the wafer refers to the angle between the probe and the main surface of the wafer, for example, the angle between the extension direction of the probe and the horizontal direction (e.g., the horizontal direction including the second direction D2 shown in the figure). It should be understood that, considering that the included angle between the elastic extension 123 and the fixing part 122 is an obtuse angle, while the included angle between the probe 125 and the wafer 200 is an acute angle, it can be deduced that the second included angle θ between the probe 125 and the elastic extension 123 is an obtuse angle. In some embodiments, the elastic modulus of probe 125 is greater than that of the elastic probe holder 124, meaning the rigidity of probe 125 is greater than that of the elastic probe holder 124. This allows the probe assembly to maintain elasticity while effectively contacting the wafer during testing, ensuring accurate wafer testing. For example, probe 125 may be made of a wear-resistant material, such as tungsten or its alloys; that is, probe 125 may be a tungsten needle.

[0101] In some embodiments, during wafer testing, a probe 125 contacts the wafer 200. In response to the reaction force of the wafer 200 on the probe 125, the elastic extension 123 of the fixed probe 125 undergoes elastic displacement, and the probe 125 slides from a first position to a second position on the wafer 200. For example, the sliding distance between the first position and the second position can be controlled within the range of 10 micrometers to 30 micrometers.

[0102] For example, during wafer testing, when probe 125 contacts wafer 200 for testing, probe 125 applies pressure to wafer 200, while wafer 200 applies a reaction force to probe 125 and its elastic extension 123. Due to the elasticity of the elastic probe holder and the aforementioned angle settings of the elastic probe holder and probe, the elastic extension 123 undergoes elastic displacement when subjected to the reaction force, simultaneously causing probe 125 to slide a distance on wafer 200. The sliding distance of the probe is proportional to the pressure applied by the probe; that is, the greater the pressure applied by the probe to the wafer, the longer the sliding distance; the smaller the pressure applied by the probe to the wafer, the smaller the sliding distance. In other words, the sliding distance reflects the magnitude of the probe pressure. For wafers including semiconductor devices with cavities or thin wafer wafers, excessive pressure applied by the probe to the wafer during wafer testing may damage the device structure. In the embodiments of this disclosure, the sliding distance of the probe can be controlled by the elasticity of the probe holder and the aforementioned angle and other structural settings, thereby controlling the pressure of the probe on the wafer. Therefore, through the above-mentioned settings, during the testing process, the probe can effectively provide probe pressure for effective testing while maintaining a certain degree of elasticity, controlling the pressure of the probe on the wafer within a suitable range, and maintaining the stability of the probe pressure. This allows for effective wafer testing while avoiding damage to the device structure within the wafer, enabling repeated testing of the wafer device structure by the probe.

[0103] Figure 8 The diagram illustrates the movement of a probe as it slides under pressure on the wafer during wafer testing, with the elastic extension and the position of the probe after displacement indicated by dashed lines.

[0104] refer to Figure 8During wafer testing, a probe 125 is used to contact the wafer 200 to perform wafer testing. For example, the probe 125 can contact the test pads on the semiconductor device of the wafer 200 to perform electrical testing on the semiconductor device. When the probe 125 contacts the wafer 200, it applies pressure to the wafer 200, and the wafer 200 applies a reaction force to the probe 125. This reaction force is transmitted through the probe 125 to the elastic extension 123 of the elastic probe holder. Because the elastic extension 123 is elastic and the angle between the probe 125 and the wafer is acute, the elastic extension 123 will undergo elastic displacement when subjected to the reaction force. For example, it may move away from the wafer in the first direction D1, while simultaneously causing the probe 125 to slide a distance on the wafer 200, for example, the probe 125 may slide a distance in a horizontal direction such as the second direction D2. For example, the probe 125 may slide from a first position P1 to a second position P2 on the wafer 200. The distance between the first position P1 and the second position P2 is the sliding distance S1 of probe 125.

[0105] In some embodiments, the sliding distance S1 is controlled within the range of 10 micrometers to 30 micrometers. By controlling the sliding distance within a suitable range, the pressure applied by the probe to the wafer can be controlled within a suitable range, thereby avoiding damage to the device structure in the wafer by the probe.

[0106] In the embodiments disclosed herein, compared to using a completely rigid fixing bracket without any elasticity, the elastic probe fixing bracket is elastic, and the angle between the probe and the wafer is set to an acute angle, which can reduce the pressure or stress on the wafer from the probe, thereby avoiding damage to the device structure of the wafer.

[0107] It should be understood that the wafer testing equipment and testing methods disclosed herein are applicable to any type of semiconductor device, and can improve the testing accuracy, especially for wafers with special device structures such as cavities. Figure 2 and Figure 7 The diagram schematically shows the cavity and diaphragm of a semiconductor device in a wafer, without showing the specific structure of all components of the semiconductor device.

[0108] Figure 9 A schematic cross-sectional view of a semiconductor device in a wafer according to some embodiments of the present disclosure is shown.

[0109] refer to Figure 9In some embodiments, the semiconductor device 204 may be a MEMS device and may include a substrate 30, a first dielectric layer 31, a diaphragm 206, a second dielectric layer 32, a backplate 33, a first conductive pad 35, and a second conductive pad 36. The substrate 30 may be a semiconductor substrate, such as a silicon substrate. The first dielectric layer 31 is disposed on one side of the substrate 30, the diaphragm 206 is disposed on the side of the first dielectric layer 31 away from the substrate 30, and the backplate 33 is disposed on the side of the diaphragm 206 away from the substrate 30 and spaced apart from the diaphragm 206. For example, a second dielectric layer 32 is disposed between the backplate 33 and the diaphragm 206. A cavity 205 is provided on the back side of the semiconductor device 204. For example, the cavity 205 extends from the surface of the substrate 30 away from the diaphragm 206 (i.e., the back surface) through the substrate 30 and the first dielectric layer 31 and exposes the diaphragm 206.

[0110] In some embodiments, an additional cavity 34 is provided between the back plate 33 and the diaphragm 206, and a through hole is provided on the back plate 33, the through hole being spatially connected to the additional cavity 34, so that the additional cavity 34 is connected to the external environment, that is, the air pressure of the additional cavity 34 is the same as the ambient air pressure. The cavity 205 and the additional cavity 34 located on opposite sides of the diaphragm 206 are separated by the diaphragm 206. For example, the diaphragm 206 may not have a through hole.

[0111] Both the diaphragm 206 and the backplate 33 include electrode materials, such as doped semiconductor materials.

[0112] The first conductive pad 35 is electrically connected to the diaphragm 206, and the second conductive pad 36 is electrically connected to the backplate 33. In this way, the diaphragm 206, the backplate 33, the second dielectric layer 32, and the additional cavity 34 constitute a capacitor element, wherein the diaphragm 206 and the backplate 33 serve as the electrode plates of the capacitor element, and the second dielectric layer 32 and the additional cavity 34 constitute the inter-electrode dielectric. The first conductive pad 35 and the second conductive pad 36 serve as conductive terminals of the capacitor element and can be used to detect the capacitance value of the capacitor element. The first conductive pad 35 and the second conductive pad 36 can also serve as test pads. For example, during wafer inspection, a probe can be used to contact the test pads to test the corresponding electrical performance of the capacitor element.

[0113] The capacitance of a capacitor element is directly proportional to the area of ​​the opposing electrode plates and inversely proportional to the distance between the electrode plates. For example, when the diaphragm 206 is subjected to upward or downward pressure, the diaphragm 206 will move toward or away from the back plate 33 (e.g., bend), at which time the distance between the diaphragm 206 and the back plate 33 changes, and the capacitance of the capacitor element also changes accordingly.

[0114] Combination Figure 2 and Figure 9During wafer testing, the substrate 30 of the semiconductor device 204 in the wafer contacts the test platform 100. A cavity 205 is located between the diaphragm 206 and the test platform 100. By providing a vacuum adsorption channel and an isolation venting channel within the test platform, the wafer can be stably fixed to the test platform while preventing the cavity 205 from being evacuated, and ensuring that the air pressure in the cavity 205 is approximately the same as the ambient air pressure. Similarly, the air pressure in the additional cavity 34 is also approximately the same as the ambient air pressure. Therefore, the air pressure on both sides of the diaphragm 206 is approximately the same, preventing the diaphragm 206 from shifting due to vacuum adsorption fixing of the wafer, thus ensuring the accuracy of wafer testing.

[0115] It should be understood that Figure 9 The specific structure of the semiconductor device 204 shown is merely illustrative and is not intended to limit the scope of this disclosure. For example, in some embodiments, the semiconductor device 204 may include a cavity 205 and a diaphragm 206, but may not have a backplate 33. This disclosure does not limit the specific type of semiconductor device; for example, the semiconductor device may also be other types of MEMS devices including cavities and diaphragms to improve the testing accuracy of these semiconductor devices. Of course, the wafer testing equipment and methods of this disclosure can also be applied to semiconductor devices that do not have cavities and diaphragms.

[0116] Figure 10 A schematic flowchart illustrating a wafer testing method according to some embodiments of the present disclosure is shown.

[0117] For example, refer to Figures 1 to 8 and Figure 10 In the first step S10, a wafer 200 and a wafer testing device 50 are provided. The wafer 200 has a wafer device region 201 and a wafer edge region 202. The test stage 100 of the wafer testing device 50 includes a main support portion 101 and an edge support portion 102. The edge support portion 102 of the test stage 100 includes a vacuum adsorption channel 103 and an isolation venting channel 105. The wafer testing device 50 also includes a probe assembly 150. For the specific structure of the wafer 200 and the wafer testing device 50, please refer to the above description. Figures 1 to 8 The description will not be repeated here.

[0118] In the second step S20, the wafer 200 is placed on the test tray 100 of the wafer testing equipment, wherein the wafer device region 201 is located on the main support portion 101, and the wafer edge region 202 is located on the edge support portion 102. For example, the vacuum adsorption channel 103 and the isolation venting channel 105 have openings facing the wafer edge region 202. In some embodiments, the wafer 200 and the test tray 100 have matching sizes and shapes, such that the wafer device region and the main support portion are correspondingly arranged, and the wafer edge region and the edge support portion are correspondingly arranged.

[0119] In the third step S30, the wafer 200 is adsorbed and fixed onto the test platform 100 using a vacuum adsorption method through the vacuum adsorption channel 103. The air pressure between the wafer edge region 202 and the edge support portion 102 is lower than the ambient air pressure, and the space between the wafer device region 201 and the main support portion 101 is separated from the vacuum adsorption channel 103. For example, a vacuum pump can be used to extract gas from the vacuum adsorption channel 103 and the space between the wafer edge region 202 and the edge support portion 102, making the air pressure between the wafer edge region 202 and the edge support portion 102 lower than the ambient air pressure, thereby adsorbing and fixing the wafer 200 onto the test platform 100. The isolation venting channel 105 is connected to the ambient air pressure and separates the space between the wafer device region 201 and the main support portion 101 from the vacuum adsorption channel.

[0120] In the fourth step S40, probe 125 is used to test wafer 200. The specific settings of the elastic probe holder and probe can be found in the relevant description above, and will not be repeated here.

[0121] In the aforementioned wafer testing method, by setting up an isolation venting channel to separate the space between the wafer device area and the main support from the vacuum adsorption channel, the gas between the wafer device area and the main support can be prevented from being drawn away by the vacuum pump through the vacuum adsorption channel. This ensures the structural stability of the semiconductor devices located in the wafer device area, prevents structural changes in the semiconductor devices due to vacuum adsorption, maintains the structural stability of the devices, and thus ensures the accuracy of the test. For example, in embodiments where the semiconductor devices have cavities and diaphragms, displacement of the diaphragm due to vacuum adsorption can be prevented during the test, thereby improving the accuracy of the test. Moreover, the aforementioned testing method can effectively, comprehensively, and accurately test all semiconductor devices on the wafer, ensuring that chips entering subsequent process stages (e.g., packaging and testing stages) are all qualified chips, and preventing invalid chips from entering subsequent processes and causing losses.

[0122] In some embodiments, the probe assembly incorporates an elastic design. Through the elastic probe fixing bracket and related probe structure settings, the pressure exerted on the wafer by the probe can be reduced during wafer testing, while the probe can effectively perform the test. This avoids damage to the wafer's device structure and allows for control over probe pressure, improving the stability of the test and / or enhancing the stability and / or accuracy of the test.

[0123] The following points need to be explained:

[0124] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0125] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0126] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A wafer testing method, comprising: A wafer is provided having a wafer device region and a wafer edge region, the wafer device region including semiconductor devices, and the wafer edge region surrounding the wafer device region; A wafer testing device with a test tray is provided, the test tray including a main support portion and an edge support portion, the edge support portion surrounding the main support portion and including a vacuum adsorption channel and an isolation venting channel spaced apart; The wafer is placed on the test tray of the wafer testing equipment, wherein the wafer device area is located on the main support portion; the wafer edge area is located on the edge support portion, and the vacuum adsorption channel and the isolation venting channel each have an opening facing the wafer edge area; The vacuum adsorption channel extracts gas from the vacuum adsorption channel and the space between the wafer edge area and the edge support, making the gas pressure between the wafer edge area and the edge support less than the ambient gas pressure, thereby adsorbing and fixing the wafer onto the test platform. The isolation venting channel is connected to the ambient gas pressure and separates the space between the wafer device area and the main support from the vacuum adsorption channel. as well as The wafer was tested using a probe. The wafer testing equipment includes a probe assembly, which comprises the probe and a flexible probe holder. The elastic modulus of the probe is greater than that of the flexible probe holder. The flexible probe holder includes a fixed portion and a flexible extension portion connected to each other, and the probe is fixed to the flexible extension portion. The fixed portion extends in a direction perpendicular to the main surface of the wafer. The initial angle between the flexible extension portion and the fixed portion is obtuse, and the angle between the probe and the wafer is acute. The elastic extension is elastically movable in a direction perpendicular to the main surface of the wafer. During the testing of the wafer using the probe, the probe comes into contact with the wafer. In response to the reaction force of the wafer on the probe, the elastic extension fixing the probe undergoes elastic displacement in a direction perpendicular to the main surface of the wafer. The angle between the elastic extension and the fixing part changes, and the elastic extension drives the probe to slide on the wafer in a direction parallel to the main surface of the wafer.

2. The wafer testing method according to claim 1, wherein the semiconductor device has a cavity and a diaphragm, and the cavity is located between the diaphragm and the main support portion, and the space between the wafer device region and the main support portion includes the cavity and the space at the contact interface between the wafer device region and the main support portion; During the test, the air pressure in the cavity is the same as the air pressure on the side of the diaphragm furthest from the cavity.

3. The wafer testing method according to claim 2, wherein the orthographic projection of the isolation venting channel on a reference plane parallel to the main surface of the wafer is located between the orthographic projection of the cavity on the reference plane and the orthographic projection of the vacuum adsorption channel on the reference plane.

4. The wafer testing method according to claim 2, wherein the air pressure on the side of the diaphragm away from the cavity is the ambient air pressure, and the space between the wafer device area and the main support portion is connected to the ambient air pressure through the isolation venting channel.

5. The wafer testing method according to any one of claims 1-4, wherein the test stage has a first surface and a second surface opposite each other in a direction perpendicular to the main surface of the wafer, the first surface being in contact with the wafer, and the vacuum adsorption channel comprising: The first groove is recessed from the first surface of the test platform toward the second surface; as well as The first connecting channel communicates with the first trench and is connected to the vacuum pump.

6. The wafer testing method according to claim 5, wherein the first connection channel extends from the first trench to the sidewall of the test platform.

7. The wafer testing method according to claim 5, wherein the first trench is annular, or the first trench includes a plurality of first holes.

8. The wafer testing method according to any one of claims 1-4, wherein the isolated venting channel comprises: The second trench is recessed from the first surface of the test tray that contacts the wafer toward the second surface of the test tray that is opposite to the first surface; as well as The second connection channel is connected to the second trench and the ambient air pressure.

9. The wafer testing method of claim 8, wherein the second trench is located in the upper portion of the test platform, and the second connection channel extends from the bottom of the second trench to the second surface of the test platform.

10. The wafer testing method according to claim 8, wherein the second trench is annular, or the second trench includes a plurality of second holes.

11. The wafer testing method according to any one of claims 1-4, wherein the elastic extension drives the probe to slide from a first position to a second position on the wafer, and the sliding distance between the first position and the second position is in the range of 10 micrometers to 30 micrometers.

12. A wafer testing apparatus, comprising: A test tray is configured to carry a wafer during wafer testing. The test tray includes a main support portion and an edge support portion. The edge support portion surrounds the main support portion and includes a spaced-apart vacuum adsorption channel and an isolation venting channel. The vacuum adsorption channel is configured to be connected to a vacuum pump, and the isolation venting channel is configured to be in communication with the ambient air pressure and is located on the side of the vacuum adsorption channel away from the side wall of the test tray. as well as A probe assembly includes a probe and a flexible probe holder, wherein the elastic modulus of the probe is greater than the elastic modulus of the flexible probe holder. The probe is configured to test the wafer during wafer testing. The flexible probe holder includes a fixing portion and a flexible extension connected to each other, and the probe is fixed to the flexible extension. The fixing portion extends in a direction perpendicular to the main surface of the wafer, and the initial angle between the flexible extension and the fixing portion is obtuse. The probe is configured to form an acute angle with the wafer. The elastic extension is configured to be elastically movable in a direction perpendicular to the main surface of the wafer. During the testing of the wafer using the probe, the probe assembly is configured to contact the probe with the wafer. In response to the reaction force of the wafer on the probe, the elastic extension fixing the probe undergoes elastic displacement in a direction perpendicular to the main surface of the wafer, the angle between the elastic extension and the fixing part changes, and the elastic extension drives the probe to slide on the wafer in a direction parallel to the main surface of the wafer.

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