Backside integrated voltage regulator for integrated circuits

Abstract

The invention relates to a backside integrated voltage regulator for an integrated circuit. The technology relates to an integrated circuit (IC) package. The IC package may include a package substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the package substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the package substrate via one or more through-mode vias (TMVs) or through-dielectric vias (TDVs). The IC die may be an application specific integrated circuit (ASIC) die.

Description

Description of the case This application is a divisional application of the patent application with application number 202011056882.5 submitted to the China Patent Office on September 30, 2020, and the invention name is "Back-side integrated voltage regulator for integrated circuits". Technical Field

[0001] The present disclosure relates to a backside integrated voltage regulator for an integrated circuit. Background Art

[0002] Application-specific integrated circuit (ASIC) packages that include one or more ASIC dies are becoming increasingly capable of high-speed processing. As the processing speed of the ASIC dies continues to increase, the power consumed by the ASIC dies may also increase. The increase in power consumption of the ASIC dies may result in increased heat within the ASIC package, which may cause components in the ASIC package to fail or degrade the performance of the ASIC package. Summary of the invention

[0003] One aspect of the present disclosure provides an integrated circuit (IC) package. The IC package may include a package substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the package substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the package substrate via one or more through-mold vias (TMVs) or through-dielectric vias (TDVs).

[0004] In some cases, the integrated voltage regulator die is connected to the silicon layer by a power distribution network (PDN). In some examples, the PDN includes one or more through silicon vias (TSVs) within the silicon layer. In some examples, the PDN also includes a redistribution layer configured to provide power from the integrated voltage regulator die to the TSVs. In some examples, the TSVs and the redistribution layer form an inductor.

[0005] In some cases, each of the one or more TMVs is flip-chip bump connected to the package substrate on a first end and connected to the integrated voltage regulator die at a second, opposite end.

[0006] In some cases, the silicon layer is connected to the package substrate via one or more flip chip bumps.

[0007] In some cases, the package substrate is configured to connect to a land grid array (LGA) socket or a ball grid array (BGA) socket. In some examples, power is delicered to the integrated voltage regulator die via the LGA socket or the BGA socket. In some examples, the package substrate includes a redistribution layer configured to route power from the LGA socket or the BGA socket to the one or more TMVs.

[0008] Another aspect of the technology relates to an integrated circuit (IC) package, the integrated circuit (IC) package including a package substrate, an application specific integrated circuit (ASIC) die and an integrated voltage regulator die. The ASIC die may include a metal layer and a silicon layer, the metal layer being connected to the package substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the package substrate via one or more through-mold vias (TMVs) or through-dielectric vias (TDVs), the integrated voltage regulator die being configured to provide power to the ASIC die.

[0009] In some cases, the integrated voltage regulator die is connected to the silicon layer by a power distribution network (PDN). In some examples, the PDN includes one or more through silicon vias (TSVs) within the silicon layer, and the integrated voltage regulator die is configured to provide power to the ASIC die via the TSVs. In some examples, the PDN also includes a redistribution layer configured to provide power from the integrated voltage regulator die to the TSVs. In some examples, the TSVs and the redistribution layer form an inductor.

[0010] In some cases, each of the one or more TMVs is flip-chip bump connected to the package substrate on a first end and connected to the integrated voltage regulator die at a second, opposite end.

[0011] In some cases, the silicon layer is connected to the package substrate via one or more flip chip bumps.

[0012] In some cases, the package substrate is configured to connect to a land grid array (LGA) socket or a ball grid array (BGA) socket. In some examples, power is transmitted to the integrated voltage regulator die via the LGA socket or the BGA socket. In some examples, the package substrate includes a redistribution layer configured to route power from the LGA socket or the BGA socket to the one or more TMVs.

[0013] In some cases, the IC package also includes deep trench capacitors embedded in or stacked on the silicon layer for use with the integrated voltage regulator die. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1is a side cross-sectional view of an ASIC package with an integrated voltage regulator die according to aspects of the present disclosure.

[0015] Figure 2A is a top-down view of a package substrate according to aspects of the present disclosure.

[0016] Figure 2B is a view of the bottom of a package substrate according to aspects of the present disclosure.

[0017] Figure 3A is a side cross-sectional view of an ASIC package with an integrated voltage regulator die according to aspects of the present disclosure.

[0018] Figure 3B is an exploded, side cross-sectional view of a portion of an ASIC package according to aspects of the present disclosure.

[0019] Figure 4A is a side cross-sectional view of an ASIC package showing power delivery to an integrated voltage regulator die according to aspects of the present disclosure.

[0020] Figure 4B is a side cross-sectional view of an ASIC package showing power delivery from an integrated voltage regulator die to the ASIC die according to aspects of the present disclosure.

[0021] Figure 5 is a top-down view of a package substrate with internal and external connectors according to aspects of the present disclosure.

[0022] Figure 6 is a side cross-sectional view of an ASIC package showing data communications according to aspects of the present disclosure. DETAILED DESCRIPTION

[0023] This technology generally involves integrating a voltage regulator die onto the back side of an application specific integrated circuit (ASIC) package. Figure 1 As shown in , the ASIC package 101 includes an ASIC die 103, which includes a silicon substrate 131 and one or more metal layers 133. The ASIC die 103 can be positioned so that the metal layer is adjacent to the package substrate 109. The integrated voltage regulator die 105 can be mounted to the back side of the ASIC die 103 adjacent to the silicon substrate 131. Power can be transmitted from the integrated voltage regulator die 105 to the ASIC die 103 using a backside power distribution network PDN 107, wherein the backside power distribution network PDN 107 includes through silicon vias (TSVs) 171 and redistribution layers 173. The ASIC package 201 can include a housing, such as the housing 140, in which at least some of the components of the ASIC package 101 can be located.

[0024] As previously described, increases in the processing speed of an ASIC die may increase the amount of power required to operate the ASIC die. Increases in the power consumed by the ASIC die within a typical ASIC package may result in increased heat within the ASIC package due to copper losses generated by wires and / or other such connections that carry power through the ASIC package. Copper losses (also known as “I 2 R losses, where “I” is the current flowing through the copper wiring and “R” is the resistance of the wiring) is the heat dissipated when the current passes through the wiring. The increase in temperature generated by the increased power consumption of the ASIC die may cause solder electromigration and potential failure of the solder joints. The increase in temperature may also affect the thermal performance of the ASIC die and other components within the ASIC package, which may lead to failure of the ASIC die, failure of other components of the ASIC package, or reduced processing performance.

[0025] To reduce or remedy the amount of copper losses created by wires, planes such as copper planes, redistribution layers, and / or other such connections that deliver power to the ASIC die through the ASIC package, a voltage regulator may be integrated into the ASIC package.

[0026] The package substrate 109 may be configured to connect the ASIC package 101 to a circuit board or other such chip carrier. Figure 2A and Figure 2B As shown in , the package substrate 109 can have an array of connectors on its top and bottom sides. In some cases, connectors can be included on the side of the package substrate 109. Figure 1 Although the packaging substrate 109 is shown as being outside of the housing 140 , the packaging substrate 109 may be positioned completely or partially within the housing 140 .

[0027] refer to Figure 2A , the top side 119 of the package substrate 109 shows a plurality of connectors, including connectors 191-193. For clarity, only a portion of the connectors on the top side 119 of the package substrate 109 are labeled. As described herein, the connectors, including connectors 191-193, can be connector pads to which other components of the ASIC package 101 can be connected. The connector pads can be gold, nickel, tin, copper, solder, or other such conductive materials.

[0028] The top side 119 of the package substrate 109 may include any number of connector pads arranged in any layout. Figure 2AThe arrangement and number of connectors including connector pads 191-193 shown in the figure are for illustration only. For example, the number and arrangement of connector pads on the top side of the package substrate can be based on the design and arrangement of ASIC die 103, integrated voltage regulator die 105, and / or other components within ASIC package 101 to allow the ASIC package to be attached to the top side of the package substrate 119.

[0029] Figure 2B The bottom side 129 of the package substrate is shown, which includes a plurality of connectors, including connectors 197-199. For clarity, only a portion of the connectors on the bottom side 129 are labeled. The connectors, including connectors 197-199, can be configured to connect or otherwise mount the ASIC package 101 to a printed circuit board (PCB), a socket, or other such chip carrier. The connectors can be solder balls, pins, sockets, etc. The connectors 197-199 can be gold, nickel, tin, copper, solder, or other such conductive materials.

[0030] The bottom side 129 of the package substrate may include any number of connectors in any arrangement. In this regard, Figure 2B The arrangement and number of connectors including connectors 197-199 shown in the figure are for illustration only. For example, the connectors on the bottom side 129 of the package substrate can be solder balls arranged as a ball grid array (BGA). Other such arrangements and connectors can include contacts arranged in a land grid array (LGA), connector pins arranged in a pin grid array (PGA), etc.

[0031] The integrated voltage regulator die 105 may be connected to one or more connector pads on the top side 119 of the package substrate 109. For example, Figure 3A As shown in FIG. 1 , the connection between the voltage regulator die 105 and the package substrate 109 may be achieved via one or more through-mold vias (TMVs) such as TMV 305. For clarity, only the Figure 3A A portion of the TMV is shown in FIG.

[0032] Each TMV may connect the integrated voltage regulator die 105 to the packaging substrate 109 via a connector pad or other such connector. For example, a first end 315 of the TMV 305 may be attached to the connector pad 399 and an opposite end 325 of the TMV 305 may be attached to the integrated voltage regulator die 105.

[0033] The connection between the TMV and the connector pad can be achieved via soldered flip chip bumps. For example, Figure 3BAn exploded side view of a portion 301 of an ASIC package 101 is shown, which includes a connection between a TMV 305 and a connector pad 399. A first end 315 of the TMV 305 is connected to the connector pad 399 on the top side 119 of the package substrate 109 via a soldered flip chip bump 398. Figure 3B The TMVs are shown as being connected via soldered flip chip bumps, but other connectors and connections may be used.

[0034] The metal layer 133 of the ASIC die 103 may also be connected to the package substrate 109. The connection of the metal layer 133 to the package substrate 109 may be achieved via flip chip bumps and connector pads or other such connectors. Figure 3B As further shown in FIG. 1 , flip chip bumps 396 connect metal layer 133 to connector pads 397 on top side 119 of the package substrate. Figure 3B The flip chip bumps are shown as being soldered to connector pads (such as flip chip bump 396 soldered to connector pad 397), but other connections may be used.

[0035] Power may be supplied to ASIC package 101 via an external power source. In this regard, the external power source may provide power to ASIC package 101 via a chip carrier to which ASIC package 101 is mounted. For example, and as in Figure 4A As illustrated in FIG. 4 , power, shown as arrow 490, may be supplied from an external power source (not shown) to PCB 409. PCB 409 may supply power to a connector on the package substrate.

[0036] The package substrate may include a redistribution layer etched onto or otherwise embedded within the package substrate that routes power between connectors on the bottom side 129 of the package substrate and connector pads 119 on the top side of the package substrate 109. For example, power 490 delivered by a PCB or other such chip mount at a connector 492 on the bottom side 129 of the package substrate 109 may be routed by the redistribution layer to connector pads 494 on the top side 119 of the package substrate. Although Figure 4APower 490 is illustrated as being supplied to connector 492 and routed to connector pads 494, but power may be supplied to any one of the connectors on the bottom side of package substrate 109, and in some cases, may be supplied to more than one connector. Power may be routed from the one or more connectors to one or more of the connector pads by the redistribution layer. For example, power may be routed from one or more of the connectors on bottom side 129 of package substrate 109 to one, two, three, or more connector pads on top side 119 of package substrate 109.

[0037] Power may be delivered from the package substrate 109 to the integrated voltage regulator die 105 by one or more TMVs. Figure 4A Power 490 is shown being routed from connector pads 494 to the integrated voltage regulator die 105 by TMVs 405. For clarity, power is shown as being routed only through TMVs 405. In some cases, power may be routed to the integrated voltage regulator die 105 by more than one TMV.

[0038] The power received by the integrated voltage regulator die can be considered as an input power supply. The input power supply can be transmitted to the integrated voltage regulator die 105 at a higher voltage level and a lower current level than the input power supply transmitted directly to the ASIC die. The integrated voltage regulator die 105 can provide power to the ASIC die 103 at different supply voltage levels. For example, the integrated voltage regulator die 105 can operate as a switching voltage regulator and adjust the amount of voltage supplied to the ASIC die based on the needs of the ASIC die or other components within the ASIC package 101.

[0039] The integrated voltage regulator die 105 can deliver power to the ASIC die 107 via the backside TSVs. Figure 4B As shown in FIG. 1 , power, indicated by arrow 480, may be provided from the integrated voltage regulator die 105 to the backside redistribution layer 173. The redistribution layer 173 may direct power to one or more TSVs 470, including TSV 171, embedded within the silicon layer 131 of the ASIC die 107. Although Figure 4B Power is illustrated as being delivered to all TSVs 470 , but power may be delivered to any number of TSVs.

[0040] refer to Figure 4B, the backside redistribution layer 173 can be etched into the silicon layer 131 and / or positioned above the silicon layer 131. The backside redistribution layer 173 together with the TSV can be used to create an inductor for use with the integrated voltage regulator die 105. Deep trench capacitors (DTCs) can also be embedded in the silicon layer 131 of the ASIC die 107 for use with the integrated voltage regulator die 105. In this regard, a switching voltage regulator typically requires a lot of inductors and capacitors to operate. In the case where the integrated voltage regulator die 105 is a switching voltage regulator, the backside redistribution layer 173, TSV 470, and the embedded silicon (not shown) of the DTC can provide at least some of the functions of the inductor and capacitor. In some cases, the inductor and the DTC can be stacked onto the ASIC die.

[0041] As discussed herein, increasing the processing speed of an ASIC die can increase the amount of power required to operate the ASIC die. Due to copper losses generated by wires and / or other such connections that deliver power through the ASIC package, an increase in the power consumed by an ASIC die within an ASIC package that does not have an integrated voltage regulator die may result in an increase in heat within the ASIC package. By integrating the integrated voltage regulator die in the ASIC package (such as integrating the integrated voltage regulator die 105 in the ASIC package 101), the power consumed by the ASIC package from an external power source can be limited, controlled, or otherwise regulated. For example, the integrated voltage regulator die 105 can limit (cap) the amount of power consumed by components within the ASIC package 101 (such as the ASIC die 107). In some examples, the integrated voltage regulator die 105 can include a closed-loop feedback system to provide a stable voltage output.

[0042] In another example, the integrated voltage regulator die 105 can throttle the amount of power consumed, such as when the temperature of the ASIC die 107 is above a certain value or the ASIC die 107 does not require full power to operate. The integrated voltage regulator die 105 can also accept a higher input voltage, thereby reducing the current supplied to the ASIC package 101 by the external power supply. Therefore, the amount of current carried by the wires, traces, and / or other such connections on or within the ASIC package can be reduced, thereby reducing the amount of copper loss and minimizing the risk of electromigration failures in the ASIC package. In addition, the integrated voltage regulator die 105 can reduce the overall power consumption and improve the power efficiency of the ASIC package 101.

[0043] The voltage regulator can maintain consistent power consumption from an external power source, thereby preventing or reducing the number of times that the power delivered by the wires, traces and / or other such connections on or within the ASIC package increases. In some cases, the integrated voltage regulator die 105 can include a closed-loop feedback system to minimize the voltage fluctuations of the output. In this regard, the feedback sense line can monitor the voltage output by the integrated voltage regulator die 105, and the monitored voltage level is fed back to the integrated voltage regulator die 105. The feedback sense line can have a high bandwidth, so that the integrated voltage regulator die 105 can be able to quickly compensate for voltage fluctuations. By doing so, the inductive noise caused by voltage fluctuations can be reduced.

[0044] A typical ASIC die will receive power from a connector on the package substrate that is closer to the ASIC die to reduce the heat generated by the power transmission. Therefore, it may be necessary for the data signal to traverse a longer path from the ASIC die to the connector located on the outside of the package substrate, thereby slowing down the processing speed of the ASIC package. Figure 5 Illustrated are the internal and external sets of connectors 595 and 590, respectively, on the top side 519 of the package substrate 509. In a typical ASIC package, power may be transmitted by connectors within the interior 595 of the package substrate 509, and data may be transmitted by connections within the exterior 590 of the package substrate 509.

[0045] refer to Figure 6 By positioning the integrated voltage regulator die 605 above the ASIC die 607 and connecting the integrated voltage regulator die 605 to the package substrate via TMVs 615 located around the outside of the ASIC die 607, the data connections between the ASIC die 607 and the package substrate 609 can be moved to an internal set of connectors 695. Thus, the distance required for data to travel from the ASIC die 607 to the package substrate 609 can be reduced, as indicated by arrow 696, thereby increasing communication speeds and reducing signal losses. The data connections can be routed through redistribution layers in the package substrate and can include SERDES connections, parallel connections, serial connections, etc.

[0046] Although the example ASIC packages 101 and 601 described herein are described with reference to a single ASIC die 105, 605, respectively, each ASIC package may include any number of ASIC dies. Moreover, each ASIC package may include any number of voltage regulators or other components. Additionally, although the packages described herein are described as ASIC packages having an ASIC die, any type of die may be used, such as a memory die or an integrated circuit die.

[0047] The features described herein allow an integrated voltage regulator die to be integrated into an ASIC package. By doing so, copper losses resulting from wires, traces, and / or other such connections that deliver power through the ASIC package to the ASIC die can be reduced. Furthermore, by positioning the integrated voltage regulator die above the ASIC die, the distance that data communications travel between the ASIC die and the PCB can be reduced.

[0048] Although the technology herein has been described with reference to specific embodiments, it should be understood that these embodiments are only illustrative of the principles and applications of the present technology. Therefore, it should be understood that various modifications may be made to the illustrative embodiments, and other arrangements may be devised, without departing from the spirit and scope of the present technology as defined by the appended claims.

Claims

1. An integrated circuit IC package, comprising: An IC die comprising a silicon layer; and An integrated power conditioner configured to provide power to the IC die is positioned adjacent to the silicon layer and connected to the silicon layer via an intermediate power distribution network (PDN).

2. The IC package according to claim 1, wherein: The IC package further includes a package substrate, wherein the integrated power conditioner is connected to the package substrate via one or more through-mold vias (TMVs) or one or more dielectric through-mold vias (TDVs), wherein the integrated power conditioner is configured to receive power through the one or more TMVs or TDVs.

3. The IC package according to claim 2, wherein: The PDN includes one or more through silicon vias (TSVs) within the silicon layer.

4. The IC package according to claim 3, wherein: The PDN also includes a redistribution layer configured to provide power from the integrated power conditioner to the TSV.

5. The IC package according to claim 4, wherein: The TSV and the redistribution layer form an inductor.

6. The IC package according to claim 2, wherein: Each of the TMVs or TDVs is flip-chip bump connected to the package substrate on a first end and connected to the integrated power conditioner at an opposing second end.

7. The IC package according to claim 1, wherein: The IC package also includes a packaging substrate, and wherein the silicon layer is connected to the packaging substrate via one or more flip chip bumps.

8. The IC package according to claim 1, wherein: The IC package further includes a package substrate, and wherein the package substrate is configured to be connected to a land grid array (LGA) socket or a ball grid array (BGA) socket.

9. The IC package according to claim 8, wherein: Power is transmitted to the integrated power conditioner via the LGA socket or the BGA socket.

10. The IC package according to claim 9, wherein: The integrated power conditioner is connected to the package substrate via one or more through-mold vias (TMVs), and The package substrate includes a redistribution layer configured to route power from the LGA socket or the BGA socket to the one or more TMVs.

11. The IC package according to claim 9, wherein: The IC die is an application specific integrated circuit ASIC die.

12. The IC package according to claim 1, wherein: The power conditioner is also configured to control a voltage of power delivered to the IC.

13. The IC package according to claim 1, wherein: The power conditioner is also configured to control the amperage of power delivered to the IC.

14. The IC package according to claim 13, wherein: The amperage of the power delivered to the IC is higher or lower than the amperage received by the power conditioner.

15. The IC package of claim 1, wherein: The power conditioner is also positioned beneath the IC die.

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