Low-inductance SiC half-bridge power module layout based on overlapped copper bar conduction

Abstract

The invention relates to a low-inductance SiC half-bridge power module layout structure based on overlapped copper bar conduction. Under the structure, the overlapped copper bars are used for replacing bonding wires in a traditional packaging structure, pits are machined in the copper bars to be connected with the power electrodes on the top face of the chip, the copper bars are bent to be connected with the substrate coated copper, and current conduction is achieved. Based on the overlapped copper bar structure, when the upper switch tube and the lower switch tube are switched on, mutual inductance and mutual suppression exist between current paths on the lower conductive copper bar and the upper conductive copper bar, and the module has low parasitic inductance; two ends of the upper-layer copper bar and the lower-layer copper bar are fixedly connected with the substrate, and the middle positions of the upper-layer copper bar and the lower-layer copper bar are fixedly connected with a chip top surface electrode, so that the module reliability is high; the thicknesses of the upper and lower copper bars are adjustable to ensure the through-current capability of the module; the copper bar is low in processing cost, does not need a cushion block, and reduces the number of connection interfaces. Therefore, compared with the existing layout packaging structure, the module layout structure provided by the invention has outstanding advantages in the aspects of parasitic inductance, outflow capacity and cost, and is suitable for popularization and application.

Description

Technical Field

[0001] The present invention belongs to the field of power electronic device packaging, and relates to a low inductance silicon carbide (SiC) half-bridge power module layout design based on overlapping copper busbars. Specifically, the power electrode on the top surface of the SiC power semiconductor chip is connected to the conductive copper busbar, and in the half-bridge module, the conductive copper busbars connecting the upper switch tube and the lower switch tube are partially overlapped, and the mutual inductance suppression effect of the overlapping part is utilized. Background Art

[0002] As one of the representatives of wide bandgap semiconductors, SiC devices have the characteristics of high withstand voltage, low on-resistance, and high switching frequency, and have broad prospects in the fields of electric / hybrid vehicles, new energy power generation, flexible power grids, and smart manufacturing. However, with the increase in device switching frequency, the larger parasitic inductance under the traditional packaging structure causes problems such as increased module loss and electromagnetic interference, and even causes excessive voltage overshoot, threatening the operational reliability of SiC MOSFET modules. Therefore, the low inductance layout structure design of SiC MOSFET modules has become one of the key issues in its packaging manufacturing.

[0003] At present, most SiC modules of most manufacturers such as Wolfspeed, Rohm, and Infineon still use the traditional Si device packaging method, that is, the electrodes on the bottom of the SiC power semiconductor chip are welded to the ceramic direct copper (DBC) or active metal brazing (AMB) substrate, and then the power electrodes on the top of the chip and the DBC / AMB substrate copper or terminal are connected through bonding wires. However, under the traditional layout structure based on bonding wires, the on-current flows through the bonding wires, which is difficult to form mutual inductance suppression with each other or with the substrate copper current, and the module parasitic inductance is generally large (usually 20-30nH). In response to this problem, some scholars and manufacturers use flexible printed circuit boards (PCBs) to replace bonding wires, which significantly reduces the area of ​​the commutation loop, and its parasitic inductance can be controlled at around 5nH or even lower than 5nH. However, due to the limitations of PCB technology and cost, its inner copper layer is generally thin (10-70μm), which is difficult to adapt to high current requirements. On this basis, DBC or AMB substrates are further used to replace PCBs to make double-sided packaging modules, which can significantly increase the thickness of the conductive copper layer (up to 300μm or more). However, under this structure, at least two DBC or AMB substrates are required in a single module, which is costly; and the DBC / AMB substrates are non-flexible and difficult to bend. Metal / alloy pads are generally welded or sintered between the upper substrate and the power electrode on the top surface of the chip, further increasing the process difficulty and cost; in addition, the introduction of pads increases the number of connection interfaces, which is not conducive to improving reliability.

[0004] Therefore, exploring the power module layout structure based on overlapping copper busbars for conductivity can ensure the low cost and high reliability of the module while controlling the low parasitic inductance of the module, which has important practical value and significance. Summary of the invention

[0005] Purpose of the Invention

[0006] The purpose of the present invention is to provide a low-inductance SiC half-bridge power module layout structure based on overlapping copper busbars. Specifically, the bottom electrode of the power semiconductor chip is welded to the DBC or AMB, and the power electrode on the top of the chip is connected to the conductive copper busbar; wherein, the conductive copper busbars connecting the upper and lower switch tubes are partially overlapped, and the mutual inductance suppression effect of the overlapping part is utilized to reduce the module parasitic inductance.

[0007] Technical Solution

[0008] A low-inductance SiC half-bridge power module layout structure based on overlapping copper busbar conduction comprises a DBC or AMB substrate (1), an upper conductive copper busbar (2), a planar copper busbar (3), a lower conductive copper busbar (4), an upper switch tube SiC power semiconductor chip (5), a lower switch tube SiC power semiconductor chip (6), a signal terminal (7), and a negative temperature coefficient (NTC) thermistor (8); wherein the substrate (1) comprises a lower copper layer (9), an insulating ceramic layer (10), and an upper copper layer (11); the upper copper layer (11) is etched to form a negative terminal connection area (12), an upper switch tube SiC power semiconductor chip (5) bottom electrode connection area (13), a lower conductive copper busbar (4) connection fixing area (14), an upper switch tube SiC power semiconductor chip (5) gate wiring area (15), a lower switch tube SiC power semiconductor chip (6) bottom electrode connection area (16), an upper conductive copper busbar (2) connection area (17), and a lower conductive copper busbar (2) connection area (18). The invention relates to a fixing area (17), an NTC thermistor (8) connection area (18), and a gate bonding area (19) of a lower switch tube SiC power semiconductor chip (6); a pit (20), bends (21), (22), and grooves (23), (24) are processed on the upper conductive copper busbar (2); a pit (25), bends (26), (27) are processed on the lower conductive copper busbar (4); (28) is a gate bonding wire of the upper switch tube SiC power semiconductor chip (5) and the lower switch tube SiC power semiconductor chip (6); (29) is a current when the upper switch tube is turned on, and (30) is a current when the lower switch tube is turned on.

[0009] The invention is characterized in that: the bottom surface electrode of the upper switch tube SiC power semiconductor chip (5) is connected to the area (13) in the upper copper layer (11) of the DBC or AMB substrate (1), and the lower switch tube SiC power semiconductor chip (6) is connected to the area (16) in the upper copper layer (11) of the substrate (1); the pit (20) of the upper conductive copper busbar (2) is connected to the top surface power electrode of the lower switch tube power semiconductor chip (6), the bend (21) is connected to the fixed area (17) of the upper copper layer (11) of the substrate (1), and the bend (22) is connected to the negative terminal connection area (12) of the upper copper layer (11) of the substrate (1); in addition, the upper conductive copper busbar (2) is grooved. (23) and (24), the positions of which correspond to the pit (25) and the bend (26) processed on the lower conductive copper busbar (4); the pit (25) of the lower conductive copper busbar (4) is connected to the top surface power electrode of the upper switch tube power semiconductor chip (5), the bend (26) is connected to the area (16) of the upper copper layer (11) in the substrate (1), and the bend (27) is connected to the area (14) of the upper copper layer (11) in the substrate (1); the gate of the upper switch tube SiC power semiconductor chip (5) is connected to the wire bonding area (15) through a bonding wire (28), and the gate of the lower switch tube SiC power semiconductor chip (6) is connected to the wire bonding area (19) through a bonding wire (28).

[0010] The invention is characterized in that: when the upper switch tube SiC power semiconductor chip (5) is turned on, the current (29) flows in from the plane copper bus (3) connected to the area (13) of the upper copper layer (11) in the substrate (1), flows into the lower conductive copper bus (4) through the upper switch tube SiC power semiconductor chip (5), and then flows into the area (16) of the upper copper layer (11) from the position (26), and finally flows out from the plane copper bus (3) connected to the area (16); when the lower switch tube SiC power semiconductor chip (6) is turned on, the current (30) flows in from the plane copper bus (3) connected to the area (16), flows into the upper conductive copper bus (2) through the lower switch tube SiC power semiconductor chip (6), and finally flows out from the bend (22) connected to the area (12). The planar copper busbar (3) connected to the region (13) serves as the positive terminal of the module, the bend (22) of the upper conductive copper busbar (2) connected to the region (12) serves as the negative terminal of the module, and the planar copper busbar (3) connected to the region (16) serves as an AC terminal.

[0011] The invention is characterized in that: the signal terminal (7) is connected to regions (13), (14), (15), (17), (18), and (19) of the upper copper layer (11) in the substrate (1); the NTC thermistor (8) is connected to the region (18); and the top surface power electrode of the NTC thermistor (8) is connected to the signal terminal (7).

[0012] Advantages and effects

[0013] Compared with the prior art, the advantages and positive effects of the present invention are:

[0014] First, the existing layout packaging structure based on bonding wires has a low cost, but it is difficult to utilize the mutual inductance suppression effect, and the parasitic inductance is relatively large; the structure of the present invention uses overlapping copper bars for conduction, which can significantly reduce the module parasitic inductance on the basis of a cost similar to that of the bonding wire structure. Secondly, the existing layout packaging structure based on flexible PCB can obtain a lower module parasitic inductance at a relatively low cost, but its current capacity is limited by the thickness of the copper layer constrained by the PCB process and cost; the structure of the present invention can increase the thickness of the conductive copper layer to ensure the module's outflow capacity while having a lower cost than the PCB layout and a parasitic inductance not higher than the PCB layout. Finally, the double-sided packaging structure with DBC or AMB substrates on both sides can have lower parasitic inductance while ensuring the outflow capacity, but a single module must use at least two DBC or AMB substrates, and the power electrode on the top surface of the chip and the substrate are generally welded or sintered with metal / alloy pads, which has a high overall cost and many connection interfaces, which is not conducive to improving the reliability of the module. The structure of the present invention can reduce the module cost and improve reliability while maintaining a flow capacity not lower than that of the double-sided package and a parasitic inductance not higher than that of the double-sided package.

[0015] In summary, the present invention proposes a low-inductance SiC half-bridge power module layout structure based on overlapping copper busbar conduction. From the perspective of parasitic inductance, current output capacity, and cost, compared with the existing layout packaging structure, it can ensure that at least one item is significantly better than the existing structure while other items are not weaker than the existing structure, and has outstanding advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the layout structure of a low-inductance SiC half-bridge power module based on overlapping copper busbar conduction.

[0017] Figure 2 Schematic diagram of the DBC or AMB substrate structure.

[0018] Figure 3 Schematic diagram of the upper conductive copper busbar.

[0019] Figure 4 Schematic diagram of the lower conductive copper busbar.

[0020] Figure 5 It is the gate bonding structure of the power semiconductor chip.

[0021] Figure 6 It is the current path when the upper switch tube power semiconductor chip is turned on.

[0022] Figure 7 It is the current path when the lower switch power semiconductor chip is turned on.

[0023] Figure 8 This is the parasitic inductance simulation model of the layout structure and the parasitic inductance at a frequency of 1MHz to 10MHz.

[0024] Description of reference numerals:

[0025] 1. Shell, 2. Liquid cooling radiator, 3. Radiator-substrate connection layer (can be silicone grease, adhesive or solder layer), 4. DBC substrate lower copper layer, 5. DBC substrate ceramic layer, 6. DBC substrate upper copper layer, 7. Cooling oil, 8. Chip-DBC substrate solder layer, 9. Power semiconductor chip, 10. Partition, 11. Shell opening, 12. Drainage fins.

[0026] 1. DBC or AMB substrate, 2. Upper conductive copper busbar, 3. Planar copper busbar, 4. Lower conductive copper busbar, 5. Upper switch tube SiC power semiconductor chip, 6. Lower switch tube SiC power semiconductor chip, 7. Signal terminal, 8. Negative temperature coefficient (negativetemperature coefficient, NTC) thermistor, 9. Copper layer under substrate, 10. Insulating ceramic layer of substrate, 11. Copper layer on substrate, 12. Negative terminal connection area, 13. Electrode connection area on the bottom surface of upper switch tube chip, 14. Connection and fixing area of ​​lower conductive copper bar, 15. Gate bonding area of ​​upper switch tube chip, 16. Electrode connection area on the bottom surface of lower switch tube chip, 17. Connection and fixing area of ​​upper conductive copper bar, 18. NTC thermistor connection area, 19. Gate bonding area of ​​lower switch tube chip, 20. Concave pit of upper conductive copper bar, 21. Bend of upper conductive copper bar, 22. Bend of upper conductive copper bar, 23. Groove of upper conductive copper bar, 24. Groove of upper conductive copper bar, 25. Concave pit of lower conductive copper bar, 26. Bend of lower conductive copper bar, 27. Bend of lower conductive copper bar, 28. Chip gate bonding wire, 29. Current when upper switch tube is turned on, 30. Current when lower switch tube is turned on. DETAILED DESCRIPTION

[0027] The present invention will be further described below in conjunction with the accompanying drawings:

[0028] like Figure 1 As shown, the present invention is based on a low inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction, and the main structure comprises a DBC or AMB substrate (1), an upper conductive copper busbar (2), a planar copper busbar (3), a lower conductive copper busbar (4), an upper switch tube SiC power semiconductor chip (5), a lower switch tube SiC power semiconductor chip (6), a signal terminal (7), and an NTC thermistor (8).

[0029] like Figure 2As shown, the present invention is based on a low-inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction, wherein a DBC or AMB substrate (1) comprises a lower copper layer (9), an insulating ceramic layer (10), and an upper copper layer (11); the upper copper layer (11) is etched to form a negative terminal connection area (12), an upper switch tube SiC power semiconductor chip (5) bottom electrode connection area (13), a lower conductive copper busbar (4) connection fixing area (14), an upper switch tube SiC power semiconductor chip (5) gate wiring area (15), a lower switch tube SiC power semiconductor chip (6) bottom electrode connection area (16), an upper conductive copper busbar (2) connection fixing area (17), an NTC thermistor (8) connection area (18), and a lower switch tube SiC power semiconductor chip (6) gate wiring area (19).

[0030] like Figure 3 As shown, the present invention is based on the layout structure of a low inductance SiC half-bridge power module with overlapping copper busbars for conduction. On the upper conductive copper busbar (2), pits (20), bends (21), (22), and grooves (23), (24) are processed; the thickness of the upper conductive copper busbar (2) is adjustable to ensure the current carrying capacity of the module.

[0031] like Figure 4 As shown, the present invention is based on a low inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction. On the lower conductive copper busbar (4), pits (25) and bends (26) and (27) are processed; the thickness of the lower conductive copper busbar (4) is adjustable to ensure the current carrying capacity of the module.

[0032] Combination Figure 1-4The present invention is based on a low-inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction, wherein the bottom electrode of the upper switch tube SiC power semiconductor chip (5) is connected to a region (13) in the upper copper layer (11) of a DBC or AMB substrate (1), and the lower switch tube SiC power semiconductor chip (6) is connected to a region (16) in the upper copper layer (11) of the substrate (1); the pit (20) of the upper conductive copper busbar (2) is connected to the top power electrode of the lower switch tube power semiconductor chip (6), the bend (21) is connected to a fixed region (17) of the upper copper layer (11) of the substrate (1), and the bend (22) is connected to a negative terminal connection region (12) of the upper copper layer (11) of the substrate (1); in addition, Grooves (23) and (24) are formed on the upper conductive copper busbar (2), and their positions correspond to the recesses (25) and bends (26) processed on the lower conductive copper busbar (4); the recesses (25) of the lower conductive copper busbar (4) are connected to the top surface power electrode of the upper switch tube power semiconductor chip (5), the bends (26) are connected to the region (16) of the upper copper layer (11) in the substrate (1), and the bends (27) are connected to the region (14) of the upper copper layer (11) in the substrate (1); the gate of the upper switch tube SiC power semiconductor chip (5) is connected to the wire bonding region (15) via a bonding wire (28), and the gate of the lower switch tube SiC power semiconductor chip (6) is connected to the wire bonding region (19) via a bonding wire (28).

[0033] Combination Figure 1-4 The present invention is based on a low-inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction. The left, middle and right regions of the upper conductive copper busbar (2) are all fixedly connected (respectively: the bending region (22) is fixedly connected to the region (12) of the upper copper layer (11) of the substrate (1), the pit (20) is fixedly connected to the top surface power electrode of the lower switch tube SiC power semiconductor chip (6), and the bending region (21) is fixedly connected to the region (17) of the upper copper layer (11) of the substrate (1)), and the connection reliability is high; the left, middle and right regions of the lower conductive copper busbar (4) are also fixedly connected (respectively: the bending region (27) is fixedly connected to the region (14) of the upper copper layer (11) of the substrate (1), the pit (25) is fixedly connected to the top surface power electrode of the upper switch tube SiC power semiconductor chip (5), and the bending region (26) is fixedly connected to the region (16) of the upper copper layer (11) of the substrate (1)), and the connection reliability is also high.

[0034] like Figure 1As shown, the present invention is based on a low inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction, wherein the planar copper busbar (3) connected to the region (13) serves as the module positive terminal, the bend (22) of the upper conductive copper busbar (2) connected to the region (12) serves as the module negative terminal, and the planar copper busbar (3) connected to the region (16) serves as an AC terminal; the signal terminal (7) is connected to the regions (13), (14), (15), (17), (18), and (19) of the upper copper layer (11) in the substrate (1); the NTC thermistor (8) is connected to the region (18), and the top surface power electrode of the NTC thermistor (8) is connected to the signal terminal (7).

[0035] like Figure 5 As shown, the present invention is based on a low-inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction, wherein the gate of the upper switch tube SiC power semiconductor chip (5) is connected to the wiring area (15) via a bonding wire (28), and the gate of the lower switch tube SiC power semiconductor chip (6) is connected to the wiring area (19) via a bonding wire (28).

[0036] like Figure 6 As shown, the present invention is based on a low-inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction. When the upper switch tube SiC power semiconductor chip (5) is turned on, the current (29) flows into the planar copper busbar (3) connected to the area (13) of the upper copper layer (11) in the substrate (1), flows into the lower conductive copper busbar (4) through the upper switch tube SiC power semiconductor chip (5), and then flows into the area (16) of the upper copper layer (11) from the position (26), and finally flows out from the planar copper busbar (3) connected to the area (16).

[0037] like Figure 7 As shown, the present invention is based on a low inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction. When the lower switch tube SiC power semiconductor chip (6) is turned on, the current (30) flows into the planar copper busbar (3) connected to the area (16), flows into the upper conductive copper busbar (2) through the lower switch tube SiC power semiconductor chip (6), and finally flows out from the bend (22) connected to the area (12).

[0038] Combination Figure 6-7 The present invention is based on a low-inductance SiC half-bridge power module layout structure with overlapping copper busbars for conduction. The current (29) when the upper switch tube chip (5) of the module is turned on and the current (30) when the lower switch tube SiC power semiconductor chip (6) is turned on are close in space and have opposite current directions, which plays a role in mutual inductance suppression and reduces the overall parasitic inductance of the module's commutation circuit.

[0039] like Figure 8As shown, the present invention is based on the layout structure of low inductance SiC half-bridge power module with overlapping copper busbars for conduction, and the parasitic inductance of its commutation circuit is simulated. In the main operating frequency range of SiC of 1MHz to 10MHz, its parasitic inductance is <4.15nH; the present invention is based on the layout structure of low inductance SiC half-bridge power module with overlapping copper busbars for conduction, which can achieve low parasitic inductance of the module.

Claims

1. A low inductance SiC half-bridge power module layout structure based on overlapping copper busbar conduction, the overall structure includes: DBC or AMB substrate (1), upper conductive copper busbar (2), planar copper busbar (3), lower conductive copper busbar (4), upper switch tube SiC power semiconductor chip (5), lower switch tube SiC power semiconductor chip (6), signal terminal (7), NTC thermistor (8); wherein the substrate (1) comprises a lower copper layer (9), an insulating ceramic layer (10), and an upper copper layer (11); the upper copper layer (11) comprises a negative terminal connection area (12), an upper switch tube chip bottom electrode connection area (13), a lower conductive copper busbar connection fixing area (14), An upper switch tube chip gate bonding area (15), a lower switch tube chip bottom electrode connection area (16), an upper conductive copper busbar connection fixing area (17), an NTC thermistor connection area (18), and a lower switch tube chip gate bonding area (19); the upper conductive copper busbar (2) is processed with pits (20), bends (21), (22), and grooves (23), (24); the lower conductive copper busbar (4) is processed with pits (25), bends (26), (27); and bonding wires (28) are connected between the power semiconductor chip gate and the substrate copper cladding.

2. The low inductance SiC half-bridge power module layout structure based on overlapping copper busbar conduction according to claim 1, characterized in that: The top surface power electrode of the upper switch tube power semiconductor chip (5) is connected to the pit (25) of the lower conductive copper busbar (4); the lower conductive copper busbar (4) is bent (26) and connected to the area (16) of the upper copper layer (11) in the substrate (1); and the bend (27) is connected to the area (14) of the upper copper layer (11) in the substrate (1); when the upper switch tube chip (5) is turned on, the current (29) flows in from the plane copper busbar (3) connected to the area (13) of the upper copper layer (11) in the substrate (1), flows into the lower conductive copper busbar (4) through the upper switch tube chip (5), and then flows into the area (16) of the upper copper layer (11) from the position (26), and finally flows out from the plane copper busbar (3) connected to the area (16). The top surface power electrode of the lower switch tube power semiconductor chip (6) is connected to the pit (20) of the upper conductive copper busbar (2), the upper conductive copper busbar (2) is bent (21) and connected to the fixed area (17) of the upper copper layer (11) in the substrate (1), and the upper conductive copper busbar (2) is bent (22) and connected to the negative terminal connection area (12) of the upper copper layer (11) in the substrate (1); when the lower switch tube chip (6) is turned on, the current (30) flows in from the plane copper busbar (3) connected to the area (16), flows into the upper conductive copper busbar (2) through the lower switch tube chip (6), and finally flows out from the bend (22) connected to the area (12). Since the current (29) when the upper switch tube chip (5) of the module is turned on and the current (30) when the lower switch tube SiC power semiconductor chip (6) is turned on are close in space and have opposite current directions, a mutual inductance suppression effect is achieved, thereby reducing the overall parasitic inductance of the module's commutation circuit.

3. The low inductance SiC half-bridge power module layout structure based on overlapping copper busbar conduction according to claim 1, characterized in that: The left, middle and right regions of the upper conductive copper busbar (2) are all fixedly connected (respectively: the bending region (22) is fixedly connected to the region (12) of the upper copper layer (11) of the substrate (1), the pit (20) is fixedly connected to the top surface power electrode of the lower switch tube SiC power semiconductor chip (6), and the bending region (21) is fixedly connected to the region (17) of the upper copper layer (11) of the substrate (1)), and the connection reliability is high; the left, middle and right regions of the lower conductive copper busbar (4) are also fixedly connected (respectively: the bending region (27) is fixedly connected to the region (14) of the upper copper layer (11) of the substrate (1), the pit (25) is fixedly connected to the top surface power electrode of the upper switch tube SiC power semiconductor chip (5), and the bending region (26) is fixedly connected to the region (16) of the upper copper layer (11) of the substrate (1)), and the connection reliability is also high.

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