Control circuit, switched capacitor converter, chip and electronic equipment

Abstract

The invention provides a control circuit, a switched capacitor converter, a chip and electronic equipment. The control circuit comprises a control voltage output circuit and a level conversion circuit. The control voltage output circuit can obtain the control voltage according to the reference voltage and the feedback voltage and transmit the control voltage to the level conversion circuit, so that the level conversion circuit can obtain the control voltage. Therefore, the level conversion circuit can convert the control voltage into the voltage domain where the first driving circuit is located, so that the control voltage can control the input voltage of the first driving circuit. Furthermore, the control circuit can utilize the control voltage to control the turn-on voltage of the first power tube so as to control the input current or the output current or the output voltage and change the impedance of the switched capacitor converter. Therefore, overvoltage and overcurrent or other dangerous working conditions of the switched capacitor converter in an abnormal working state can be avoided.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a control circuit, a switched capacitor converter, a chip and an electronic device. Background Art

[0002] The switched capacitor converter (also called a charge pump) can convert an input voltage into a first output voltage and a second output voltage to meet the load demand. Since the switched capacitor converter is usually used in high-power charging applications. Therefore, the switched capacitor converter often needs to limit the input current, output current, or output voltage of the switched capacitor converter, otherwise the switching power converter may have overvoltage and overcurrent problems under abnormal working conditions, or other dangerous working conditions caused by heat may occur. Summary of the invention

[0003] The present application provides a control circuit, a switched capacitor converter, a chip and an electronic device, which can control the input current, or the output current, or the output voltage to avoid the problem of overvoltage and overcurrent in the switched capacitor converter under abnormal working conditions, or other dangerous conditions.

[0004] In a first aspect, the present application provides a control circuit, the control circuit is applied to a switched capacitor converter, the switched capacitor converter comprises: a first power tube and a first drive circuit. The control circuit comprises: a control voltage output circuit and a level conversion circuit;

[0005] The first input end of the control voltage output circuit is used to access the reference voltage, the second input end of the control voltage output circuit is used to access the feedback voltage, the feedback voltage is used to characterize the conversion of the input current, or the output current, or the output voltage of the switch capacitor converter, the output end of the control voltage output circuit is electrically connected to the input end of the level conversion circuit, the output end of the level conversion circuit is electrically connected to the input end of the first drive circuit, the output end of the first drive circuit is electrically connected to the gate of the first power tube, and the ground end of the first drive circuit is electrically connected to the source of the first power tube;

[0006] The control voltage output circuit is used to obtain a control voltage according to the reference voltage and the feedback voltage, and transmit the control voltage to the level conversion circuit, wherein the control voltage is used to control the input voltage of the first driving circuit;

[0007] The level conversion circuit is used to convert the control voltage into the voltage domain where the first drive circuit is located, so that the control circuit uses the control voltage to control the start-up voltage of the first power tube to control the input current, or the output current, or the output voltage.

[0008] Through the control circuit provided by the first aspect, the control voltage output circuit can obtain the control voltage according to the reference voltage and the feedback voltage, and transmit the control voltage to the level conversion circuit, so that the level conversion circuit can obtain the control voltage. In this way, the level conversion circuit can convert the control voltage to the voltage domain where the first drive circuit is located, so that the control voltage can control the input voltage of the first drive circuit. Furthermore, the control circuit can use the control voltage to control the turn-on voltage of the first power tube to control the input current, or the output current, or the output voltage, and change the impedance of the switched capacitor converter. Thereby, it is possible to avoid overvoltage, overcurrent, or other dangerous conditions in the switched capacitor converter under abnormal working conditions.

[0009] In one possible design, the level conversion circuit includes: a current mirror, a voltage conversion current circuit, a first transistor, and a first resistor;

[0010] The input end of the voltage conversion current circuit is electrically connected to the output end of the control voltage output circuit, the output end of the voltage conversion current circuit is electrically connected to the source of the first transistor, the gate of the first transistor is used to receive a control signal, and the control signal is used to control the conduction or shutdown of the first transistor, the drain of the first transistor is electrically connected to the input end of the current mirror, the output end of the current mirror is electrically connected to the first end of the first resistor and the input end of the first drive circuit respectively, and the second end of the first resistor is electrically connected to the ground end of the first drive circuit;

[0011] The voltage-to-current conversion circuit is used to convert the control voltage into a first current, and transmit the first current to the current mirror through the first transistor;

[0012] The current mirror is used to mirror the first current to the first resistor so that the voltage across the first resistor is the control voltage, and the control voltage is within the voltage domain.

[0013] In one possible design, the voltage-to-current conversion circuit includes: a second transistor and a second resistor;

[0014] The gate of the second transistor is electrically connected to the output end of the control voltage output circuit, the drain of the second transistor is electrically connected to the source of the first transistor, the source of the second transistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is grounded.

[0015] In one possible design, the current mirror includes: a first P-type transistor and a second P-type transistor;

[0016] The source of the first P-type transistor and the source of the second P-type transistor are both used to access a first power supply voltage, the gate of the first P-type transistor, the drain of the first P-type transistor and the gate of the second P-type transistor are all electrically connected to the drain of the first transistor, and the drain of the second P-type transistor is electrically connected to the first end of the first resistor.

[0017] In one possible design, the level conversion circuit includes: a charge pump;

[0018] The input end of the charge pump is electrically connected to the output end of the control voltage output circuit, and the output end of the charge pump is electrically connected to the input end of the first drive circuit;

[0019] The charge pump is used to store the charge corresponding to the control voltage using the first capacitor in the charge pump in the first stage, and release the charge stored in the first capacitor in the second stage to convert the control voltage into the voltage domain.

[0020] In one possible design, the level conversion circuit further includes: a buffer, wherein the unit gain of the buffer is 1;

[0021] The positive phase input terminal of the buffer is electrically connected to the output terminal of the control voltage output circuit, and the negative phase input terminal of the buffer is electrically connected to the output terminal of the buffer and the input terminal of the charge pump respectively;

[0022] The buffer is used to proportionally amplify the control voltage to eliminate interference signals during the on and off process of the first switch tube in the charge pump.

[0023] In a possible design, the charge pump includes: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a first capacitor;

[0024] The first end of the first switch tube is electrically connected to the output end of the control voltage output circuit, the second end of the first switch tube is electrically connected to the first end of the third switch tube, the second end of the third switch tube is electrically connected to the input end of the first drive circuit, the first end of the second switch tube is grounded, the second end of the second switch tube is electrically connected to the first end of the fourth switch tube, the second end of the fourth switch tube is electrically connected to the ground end of the first drive circuit, the upper plate of the first capacitor is electrically connected between the second end of the first switch tube and the first end of the third switch tube, the lower plate of the first capacitor is electrically connected between the second end of the second switch tube and the first end of the fourth switch tube, and the control end of the first switch tube, the control end of the second switch tube, the control end of the third switch tube and the control end of the fourth switch tube are all used to access control signals, and the control signals are used to control the conduction or shutdown of the switch tubes.

[0025] In one possible design, the level conversion circuit includes: a voltage conversion current circuit, a current mirror, a first voltage output circuit and an error amplifier;

[0026] The first end of the voltage conversion current circuit is electrically connected to the input end of the current mirror, the input end of the first drive circuit and the output end of the error amplifier respectively, the second end of the voltage conversion current circuit is electrically connected to the ground end of the first drive circuit, the output end of the current mirror is electrically connected to the input end of the first voltage output circuit, the output end of the first voltage output circuit is electrically connected to the first input end of the error amplifier, and the second input end of the error amplifier is electrically connected to the output end of the control voltage output circuit;

[0027] The voltage-to-current conversion circuit is used to convert the input voltage of the first driving circuit into a first current and transmit the first current to the current mirror;

[0028] The current mirror is used to mirror the first current to the first voltage output circuit;

[0029] The first voltage output circuit is used to generate the first voltage according to the first current, and transmit the first voltage to the error amplifier, wherein the first voltage is used to characterize the change of the input voltage of the first driving circuit;

[0030] The error amplifier is used to keep the input voltage of the first driving circuit stable according to the control voltage and the first voltage, so that the control voltage is converted into the voltage domain.

[0031] In one possible design, the level conversion circuit further includes: a sample and hold circuit;

[0032] The input end of the sampling and holding circuit is electrically connected to the output end of the first voltage output circuit, and the output end of the sampling and holding circuit is electrically connected to the first input end of the error amplifier;

[0033] The sampling and holding circuit is used to sample and hold the first voltage when the first power tube is turned on to obtain a second voltage, and transmit the second voltage to the error amplifier so that the error amplifier keeps the input voltage of the first drive circuit stable according to the control voltage and the second voltage.

[0034] In a possible design, the sample-and-hold circuit includes: a first switch tube and a first capacitor;

[0035] The first end of the first switch tube is electrically connected to the output end of the first voltage output circuit, the control end of the first switch tube is used to access a first control signal, and the first control signal is used to control the conduction or shutdown of the first switch tube, the second end of the first switch tube is electrically connected to the first input end of the error amplifier, the upper plate of the first capacitor is electrically connected between the second end of the first switch tube and the first input end of the error amplifier, and the lower plate of the first capacitor is grounded.

[0036] In one possible design, the error amplifier includes: a first differential transconductance amplifier, a first P-type transistor, a second P-type transistor, a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0037] The source of the first P-type transistor and the source of the second P-type transistor are both used to access a first power supply voltage, the gate of the first P-type transistor, the drain of the first P-type transistor and the gate of the second P-type transistor are all electrically connected to the drain of the first transistor, the source of the first transistor is electrically connected to the drain of the third transistor, the drain of the second P-type transistor is electrically connected to the drain of the second transistor and the first end of the voltage conversion current circuit respectively, the source of the second transistor is electrically connected to the drain of the fourth transistor, the gate of the fourth transistor is electrically connected to the second output end of the first differential transconductance amplifier, the gate of the third transistor is electrically connected to the first output end of the first differential transconductance amplifier, the positive phase input end of the first differential transconductance amplifier is electrically connected to the output end of the control voltage output circuit, the negative phase input end of the first differential transconductance amplifier is electrically connected to the output end of the first voltage output circuit, the gate of the first transistor and the gate of the second transistor are both used to access a second control signal, the second control signal is used to control the conduction or disconnection of the first transistor and the second transistor, and the source of the third transistor and the source of the fourth transistor are both grounded.

[0038] In one possible design, the first voltage output circuit includes: a fifth transistor and a first resistor;

[0039] The gate of the fifth transistor is electrically connected to the first input terminal of the error amplifier, the drain of the fifth transistor and the output terminal of the current mirror respectively, the source of the fifth transistor is electrically connected to the first end of the first resistor, and the second end of the first resistor is grounded.

[0040] In one possible design, the voltage-to-current conversion circuit includes: a sixth transistor and a second resistor;

[0041] The gate of the sixth transistor is electrically connected to the input end of the first drive circuit and the output end of the error amplifier respectively, the drain of the sixth transistor is electrically connected to the input end of the current mirror, the source of the sixth transistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is electrically connected to the ground end of the first drive circuit.

[0042] In one possible design, the control voltage output circuit includes: a second differential transconductance amplifier, a current source, an N-type transistor, and a second capacitor;

[0043] The positive phase input terminal of the second differential transconductance amplifier is used to access the reference voltage, the negative phase input terminal of the second differential transconductance amplifier is used to access the feedback voltage, the output terminal of the second differential transconductance amplifier is electrically connected to the gate of the N-type transistor, the input terminal of the current source is used to access the second power supply voltage, the output terminal of the current source is electrically connected to the drain of the N-type transistor, the upper plate of the second capacitor is electrically connected between the output terminal of the current source and the drain of the N-type transistor, the upper plate of the second capacitor is also electrically connected to the input terminal of the level conversion circuit, and the lower plate of the second capacitor and the source of the N-type transistor are both grounded;

[0044] The second differential transconductance amplifier is used to control the conduction of the N-type transistor according to the reference voltage and the feedback voltage, so as to convert the voltage difference between the reference voltage and the feedback voltage into a current, so as to generate the control voltage.

[0045] In a second aspect, the present application provides a switched capacitor converter, the switched capacitor converter comprising: a first power tube, a plurality of second power tubes, a first drive circuit, a plurality of second drive circuits, a plurality of flying capacitors, and the control circuit in the first aspect and each possible design of the first aspect;

[0046] The first driving circuit is used to drive the first power tube to switch between on and off;

[0047] The second driving circuit is used to drive the second power tube to switch between on and off;

[0048] The first power tube and the plurality of second power tubes are used to control the plurality of flying capacitors to switch between charging and discharging when switching between on and off, so as to convert the input voltage of the switched capacitor converter into a plurality of output voltages;

[0049] The control circuit is used to control the turn-on voltage of the first power tube to control the input current, output current, or output voltage of the switch capacitor converter.

[0050] The beneficial effects of the switched capacitor converter provided in the second aspect and each possible design of the second aspect can be referred to the beneficial effects brought about by the first aspect and each possible implementation method of the first aspect, which will not be repeated here.

[0051] In a third aspect, the present application provides a chip, comprising: the control circuit in the above-mentioned first aspect and each possible design of the above-mentioned first aspect, and / or the switched capacitor converter in the above-mentioned first aspect.

[0052] In a fourth aspect, the present application provides an electronic device, comprising: the chip in the third aspect above.

[0053] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0055] Figure 1 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0056] Figure 2 A schematic diagram of the structure of another control circuit provided in an embodiment of the present application;

[0057] Figure 3 A schematic diagram of the structure of another control circuit provided in an embodiment of the present application;

[0058] Figure 4A schematic diagram of the structure of another control circuit provided in an embodiment of the present application;

[0059] Figure 5 for Figure 1-Figure 4 A schematic diagram of the relationship between the gate voltage of the first power tube and the input voltage of the first driving circuit;

[0060] Figure 6 A schematic diagram of the structure of a switched capacitor converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0062] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0063] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0064] Reference Figure 1 , Figure 1This is a schematic diagram of a control circuit provided in an embodiment of the present application. Figure 1 As shown, the control circuit 100 may include: a control voltage output circuit 110 and a level conversion circuit 120 .

[0065] The first input terminal of the control voltage output circuit 110 is used to access the reference voltage VREF, the second input terminal of the control voltage output circuit 110 is used to access the feedback voltage VFB, the feedback voltage VFB is used to characterize the conversion of the input current, or the output current, or the output voltage of the switched capacitor converter 1000, the output terminal of the control voltage output circuit 110 is electrically connected to the input terminal of the level conversion circuit 120, the output terminal of the level conversion circuit 120 is electrically connected to the input terminal of the first drive circuit 200, the output terminal of the first drive circuit 200 is electrically connected to the gate of the first power tube Q1, and the ground terminal of the first drive circuit 200 is electrically connected to the source of the first power tube Q1.

[0066] The control voltage output circuit 110 and the level conversion circuit 120 may be provided separately or integrated, and this is not specifically limited in the embodiment of the present application.

[0067] The feedback voltage VFB is obtained by detecting the input current, output current, or output voltage of the switched capacitor converter 1000 through a corresponding detection circuit.

[0068] The control circuit 100 is a circuit that realizes a current stabilization function for the input current or output current of the switched capacitor converter 1000 and a voltage stabilization function for the output voltage of the switched capacitor converter 1000, that is, a Regulation control circuit.

[0069] The control voltage output circuit 110 can obtain the control voltage VCOMP according to the reference voltage VREF and the feedback voltage VFB. In addition, the control voltage output circuit 110 can transmit the control voltage VCOMP to the level conversion circuit 120 so that the level conversion circuit 120 can obtain the control voltage VCOMP.

[0070] The control voltage VCOMP is used to control the input voltage VC of the first driving circuit 200, that is, the control voltage VCOMP is used to control the voltage difference VC-HVSS between the input voltage VC of the first driving circuit 200 and the voltage HVSS of the ground terminal of the first driving circuit 200. The voltage at the input terminal of the first driving circuit 200 is the input voltage VC of the first driving circuit 200.

[0071] Thus, the level conversion circuit 120 can convert the control voltage VCOMP to the voltage domain of the first driving circuit 200 so that the voltage difference VC-HVSS between the input voltage VC of the first driving circuit 200 and the voltage HVSS at the ground terminal of the first driving circuit 200 is equal to the control voltage VCOMP.

[0072] Since the maximum gate voltage that the first power tube Q1 can reach when turned on is the input voltage VC of the first driving circuit 200, and the source voltage of the first power tube Q1 is equal to the voltage HVSS of the ground terminal of the first driving circuit 200, the control circuit 100 can control the voltage difference VC-HVSS between the input voltage VC of the first driving circuit 200 and the voltage HVSS of the ground terminal of the first driving circuit 200 by using the control voltage VCOMP.

[0073] Furthermore, the control circuit 100 can use the control voltage VCOMP to control the turn-on voltage of the first power tube Q1 to control the input current, or the output current, or the output voltage, so that the impedance of the switched capacitor converter 1000 changes, and a closed-loop negative feedback is realized. Thus, the switched capacitor converter 1000 can be prevented from having overvoltage and overcurrent problems or other dangerous working conditions in an abnormal working state.

[0074] When the feedback voltage VFB represents the transformation of the input current of the switched capacitor converter 1000, the control circuit 100 can use the control voltage VCOMP to control the input current of the switched capacitor converter 1000. When the feedback voltage VFB represents the transformation of the output current of the switched capacitor converter 1000, the control circuit 100 can use the control voltage VCOMP to control the output current of the switched capacitor converter 1000. When the feedback voltage VFB represents the transformation of the output voltage of the switched capacitor converter 1000, the control circuit 100 can use the control voltage VCOMP to control the output voltage of the switched capacitor converter 1000.

[0075] The control circuit, switch capacitor converter, chip and electronic device provided by the present application, the control voltage output circuit can obtain the control voltage according to the reference voltage and the feedback voltage, and transmit the control voltage to the level conversion circuit, so that the level conversion circuit can obtain the control voltage. In this way, the level conversion circuit can convert the control voltage to the voltage domain where the first drive circuit is located, so that the control voltage can control the voltage difference between the input voltage of the first drive circuit and the voltage of the ground terminal of the first drive circuit. Furthermore, the control circuit can use the control voltage to control the turn-on voltage of the first power tube to control the input current, or the output current, or the output voltage, and change the impedance of the switch capacitor converter. Thereby, it is possible to avoid overvoltage and overcurrent, or other dangerous conditions in the switch capacitor converter under abnormal working conditions.

[0076] Based on the description of the above embodiments, the level conversion circuit 120 can be implemented in a variety of feasible ways.

[0077] As a feasible implementation of the level conversion circuit 120, refer to Figure 2 , Figure 2 This is a schematic diagram of another control circuit provided in an embodiment of the present application. Figure 2 As shown, the level conversion circuit 120 may include: a current mirror 121, a voltage conversion current circuit 122, a first transistor ML1 and a first resistor R1.

[0078] The input end of the voltage conversion current circuit 122 is electrically connected to the output end of the control voltage output circuit 110, the output end of the voltage conversion current circuit 122 is electrically connected to the source of the first transistor ML1, the gate of the first transistor ML1 is used to access the control signal, the control signal is used to control the conduction or shutdown of the first transistor ML1, the drain of the first transistor ML1 is electrically connected to the input end of the current mirror 121, the output end of the current mirror 121 is electrically connected to the first end of the first resistor R1 and the input end of the first drive circuit 200 respectively, and the second end of the first resistor R1 is electrically connected to the ground end of the first drive circuit 200.

[0079] The input end of the voltage-to-current conversion circuit 122 is the input end of the level conversion circuit 120 , and the first end of the first resistor R1 is the output end of the level conversion circuit 120 .

[0080] The first transistor ML1 is a high voltage transistor, which is used to withstand a high voltage, ie, a first power supply voltage HVDD.

[0081] The voltage-to-current conversion circuit 122 may convert the control voltage VCOMP into a first current I1 . Furthermore, the voltage-to-current conversion circuit 122 may transmit the first current I1 to the current mirror 121 through the first transistor ML1 , so that the current mirror 121 may obtain the first current I1 .

[0082] In this way, the current mirror 121 can mirror the first current I1 to the first resistor R1, so that the first current I1 passes through the first resistor R1. Furthermore, the voltage at the first end of the first resistor R1 is the input voltage VC of the first drive circuit 200, so that the voltage across the first resistor R1 is the control voltage VCOMP, so that the control voltage VCOMP is in the voltage domain. Therefore, the level conversion circuit 120 can convert the control voltage VCOMP to the voltage domain where the first drive circuit 200 is located, thereby realizing the shift of the analog voltage.

[0083] In summary, the voltage conversion current circuit can convert the control voltage into a first current, and transmit the first current to the current mirror through the first transistor, so that the current mirror can obtain the first current. In this way, the current mirror can mirror the first current to the first resistor, so that the voltage across the first resistor is the control voltage, so that the control voltage is within the voltage domain. Thus, the level conversion circuit can convert the control voltage into the voltage domain.

[0084] Based on the description of the above embodiment, a possible implementation of the voltage conversion current circuit 122 is exemplified. Figure 2 As shown, the voltage conversion current circuit 122 may include: a second transistor MN1 and a second resistor R2.

[0085] The gate of the second transistor MN1 is electrically connected to the output end of the control voltage output circuit 110, the drain of the second transistor MN1 is electrically connected to the source of the first transistor ML1, the source of the second transistor MN1 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0086] The gate of the second transistor MN1 is the input terminal of the voltage-to-current conversion circuit 122 , and the drain of the second transistor MN1 is the output terminal of the voltage-to-current conversion circuit 122 .

[0087] Exemplarily, the second transistor MN1 is a depletion-type Native transistor.

[0088] The first current I1 can be expressed by formula (1):

[0089] I1=VCOMP / r2 (1)

[0090] Wherein, I1 is the first current, VCOMP is the control voltage, and r2 is the resistance value of the second resistor R2.

[0091] Since the resistance of the first resistor R1 is equal to the resistance of the second resistor R2, the voltage across the first resistor R1 is the control voltage VCOMP.

[0092] Based on the description of the above embodiment, a possible implementation of the current mirror 121 is exemplified. Figure 2 As shown, the current mirror 121 may include: a first P-type transistor MP1 and a second P-type transistor MP2.

[0093] The source of the first P-type transistor MP1 and the source of the second P-type transistor MP2 are both used to access the first power supply voltage HVDD, the gate of the first P-type transistor MP1, the drain of the first P-type transistor MP1 and the gate of the second P-type transistor MP2 are all electrically connected to the drain of the first transistor ML1, and the drain of the second P-type transistor MP2 is electrically connected to the first end of the first resistor R1.

[0094] The drain of the first P-type transistor MP1 is the input terminal of the current mirror 121 , and the drain of the second P-type transistor MP2 is the output terminal of the current mirror 121 .

[0095] As another feasible implementation of the level conversion circuit 120, refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of another control circuit provided in an embodiment of the present application. Figure 3 As shown, the level conversion circuit 120 may include: a charge pump 121 .

[0096] An input terminal of the charge pump 121 is electrically connected to an output terminal of the control voltage output circuit 110 , and an output terminal of the charge pump 121 is electrically connected to an input terminal of the first driving circuit 200 .

[0097] The input end of the charge pump 121 is the input end of the level conversion circuit 120 , and the output end of the charge pump 121 is the output end of the level conversion circuit 120 .

[0098] In the first stage, the charge pump 121 can use the first capacitor Cpump in the charge pump 121 to store charges, so that the voltage on the first capacitor Cpump is the control voltage. And, in the second stage, the charge pump 121 can release the charges stored in the first capacitor Cpump, so that the charges stored in the capacitor Cpump can be transferred between the input voltage VC of the first drive circuit 200 and the voltage HVSS of the ground terminal of the first drive circuit 200. Furthermore, the charge pump 121 can convert the control voltage VCOMP into the voltage domain. Thus, the level conversion circuit 120 can convert the control voltage VCOMP into the voltage domain.

[0099] In summary, the charge pump can use the first capacitor in the charge pump to store the charge corresponding to the control voltage in the first stage, and release the charge stored in the first capacitor in the second stage to convert the control voltage into the voltage domain. Thus, the level conversion circuit can convert the control voltage into the voltage domain.

[0100] Based on the description of the above embodiment, a possible implementation of the charge pump 121 is exemplified. Figure 3As shown, the charge pump 121 may include: a first switch tube SW1, a second switch tube SW2, a third switch tube SW3, a fourth switch tube SW4 and a first capacitor Cpump.

[0101] The first end of the first switch tube SW1 is electrically connected to the output end of the control voltage output circuit 110, the second end of the first switch tube SW1 is electrically connected to the first end of the third switch tube SW3, the second end of the third switch tube SW3 is electrically connected to the input end of the first drive circuit 200, the first end of the second switch tube SW2 is grounded, the second end of the second switch tube SW2 is electrically connected to the first end of the fourth switch tube SW4, the second end of the fourth switch tube SW4 is electrically connected to the ground end of the first drive circuit 200, the upper plate of the first capacitor Cpump is electrically connected between the second end of the first switch tube SW1 and the first end of the third switch tube SW3, the lower plate of the first capacitor Cpump is electrically connected between the second end of the second switch tube SW2 and the first end of the fourth switch tube SW4, and the control end of the first switch tube SW1, the control end of the second switch tube SW2, the control end of the third switch tube SW3 and the control end of the fourth switch tube SW4 are all used to access the control signal, and the control signal is used to control the conduction or shutdown of the switch tube.

[0102] The first end of the first switch tube SW1 is the input end of the charge pump 121 , and the second end of the third switch tube SW3 is the output end of the charge pump 121 .

[0103] The first switch transistor SW1 , the second switch transistor SW2 , the third switch transistor SW3 and the fourth switch transistor SW4 may include but are not limited to gallium nitride transistors, insulated gate bipolar transistors and metal-oxide semiconductor field effect transistors.

[0104] For example, when the first switch tube SW1, the second switch tube SW2, the third switch tube SW3 and the fourth switch tube SW4 are gallium nitride transistors, the control end of the first switch tube SW1, the control end of the second switch tube SW2, the control end of the third switch tube SW3 and the control end of the fourth switch tube SW4 refer to the gate of the gallium nitride transistor, the first end of the first switch tube SW1, the first end of the second switch tube SW2, the first end of the third switch tube SW3 and the first end of the fourth switch tube SW4 can be the drain or source of the gallium nitride transistor, and correspondingly, the second end of the first switch tube SW1, the second end of the second switch tube SW2, the second end of the third switch tube SW3 and the second end of the fourth switch tube SW4 can be the source or drain of the gallium nitride transistor.

[0105] For example, when the first switch tube SW1, the second switch tube SW2, the third switch tube SW3 and the fourth switch tube SW4 are metal-oxide semiconductor field effect transistors, the control end of the first switch tube SW1, the control end of the second switch tube SW2, the control end of the third switch tube SW3 and the control end of the fourth switch tube SW4 refer to the gate of the metal-oxide semiconductor field effect transistor, and the first end of the first switch tube SW1, the first end of the second switch tube SW2, the first end of the third switch tube SW3 and the first end of the fourth switch tube SW4 can be the drain or source of the metal-oxide semiconductor field effect transistor, and correspondingly, the second end of the first switch tube SW1, the second end of the second switch tube SW2, the second end of the third switch tube SW3 and the second end of the fourth switch tube SW4 can be the source or drain of the metal-oxide semiconductor field effect transistor.

[0106] For example, when the first switch tube SW1, the second switch tube SW2, the third switch tube SW3 and the fourth switch tube SW4 are field-controlled thyristors, the control end of the first switch tube SW1, the control end of the second switch tube SW2, the control end of the third switch tube SW3 and the control end of the fourth switch tube SW4 refer to the gate of the field-controlled thyristor, and the first end of the first switch tube SW1, the first end of the second switch tube SW2, the first end of the third switch tube SW3 and the first end of the fourth switch tube SW4 can be the drain or source of the field-controlled thyristor, and correspondingly, the second end of the first switch tube SW1, the second end of the second switch tube SW2, the second end of the third switch tube SW3 and the second end of the fourth switch tube SW4 can be the source or drain of the field-controlled thyristor.

[0107] In the first stage, the first switch tube SW1 and the second switch tube SW2 are turned on, and the third switch tube SW3 and the fourth switch tube SW4 are turned off. At this time, the first capacitor Cpump can store charge, so that the voltage on the first capacitor Cpump is equal to the control voltage VCOMP. In the second stage, the first switch tube SW1 and the second switch tube SW2 are turned off, and the third switch tube SW3 and the fourth switch tube SW4 are turned on. At this time, the first capacitor Cpump can release the charge, so that the charge stored in the capacitor Cpump can be transferred between the input voltage VC of the first drive circuit 200 and the voltage HVSS of the ground terminal of the first drive circuit 200.

[0108] Based on the description of the above embodiment, a possible implementation of the level conversion circuit 120 is exemplified. Figure 3 As shown, the level conversion circuit 120 may further include a buffer 122 .

[0109] The unity gain of the buffer 122 is 1.

[0110] The positive phase input terminal of the buffer 122 is electrically connected to the output terminal of the control voltage output circuit 110 , and the negative phase input terminal of the buffer 122 is electrically connected to the output terminal of the buffer 122 and the input terminal of the charge pump 121 , respectively.

[0111] The non-inverting input terminal of the buffer 122 is the input terminal of the level conversion circuit 120 , and the output terminal of the charge pump 121 is the output terminal of the level conversion circuit 120 .

[0112] The buffer 122 can amplify the control voltage VCOMP in equal proportion to obtain the amplified control voltage Vcomp_b. Since the unit gain of the buffer 122 is 1, the amplitude of the amplified control voltage Vcomp_b is equal to the amplitude of the control voltage VCOMP. In this way, the interference signal of the first switch tube SW1 in the charge pump 121 during the on and off process can be eliminated to eliminate interference such as clock feedthrough effect, thereby improving the control accuracy of the control circuit 100.

[0113] As another feasible implementation of the level conversion circuit 120, refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of another control circuit provided in an embodiment of the present application. Figure 4 As shown, the level conversion circuit 120 may include: a voltage conversion current circuit 121 , a current mirror 122 , a first voltage output circuit 123 and an error amplifier 124 .

[0114] The implementation of the level conversion circuit 120 is based on negative feedback.

[0115] The first end of the voltage conversion current circuit 121 is electrically connected to the input end of the current mirror 122, the input end of the first drive circuit 200 and the output end of the error amplifier 124, respectively; the second end of the voltage conversion current circuit 121 is electrically connected to the ground end of the first drive circuit 200; the output end of the current mirror 122 is electrically connected to the input end of the first voltage output circuit 123; the output end of the first voltage output circuit 123 is electrically connected to the first input end of the error amplifier 124; and the second input end of the error amplifier 124 is electrically connected to the output end of the control voltage output circuit 110.

[0116] The second input terminal of the error amplifier 124 is the input terminal of the level conversion circuit 120 , and the first terminal of the voltage conversion current circuit 121 is the output terminal of the level conversion circuit 120 .

[0117] The voltage-to-current conversion circuit 121 can convert the input voltage VC of the first driving circuit 200 into the first current I1. Furthermore, the voltage-to-current conversion circuit 121 can transmit the first current I1 to the current mirror 122, so that the current mirror 122 can obtain the first current I1.

[0118] In this way, the current mirror 122 can mirror the first current I1 to the first voltage output circuit 123. In this way, the first voltage output circuit 123 can generate the first voltage V1 according to the first current I1. In addition, the first voltage output circuit 123 can transmit the first voltage V1 to the error amplifier 124, so that the error amplifier 124 can obtain the first voltage V1.

[0119] The first voltage V1 is used to represent the change of the input voltage VC of the first driving circuit 200 .

[0120] Furthermore, the error amplifier 124 can keep the voltage difference VC-HVSS stable according to the control voltage VCOMP and the first voltage V1, so that the voltage difference VC-HVSS is equal to the control voltage VCOMP. Thus, the level conversion circuit 120 can convert the control voltage VCOMP into the voltage domain to achieve analog voltage shifting.

[0121] In summary, the voltage-to-current circuit can convert the input voltage of the first drive circuit into a first current, and transmit the first current to the current mirror so that the current mirror can obtain the first current. In this way, the current mirror can mirror the first current to the first voltage output circuit. In this way, the first voltage output circuit can generate a first voltage for characterizing the change of the input voltage of the first drive circuit according to the first current, and transmit the first voltage to the error amplifier so that the error amplifier can obtain the first voltage. Furthermore, the error amplifier can keep the voltage difference stable according to the control voltage and the first voltage so that the control voltage is converted into the voltage domain.

[0122] Based on the description of the above embodiment, a possible implementation of the error amplifier 124 is exemplified. Figure 4 As shown, the error amplifier 124 may include: a first differential transconductance amplifier Gm1 , a first P-type transistor MP1 , a second P-type transistor MP2 , a first transistor ML1 , a second transistor ML2 , a third transistor MN1 , and a fourth transistor MN2 .

[0123] The source of the first P-type transistor MP1 and the source of the second P-type transistor MP2 are both used to access the first power supply voltage, the gate of the first P-type transistor MP1, the drain of the first P-type transistor MP1 and the gate of the second P-type transistor MP2 are all electrically connected to the drain of the first transistor ML1, the source of the first transistor ML1 is electrically connected to the drain of the third transistor MN1, the drain of the second P-type transistor MP2 is electrically connected to the drain of the second transistor ML2 and the first end of the voltage conversion current circuit 121, the source of the second transistor ML2 is electrically connected to the drain of the fourth transistor MN2, and the gate of the fourth transistor MN2 is electrically connected to the first differential transconductance amplifier The second output terminal of Gm1 is electrically connected, the gate of the third transistor MN1 is electrically connected to the first output terminal of the first differential transconductance amplifier Gm1, the positive phase input terminal of the first differential transconductance amplifier Gm1 is electrically connected to the output terminal of the control voltage output circuit 110, the negative phase input terminal of the first differential transconductance amplifier Gm1 is electrically connected to the output terminal of the first voltage output circuit 123, the gate of the first transistor ML1 and the gate of the second transistor ML2 are both used to access the second control signal, the second control signal is used to control the conduction or shutoff of the first transistor ML1 and the second transistor ML2, and the source of the third transistor MN1 and the source of the fourth transistor MN2 are both grounded.

[0124] The positive input terminal of the first differential transconductance amplifier Gm1 is the second input terminal of the error amplifier 124 , the negative input terminal of the first differential transconductance amplifier Gm1 is the first input terminal of the error amplifier 124 , and the drain of the second P-type transistor MP2 is the output terminal of the error amplifier 124 .

[0125] The first transistor ML1 and the second transistor ML2 are high voltage transistors and are used to withstand a high voltage, namely, a first power supply voltage HVDD.

[0126] Based on the description of the above embodiment, a possible implementation of the first voltage output circuit 123 is exemplified. Figure 4 As shown, the first voltage output circuit 123 may include: a fifth transistor MN3 and a first resistor R1.

[0127] The gate of the fifth transistor MN3 is electrically connected to the first input terminal of the error amplifier 124, the drain of the fifth transistor MN3 and the output terminal of the current mirror 122 respectively, the source of the fifth transistor MN3 is electrically connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded.

[0128] The drain of the fifth transistor MN3 is the input terminal of the first voltage output circuit 123 , and the gate of the fifth transistor MN3 is the output terminal of the first voltage output circuit 123 .

[0129] After the first current I1 passes through the fifth transistor MN3 and the first resistor R1, a first voltage V1 can be generated. The first voltage V1 can be expressed by formula (2):

[0130] V1=I1*r1+Vth1 (2)

[0131] Wherein, V1 is the first voltage, I1 is the first current, r1 is the resistance of the first resistor R1, and Vth1 is the threshold voltage of the fifth transistor MN3.

[0132] Based on the description of the above embodiment, a possible implementation of the voltage conversion current circuit 121 is exemplified. Figure 4 As shown, the voltage conversion current circuit 121 may include: a sixth transistor MN4 and a second resistor R2.

[0133] The gate of the sixth transistor MN4 is electrically connected to the input terminal of the first drive circuit 200 and the output terminal of the error amplifier 124 respectively, the drain of the sixth transistor MN4 is electrically connected to the input terminal of the current mirror 122, the source of the sixth transistor MN4 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is electrically connected to the ground terminal of the first drive circuit 200.

[0134] The gate of the sixth transistor MN4 is the first end of the voltage conversion current circuit 121 , and the second end of the second resistor R2 is the second end of the voltage conversion current circuit 121 .

[0135] The input voltage VC of the first driving circuit 200 can be converted into a first current I1 through the sixth transistor MN4 and the second resistor R2. The first current I1 can be expressed by formula (3):

[0136] I1=(VC-Vth2) / r2 (3)

[0137] Wherein, I1 is the first current, VC is the input voltage of the first driving circuit 200, Vth2 is the threshold voltage of the sixth transistor MN4, and r2 is the resistance value of the second resistor R2.

[0138] Since the resistance of the first resistor R1 is equal to the resistance of the second resistor R2 , the first voltage V1 is equal to the input voltage VC of the first driving circuit 200 .

[0139] Based on the description of the above embodiment, another possible implementation of the level conversion circuit 120 is exemplified. Figure 4 As shown, the level conversion circuit 120 may further include: a sample and hold circuit 125 .

[0140] An input terminal of the sample and hold circuit 125 is electrically connected to an output terminal of the first voltage output circuit 123 , and an output terminal of the sample and hold circuit 125 is electrically connected to a first input terminal of the error amplifier 124 .

[0141] The sampling and holding circuit 125 can sample and hold the first voltage V1 when the first power tube Q1 is turned on to obtain the second voltage V2. In addition, the sampling and holding circuit 125 can transmit the second voltage V2 to the error amplifier 124, so that the error amplifier 124 can obtain the second voltage V2. In this way, the error amplifier 124 can keep the voltage difference VC-HVSS stable according to the control voltage VCOMP and the second voltage V2, thereby improving the stability of the error amplifier 124. Thus, the control accuracy of the control circuit 100 on the turn-on voltage of the first power tube Q1 is improved.

[0142] Based on the description of the above embodiment, a possible implementation of the sample and hold circuit 125 is exemplified. Figure 4 As shown, the sample-and-hold circuit 125 may include: a first switch tube S1 and a first capacitor C1.

[0143] The first end of the first switch tube S1 is electrically connected to the output end of the first voltage output circuit 123, the control end of the first switch tube S1 is used to access the first control signal, and the first control signal is used to control the conduction or shutdown of the first switch tube S1, the second end of the first switch tube S1 is electrically connected to the first input end of the error amplifier 124, the upper plate of the first capacitor C1 is electrically connected between the second end of the first switch tube S1 and the first input end of the error amplifier 124, and the lower plate of the first capacitor C1 is grounded.

[0144] The first end of the first switch tube S1 is the input end of the sample and hold circuit 125 , and the upper plate of the first capacitor C1 is the output end of the sample and hold circuit 125 .

[0145] Based on the description of the above embodiment, a possible implementation of the control voltage output circuit 110 is exemplified. Figure 1-3 As shown, the control voltage output circuit 110 may include: a second differential transconductance amplifier Gm2, a current source 111, an N-type transistor N1 and a second capacitor Cp.

[0146] The positive input terminal of the second differential transconductance amplifier Gm2 is used to access the reference voltage VREF, the negative input terminal of the second differential transconductance amplifier Gm2 is used to access the feedback voltage VFB, the output terminal of the second differential transconductance amplifier Gm2 is electrically connected to the gate of the N-type transistor N1, the input terminal of the current source 111 is used to access the second power supply voltage VDD, the output terminal of the current source 111 is electrically connected to the drain of the N-type transistor N1, the upper plate of the second capacitor Cp is electrically connected between the output terminal of the current source 111 and the drain of the N-type transistor N1, the upper plate of the second capacitor Cp is also electrically connected to the input terminal of the level conversion circuit 120, and the lower plate of the second capacitor Cp and the source of the N-type transistor N1 are both grounded.

[0147] Among them, the positive phase input terminal of the second differential transconductance amplifier Gm2 is the first input terminal of the control voltage output circuit 110, the negative phase input terminal of the second differential transconductance amplifier Gm2 is the second input terminal of the control voltage output circuit 110, and the upper plate of the second capacitor Cp is the output terminal of the control voltage output circuit 110.

[0148] The second differential transconductance amplifier Gm2 can amplify the voltage difference between the reference voltage VREF and the feedback voltage VFB and control the N-type transistor N1 to be turned on. In this way, the voltage difference between the reference voltage VREF and the feedback voltage VFB is converted into a current and compared with the reference current output by the current source 111 to generate a control voltage VCOMP.

[0149] Based on the description of the above embodiment, a possible implementation of the first driving circuit 200 is exemplified. Figure 1-4 As shown, the first driving circuit 200 may include: a transistor MPB, a transistor MNA, a transistor MNB and a capacitor C1.

[0150] The source of transistor MPB is used to access the first power supply voltage HVDD, the drain of transistor MPB is electrically connected to the drain of transistor MNA, the gate of transistor MNA is electrically connected to the output end of the level conversion circuit 120, the source of transistor MNA is electrically connected to the drain of transistor MNB, the upper plate of capacitor C1 is electrically connected between the gate of transistor MNA and the output end of the level conversion circuit 120, and the lower plate of capacitor C1 and the source of transistor MNB are both electrically connected to the source of the first power tube Q1.

[0151] Combine the following Figure 5 , Figure 5 for Figure 1-Figure 4 Detailed description of the relationship between the gate voltage VGATE of the first power tube Q1 and the input voltage VC of the first drive circuit 200. The content is as follows:

[0152] like Figure 5 As shown, when the first power tube Q1 is turned on, the transistor MPB is turned on and the transistor MNB is turned off, so that the gate voltage VGATE of the first power tube Q1 increases, and the maximum voltage that the gate voltage VGATE of the first power tube Q1 can reach is the input voltage VC of the first driving circuit 200.

[0153] When the first power tube Q1 is turned off, the transistor MPB is turned off and the transistor MNB is turned on, so that the gate voltage VGATE of the first power tube Q1 is reduced and pulled down to the voltage HVSS of the ground terminal of the first driving circuit 200 .

[0154] The present application also provides a switched capacitor converter 1000. Figure 6 , Figure 6 Schematic diagram of a switched capacitor converter provided in an embodiment of the present application. Figure 6 As shown, the switched capacitor converter 1000 may include: a first power tube Q1 , a plurality of second power tubes, a first drive circuit 200 , a plurality of second drive circuits, a plurality of flying capacitors CF and a control circuit 100 .

[0155] The first driving circuit 200 can drive the first power tube Q1 to switch between on and off.

[0156] The second driving circuit can drive the second power tube to switch between on and off.

[0157] When the first power tube Q1 and the plurality of second power tubes are switched between on and off, the plurality of flying capacitors CF can be controlled to switch between charging and discharging, so as to convert the input voltage of the switched capacitor converter 1000 into a plurality of output voltages.

[0158] The control circuit 100 can control the turn-on voltage of the first power tube Q1 to control the input current, output current, or output voltage of the switched capacitor converter 1000 .

[0159] The plurality of flying capacitors CF may include: a flying capacitor CF1A, a flying capacitor CF1B, a flying capacitor CF2A and a flying capacitor CF2B.

[0160] There are two first power tubes Q1, namely, the first power tube Q1A and the first power tube Q1B. Correspondingly, there are two first drive circuits 200 and two control circuits 100. For ease of explanation, Figure 6 Only the first driving circuit 100 corresponding to the first power tube Q1B and the control circuit 100 are illustrated.

[0161] Among them, the multiple second power tubes may include: power tube Q2A, power tube Q2B, power tube Q3A, power tube Q3B, power tube Q4A, power tube Q4B, power tube Q5A, power tube Q5B, power tube Q6A, power tube Q6B, power tube Q7A, power tube Q7B, power tube Q8A and power tube Q8B.

[0162] The drain of the first power tube Q1A and the drain of the first power tube Q1B are both used to access the input voltage VIN of the switched capacitor converter 1000, the source of the first power tube Q1B is electrically connected to the drain of the power tube Q3B, the source of the power tube Q3B is electrically connected to the drain of the power tube Q5B, the source of the first power tube Q1B is electrically connected to the drain of the power tube Q3A, the source of the power tube Q3A is electrically connected to the drain of the power tube Q5A, and the source of the power tube Q2A is electrically connected to the drain of the power tube Q3B. The electrode and the source of the power tube Q2B are both grounded, the drain of the power tube Q2A is electrically connected to the source of the power tube Q4A, the drain of the power tube Q2B is electrically connected to the source of the power tube Q4B, the first output terminal O1 of the switched capacitor converter 1000 is electrically connected between the source of the power tube Q3B and the drain of the power tube Q5B, and the first output terminal O1 of the switched capacitor converter 1000 is also electrically connected between the source of the power tube Q3A and the drain of the power tube Q5A.

[0163] The first plate of the flying capacitor CF1A is electrically connected between the source of the first power tube Q1B and the drain of the power tube Q3B, the second plate of the flying capacitor CF1A is electrically connected between the drain of the power tube Q2A and the source of the power tube Q4A, the first plate of the flying capacitor CF1B is electrically connected between the source of the first power tube Q1B and the drain of the power tube Q3A, and the second plate of the flying capacitor CF1B is electrically connected between the drain of the power tube Q2B and the source of the power tube Q4B.

[0164] The drain of the power tube Q4A is electrically connected to the first plate of the flying capacitor CF2A, the second plate of the flying capacitor CF2A is electrically connected to the drain of the power tube Q8A, the source of the power tube Q8A is grounded, the source of the power tube Q5A and the drain of the power tube Q6A are both electrically connected between the drain of the power tube Q4A and the first plate of the flying capacitor CF2A, the source of the power tube Q7A is electrically connected between the second plate of the flying capacitor CF2A and the drain of the power tube Q8A, and the source of the power tube Q6A and the drain of the power tube Q7A are both electrically connected to the second output terminal O2 of the switched capacitor converter 1000.

[0165] The drain of the power tube Q4B is electrically connected to the first plate of the flying capacitor CF2B, the second plate of the flying capacitor CF2B is electrically connected to the source of the power tube Q8B, the source of the power tube Q8B is grounded, the source of the power tube Q5B and the drain of the power tube Q6B are both electrically connected between the drain of the power tube Q4B and the first plate of the flying capacitor CF2B, the source of the power tube Q7B is electrically connected between the second plate of the flying capacitor CF2B and the source of the power tube Q8B, and the source of the power tube Q6B and the drain of the power tube Q7B are both electrically connected to the second output terminal O2 of the switched capacitor converter 1000.

[0166] The gate of the first power tube Q1 is electrically connected to the output end of the first driving circuit 200 , and the gate of the second power tube is electrically connected to the gate of the second driving circuit.

[0167] exist Figure 6 , CF1HA represents the first plate voltage of the flying capacitor CF1A, CF1LA represents the second plate voltage of the flying capacitor CF1A. CF1HB represents the first plate voltage of the flying capacitor CF1B, and CF1LB represents the second plate voltage of the flying capacitor CF1B. CF2HA represents the first plate voltage of the flying capacitor CF2A, CF2LA represents the second plate voltage of the flying capacitor CF2A. CF2HB represents the first plate voltage of the flying capacitor CF2B, and CF2LB represents the second plate voltage of the flying capacitor CF2B.

[0168] When the first power tube Q1 is the first power tube Q1A, the voltage HVSS at the ground end of the first driving circuit 200 is the second plate voltage CF1LB of the flying capacitor CF1B. When the first power tube Q1 is the first power tube Q1B, the voltage HVSS at the ground end of the first driving circuit 200 is the first plate voltage CF1HA of the flying capacitor CF1A.

[0169] Among them, in the first phase Φ1, the first power tube Q1B, the power tube Q2B, the power tube Q6B, the power tube Q8B, the power tube Q3A, the power tube Q4A, the power tube Q5A and the power tube Q7A are turned on; the first power tube Q1A, the power tube Q2A, the power tube Q8A, the power tube Q3B, the power tube Q4B, the power tube Q5B and the power tube Q7B are turned off.

[0170] Among them, in the second phase Φ2, the first power tube Q1B, the power tube Q2B, the power tube Q6B, the power tube Q8B, the power tube Q3A, the power tube Q4A, the power tube Q5A and the power tube Q7A are turned off; the first power tube Q1A, the power tube Q2A, the power tube Q8A, the power tube Q3B, the power tube Q4B, the power tube Q5B and the power tube Q7B are turned on.

[0171] Wherein, when there is no load on the first output terminal O1 and the second output terminal O2, the bus voltage, input voltage, first output voltage and second output voltage of the switched capacitor converter 1000 can be expressed by formula (4):

[0172] VBUS=VIN=2*VO1=4*VO2 (4)

[0173] Wherein, VBUS is the bus voltage of the switching power converter 1000 , VIN is the input voltage, VO1 is the first output voltage, and VO2 is the second output voltage.

[0174] The first output voltage is the voltage of the first output terminal O1 , the second output voltage is the voltage of the second output terminal O2 , and the input voltage is the voltage of the input terminal of the switched capacitor converter 1000 .

[0175] In some examples, the switched capacitor converter 1000 may further include: a switch tube QB.

[0176] The source of the switch tube QB is used to access the bus voltage VBUS, and the drain of the switch tube QB is electrically connected to the input voltage VIN.

[0177] The parasitic diode of the switch tube QB points from the bus voltage VBUS to the input voltage VIN.

[0178] When the switched capacitor converter 1000 is operating normally, the switch tube QB is turned on. When the switched capacitor converter 1000 is in an abnormal operating state, the switch tube QB is turned off to avoid a reverse current path from the input voltage VIN to the bus voltage VBUS.

[0179] The present application also provides a chip, including: Figure 1-4 The control circuit 100 provided in the embodiment, and / or, Figure 6 The embodiment provides a switched capacitor converter 1000 .

[0180] The control circuit and the switched capacitor converter may be integrated into one chip or into different chips, which is not specifically limited in the embodiments of the present application.

[0181] The chip provided in the embodiment of the present application has the same beneficial effects as the drive control circuit provided in the embodiment of the present application, which will not be described in detail here.

[0182] An embodiment of the present application also provides an electronic device, including: a chip.

[0183] In this application, electronic devices may include but are not limited to: tablet computers, sensors, medical devices, and wireless communication devices.

[0184] The electronic device provided in the embodiment of the present application has the same beneficial effects as the chip provided in the embodiment of the present application, which will not be described in detail here.

[0185] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A control circuit, characterized in that: The control circuit is applied to a switched capacitor converter, and the switched capacitor converter comprises: a first power tube and a first drive circuit; the control circuit comprises: a control voltage output circuit and a level conversion circuit; The first input end of the control voltage output circuit is used to access the reference voltage, the second input end of the control voltage output circuit is used to access the feedback voltage, the feedback voltage is used to characterize the conversion of the input current, or the output current, or the output voltage of the switch capacitor converter, the output end of the control voltage output circuit is electrically connected to the input end of the level conversion circuit, the output end of the level conversion circuit is electrically connected to the input end of the first drive circuit, the output end of the first drive circuit is electrically connected to the gate of the first power tube, and the ground end of the first drive circuit is electrically connected to the source of the first power tube; The control voltage output circuit is used to obtain a control voltage according to the reference voltage and the feedback voltage, and transmit the control voltage to the level conversion circuit, wherein the control voltage is used to control the input voltage of the first driving circuit; The level conversion circuit is used to convert the control voltage to the voltage domain where the first drive circuit is located, so that the control circuit uses the control voltage to control the start-up voltage of the first power tube to control the input current, or the output current, or the output voltage.

2. The control circuit according to claim 1, characterized in that: The level conversion circuit includes: a current mirror, a voltage conversion current circuit, a first transistor and a first resistor; The input end of the voltage conversion current circuit is electrically connected to the output end of the control voltage output circuit, the output end of the voltage conversion current circuit is electrically connected to the source of the first transistor, the gate of the first transistor is used to receive a control signal, and the control signal is used to control the conduction or shutdown of the first transistor, the drain of the first transistor is electrically connected to the input end of the current mirror, the output end of the current mirror is electrically connected to the first end of the first resistor and the input end of the first drive circuit respectively, and the second end of the first resistor is electrically connected to the ground end of the first drive circuit; The voltage-to-current conversion circuit is used to convert the control voltage into a first current, and transmit the first current to the current mirror through the first transistor; The current mirror is used to mirror the first current to the first resistor so that the voltage across the first resistor is the control voltage, and the control voltage is within the voltage domain.

3. The control circuit according to claim 2, characterized in that: The voltage conversion current circuit includes: a second transistor and a second resistor; The gate of the second transistor is electrically connected to the output end of the control voltage output circuit, the drain of the second transistor is electrically connected to the source of the first transistor, the source of the second transistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is grounded.

4. The control circuit according to claim 2, characterized in that: The current mirror comprises: a first P-type transistor and a second P-type transistor; The source of the first P-type transistor and the source of the second P-type transistor are both used to access a first power supply voltage, the gate of the first P-type transistor, the drain of the first P-type transistor and the gate of the second P-type transistor are all electrically connected to the drain of the first transistor, and the drain of the second P-type transistor is electrically connected to the first end of the first resistor.

5. The control circuit according to claim 1, characterized in that: The level conversion circuit comprises: a charge pump; The input end of the charge pump is electrically connected to the output end of the control voltage output circuit, and the output end of the charge pump is electrically connected to the input end of the first drive circuit; The charge pump is used to store the charge corresponding to the control voltage using the first capacitor in the charge pump in the first stage, and release the charge stored in the first capacitor in the second stage to convert the control voltage into the voltage domain.

6. The control circuit according to claim 5, characterized in that: The level conversion circuit further includes: a buffer, wherein the unit gain of the buffer is 1; The positive phase input terminal of the buffer is electrically connected to the output terminal of the control voltage output circuit, and the negative phase input terminal of the buffer is electrically connected to the output terminal of the buffer and the input terminal of the charge pump respectively; The buffer is used to proportionally amplify the control voltage to eliminate interference signals during the on and off process of the first switch tube in the charge pump.

7. The control circuit according to claim 5, characterized in that: The charge pump comprises: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a first capacitor; The first end of the first switch tube is electrically connected to the output end of the control voltage output circuit, the second end of the first switch tube is electrically connected to the first end of the third switch tube, the second end of the third switch tube is electrically connected to the input end of the first drive circuit, the first end of the second switch tube is grounded, the second end of the second switch tube is electrically connected to the first end of the fourth switch tube, the second end of the fourth switch tube is electrically connected to the ground end of the first drive circuit, the upper plate of the first capacitor is electrically connected between the second end of the first switch tube and the first end of the third switch tube, the lower plate of the first capacitor is electrically connected between the second end of the second switch tube and the first end of the fourth switch tube, and the control end of the first switch tube, the control end of the second switch tube, the control end of the third switch tube and the control end of the fourth switch tube are all used to access control signals, and the control signals are used to control the conduction or shutdown of the switch tubes.

8. The control circuit according to claim 1, characterized in that: The level conversion circuit comprises: a voltage conversion current circuit, a current mirror, a first voltage output circuit and an error amplifier; The first end of the voltage conversion current circuit is electrically connected to the input end of the current mirror, the input end of the first drive circuit and the output end of the error amplifier respectively, the second end of the voltage conversion current circuit is electrically connected to the ground end of the first drive circuit, the output end of the current mirror is electrically connected to the input end of the first voltage output circuit, the output end of the first voltage output circuit is electrically connected to the first input end of the error amplifier, and the second input end of the error amplifier is electrically connected to the output end of the control voltage output circuit; The voltage-to-current conversion circuit is used to convert the input voltage of the first driving circuit into a first current and transmit the first current to the current mirror; The current mirror is used to mirror the first current to the first voltage output circuit; The first voltage output circuit is used to generate the first voltage according to the first current, and transmit the first voltage to the error amplifier, wherein the first voltage is used to characterize the change of the input voltage of the first driving circuit; The error amplifier is used to keep the input voltage of the first driving circuit stable according to the control voltage and the first voltage, so that the control voltage is converted into the voltage domain.

9. The control circuit according to claim 8, characterized in that: The level conversion circuit further includes: a sampling and holding circuit; The input end of the sampling and holding circuit is electrically connected to the output end of the first voltage output circuit, and the output end of the sampling and holding circuit is electrically connected to the first input end of the error amplifier; The sampling and holding circuit is used to sample and hold the first voltage when the first power tube is turned on to obtain a second voltage, and transmit the second voltage to the error amplifier so that the error amplifier keeps the input voltage of the first drive circuit stable according to the control voltage and the second voltage.

10. The control circuit according to claim 9, characterized in that: The sample-and-hold circuit comprises: a first switch tube and a first capacitor; The first end of the first switch tube is electrically connected to the output end of the first voltage output circuit, the control end of the first switch tube is used to access a first control signal, and the first control signal is used to control the conduction or shutdown of the first switch tube, the second end of the first switch tube is electrically connected to the first input end of the error amplifier, the upper plate of the first capacitor is electrically connected between the second end of the first switch tube and the first input end of the error amplifier, and the lower plate of the first capacitor is grounded.

11. The control circuit according to claim 8, characterized in that: The error amplifier includes: a first differential transconductance amplifier, a first P-type transistor, a second P-type transistor, a first transistor, a second transistor, a third transistor and a fourth transistor; The source of the first P-type transistor and the source of the second P-type transistor are both used to access a first power supply voltage, the gate of the first P-type transistor, the drain of the first P-type transistor and the gate of the second P-type transistor are all electrically connected to the drain of the first transistor, the source of the first transistor is electrically connected to the drain of the third transistor, the drain of the second P-type transistor is electrically connected to the drain of the second transistor and the first end of the voltage conversion current circuit respectively, the source of the second transistor is electrically connected to the drain of the fourth transistor, the gate of the fourth transistor is electrically connected to the second output end of the first differential transconductance amplifier, the gate of the third transistor is electrically connected to the first output end of the first differential transconductance amplifier, the positive phase input end of the first differential transconductance amplifier is electrically connected to the output end of the control voltage output circuit, the negative phase input end of the first differential transconductance amplifier is electrically connected to the output end of the first voltage output circuit, the gate of the first transistor and the gate of the second transistor are both used to access a second control signal, the second control signal is used to control the conduction or disconnection of the first transistor and the second transistor, and the source of the third transistor and the source of the fourth transistor are both grounded.

12. The control circuit according to claim 8, characterized in that: The first voltage output circuit includes: a fifth transistor and a first resistor; The gate of the fifth transistor is electrically connected to the first input terminal of the error amplifier, the drain of the fifth transistor and the output terminal of the current mirror respectively, the source of the fifth transistor is electrically connected to the first end of the first resistor, and the second end of the first resistor is grounded.

13. The control circuit according to claim 8, characterized in that: The voltage conversion current circuit includes: a sixth transistor and a second resistor; The gate of the sixth transistor is electrically connected to the input end of the first drive circuit and the output end of the error amplifier respectively, the drain of the sixth transistor is electrically connected to the input end of the current mirror, the source of the sixth transistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is electrically connected to the ground end of the first drive circuit.

14. The control circuit according to any one of claims 1 to 13, characterized in that: The control voltage output circuit includes: a second differential transconductance amplifier, a current source, an N-type transistor and a second capacitor; The positive phase input terminal of the second differential transconductance amplifier is used to access the reference voltage, the negative phase input terminal of the second differential transconductance amplifier is used to access the feedback voltage, the output terminal of the second differential transconductance amplifier is electrically connected to the gate of the N-type transistor, the input terminal of the current source is used to access the second power supply voltage, the output terminal of the current source is electrically connected to the drain of the N-type transistor, the upper plate of the second capacitor is electrically connected between the output terminal of the current source and the drain of the N-type transistor, the upper plate of the second capacitor is also electrically connected to the input terminal of the level conversion circuit, and the lower plate of the second capacitor and the source of the N-type transistor are both grounded; The second differential transconductance amplifier is used to control the N-type transistor to be turned on according to the reference voltage and the feedback voltage, so as to convert the voltage difference between the reference voltage and the feedback voltage into a current, so as to generate the control voltage.

15. A switched capacitor converter, characterized in that: The switched capacitor converter comprises: a first power tube, a plurality of second power tubes, a first drive circuit, a plurality of second drive circuits, a plurality of flying capacitors and a control circuit as claimed in any one of claims 1 to 14; The first driving circuit is used to drive the first power tube to switch between on and off; The second driving circuit is used to drive the second power tube to switch between on and off; The first power tube and the plurality of second power tubes are used to control the plurality of flying capacitors to switch between charging and discharging when switching between on and off, so as to convert the input voltage of the switched capacitor converter into a plurality of output voltages; The control circuit is used to control the turn-on voltage of the first power tube to control the input current, output current, or output voltage of the switch capacitor converter.

16. A chip, characterized in that: include: A control circuit as claimed in any one of claims 1 to 14, and / or a switched capacitor converter as claimed in claim 15.

17. An electronic device, characterized in that: include: The chip as claimed in claim 16.

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