DC conversion circuit, switching power supply and electronic equipment for suppressing overshoot

Abstract

The present application belongs to the field of circuits, and provides a DC conversion circuit, a switching power supply and an electronic device for suppressing overshoot. The circuit includes a ripple injection module, a conversion module, a driving module, a feedback module, a signal detection module and a signal generation module. The conversion module is respectively connected to the feedback module, the driving module, the ripple injection module and the load, the feedback module is respectively connected to the driving module and the ripple injection module, the signal generation module is respectively connected to the driving module and the signal detection module, and the signal detection module is connected to the ripple injection module. The present application generates a first signal through a signal generation module, the frequency of the first signal is the same as the switching frequency of the DC conversion circuit, and the first signal is detected by a signal detection module. When the frequency of the first signal is less than a preset frequency, the ripple injection module is controlled to stop outputting a ripple signal, so as to avoid turning on the upper tube in the process of the load jumping from heavy load to light load, so as to achieve overshoot suppression of the output voltage.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a DC conversion circuit, a switching power supply and an electronic device for suppressing overshoot. Background Art

[0002] At present, the BUCK converter using COT (Constant-on-time) control mode uses ceramic capacitors with small ESR (equivalent series resistance) as output capacitors, which is prone to instability while obtaining a small output voltage and high efficiency. In order to avoid this situation, researchers have proposed a variety of solutions for loop compensation, including adding feedforward capacitors, sampling inductor current ripple injection, simulated inductor current ripple injection, sampling capacitor current ripple injection, slope compensation, etc. Considering factors such as circuit structure, cost and implementation complexity, simulated inductor current ripple injection is generally regarded as a practical and effective solution.

[0003] However, this ripple injection compensation method will inject a negative ripple signal into the loop during the heavy load to light load transition process. This ripple signal may cause the upper tube in the buck converter to turn on again, causing a larger output voltage overshoot and worsening the transient response of the buck converter. Summary of the invention

[0004] The embodiments of the present application provide a DC conversion circuit, a switching power supply and an electronic device for suppressing overshoot, which can solve the problem of a BUCK converter that uses simulated inductor current ripple injection compensation causing a larger output voltage overshoot during a heavy load transition to a light load.

[0005] In a first aspect, an embodiment of the present application provides a DC conversion circuit for suppressing overshoot, comprising a ripple injection module, a conversion module, a drive module, a feedback module, a signal detection module and a signal generation module, wherein the conversion module is respectively connected to the feedback module, the drive module, the ripple injection module and the load, the feedback module is respectively connected to the drive module and the ripple injection module, the signal generation module is respectively connected to the drive module and the signal detection module, and the signal detection module is connected to the ripple injection module;

[0006] The driving module is configured to output a first driving signal, a second driving signal, a first logic signal, and a second logic signal according to a control signal; the transformation module is configured to transform an input voltage according to the first driving signal and the second driving signal to obtain an output voltage; the signal generation module is configured to output a first signal according to the first logic signal and the second logic signal; the signal detection module is configured to detect the first signal, and when the frequency of the first signal is greater than a preset frequency, output a first level signal to the ripple injection module, so that the ripple injection module outputs a ripple signal according to the first level signal and the voltage at the switching node in the transformation module, and further enables the feedback module to output a control signal according to the ripple signal and the output voltage. When the frequency of the first signal is less than the preset frequency, a second level signal is output to the ripple injection module, so that the ripple injection module stops outputting the ripple signal.

[0007] In a possible implementation manner of the first aspect, the signal generation module includes a first inverter, a NOR gate, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a first resistor, a second resistor, a first NAND gate, and a second NAND gate. The input end of the first inverter is connected to the driving module, the output end of the first inverter is connected to the first input end of the NOR gate, the second input end of the NOR gate receives a first enable signal, the output end of the NOR gate is respectively connected to the gate electrodes of the first field effect transistor and the second field effect transistor. The source electrodes of the first field effect transistor and the fourth field effect transistor both receive a power supply voltage. The drain electrode of the first field effect transistor is respectively connected to the first end of the first resistor, the gate electrode of the third field effect transistor, the gate electrode of the fourth field effect transistor, and the gate electrode of the fifth field effect transistor. The second end of the first resistor is connected to the drain electrode of the second field effect transistor. The drain electrode of the fourth field effect transistor is connected to the first end of the second resistor. The second end of the second resistor is respectively connected to the drain electrode of the fifth field effect transistor and the first input end of the first NAND gate. The second input end of the first NAND gate is connected to the driving module. The output end of the first NAND gate is connected to the first input end of the second NAND gate. The second input end of the second NAND gate receives a second enable signal. The output end of the second NAND gate is connected to the signal detection module. The source electrodes of the second field effect transistor, the third field effect transistor, the drain electrode of the third field effect transistor, and the source electrode of the fifth field effect transistor are all grounded.

[0008] In a possible implementation manner of the first aspect, the signal detection module includes a sixth field effect transistor, a seventh field effect transistor, a third resistor, a first capacitor, a Schmitt trigger, a second inverter, a third NAND gate and a third inverter, the gate of the sixth field effect transistor is respectively connected to the gate of the seventh field effect transistor and the signal generation module, the source of the sixth field effect transistor receives a power supply voltage, the drain of the sixth field effect transistor is connected to the first end of the third resistor, the second end of the third resistor is respectively connected to the drain of the seventh field effect transistor, the first end of the first capacitor and the input end of the Schmitt trigger, the output end of the Schmitt trigger is connected to the input end of the second inverter, the output end of the second inverter is connected to the first input end of the third NAND gate, the second input end of the third NAND gate receives a second enable signal, the output end of the third NAND gate is respectively connected to the input end of the third inverter and the ripple injection module, the output end of the third inverter is connected to the ripple injection module, and the source of the seventh field effect transistor and the second end of the first capacitor are both grounded.

[0009] In a possible implementation manner of the first aspect, the ripple injection module includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second capacitor, a third capacitor, a fourth capacitor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a fourth inverter and a differential unit, a first end of the fourth resistor is connected to a switch node in the conversion module, a second end of the fourth resistor is respectively connected to a first end of the fifth resistor, a first end of the sixth resistor and a first end of the eighth resistor, a second end of the sixth resistor is respectively connected to a first end of the second capacitor and a first end of the seventh resistor, a second end of the seventh resistor is respectively connected to a first end of the third capacitor, a source of the eleventh field effect transistor, a The drain of the eleventh field effect transistor, the drain of the ninth field effect transistor and the differential unit are connected, the second end of the eighth resistor is respectively connected to the first end of the ninth resistor and the drain of the eighth field effect transistor, the second end of the ninth resistor is respectively connected to the source of the eighth field effect transistor, the first end of the fourth capacitor, the source of the tenth field effect transistor, the drain of the tenth field effect transistor, the source of the ninth field effect transistor and the differential unit, the differential unit is connected to the feedback module, the gate of the eighth field effect transistor is connected to the output end of the fourth inverter, the input end of the fourth inverter is connected to the conversion module, and the second end of the fifth resistor, the second end of the second capacitor, the second end of the third capacitor and the second end of the fourth capacitor are all grounded.

[0010] In a possible implementation manner of the first aspect, the conversion module includes an upper tube, a lower tube, an inductor and an output capacitor, the first conduction end of the upper tube is used to receive the input voltage, the second conduction end of the upper tube is respectively connected to the first conduction end of the lower tube, the first end of the inductor and the ripple injection module, the control end of the upper tube and the control end of the lower tube are respectively connected to the driving module, the control end of the lower tube is also connected to the ripple injection module, the second conduction end of the lower tube is grounded, the second end of the inductor is respectively connected to the first end of the output capacitor, the feedback module and the load, and the second end of the output capacitor is grounded; wherein a common end of the second conduction end of the upper tube, the first conduction end of the lower tube and the first end of the inductor is a switch node.

[0011] In a possible implementation of the first aspect, the feedback module includes a voltage divider unit, an operational amplifier, an adder, a comparator and an on-time generator, the voltage divider unit is respectively connected to the conversion module, the load, the first input terminal of the operational amplifier and the first input terminal of the adder, the second input terminal of the operational amplifier receives a reference voltage, the second input terminal of the adder is connected to the ripple injection module, the output terminal of the operational amplifier is connected to the first input terminal of the comparator, the output terminal of the adder is connected to the second input terminal of the comparator, the output terminal of the comparator is connected to the input terminal of the on-time generator, and the output terminal of the on-time generator is connected to the driving module.

[0012] In a possible implementation of the first aspect, the voltage divider unit includes a tenth resistor and an eleventh resistor, the first end of the tenth resistor is respectively connected to the conversion module and the load, the second end of the tenth resistor is respectively connected to the first end of the eleventh resistor, the first input end of the adder and the first input end of the operational amplifier, and the second end of the eleventh resistor is grounded.

[0013] In a possible implementation manner of the first aspect, the driving module includes a control unit, a first driving unit, and a second driving unit, the control unit is connected to the first driving unit, the second driving unit, and the feedback module, respectively, and the first driving unit and the second driving unit are connected to the transformation module, respectively;

[0014] The control unit is used to output a first logic signal to the first drive unit and a second logic signal to the second drive unit according to the control signal; the first drive unit is used to output a first drive signal to the conversion module according to the first logic signal; the second drive unit is used to output a second drive signal to the conversion module according to the second logic signal.

[0015] In a second aspect, an embodiment of the present application provides a switching power supply, comprising a DC conversion circuit for suppressing overshoot as described in any one of the first aspects.

[0016] In a third aspect, an embodiment of the present application provides an electronic device, comprising a DC conversion circuit for suppressing overshoot as described in any one of the first aspects.

[0017] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0018] An embodiment of the present application provides a DC conversion circuit for suppressing overshoot, including a ripple injection module, a conversion module, a drive module, a feedback module, a signal detection module and a signal generation module, wherein the conversion module is respectively connected to the feedback module, the drive module, the ripple injection module and the load, the feedback module is respectively connected to the drive module and the ripple injection module, the signal generation module is respectively connected to the drive module and the signal detection module, and the signal detection module is connected to the ripple injection module.

[0019] The driving module is used to output a first driving signal, a second driving signal, a first logic signal and a second logic signal according to a control signal. The conversion module is used to convert the input voltage according to the first driving signal and the second driving signal to obtain an output voltage. The signal generation module is used to output a first signal according to the first logic signal and the second logic signal. The signal detection module is used to detect the first signal. When the frequency of the first signal is greater than a preset frequency (the preset frequency is less than the switching frequency when the DC conversion circuit is in a steady state), the first level signal is output to the ripple injection module, so that the ripple injection module outputs a ripple signal according to the first level signal and the voltage at the switch node in the conversion module, and then the feedback module outputs a control signal according to the ripple signal and the output voltage to ensure the stability of the output voltage; when the frequency of the first signal is less than the preset frequency, it indicates that the load jumps from heavy load to light load, and then the second level signal is output to the ripple injection module, so that the ripple injection module stops outputting the ripple signal to avoid injecting a negative ripple signal into the loop, so that the upper tube in the conversion module will not be turned on during the process of the load jumping from heavy load to light load, so as to achieve overshoot suppression of the output voltage.

[0020] As can be seen from the above, the present application generates a first signal through a signal generation module, the frequency of the first signal is the same as the switching frequency of the DC conversion circuit, and the frequency of the first signal is detected by a signal detection module. When the frequency of the first signal is less than a preset frequency, the ripple injection module is controlled to stop outputting a ripple signal, so as to avoid turning on the upper tube when the load changes from a heavy load to a light load, thereby achieving output voltage overshoot suppression. When the frequency of the first signal is greater than a preset frequency, the ripple injection module is controlled to output a ripple signal, and the stability of the output voltage is ensured through the coordinated action of the feedback module, the drive module, and the conversion module.

[0021] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 This is the principle block diagram of the BUCK converter using the COT control mode;

[0024] Figure 2 This is the schematic diagram for simulating the inductor current ripple injection;

[0025] Figure 3 It is a schematic diagram of the simulated inductor current ripple injection waveform;

[0026] Figure 4 This is a waveform diagram of a BUCK converter using the COT control mode when the load changes from heavy load to light load;

[0027] Figure 5 It is the schematic diagram of the on-time generator of the BUCK converter using the COT control mode;

[0028] Figure 6 It is a principle block diagram of a DC conversion circuit for suppressing overshoot provided in an embodiment of the present application;

[0029] Figure 7 This is a circuit connection diagram of a DC conversion circuit for suppressing overshoot provided by an embodiment of the present application;

[0030] Figure 8 is a circuit connection diagram of a DC conversion circuit for suppressing overshoot provided by another embodiment of the present application;

[0031] Fig. 9 This is a waveform diagram of a DC conversion circuit for suppressing overshoot provided by an embodiment of the present application when the load changes from heavy load to light load.

[0032] In the figure: 10, ripple injection module; 11, differential unit; 20, conversion module; 30, drive module; 31, control unit; 32, first drive unit; 33, second drive unit; 40, feedback module; 41, voltage divider unit; 50, signal generation module; 60, signal detection module; 70, load. DETAILED DESCRIPTION

[0033] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0034] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0035] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0036] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0037] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0038] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0039] The principle block diagram of the BUCK converter using the COT control mode is as follows: Figure 1As shown in the figure, due to the use of ceramic capacitors with smaller ESR as output capacitors, while obtaining a small output voltage and higher efficiency, instability problems are prone to occur. In order to avoid this situation, researchers have proposed a variety of solutions for loop compensation, including adding feedforward capacitors, sampling inductor current ripple injection, simulated inductor current ripple injection, sampling capacitor current ripple injection, slope compensation, etc. Considering factors such as circuit structure, cost, and implementation complexity, simulated inductor current ripple injection is generally regarded as a practical and effective solution. Its implementation principle is as follows: Figure 2 As shown, the voltage at the switch node SW is filtered to convert the square wave signal into a signal SW_RC1 in phase with the inductor current. The sufficiently large time constant of the second-order filter makes the signal SW_RC2 approximately equal to the DC component of the output voltage. Since the signal SW_RC1 also includes the signal SW_RC2, the DC amount needs to be removed to obtain a suitable ripple signal for the compensation loop.

[0040] The simulated inductor current ripple injection waveform is as follows Figure 3 As shown, the solid line represents the signal SW_RC1 and the dotted line represents the signal SW_RC2. In each switching cycle, when the lower tube S2 is turned on, if the signal SW_RC1 is greater than the signal SW_RC2, a positive ripple signal is injected into the loop, and the positive ripple signal has the effect of inhibiting the upper tube S1 from turning on, thereby enhancing the stability of the loop. If the signal SW_RC1 is less than the signal SW_RC2, a negative ripple signal is injected into the loop, and the negative ripple signal has the effect of promoting the upper tube S1 to turn on.

[0041] However, this ripple injection compensation method that simulates the inductor current will cause a larger output voltage overshoot when the load changes from heavy load to light load, which will deteriorate the transient response of the buck converter. The waveform of the buck converter using the COT control mode when the load changes from heavy load to light load is as follows: Figure 4 As shown, the load current iload (as Figure 4 The inductor current iL (shown as the dotted line in Figure 4 The change of the load current iload (shown by the solid line in the figure) lags behind the change of the load current iload. As the lower tube S2 continues to be turned on, the voltage at the switch node SW is maintained near 0, so the signal SW_RC1 will continue to decrease. Due to the different filtering speeds, the signal SW_RC2 changes very little. After the signal SW_RC1 intersects with the signal SW_RC2 at time t2, it will continue to decrease, which is equivalent to injecting a negative ripple signal into the loop. This ripple signal may cause the upper tube S1 to turn on again in the middle of the continuous decrease of the inductor current iL (at time t3), causing a larger output voltage overshoot, which is undesirable but is also a problem that this compensation method inevitably brings.

[0042] Common buck on-time generators using COT control mode include: Figure 5 As shown, the on-time generator is triggered by the duty signal output by the comparator. After a fixed time, the logic level of the ontime_delay signal flips. , is a constant charging current, is the input voltage, is the impedance used to generate a constant charging current. , is the on-time, is the output voltage, is the capacitance in the on-time generator. , is the switching cycle. and The switching frequency can be kept approximately constant.

[0043] The present application generates a signal with the same frequency as the switching frequency of the DC conversion circuit, and then detects the frequency of the signal. When the frequency of the signal is less than the preset frequency, the signal SW_RC1 and the signal SW_RC2 are connected together in time to stop outputting the ripple signal, thereby preventing the load from turning on the upper tube S1 during the transition from heavy load to light load, thereby achieving output voltage overshoot suppression.

[0044] The present application proposes a DC conversion circuit for suppressing overshoot, such as Figure 6 As shown, the DC conversion circuit for suppressing overshoot includes a ripple injection module 10, a conversion module 20, a driving module 30, a feedback module 40, a signal detection module 60 and a signal generation module 50. The conversion module 20 is respectively connected to the feedback module 40, the driving module 30, the ripple injection module 10 and the load 70, the feedback module 40 is respectively connected to the driving module 30 and the ripple injection module 10, the signal generation module 50 is respectively connected to the driving module 30 and the signal detection module 60, and the signal detection module 60 is connected to the ripple injection module 10.

[0045] Specifically, the driving module 30 is used to output a first driving signal HS_driver, a second driving signal LS_driver, a first logic signal HS_ONB and a second logic signal LS_ONB according to the control signal. The conversion module 20 is used to convert the input voltage Vin according to the first driving signal HS_driver and the second driving signal LS_driver to obtain the output voltage Vout. The signal generation module 50 is used to output the first signal MOS_ONB according to the first logic signal HS_ONB and the second logic signal LS_ONB. The signal detection module 60 is used to detect the first signal MOS_ONB. When the frequency of the first signal MOS_ONB is greater than the preset frequency (the preset frequency is less than the switching frequency when the DC conversion circuit is in a steady state), the first level signal (the first level signal is a low level) is output to the ripple injection module 10, so that the ripple injection module 10 outputs the ripple signal VRipple according to the first level signal and the voltage at the switch node SW in the conversion module 20, and then the feedback module 40 outputs the control signal according to the ripple signal VRipple and the output voltage Vout to ensure the stability of the output voltage Vout. When the frequency of the first signal MOS_ONB is less than the preset frequency, indicating that the load 70 changes from heavy load to light load, a second level signal (the second level signal is a high level) is output to the ripple injection module 10, so that the ripple injection module 10 stops outputting the ripple signal VRipple to avoid injecting a negative ripple signal into the loop, so that the upper tube S1 in the conversion module 20 will not be turned on during the process of the load 70 changing from heavy load to light load, thereby achieving overshoot suppression of the output voltage Vout.

[0046] As can be seen from the above, the present application generates a first signal MOS_ONB having the same frequency as the switching frequency of the DC conversion circuit through the signal generation module 50, and detects the frequency of the first signal MOS_ONB through the signal detection module 60. When the frequency of the first signal MOS_ONB is less than the preset frequency, the ripple injection module 10 is controlled to stop outputting the ripple signal VRipple, so as to avoid turning on the upper tube S1 during the process of the load 70 jumping from heavy load to light load, thereby achieving overshoot suppression of the output voltage Vout and optimizing the transient response of the DC conversion circuit. When the frequency of the first signal MOS_ONB is greater than the preset frequency, the ripple injection module 10 is controlled to output the ripple signal VRipple, and the stability of the output voltage Vout is ensured through the synergistic effect of the feedback module 40, the driving module 30 and the conversion module 20.

[0047] It should be noted that the present application does not limit the type of DC conversion circuit, and the DC conversion circuit may be a BUCK circuit, a BOOST circuit or a BUCK-BOOST circuit, as long as these circuits use simulated inductor current ripple injection for loop compensation.

[0048] In some embodiments, as Figure 7 shown, the conversion module 20 includes an upper transistor S1, a lower transistor S2, an inductor L, and an output capacitor Cout. The first conduction end of the upper transistor S1 is used to receive the input voltage Vin. The second conduction end of the upper transistor S1 is respectively connected to the first conduction end of the lower transistor S2, the first end of the inductor L, and the ripple injection module 10. The control ends of the upper transistor S1 and the lower transistor S2 are respectively connected to the drive module 30. The control end of the lower transistor S2 is also connected to the ripple injection module 10. The second conduction end of the lower transistor S2 is grounded. The second end of the inductor L is respectively connected to the first end of the output capacitor Cout, the feedback module 40, and the load 70. The second end of the output capacitor Cout is grounded. Among them, the common end of the second conduction end of the upper transistor S1, the first conduction end of the lower transistor S2, and the first end of the inductor L is the switching node SW. It should be noted that the upper transistor S1 and the lower transistor S2 are used as switching elements to control the on and off of the circuit. The inductor L is used to store and release energy to achieve voltage conversion. The output capacitor Cout is used to smooth the output voltage and reduce the ripple.

[0049] Specifically, the drive signal of the upper transistor S1 is the first drive signal HS_driver, and the drive signal of the lower transistor S2 is the second drive signal LS_driver. When the upper transistor S1 is turned on and the lower transistor S2 is turned off, the inductor current iL starts to rise, and the inductor L stores energy. When the lower transistor S2 is turned on and the upper transistor S1 is turned off, the inductor current iL starts to fall, and the inductor L releases energy. By reasonably setting the duty cycles of the first drive signal HS_driver and the second drive signal LS_driver, the storage and release of energy in the inductor L can be controlled, so as to achieve the conversion of the input voltage Vin to obtain the desired output voltage Vout.

[0050] In the embodiments of the present application, both the upper transistor S1 and the lower transistor S2 are NMOS (N-Metal-Oxide-Semiconductor) transistors.

[0051] In some embodiments, as Figure 7 shown, the feedback module 40 includes a voltage dividing unit 41, an operational amplifier, an adder, a comparator, and a conduction time generator. The voltage dividing unit 41 is respectively connected to the conversion module 20, the load 70, the first input end of the operational amplifier, and the first input end of the adder. The second input end of the operational amplifier receives the reference voltage Vref. The second input end of the adder is connected to the ripple injection module 10 to receive the ripple signal VRipple. The output end of the operational amplifier is connected to the first input end of the comparator. The output end of the adder is connected to the second input end of the comparator. The output end of the comparator is connected to the input end of the conduction time generator. The output end of the conduction time generator is connected to the drive module 30. According to Figure 7It can be known that the voltage dividing unit 41 is specifically connected to the first end of the output capacitor Cout in the conversion module 20 .

[0052] Specifically, the voltage divider unit 41 divides the output voltage Vout to obtain the feedback voltage Vfb. The operational amplifier outputs the amplified error signal Vc according to the feedback voltage Vfb and the reference voltage Vref. The adder superimposes the feedback voltage Vfb and the ripple signal VRipple. The comparator outputs the duty signal according to the voltage after the feedback voltage Vfb and the ripple signal VRipple are superimposed and the error signal Vc. The on-time generator is triggered by the duty signal, and after a fixed time, the logic level of the ontime_delay signal (that is, the control signal output by the feedback module 40) is flipped.

[0053] It should be noted that the on-time generator in the present application directly adopts the on-time generator in the existing conversion circuit, and the present application does not limit its specific structure.

[0054] For example, Figure 8 As shown, the voltage dividing unit 41 includes a tenth resistor R10 and an eleventh resistor R11, the first end of the tenth resistor R10 is connected to the conversion module 20 and the load 70 respectively, the second end of the tenth resistor R10 is connected to the first end of the eleventh resistor R11, the first input end of the adder and the first input end of the operational amplifier respectively, and the second end of the eleventh resistor R11 is grounded. Figure 7 It can be known that the first end of the tenth resistor R10 is specifically connected to the first end of the output capacitor Cout in the conversion module 20. Specifically, the tenth resistor R10 and the eleventh resistor R11 divide the output voltage Vout to obtain the feedback voltage Vfb.

[0055] In some embodiments, Figure 7 As shown, the driving module 30 includes a control unit 31, a first driving unit 32 and a second driving unit 33. The control unit 31 is connected to the first driving unit 32, the second driving unit 33 and the feedback module 40 respectively, and the first driving unit 32 and the second driving unit 33 are connected to the transformation module 20 respectively. Figure 7 It can be seen that the control unit 31 is specifically connected to the output end of the conduction time generator in the feedback module 40. The first driving unit 32 is specifically connected to the control end of the upper tube S1 in the conversion module 20. The second driving unit 33 is specifically connected to the control end of the lower tube S2 in the conversion module 20.

[0056] Specifically, the control unit 31 is used to output the first logic signal HS_ONB to the first driving unit 32 according to the control signal (i.e., the ontime_delay signal), and output the second logic signal LS_ONB to the second driving unit 33. The first driving unit 32 is used to output the first driving signal HS_driver to the upper tube S1 in the conversion module 20 according to the first logic signal HS_ONB. The second driving unit 33 is used to output the second driving signal LS_driver to the lower tube S2 in the conversion module 20 according to the second logic signal LS_ONB.

[0057] In some embodiments, Figure 7 As shown, the signal generating module 50 includes a first inverter INV1, a NOR gate NOR, a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5, a first resistor R1, a second resistor R2, a first NAND gate NAND1 and a second NAND gate NAND2. The input end of the first inverter INV1 is connected to the driving module 30 to receive the first logic signal HS_ONB. The output end of the first inverter INV1 is connected to the first input end of the NOR gate NOR. The second input end of the NOR gate NOR receives the first enable signal ENB (when the DC conversion circuit is in the working state, the first enable signal ENB is at a low level). The output end of the NOR gate NOR is respectively connected to the gate of the first field effect transistor M1 and the gate of the second field effect transistor M2. The source of the first field effect transistor M1 and the source of the fourth field effect transistor M4 both receive the power supply voltage VDD. The drain of the first field effect transistor M1 is respectively connected to the first end of the first resistor R1, the third field effect transistor M3 and the fourth field effect transistor M4. The gate of the transistor M3, the gate of the fourth field effect transistor M4 and the gate of the fifth field effect transistor M5 are connected, the second end of the first resistor R1 is connected to the drain of the second field effect transistor M2, the drain of the fourth field effect transistor M4 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is respectively connected to the drain of the fifth field effect transistor M5 and the first input end of the first NAND gate NAND1, the second input end of the first NAND gate NAND1 is connected to the driving module 30, and receives the second logic signal LS_ONB, the output end of the first NAND gate NAND1 is connected to the first input end of the second NAND gate NAND2, the second input end of the second NAND gate NAND2 receives the second enable signal EN (when the DC conversion circuit is in the working state, the second enable signal EN is a high level), the output end of the second NAND gate NAND2 is connected to the signal detection module 60, the source of the second field effect transistor M2, the source of the third field effect transistor M3, the drain of the third field effect transistor M3 and the source of the fifth field effect transistor M5 are all grounded. According to Figure 7It can be seen that the input end of the first inverter INV1 is specifically connected to the first driving unit 32 in the driving module 30 . The second input end of the first NAND gate NAND1 is specifically connected to the second driving unit 33 in the driving module 30 .

[0058] Specifically, the first logic signal HS_ONB is a logic signal for generating the first drive signal HS_driver. When the first logic signal HS_ONB is at a low level, the upper tube S1 is controlled to be turned on. The second logic signal LS_ONB is a logic signal for generating the second drive signal LS_driver. When the second logic signal LS_ONB is at a low level, the lower tube S2 is controlled to be turned on. The rising edge of the first signal MOS_ONB is triggered by the rising edge of the second logic signal LS_ONB, and the falling edge of the first signal MOS_ONB is triggered by the falling edge of the first logic signal HS_ONB. The waveform of the first signal MOS_ONB is as follows: Fig. 9 As shown. The delay of the rising edge of the first logic signal HS_ONB set by the first resistor R1 and the third field effect transistor M3 (the third field effect transistor M3 is equivalent to a capacitor) should ensure that the first signal MOS_ONB generates a pulse only before the upper tube S1 is turned on. The delay needs to be greater than the dead time before the upper tube S1 turns off the lower tube S2 and is less than the time when the lower tube S2 is turned on. The frequency of the first signal MOS_ONB is equal to the switching frequency of the DC conversion circuit. In the process of the load 70 jumping from heavy load to light load, the second logic signal LS_ONB will flip to a high level after a long time, resulting in a decrease in the frequency of the first signal MOS_ONB. By using the change in the frequency of the first signal MOS_ONB, the switching frequency can be detected and a signal for controlling whether the ripple injection module 10 outputs the ripple signal VRipple can be generated.

[0059] In some embodiments, Figure 7As shown, the signal detection module 60 includes a sixth field effect transistor M6, a seventh field effect transistor M7, a third resistor R3, a first capacitor C1, a Schmitt trigger, a second inverter INV2, a third NAND gate NAND3 and a third inverter INV3, the gate of the sixth field effect transistor M6 is respectively connected to the gate of the seventh field effect transistor M7 and the signal generation module 50, the source of the sixth field effect transistor M6 receives the power supply voltage VDD, the drain of the sixth field effect transistor M6 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is respectively connected to the drain of the seventh field effect transistor M7, the first capacitor C1 The first end of is connected to the input end of the Schmitt trigger, the output end of the Schmitt trigger is connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is connected to the first input end of the third NAND gate NAND3, the second input end of the third NAND gate NAND3 receives the second enable signal EN, the output end of the third NAND gate NAND3 is respectively connected to the input end of the third inverter INV3 and the ripple injection module 10, the output end of the third inverter INV3 is connected to the ripple injection module 10, and the source of the seventh field effect transistor M7 and the second end of the first capacitor C1 are both grounded. According to Figure 7 It can be known that the gate of the sixth field effect transistor M6 is specifically connected to the output end of the second NAND gate NAND2 in the signal generating module 50 .

[0060] Specifically, the falling delay of the first signal MOS_ONB is realized by the third resistor R3 and the first capacitor C1. In the embodiment of the present application, the falling delay of the first signal MOS_ONB is set to be approximately 1.2 times of the switching cycle (the inverse of the switching cycle is the switching frequency). It should be noted that the third resistor R3 and the first capacitor C1 should match Ron and Con in the on-time generator in the feedback module 40. The matching here emphasizes that factors such as layout, wiring, and use environment are the same to reduce random errors and thus improve the accuracy of the circuit.

[0061] When the circuit is working normally, the SET signal (SET signal includes a first level signal and a second level signal) output by the signal detection module 60 is a low level (i.e., a first level signal), and the low level will be transmitted to the ripple injection module 10, and the ripple injection module 10 will normally output the ripple signal VRipple according to the low level to ensure the stability of the loop. Only when it is detected that the interval time between the falling edge of the first signal MOS_ONB and the adjacent next rising edge is greater than the set delay, the SET signal will flip to a high level (i.e., a second level signal), and the high level will be transmitted to the ripple injection module 10, and the ripple injection module 10 will stop outputting the ripple signal VRipple according to the high level, avoiding turning on the upper tube S1 when the load 70 jumps from heavy load to light load, so as to achieve overshoot suppression of the output voltage Vout. It should be noted that the SETB signal is logically opposite to the SET signal.

[0062] In some embodiments, Figure 7 As shown, the ripple injection module 10 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, a fourth inverter INV4 and a differential unit 11, a first end of the fourth resistor R4 is connected to the switch node SW in the conversion module 20, a second end of the fourth resistor R4 is respectively connected to the first end of the fifth resistor R5, the first end of the sixth resistor R6 and the first end of the eighth resistor R8, a second end of the sixth resistor R6 is respectively connected to the first end of the second capacitor C2 and the first end of the seventh resistor R7, a second end of the seventh resistor R7 is respectively connected to the first end of the third capacitor C3, the first end of the eleventh field effect transistor M9, and the second end of the seventh resistor R7 is respectively connected to the first end of the third capacitor C3, the first end of the eleventh field effect transistor M10, and the first end of the eighth resistor R8. The source of M11, the drain of the eleventh field effect transistor M11, the drain of the ninth field effect transistor M9 and the differential unit 11 are connected, the second end of the eighth resistor R8 is respectively connected to the first end of the ninth resistor R9 and the drain of the eighth field effect transistor M8, the second end of the ninth resistor R9 is respectively connected to the source of the eighth field effect transistor M8, the first end of the fourth capacitor C4, the source of the tenth field effect transistor M10, the drain of the tenth field effect transistor M10, the source of the ninth field effect transistor M9 and the differential unit 11, the differential unit 11 is connected to the feedback module 40, the gate of the eighth field effect transistor M8 is connected to the output end of the fourth inverter INV4, the input end of the fourth inverter INV4 is connected to the conversion module 20, the second end of the fifth resistor R5, the second end of the second capacitor C2, the second end of the third capacitor C3 and the second end of the fourth capacitor C4 are all grounded. According to Figure 7 It can be seen that the input end of the fourth inverter INV4 is specifically connected to the control end of the lower tube S2 in the conversion module 20. The differential unit 11 is specifically connected to the second input end of the adder in the feedback module 40. In the embodiment of the present application, the ratio of the fourth resistor R4 to the fifth resistor R5 is 3:1.

[0063] Specifically, the voltage at the switch node SW is divided by the fourth resistor R4 and the fifth resistor R5, and then filtered to obtain the signal SW_RC1 and the signal SW_RC2. When the circuit is working normally, the signal detection module 60 outputs a first level signal (that is, the SET signal is low level). When the SET signal is low level, the ninth field effect tube M9 is disconnected, and the signal SW_RC1 and the signal SW_RC2 are respectively transmitted to the differential unit 11 for differential operation to obtain the ripple signal VRipple. In the process of the load 70 jumping from heavy load to light load, the signal detection module 60 outputs a second level signal (that is, the SET signal is high level). When the SET signal is high level, the ninth field effect tube M9 is turned on, so that the signal SW_RC1 is connected to the signal SW_RC2. After the signal SW_RC1 is connected to the signal SW_RC2, the differential unit 11 stops outputting the ripple signal VRipple, thereby avoiding the injection of negative ripple signals into the loop, so that the upper tube S1 will not be turned on during the rapid decrease of the load 70, and the overshoot suppression of the output voltage Vout is achieved.

[0064] The eighth field effect transistor M8 is used to control whether the ninth resistor R9 is connected to the branch where it is located, and by controlling the size of the resistance of the branch, the discharge current is reduced, and the DC error introduced by the injected ripple in the DC conversion circuit in the CCM (Continuous Conduction Mode) mode is eliminated. Specifically, since the lower tube S2 is an NMOS tube, when the lower tube S2 is turned on, the second drive signal LS_driver is at a high level, and the second drive signal LS_driver becomes a low level after passing through the fourth inverter INV4, then the eighth field effect transistor M8 is disconnected, and the ninth resistor R9 is connected to the branch where it is located. At this time, the fourth capacitor C4 discharges the switch node SW. Since the resistance of its discharge branch increases, the discharge current can be reduced. The above-mentioned method of eliminating the DC error introduced by the injected ripple in the DC conversion circuit in the CCM mode is not unique, and the same function can also be achieved through circuits such as S / H (sample / hold).

[0065] The tenth field effect transistor M10 and the eleventh field effect transistor M11 in the circuit are controlled by the SETB signal, and their functions are to offset the influence of clock feedthrough and charge injection effects.

[0066] It should be noted that, in the present application, when the load 70 changes from a heavy load to a light load, the signal SW_RC1 is connected to the signal SW_RC2, so as to achieve the purpose of suppressing the overshoot of the output voltage Vout. However, the present application is not limited to this implementation method, and can also be implemented by timely cutting off the ripple injection or reducing the impact of the injected ripple on the loop.

[0067] Exemplarily, the differential unit 11 may be implemented using a differential pair.

[0068] Combine the following Figure 8 and Fig. 9 The working principle of this application is explained again.

[0069] like Figure 8 As shown, the first logic signal HS_ONB is a logic signal for generating the first drive signal HS_driver. When the first logic signal HS_ONB is at a low level, the upper tube S1 is controlled to be turned on. The second logic signal LS_ONB is a logic signal for generating the second drive signal LS_driver. When the second logic signal LS_ONB is at a low level, the lower tube S2 is controlled to be turned on. The first signal MOS_ONB is a pulse signal for detecting the switching frequency, and its frequency is equal to the switching frequency of the DC conversion circuit, and the pulse width is approximately the time length before the lower tube S2 turns off the upper tube S1. The rising edge of the first signal MOS_ONB is triggered by the rising edge of the second logic signal LS_ONB, and the falling edge of the first signal MOS_ONB is triggered by the falling edge of the first logic signal HS_ONB. When the load 70 jumps from heavy load to light load, the first signal MOS_ONB needs to take a long time to flip to a high level, and the frequency of the first signal MOS_ONB is reduced. By using the change in the frequency of the first signal MOS_ONB, the detection of the switching frequency can be realized, and a signal for controlling whether the ripple injection module 10 outputs the ripple signal VRipple can be generated.

[0070] When the circuit works normally, the SET signal always maintains a low level, and only turns to a high level when it is detected that the interval between the falling edge of the first signal MOS_ONB and the next adjacent rising edge is greater than the set delay.

[0071] like Fig. 9 As shown, when the load 70 changes from a heavy load to a light load, the signal SW_RC1 (such as Fig. 9 The solid line in Fig. 9 ) and then decreases. In the time period from t2 to t3, the signal SW_RC1 is less than the signal SW_RC2. At t3, it is detected that the switching cycle increases to the set duration, and the SET signal flips to a high level. After the SET signal flips to a high level, the signal SW_RC1 is connected to the signal SW_RC2. After the signal SW_RC1 is connected to the signal SW_RC2, the differential unit 11 stops outputting the ripple signal VRipple, thereby avoiding the injection of a negative ripple signal into the loop, so that the upper tube S1 will not turn on during the rapid decrease of the load 70, thereby achieving overshoot suppression of the output voltage VOUT. At t4, the second logic signal LS_ONB flips to a high level, the SET signal flips to a low level, and the ripple injection module 10 outputs the ripple signal VRipple.

[0072] In summary, the present application detects the frequency of the first signal MOS_ONB through the signal detection module 60. When the frequency of the first signal MOS_ONB is less than the preset frequency, the signal SW_RC1 is connected to the signal SW_RC2, thereby avoiding the injection of negative ripple signals into the loop, so that the upper tube S1 will not be turned on during the rapid decrease of the load 70, thereby achieving overshoot suppression of the output voltage Vout.

[0073] The embodiment of the present application also provides a switching power supply, including the DC conversion circuit for suppressing overshoot described above. Since the switching power supply provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0074] The embodiment of the present application also provides an electronic device, including the DC conversion circuit for suppressing overshoot described above. Since the electronic device provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0075] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0076] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A DC conversion circuit for suppressing overshoot, characterized in that: It includes a ripple injection module, a conversion module, a driving module, a feedback module, a signal detection module and a signal generation module, wherein the conversion module is respectively connected to the feedback module, the driving module, the ripple injection module and the load, the feedback module is respectively connected to the driving module and the ripple injection module, the signal generation module is respectively connected to the driving module and the signal detection module, and the signal detection module is connected to the ripple injection module; The driving module is used to output a first driving signal, a second driving signal, a first logic signal and a second logic signal according to a control signal; the conversion module is used to convert an input voltage according to the first driving signal and the second driving signal to obtain an output voltage; the signal generation module is used to output a first signal according to the first logic signal and the second logic signal; The signal detection module is used to detect the first signal, and when the frequency of the first signal is greater than a preset frequency, output a first level signal to the ripple injection module, so that the ripple injection module outputs a ripple signal according to the first level signal and the voltage at the switch node in the conversion module, and then the feedback module outputs a control signal according to the ripple signal and the output voltage, and when the frequency of the first signal is less than the preset frequency, output a second level signal to the ripple injection module, so that the ripple injection module stops outputting the ripple signal; The signal generating module comprises a first inverter, a NOR gate, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a first resistor, a second resistor, a first NAND gate and a second NAND gate. The input end of the first inverter is connected to the driving module. The input end of the first inverter is used to receive the first logic signal. The output end of the first inverter is connected to the first input end of the NOR gate. The second input end of the NOR gate receives a first enable signal. The output end of the NOR gate is respectively connected to the gate of the first field effect transistor and the gate of the second field effect transistor. The source of the first field effect transistor and the source of the fourth field effect transistor both receive a power supply voltage. The drain of the first field effect transistor is respectively connected to the first end of the first resistor, the gate of the third field effect transistor, the drain of the fourth field effect transistor, and the drain of the first field effect transistor. The gate of the first resistor is connected to the gate of the fifth field effect transistor, the second end of the first resistor is connected to the drain of the second field effect transistor, the drain of the fourth field effect transistor is connected to the first end of the second resistor, the second end of the second resistor is respectively connected to the drain of the fifth field effect transistor and the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the driving module, the second input end of the first NAND gate is used to receive the second logic signal, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate receives the second enable signal, the output end of the second NAND gate is connected to the signal detection module, and the source of the second field effect transistor, the source of the third field effect transistor, the drain of the third field effect transistor and the source of the fifth field effect transistor are all grounded.

2. The DC conversion circuit for suppressing overshoot according to claim 1, characterized in that: The signal detection module includes a sixth field effect transistor, a seventh field effect transistor, a third resistor, a first capacitor, a Schmitt trigger, a second inverter, a third NAND gate and a third inverter. The gate of the sixth field effect transistor is respectively connected to the gate of the seventh field effect transistor and the signal generation module, the source of the sixth field effect transistor receives a power supply voltage, the drain of the sixth field effect transistor is connected to the first end of the third resistor, the second end of the third resistor is respectively connected to the drain of the seventh field effect transistor, the first end of the first capacitor and the input end of the Schmitt trigger, the output end of the Schmitt trigger is connected to the input end of the second inverter, the output end of the second inverter is connected to the first input end of the third NAND gate, the second input end of the third NAND gate receives a second enable signal, the output end of the third NAND gate is respectively connected to the input end of the third inverter and the ripple injection module, the output end of the third inverter is connected to the ripple injection module, and the source of the seventh field effect transistor and the second end of the first capacitor are both grounded.

3. The DC conversion circuit for suppressing overshoot according to claim 1, characterized in that: The ripple injection module includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second capacitor, a third capacitor, a fourth capacitor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a fourth inverter and a differential unit, wherein a first end of the fourth resistor is connected to a switch node in the conversion module, a second end of the fourth resistor is respectively connected to a first end of the fifth resistor, a first end of the sixth resistor and a first end of the eighth resistor, a second end of the sixth resistor is respectively connected to a first end of the second capacitor and a first end of the seventh resistor, and a second end of the seventh resistor is respectively connected to a first end of the third capacitor, a source of the eleventh field effect transistor, a The drain of the ninth field effect tube is connected to the differential unit, the second end of the eighth resistor is respectively connected to the first end of the ninth resistor and the drain of the eighth field effect tube, the second end of the ninth resistor is respectively connected to the source of the eighth field effect tube, the first end of the fourth capacitor, the source of the tenth field effect tube, the drain of the tenth field effect tube, the source of the ninth field effect tube and the differential unit, the differential unit is connected to the feedback module, the gate of the eighth field effect tube is connected to the output end of the fourth inverter, the input end of the fourth inverter is connected to the conversion module, the second end of the fifth resistor, the second end of the second capacitor, the second end of the third capacitor and the second end of the fourth capacitor are all grounded.

4. The DC conversion circuit for suppressing overshoot according to claim 1, characterized in that: The conversion module includes an upper tube, a lower tube, an inductor and an output capacitor, the first conduction end of the upper tube is used to receive the input voltage, the second conduction end of the upper tube is respectively connected to the first conduction end of the lower tube, the first end of the inductor and the ripple injection module, the control end of the upper tube and the control end of the lower tube are respectively connected to the driving module, the control end of the lower tube is also connected to the ripple injection module, the second conduction end of the lower tube is grounded, the second end of the inductor is respectively connected to the first end of the output capacitor, the feedback module and the load, and the second end of the output capacitor is grounded; wherein the common end of the second conduction end of the upper tube, the first conduction end of the lower tube and the first end of the inductor is a switch node.

5. The DC conversion circuit for suppressing overshoot according to claim 1, characterized in that: The feedback module includes a voltage divider unit, an operational amplifier, an adder, a comparator and an on-time generator. The voltage divider unit is respectively connected to the conversion module, the load, the first input terminal of the operational amplifier and the first input terminal of the adder. The second input terminal of the operational amplifier receives a reference voltage. The second input terminal of the adder is connected to the ripple injection module. The output terminal of the operational amplifier is connected to the first input terminal of the comparator. The output terminal of the adder is connected to the second input terminal of the comparator. The output terminal of the comparator is connected to the input terminal of the on-time generator. The output terminal of the on-time generator is connected to the driving module.

6. The DC conversion circuit for suppressing overshoot according to claim 5, characterized in that: The voltage divider unit includes a tenth resistor and an eleventh resistor, the first end of the tenth resistor is respectively connected to the conversion module and the load, the second end of the tenth resistor is respectively connected to the first end of the eleventh resistor, the first input end of the adder and the first input end of the operational amplifier, and the second end of the eleventh resistor is grounded.

7. The DC conversion circuit for suppressing overshoot according to claim 1, characterized in that: The driving module comprises a control unit, a first driving unit and a second driving unit, the control unit is connected to the first driving unit, the second driving unit and the feedback module respectively, and the first driving unit and the second driving unit are connected to the transformation module respectively; The control unit is used to output a first logic signal to the first drive unit and a second logic signal to the second drive unit according to the control signal; the first drive unit is used to output a first drive signal to the conversion module according to the first logic signal; the second drive unit is used to output a second drive signal to the conversion module according to the second logic signal.

8. A switching power supply, characterized in that: A DC conversion circuit for suppressing overshoot comprising the DC conversion circuit described in any one of claims 1 to 7.

9. An electronic device, characterized in that: A DC conversion circuit for suppressing overshoot comprising the DC conversion circuit described in any one of claims 1 to 7.

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