Power supply circuit and voltage converter

Abstract

The present application is applicable to the technical field of voltage converters, and provides a power supply circuit and a voltage converter. The power supply circuit includes a comparison module, a first logic module, a second logic module, a first switch module and a second switch module, the comparison module is electrically connected to the first logic module and the second logic module respectively, the first switch module is electrically connected to the second switch module and the first logic module respectively, the second switch module is electrically connected to the second logic module, the comparison module is used to receive an enable signal, an input voltage of a voltage conversion module in a voltage converter, and an output voltage of the voltage conversion module, the first switch module is used to receive an input voltage, the second switch module is used to receive an output voltage, and the first switch module and the second switch module are both used to be electrically connected to a gate drive module. When the enable signal of the power supply circuit provided in the embodiment of the present application is a low-level signal and the output voltage is greater than the input voltage, it can ensure that the current is small and controllable, and will not affect the chip.

Description

Technical Field

[0001] The present application belongs to the technical field of voltage converters, and in particular, relates to a power supply circuit and a voltage converter. Background Art

[0002] For voltage converters, especially synchronous rectification boost converters, it is usually hoped that complete isolation between input and output can be achieved in various scenarios. The inductor, power tube, freewheeling tube and output capacitor constitute the voltage conversion module of the boost converter. In order to achieve full isolation between input and output, the power supply circuit of the voltage conversion module is generally designed. However, when the existing power supply circuit is enabled and the output voltage is greater than the input voltage, it will cause the voltage conversion module to generate a large current, thereby burning the chip. Summary of the invention

[0003] The embodiments of the present application provide a power supply circuit and a voltage converter, which can solve the problem that when the existing power supply circuit is enabled to be shut down and the output voltage is greater than the input voltage, the voltage conversion module will generate a large current and then burn the chip.

[0004] In a first aspect, an embodiment of the present application provides a power supply circuit, including a comparison module, a first logic module, a second logic module, a first switch module, and a second switch module, wherein the comparison module is electrically connected to the first logic module and the second logic module, respectively, the first switch module is electrically connected to the second switch module and the first logic module, respectively, the second switch module is electrically connected to the second logic module, the comparison module is used to receive an enable signal, an input voltage of a voltage conversion module in a voltage converter, and an output voltage of the voltage conversion module, the first switch module is used to receive the input voltage, the second switch module is used to receive the output voltage, and the first switch module and the second switch module are both used to be electrically connected to a gate drive module in the voltage converter;

[0005] When the enable signal is a first level signal and the output voltage is greater than the input voltage, the comparison module is used to output a first comparison signal to the first logic module and the second logic module respectively according to the enable signal; the first logic module is used to output a first logic signal to the first switch module according to the enable signal and the first comparison signal, and the first switch module is used to shut down according to the first logic signal; the second logic module is used to output a second logic signal to the second switch module according to the enable signal and the first comparison signal, and the second switch module is used to shut down according to the second logic signal; the node voltage is equal to the difference between the output voltage and the preset voltage, and the node voltage is the voltage of the common end of the first switch module and the second switch module.

[0006] In a possible implementation of the first aspect, when the enable signal is the first level signal and the output voltage is equal to zero, the first logic module is used to output a third logic signal to the first switch module according to the output voltage, and the first switch module is used to be turned on according to the third logic signal so that the node voltage is equal to the input voltage.

[0007] In a possible implementation of the first aspect, the comparison module includes a comparator, a first input terminal of the comparator is used to receive the input voltage, a second input terminal of the comparator is used to receive the output voltage, an enable terminal of the comparator is used to receive the enable signal, and an output terminal of the comparator is electrically connected to the first logic module and the second logic module, respectively.

[0008] In a possible implementation manner of the first aspect, the first logic module includes a logic operation unit and a buffer unit, the logic operation unit is electrically connected to the comparison module and the buffer unit respectively, and the buffer unit is electrically connected to the first switch module and the second switch module respectively;

[0009] The logic operation unit is used to output a first operation signal to the buffer unit according to the enable signal and the first comparison signal; the buffer unit is used to receive the first operation signal and the output voltage, and output the first logic signal to the first switch module according to the first operation signal and the output voltage.

[0010] In a possible implementation of the first aspect, the logic operation unit includes an inverter and a NOR gate, the input end of the inverter is used to receive the enable signal, the output end of the inverter is electrically connected to the first input end of the NOR gate, the power supply end of the inverter and the power supply end of the NOR gate are both used to receive the node voltage, the ground end of the inverter and the ground end of the NOR gate are both grounded, the second input end of the NOR gate is electrically connected to the comparison module, and the output end of the NOR gate is electrically connected to the buffer unit.

[0011] In a possible implementation of the first aspect, the buffer unit includes a first buffer, an input end of the first buffer is electrically connected to the logic operation unit, an output end of the first buffer is electrically connected to the first switch module, a power supply end of the first buffer is used to receive the output voltage, and a ground end of the first buffer is grounded.

[0012] In a possible implementation of the first aspect, the second logic module includes a NAND gate and a second buffer, the first input end of the NAND gate is used to receive the enable signal, the second input end of the NAND gate is electrically connected to the comparison module, the output end of the NAND gate is electrically connected to the input end of the second buffer, the power supply end of the NAND gate and the power supply end of the second buffer are both used to receive the node voltage, the ground end of the NAND gate and the ground end of the second buffer are both grounded, and the output end of the second buffer is electrically connected to the second switch module.

[0013] In a possible implementation of the first aspect, the first switch module includes a first switch tube, a gate of the first switch tube is electrically connected to the first logic module, a source of the first switch tube is electrically connected to the second switch module, and a drain of the first switch tube is used to receive the input voltage.

[0014] In a possible implementation of the first aspect, the second switch module includes a second switch tube, a gate of the second switch tube is electrically connected to the second logic module, a source of the second switch tube is electrically connected to the first switch module, and a drain of the second switch tube is used to receive the output voltage.

[0015] In a second aspect, an embodiment of the present application provides a voltage converter, comprising a voltage conversion module, a gate drive module and the power supply circuit described in any one of the first aspects, wherein the voltage conversion module is electrically connected to the gate drive module and the second switch module in the power supply circuit, respectively, and the gate drive circuit is electrically connected to the first logic module, the second logic module, the first switch module and the second switch module in the power supply circuit, respectively.

[0016] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0017] The power supply circuit provided by the embodiment of the present application includes a comparison module, a first logic module, a second logic module, a first switch module and a second switch module, wherein the comparison module is used to receive an enable signal, an input voltage and an output voltage, and when the enable signal is a first level signal and the output voltage is greater than the input voltage, the comparison module outputs a first comparison signal to the first logic module and the second logic module respectively according to the enable signal. The first logic module outputs a first logic signal to the first switch module according to the enable signal and the first comparison signal, so that the first switch module is turned off. The second logic module outputs a second logic signal to the second switch module according to the enable signal and the first comparison signal, so that the second switch module is turned off. It can be seen that the power supply circuit provided by the embodiment of the present application, when the enable signal is a first level signal and the output voltage is greater than the input voltage, the first switch module and the second switch module are both in the off state. Therefore, the node voltage is neither equal to the input voltage nor the output voltage, but is equal to the difference between the output voltage and the preset voltage, wherein the preset voltage is the conduction voltage drop of the PN junction. Since the node voltage is used as the power supply voltage of the gate drive module, the gate drive module is electrically connected to the gate of the upper power tube in the voltage conversion module, and outputs the gate voltage to the gate of the upper power tube. Therefore, the gate voltage of the upper power tube in the voltage conversion module is equal to the node voltage. It can be obtained that the difference between the gate voltage of the upper power tube and the output voltage is the preset voltage, and the preset voltage is less than the conduction threshold voltage of the upper power tube, so the upper power tube is not turned on, and the output end of the voltage conversion module does not generate a large current, thereby ensuring that the current output from the output end of the voltage conversion module is small and controllable, and will not affect the chip, thereby improving the power supply safety.

[0018] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 It is a circuit connection diagram of a power supply circuit of an existing voltage conversion module;

[0021] Figure 2 is a principle block diagram of a power supply circuit provided in an embodiment of the present application;

[0022] Figure 3 It is a circuit connection diagram of a power supply circuit provided in an embodiment of the present application.

[0023] In the figure, 10, power supply circuit; 101, comparison module; 102, first logic module; 1021, logic operation unit; 1022, buffer unit; 103, second logic module; 104, first switch module; 105, second switch module; 20, gate drive module; 30, voltage conversion module. DETAILED DESCRIPTION

[0024] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0025] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0026] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0027] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0028] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0030] like Figure 1 As shown, the inductor L, the upper power tube P0, the lower power tube N0 and the output capacitor Cout constitute the voltage conversion module (power stage) of the boost converter. The gate drive module is used to control and drive the on and off of the upper power tube P0 according to IN and VPP_MAX. The comparator CMP, the inverter inv, buf1, buf2, P1 and P2 constitute the power supply circuit of the existing voltage conversion module, wherein the comparator CMP is used to receive the input voltage VIN and the output voltage VOUT, buf1 and buf2 are both in the same direction of input and output, VPP_MAX is the drive stage power supply voltage of P0, the PGATE voltage is used to control the on and off of P0, and VPP_MAX can only select the maximum voltage of input and output. Specifically, Figure 1 The operation of the power supply circuit shown mainly includes the following situations:

[0031] (1) If the enable signal of the comparator CMP is a high-level signal, when VIN>VOUT=0, net1 is a high-level signal, which is inverted by the inverter inv and output to net2. At this time, net2 is a low-level signal. After being processed by buf1, it is output to net5. Since buf1 has the same input and output direction, net5 is a low-level signal, thereby controlling P1 to conduct. During this process, P2 is not conducted, which makes VPP_MAX equal to the input voltage VIN, that is, PGATE is equal to the input voltage VIN, and P0 will not conduct.

[0032] (2) If the enable signal of the comparator CMP is a high-level signal, when VOUT>VIN=0, net1 is a low-level signal, which is processed by buf2 and output to net6. Since buf2 has the same input and output direction, net6 is a low-level signal, thereby controlling P2 to conduct. During this process, P1 is not conducted, making VPP_MAX equal to the output voltage VOUT, that is, PGATE is equal to the output voltage VOUT, and the VGS voltage of P0 is 0, which can control the normal switching of P0.

[0033] (3) When the enable signal of the comparator CMP is a low-level signal and VOUT>VIN, the net1 output by CMP is a high-level signal by default. After being inverted by the inverter inv, it outputs net2. At this time, net2 is a low-level signal. After being processed by buf1, it outputs net5. Since buf1 is in the same direction as the input and output, net5 is a low-level signal, thereby controlling P1 to turn on, and making VPP_MAX equal to the input voltage VIN. Since VPP_MAX is connected to the gate drive module, the gate voltage PGATE of the upper power tube P0 is VPP_MAX, that is, the input voltage VIN. Since the input voltage VIN is less than the output voltage VOUT, the upper power tube P0 is turned on, thereby generating a large current and burning the chip.

[0034] (4) When the enable signal of the comparator CMP is a low-level signal and VIN>VOUT, the net1 output by CMP is a high-level signal by default, so net5 is a low-level signal, thereby controlling P1 to turn on, and then making VPP_MAX equal to the input voltage VIN, that is, PGATE is equal to the input voltage VIN, and P0 will not turn on.

[0035] As can be seen from the above, when the existing power supply circuit is enabled and shut down and the output voltage VOUT is greater than the input voltage VIN, that is, situation (3), the voltage conversion module will generate a large current, thereby burning the chip.

[0036] Based on the above problems, the power supply circuit provided by the embodiment of the present application includes a comparison module, a first logic module, a second logic module, a first switch module and a second switch module, wherein the comparison module is used to receive an enable signal, an input voltage and an output voltage, and when the enable signal is a first level signal and the output voltage is greater than the input voltage, the comparison module outputs a first comparison signal to the first logic module and the second logic module respectively according to the enable signal. The first logic module outputs a first logic signal to the first switch module according to the enable signal and the first comparison signal to turn off the first switch module. The second logic module outputs a second logic signal to the second switch module according to the enable signal and the first comparison signal to turn off the second switch module. It can be seen from this that the power supply circuit provided by the embodiment of the present application, when the enable signal is a first level signal and the output voltage is greater than the input voltage, the first switch module and the second switch module are both in the off state. Therefore, the node voltage is neither equal to the input voltage nor the output voltage, but is equal to the difference between the output voltage and the preset voltage, wherein the preset voltage is the conduction voltage drop of the PN junction. Since the node voltage is used as the power supply voltage of the gate driving module, the gate driving module is electrically connected to the gate of the upper power tube in the voltage conversion module, and outputs the gate voltage to the gate of the upper power tube. Therefore, the gate voltage of the upper power tube in the voltage conversion module is equal to the node voltage. It can be obtained that the difference between the gate voltage and the output voltage of the upper power tube is the preset voltage, and the preset voltage is less than the conduction threshold voltage of the upper power tube, so the upper power tube is not turned on, and then the output end of the voltage conversion module will not generate a large current, thereby ensuring that the current output from the output end of the voltage conversion module is small and controllable, and will not affect the chip, thereby improving the power supply safety.

[0037] In order to illustrate the technical solution described in this application, a specific embodiment is provided below for illustration.

[0038] Figure 2 FIG. 1 shows a principle block diagram of a power supply circuit 10 provided in an embodiment of the present application. Figure 2As shown, the power supply circuit 10 includes a comparison module 101, a first logic module 102, a second logic module 103, a first switch module 104 and a second switch module 105. The comparison module 101 is electrically connected to the first logic module 102 and the second logic module 103 respectively, the first switch module 104 is electrically connected to the second switch module 105 and the first logic module 102 respectively, and the second switch module 105 is electrically connected to the second logic module 103. The comparison module 101 is used to receive an enable signal EN, an input voltage VIN of a voltage conversion module 30 in a voltage converter, and an output voltage VOUT of the voltage conversion module 30. The first switch module 104 is used to receive the input voltage VIN, and the second switch module 105 is used to receive the output voltage VOUT. The first switch module 104 and the second switch module 105 are both used to be electrically connected to the gate drive module 20 in the voltage converter.

[0039] Specifically, when the enable signal EN is a first level signal (for example, the first level signal is a low level signal), and the output voltage VOUT is greater than the input voltage VIN, the comparison module 101 outputs a first comparison signal to the first logic module 102 and the second logic module 103 according to the enable signal EN. The first logic module 102 outputs a first logic signal to the first switch module 104 according to the enable signal EN and the first comparison signal, so that the first switch module 104 is turned off. The second logic module 103 outputs a second logic signal to the second switch module 105 according to the enable signal EN and the first comparison signal, so that the second switch module 105 is turned off. It can be seen that the power supply circuit 10 provided in the embodiment of the present application is in a turned-off state when the enable signal EN is a low level signal and the output voltage VOUT is greater than the input voltage VIN. Therefore, the node voltage VMAX is neither equal to the input voltage VIN nor the output voltage VOUT, but is equal to the difference between the output voltage VOUT and the preset voltage, wherein the preset voltage is the conduction voltage drop of the PN junction (approximately 0.5V). Since the node voltage VMAX is used as the power supply voltage of the gate driving module 20, the gate driving module 20 is electrically connected to the gate of the upper power tube P0 in the voltage conversion module 30, and outputs the gate voltage PGATE to the gate of the upper power tube P0. Therefore, the gate voltage PGATE of the upper power tube P0 in the voltage conversion module 30 is equal to the node voltage VMAX. It can be obtained that the difference between the gate voltage PGATE of the upper power tube P0 and the output voltage VOUT is a preset voltage, and the preset voltage is less than the conduction threshold voltage of the upper power tube P0, so the upper power tube P0 is not turned on, and then the output end of the voltage conversion module 30 will not generate a large current, thereby ensuring that the current output from the output end of the voltage conversion module 30 is small and controllable, and will not affect the chip, thereby improving the power supply safety.

[0040] It should be noted that the above is only for Figure 1 The problem in the working situation (3) is that when the enable signal EN is a second level signal (for example, the second level signal is a high level signal), Figure 1 The working principle is similar and does not affect the selection of the node voltage VMAX. It is also specifically described in two cases. When the enable signal EN is a second level signal and the input voltage VIN is greater than the output voltage VOUT, the comparison module 101 outputs a second comparison signal according to the enable signal EN, the input voltage VIN and the output voltage VOUT. The first logic module 102 receives the enable signal EN and the second comparison signal, and outputs a fourth logic signal according to the enable signal EN and the second comparison signal to turn on the first switch module 104 and make the node voltage VMAX equal to the input voltage VIN. At this time, the upper power tube P0 is not turned on. When the enable signal EN is a second level signal and the output voltage VOUT is greater than the input voltage VIN, the comparison module 101 outputs a third comparison signal according to the enable signal EN, the input voltage VIN and the output voltage VOUT, and the second logic module 103 receives the enable signal EN and the third comparison signal, and outputs a fifth logic signal according to the enable signal EN and the third comparison signal, so that the second switch module 105 is turned on, so that the node voltage VMAX is equal to the output voltage VOUT, and the VGS voltage of the upper power tube P0 is 0, which can control the normal switching of the upper power tube P0.

[0041] It should be noted that, corresponding to Figure 1 In the working situation (4), the working situation of the power supply circuit 10 provided in the embodiment of the present application also includes: when the enable signal EN is a first level signal and the output voltage VOUT is equal to zero, the first logic module 102 outputs a third logic signal to the first switch module 104 according to the output voltage VOUT, and the first switch module 104 is turned on according to the third logic signal, so that the node voltage VMAX is equal to the input voltage VIN. At this time, the upper power tube P0 is not turned on, and there will be no leakage current, thereby ensuring that the current is small and controllable, and will not affect the chip. From the above, it can be seen that in the power supply circuit 10 provided in the embodiment of the present application, when the enable signal EN is a low level signal, regardless of whether the output voltage VOUT is greater than the input voltage VIN, or the input voltage VIN is greater than the output voltage VOUT (or the output voltage VOUT is zero), the upper power tube P0 is not turned on, the current is small and controllable, and the chip will not be damaged.

[0042] In one embodiment of the present application, Figure 3As shown, the comparison module 101 includes a comparator CMP, a first input terminal of the comparator CMP is used to receive an input voltage VIN, a second input terminal of the comparator CMP is used to receive an output voltage VOUT, an enable terminal of the comparator CMP is used to receive an enable signal EN, and an output terminal of the comparator CMP is electrically connected to the first logic module 102 and the second logic module 103 respectively.

[0043] Specifically, the comparator CMP can receive an enable signal EN and can be enabled according to the enable signal EN. Only when the enable signal EN is a high level signal, the comparator CMP compares the voltages of the two input terminals. The reverse input terminal of the comparator CMP is used as the first input terminal to receive the input voltage VIN, and the positive input terminal of the comparator CMP is used as the second input terminal to receive the output voltage VOUT. When the enable signal EN received by the comparator CMP is a high level signal, and the input voltage VIN is greater than the output voltage VOUT, the second comparison signal output by the comparator CMP is a low level signal. When the enable signal EN received by the comparator CMP is a high level signal, and the output voltage VOUT is greater than the input voltage VIN, the third comparison signal output by the comparator CMP is a high level signal. When the enable signal EN received by the comparator CMP is a low level signal, the first comparison signal output by the comparator CMP according to the enable signal EN defaults to a high level signal.

[0044] In one embodiment of the present application, Figure 3 As shown, the first logic module 102 includes a logic operation unit 1021 and a buffer unit 1022. The logic operation unit 1021 is electrically connected to the comparison module 101 and the buffer unit 1022 respectively. The buffer unit 1022 is electrically connected to the first switch module 104 and the second switch module 105 respectively.

[0045] Specifically, when the enable signal EN is a first level signal and the output voltage VOUT is greater than the input voltage VIN, the comparison module 101 outputs a first comparison signal, the logic operation unit 1021 receives the enable signal EN and the first comparison signal output by the comparison module 101, and performs a logic operation on the enable signal EN and the first comparison signal, and outputs a first operation signal to the buffer unit 1022 after the logic operation. The buffer unit 1022 receives the first operation signal and the output voltage VOUT, and outputs a first logic signal to the first switch module 104 according to the first operation signal and the output voltage VOUT. Specifically, if the enable signal EN is a first level signal and the output voltage VOUT is greater than the input voltage VIN, the buffer unit 1022 outputs a first logic signal to the first switch module 104 according to the first operation signal, so that the first switch module 104 is turned off. If the enable signal EN is a first level signal and the output voltage VOUT is zero, the buffer unit 1022 outputs a third logic signal to the switch module according to the output voltage VOUT to turn on the first switch module 104 and make the node voltage VMAX equal to the input voltage VIN, so that the upper power tube P0 will not be turned on.

[0046] In one embodiment of the present application, Figure 3 As shown, the logic operation unit 1021 includes an inverter inv and a NOR gate NOR, the input end of the inverter inv is used to receive an enable signal EN, the output end of the inverter inv is electrically connected to the first input end of the NOR gate NOR, the power supply end of the inverter inv and the power supply end of the NOR gate NOR are both used to receive the node voltage VMAX, the ground end of the inverter inv and the ground end of the NOR gate NOR are both grounded, the second input end of the NOR gate NOR is electrically connected to the comparison module 101, and the output end of the NOR gate NOR is electrically connected to the buffer unit 1022.

[0047] Specifically, after the inverter inv receives the enable signal EN, it inverts the enable signal EN and outputs it, that is, when the enable signal EN is a low level signal, the inverter inv outputs a high level signal; when the enable signal EN is a high level signal, the inverter inv outputs a low level signal. After the NOR gate NOR receives the first comparison signal and the signal output by the inverter inv, it performs a NOR operation on the first comparison signal and the signal output by the inverter inv, that is, the first comparison signal and the signal output by the inverter inv are firstly performed with an OR operation, and then the result after the OR operation is performed with a NOR operation, and finally the first operation signal is output. The specific operation logic of the NOR operation is: only when the first comparison signal and the signal output by the inverter inv are both low levels, the output end of the NOR gate NOR outputs a high level, otherwise, the output end of the NOR gate NOR outputs a low level. It can be seen that when the enable signal EN is a first level signal and the output voltage VOUT is greater than the input voltage VIN, the first comparison signal is a high level signal, so the first operation signal output by the output end of the NOR gate NOR is a low level signal.

[0048] It should be noted that this application only shows one component composition as the logic operation unit 1021, which does not mean that only this component composition can realize the function of the logic operation unit 1021. Other components that can realize this function can also be replaced, without limitation.

[0049] In one embodiment of the present application, Figure 3 As shown, the buffer unit 1022 includes a first buffer BUFF1, an input end of the first buffer BUFF1 is electrically connected to the logic operation unit 1021, an output end of the first buffer BUFF1 is electrically connected to the first switch module 104, a power supply end of the first buffer BUFF1 is used to receive the output voltage VOUT, and a ground end of the first buffer BUFF1 is grounded.

[0050] Specifically, the first buffer BUFF1 can enhance the driving capability of the signal to ensure that the first switch module 104 can respond reliably. In addition, the first buffer BUFF1 can filter out noise in the input signal to improve the stability and reliability of the signal.

[0051] It should be noted that the input and output of the first buffer BUFF1 are reversed, that is, when the input end of the first buffer BUFF1 receives a low-level signal, after being processed by the first buffer BUFF1, the first buffer BUFF1 outputs a high-level signal. When the input end of the first buffer BUFF1 receives a high-level signal, after being processed by the first buffer BUFF1, the first buffer BUFF1 outputs a low-level signal.

[0052] In one embodiment of the present application, Figure 3As shown, the second logic module 103 includes a NAND gate NAND and a second buffer BUFF2, the first input end of the NAND gate NAND is used to receive an enable signal EN, the second input end of the NAND gate NAND is electrically connected to the comparison module 101, the output end of the NAND gate NAND is electrically connected to the input end of the second buffer BUFF2, the power supply end of the NAND gate NAND and the power supply end of the second buffer BUFF2 are both used to receive a node voltage VMAX, the ground end of the NAND gate NAND and the ground end of the second buffer BUFF2 are both grounded, and the output end of the second buffer BUFF2 is electrically connected to the second switch module 105.

[0053] Specifically, after receiving the first comparison signal and the enable signal EN, the NAND gate NAND performs a NAND operation on the first comparison signal and the enable signal EN, that is, the first comparison signal and the enable signal EN are firstly performed with an AND operation, and then the result after the AND operation is performed with a NAND operation, and finally the NAND operation signal is output. The specific operation logic of the NAND operation is: only when the first comparison signal and the enable signal EN are both high levels, the output end of the NAND gate NAND outputs a low level, otherwise, the output end of the NAND gate NAND outputs a high level. It can be seen that when the enable signal EN is a first level signal and the output voltage VOUT is greater than the input voltage VIN, the first comparison signal is a high level signal, so the NAND operation signal output by the output end of the NAND gate NAND is a high level signal. The second buffer BUFF2 can enhance the driving capability of the signal and ensure that the second switch module 105 can respond reliably. And the second buffer BUFF2 can also filter out the noise in the input signal to improve the stability and reliability of the signal.

[0054] It should be noted that the input and output of the second buffer BUFF2 are in the same direction, that is, when the input end of the second buffer BUFF2 receives a low-level signal, after being processed by the second buffer BUFF2, the second buffer BUFF2 outputs a low-level signal. When the input end of the second buffer BUFF2 receives a high-level signal, after being processed by the second buffer BUFF2, the second buffer BUFF2 outputs a high-level signal.

[0055] It should be noted that this application only shows one component composition of the second logic module 103, which does not mean that only this component composition can realize the function of the second logic module 103. Other components that can realize the function can also be replaced, without limitation.

[0056] In one embodiment of the present application, Figure 3 As shown, the first switch module 104 includes a first switch tube Q1, a gate of the first switch tube Q1 is electrically connected to the first logic module 102, a source of the first switch tube Q1 is electrically connected to the second switch module 105, and a drain of the first switch tube Q1 is used to receive an input voltage VIN.

[0057] Specifically, the first switch tube Q1, as a switch device, can be turned off according to the first logic signal output by the first logic module 102, so that the node voltage VMAX is not equal to the input voltage VIN. The first switch tube Q1 can also be turned on according to the third logic signal / fourth logic signal output by the first logic module 102, so that the node voltage VMAX is equal to the input voltage VIN, so that the upper power tube P0 will not be turned on.

[0058] For example, designers can select the type of the first switch tube Q1 according to actual conditions, that is, fully controlled power devices such as metal oxide field effect transistors or insulated gate bipolar transistors can be used. For example, the first switch tube Q1 can be selected as a PMOS tube.

[0059] In one embodiment of the present application, Figure 3 As shown, the second switch module 105 includes a second switch tube Q2, the gate of the second switch tube Q2 is electrically connected to the second logic module 103, the source of the second switch tube Q2 is electrically connected to the first switch module 104, and the drain of the second switch tube Q2 is used to receive the output voltage VOUT.

[0060] Specifically, the second switch tube Q2, as a switch device, can be turned off according to the second logic signal output by the second logic module 103, so that the node voltage VMAX is not equal to the output voltage VOUT. The second switch tube Q2 can also be turned on according to the fifth logic signal output by the second logic module 103, so that the node voltage VMAX is equal to the output voltage VOUT, thereby turning on the upper power tube P0.

[0061] For example, the designer can select the type of the second switch tube Q2 according to the actual situation, that is, a fully controlled power device such as a metal oxide field effect transistor or an insulated gate bipolar transistor can be used. For example, the second switch tube Q2 can be selected as a PMOS tube.

[0062] Combine the following Figure 3 The working principle of the power supply circuit 10 provided in the embodiment of the present application is generally described, mainly including the following situations:

[0063] (1) If the enable signal EN of the comparator CMP is a high-level signal and the input voltage VIN is greater than the output voltage VOUT, the net1 output by the comparator CMP is a low-level signal. At this time, net2 is the inverted signal of the enable signal EN, which is a low-level signal. After the NOR gate NOR performs a NOR operation on net1 and net2, the output net3 is a high-level signal. Since the input and output of BUFF1 are reversed, the net5 output by BUFF1 based on net3 is a low-level signal, thereby driving the first switch tube Q1 to turn on, making the node voltage VMAX equal to the input voltage VIN. In this process, the NAND gate NAND performs a NAND operation on the enable signal EN and net1, and outputs net4 as a high-level signal. Since the input and output of BUFF2 are in the same direction, the net6 output by BUFF2 based on net4 is a high-level signal, thereby driving the second switch tube Q2 to turn off.

[0064] (2) If the enable signal EN of the comparator CMP is a high-level signal and the output voltage VOUT is greater than the input voltage VIN, the net1 output by the comparator CMP is a high-level signal. After the NAND gate NAND performs a NAND operation on the enable signal EN and net1, the output net4 is a low-level signal. Since the input and output of BUFF2 are in the same direction, the net6 output by BUFF2 based on net4 is a low-level signal, thereby driving the second switch tube Q2 to turn on, making the node voltage VMAX equal to the output voltage VOUT. In this process, net2 is the inverted signal of the enable signal EN, which is a low-level signal. After the NOR gate NOR performs a NOR operation on net1 and net2, the output net3 is a low-level signal. Since the input and output of BUFF1 are opposite, the net5 output by BUFF1 based on net3 is a high-level signal, thereby driving the first switch tube Q1 to turn off.

[0065] (3) If the enable signal EN of the comparator CMP is a low-level signal, and the output voltage VOUT is greater than the input voltage VIN, the net1 output by the comparator CMP defaults to a high-level signal, and net2 is the inverted signal of the enable signal EN, which is a high-level signal. After the NOR gate NOR performs a NOR operation on net1 and net2, the output net3 is a low-level signal. Since the input and output of BUFF1 are reversed, the net5 output by BUFF1 based on net3 is a high-level signal, thereby driving the first switch tube Q1 to turn off. At the same time, the NAND gate NAND performs a NAND operation on the enable signal EN and net1, and outputs net4 as a high-level signal. Since the input and output of BUFF2 are in the same direction, the net6 output by BUFF2 based on net4 is a high-level signal, thereby driving the second switch tube Q2 to turn off. At this time, the first switch tube Q1 and the second switch tube Q2 are both in the off state. Therefore, the node voltage VMAX is neither equal to the input voltage VIN nor the output voltage VOUT, but is equal to the difference between the output voltage VOUT and the preset voltage. Therefore, the upper power tube P0 is not turned on, thereby ensuring that the current is small and controllable and will not affect the chip.

[0066] (4) If the enable signal EN of the comparator CMP is a low-level signal, and the input voltage VIN is greater than the output voltage VOUT or the output voltage VOUT is equal to zero, since the supply voltage of BUFF1 is connected to the output voltage VOUT, the net5 voltage is equal to zero, the first switch tube Q1 is turned on, and the node voltage VMAX is equal to the input voltage VIN, that is, the gate voltage PGATE of the upper power tube P0 is equal to the input voltage VIN. At this time, the upper power tube P0 is not turned on, and there will be no leakage current.

[0067] The present application also discloses a voltage converter, including a voltage conversion module 30, a gate drive module 20 and the above-mentioned power supply circuit 10, wherein the voltage conversion module 30 is electrically connected to the gate drive module 20 and the second switch module 105 in the power supply circuit 10, respectively, and the gate drive circuit is electrically connected to the first logic module 102, the second logic module 103, the first switch module 104 and the second switch module 105 in the power supply circuit 10, respectively. Among them, the voltage conversion module 30 includes an inductor L, an upper power tube P0, a lower power tube N0 and an output capacitor Cout, which is used to boost the input voltage VIN and output the required output voltage VOUT. The gate drive module 20 is used to output a gate voltage PGATE to the gate of the upper power tube P0 according to the input signal IN to drive the upper power tube P0. The voltage converter adopts the above-mentioned power supply circuit 10, and the current can be small and controllable when the enable signal EN is a low-level signal and the output voltage VOUT is greater than the input voltage VIN, which will not affect the chip and improve the reliability of the voltage converter.

[0068] Since the processing and functions implemented by the voltage converter in this embodiment basically correspond to the embodiments, principles and examples of the aforementioned power supply circuit, for the details not fully described in this embodiment, please refer to the relevant descriptions in the aforementioned embodiments and will not be repeated here.

[0069] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A power supply circuit, characterized in that: The device comprises a comparison module, a first logic module, a second logic module, a first switch module and a second switch module, wherein the comparison module is electrically connected to the first logic module and the second logic module respectively, the first switch module is electrically connected to the second switch module and the first logic module respectively, the second switch module is electrically connected to the second logic module, the comparison module is used to receive an enable signal, an input voltage of a voltage conversion module in a voltage converter and an output voltage of the voltage conversion module, the first switch module is used to receive the input voltage, the second switch module is used to receive the output voltage, and a common node of the first switch module and the second switch module is used to be electrically connected to a gate drive module in the voltage converter; When the enable signal is a first level signal and the output voltage is greater than the input voltage, the comparison module is used to output a first comparison signal to the first logic module and the second logic module respectively according to the enable signal; wherein, the enable signal being a first level signal indicates that the power supply circuit is in an enabled off state; the first logic module is used to output a first logic signal to the first switch module according to the enable signal and the first comparison signal, and the first switch module is used to shut down according to the first logic signal; the second logic module is used to output a second logic signal to the second switch module according to the enable signal and the first comparison signal, and the second switch module is used to shut down according to the second logic signal; The node voltage is equal to the difference between the output voltage and the preset voltage, and the node voltage is the voltage of the common end of the first switch module and the second switch module.

2. The power supply circuit according to claim 1, characterized in that: When the enable signal is the first level signal and the output voltage is equal to zero, the first logic module is used to output a third logic signal to the first switch module according to the output voltage, and the first switch module is used to be turned on according to the third logic signal to make the node voltage equal to the input voltage.

3. The power supply circuit according to claim 1 or 2, characterized in that: The comparison module includes a comparator, a first input terminal of the comparator is used to receive the input voltage, a second input terminal of the comparator is used to receive the output voltage, an enable terminal of the comparator is used to receive the enable signal, and an output terminal of the comparator is electrically connected to the first logic module and the second logic module respectively.

4. The power supply circuit according to claim 1 or 2, characterized in that: The first logic module includes a logic operation unit and a buffer unit, the logic operation unit is electrically connected to the comparison module and the buffer unit respectively, and the buffer unit is electrically connected to the first switch module and the second switch module respectively; The logic operation unit is used to output a first operation signal to the buffer unit according to the enable signal and the first comparison signal; the buffer unit is used to receive the first operation signal and the output voltage, and output the first logic signal to the first switch module according to the first operation signal and the output voltage.

5. The power supply circuit according to claim 4, characterized in that: The logic operation unit includes an inverter and a NOR gate, the input end of the inverter is used to receive the enable signal, the output end of the inverter is electrically connected to the first input end of the NOR gate, the power supply end of the inverter and the power supply end of the NOR gate are both used to receive the node voltage, the ground end of the inverter and the ground end of the NOR gate are both grounded, the second input end of the NOR gate is electrically connected to the comparison module, and the output end of the NOR gate is electrically connected to the buffer unit.

6. The power supply circuit according to claim 4, characterized in that: The buffer unit includes a first buffer, an input end of the first buffer is electrically connected to the logic operation unit, an output end of the first buffer is electrically connected to the first switch module, a power supply end of the first buffer is used to receive the output voltage, and a ground end of the first buffer is grounded.

7. The power supply circuit according to claim 1 or 2, characterized in that: The second logic module includes a NAND gate and a second buffer, the first input end of the NAND gate is used to receive the enable signal, the second input end of the NAND gate is electrically connected to the comparison module, the output end of the NAND gate is electrically connected to the input end of the second buffer, the power supply end of the NAND gate and the power supply end of the second buffer are both used to receive the node voltage, the ground end of the NAND gate and the ground end of the second buffer are both grounded, and the output end of the second buffer is electrically connected to the second switch module.

8. The power supply circuit according to claim 1 or 2, characterized in that: The first switch module includes a first switch tube, a gate of the first switch tube is electrically connected to the first logic module, a source of the first switch tube is electrically connected to the second switch module, and a drain of the first switch tube is used to receive the input voltage.

9. The power supply circuit according to claim 1 or 2, characterized in that: The second switch module includes a second switch tube, a gate of the second switch tube is electrically connected to the second logic module, a source of the second switch tube is electrically connected to the first switch module, and a drain of the second switch tube is used to receive the output voltage.

10. A voltage converter, characterized in that: It includes a voltage conversion module, a gate drive module and the power supply circuit according to any one of claims 1 to 9, the voltage conversion module is electrically connected to the gate drive module and the second switch module in the power supply circuit respectively, and the gate drive circuit is electrically connected to the first logic module, the second logic module, the first switch module and the second switch module in the power supply circuit respectively.

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