Power-on reset circuits and electronic devices

Abstract

Embodiments of the present application relate to the field of integrated circuit technology, and provide a power-on reset circuit and electronic device that can significantly avoid the problem of reset signal mis-triggering or non-triggering due to process fluctuations and temperature changes, thereby improving the reliability of the device. The power-on reset circuit includes: a bandgap voltage reference module and an operational amplifier; the bandgap voltage reference module is configured to: control the resistance of each resistor unit in a first branch and the resistance of each resistor unit in a second branch, so that the bandgap voltage reference module has a first equilibrium voltage when the power supply voltage is in a rising phase, and has a second equilibrium voltage when the power supply voltage is in a falling phase, wherein the first equilibrium voltage is greater than the second equilibrium voltage; the operational amplifier is configured to amplify the difference between the voltage at the emitter of the first PNP transistor and the voltage at the signal input end of the third resistor unit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a power-on reset circuit and an electronic device. Background Art

[0002] The power-on reset (POR) circuit is a crucial component in analog integrated circuits. Its primary function is to generate a reset signal when the power supply voltage rises, ensuring that the system starts operating from a known initial state. With the continuous evolution of semiconductor processes, especially the widespread adoption of CMOS (Complementary Metal Oxide Semiconductor) technology, traditional POR circuit designs are prone to reset signal uncertainty under varying process, temperature (T), voltage (V), and process variation (P) conditions, leading to unreliable system initialization. Summary of the Invention

[0003] The embodiments of the present application provide a power-on reset circuit and an electronic device, which can significantly avoid the problem of false triggering or non-triggering of the reset signal due to process fluctuations and temperature changes, thereby improving the reliability of the device.

[0004] An embodiment of the present application provides a power-on reset circuit, comprising: a bandgap voltage reference module and an operational amplifier;

[0005] The bandgap voltage reference module includes a first branch and a second branch; the first branch includes a first PNP-type transistor, a first resistor unit, and a first bias resistor unit, the first bias resistor unit is arranged in parallel between the emitter and the collector of the first PNP-type transistor, the base and the collector of the first PNP-type transistor are electrically connected to the ground terminal, and the first resistor unit is arranged between a power supply and the emitter of the first PNP-type transistor;

[0006] The second branch includes a second PNP-type transistor, a second resistor unit, a second bias resistor unit, and a third resistor unit, the second resistor unit and the third resistor unit are arranged in series between the power supply and the emitter of the second PNP-type transistor, the signal input end of the third resistor unit is electrically connected to the second resistor unit, the signal output end of the third resistor unit is electrically connected to the emitter of the second PNP-type transistor, the base and collector of the second PNP-type transistor are electrically connected to the ground end, and the second bias resistor unit is arranged in parallel between the signal input end of the third resistor unit and the collector of the second PNP-type transistor;

[0007] The negative phase input terminal of the operational amplifier is electrically connected to the emitter of the first PNP transistor, and the positive phase input terminal of the operational amplifier is electrically connected to the signal input terminal of the third resistor unit;

[0008] The bandgap voltage reference module is configured to control the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch so that the bandgap voltage reference module has a first equilibrium voltage when the power supply voltage is in a rising phase, and has a second equilibrium voltage when the power supply voltage is in a falling phase, wherein the first equilibrium voltage is greater than the second equilibrium voltage. The first equilibrium voltage is the power supply voltage corresponding to when the power supply voltage is in a rising phase and the difference between the voltage at the emitter of the first PNP transistor and the voltage at the signal input end of the third resistor unit is zero; and the second equilibrium voltage is the power supply voltage corresponding to when the power supply voltage is in a falling phase and the difference between the voltage at the emitter of the first PNP transistor and the voltage at the signal input end of the third resistor unit is zero.

[0009] The operational amplifier is used to amplify the difference between the voltage of the emitter of the first PNP transistor and the voltage of the signal input end of the third resistor unit.

[0010] According to some embodiments of the present application, the power-on reset circuit further includes: a trigger; the output terminal of the operational amplifier is electrically connected to the input terminal of the trigger;

[0011] The trigger is used to:

[0012] When the voltage of the power supply is in a rising stage, when the voltage signal received by the negative phase input terminal of the operational amplifier is greater than or equal to the voltage signal received by the positive phase input terminal of the operational amplifier, a high level signal is output; when the voltage signal received by the negative phase input terminal of the operational amplifier is less than the voltage signal received by the positive phase input terminal of the operational amplifier, a low level signal is output;

[0013] When the voltage of the power supply is in a decreasing stage, when the voltage signal received by the negative input terminal of the operational amplifier is less than the voltage signal received by the positive input terminal of the operational amplifier, the low-level signal is output; when the voltage signal received by the negative input terminal of the operational amplifier is greater than or equal to the voltage signal received by the positive input terminal of the operational amplifier, the high-level signal is output.

[0014] According to some embodiments of the present application, the first bias resistor unit and the second bias resistor unit have the same structure;

[0015] The first resistance unit is configured to have a first resistance value under the control of the high-level signal; and is configured to have a second resistance value under the control of the low-level signal; the first resistance value is greater than the second resistance value;

[0016] The first bias resistor unit is configured to have a third resistance value under the control of the high-level signal; and is configured to have a fourth resistance value under the control of the low-level signal; and the third resistance value is smaller than the fourth resistance value.

[0017] According to some embodiments of the present application, the resistance value of the third resistance unit is fixed.

[0018] According to some embodiments of the present application, the resistance of the first bias resistor unit is M times the resistance of the third resistor unit, where M is greater than or equal to 6.

[0019] According to some embodiments of the present application, the second resistance unit and the first resistance unit have the same structure; the emitter area of ​​the second PNP transistor is N times the emitter area of ​​the first PNP transistor, and N is greater than 1.

[0020] According to some embodiments of the present application, the resistance of the second resistance unit is N times the resistance of the first resistance unit, and N is greater than 1; the emitter area of ​​the second PNP transistor is the same as the emitter area of ​​the first PNP transistor.

[0021] According to some embodiments of the present application, the first resistance unit includes a first switch, and a first resistor and a second resistor connected in series, the first resistor and the first switch being arranged in parallel; the first resistor being arranged between the power supply and the second resistor; the first switch being configured to remain in an off state under the control of the high-level signal, and to remain in an on state under the control of the low-level signal;

[0022] The first bias resistor unit includes a second switch, and a first bias resistor and a second bias resistor connected in series, the second bias resistor and the second switch being arranged in parallel; the second bias resistor being arranged between the first bias resistor and the ground terminal; the second switch being configured to remain in an on state under the control of the high-level signal and remain in an off state under the control of the low-level signal;

[0023] The second resistor unit includes a third switch, and a fourth resistor and a fifth resistor connected in series, wherein the fourth resistor and the third switch are arranged in parallel; the fourth resistor is arranged between the power supply and the fifth resistor; the third switch is configured to remain in an off state under the control of the high-level signal and to remain in a on state under the control of the low-level signal;

[0024] The second bias resistor unit includes a fourth switch, and a third bias resistor and a fourth bias resistor connected in series, wherein the fourth bias resistor and the fourth switch are arranged in parallel; the fourth bias resistor is arranged between the third bias resistor and the ground terminal; the fourth switch is configured to maintain an on state under the control of the high-level signal and maintain an off state under the control of the low-level signal;

[0025] The third resistance unit includes a third resistor.

[0026] According to some embodiments of the present application, the power-on reset circuit further includes an inverter;

[0027] The trigger includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor and a fifth N-type transistor;

[0028] The source of the first P-type transistor is electrically connected to the power supply, the drain of the first P-type transistor, the source of the second P-type transistor, and the source of the third P-type transistor are electrically connected, the drain of the second P-type transistor, the drain of the first N-type transistor, the gate of the third P-type transistor, and the gate of the third N-type transistor are electrically connected, the drain of the third N-type transistor is electrically connected to the ground terminal, the source of the first N-type transistor, the drain of the second N-type transistor, and the drain of the third N-type transistor are electrically connected, the source of the third N-type transistor is electrically connected to the power supply, the source of the second N-type transistor, the drain and gate of the fourth N-type transistor, and the drain of the fifth N-type transistor are electrically connected, the sources of the fourth N-type transistor and the fifth N-type transistor are electrically connected to the ground terminal, the gates of the first P-type transistor, the second P-type transistor, the first N-type transistor, and the second N-type transistor are all electrically connected to the output terminal of the operational amplifier, and the gate of the fifth N-type transistor is electrically connected to the output terminal of the inverter;

[0029] The drain of the second P-type transistor is used as the output terminal of the trigger, the input terminal of the inverter is electrically connected to the drain of the second P-type transistor, and the inverter is used to invert the signal output by the trigger.

[0030] According to some embodiments of the present application, another aspect of the present application provides an electronic device, including: the above-mentioned power-on reset circuit.

[0031] Embodiments of the present application provide a power-on reset circuit and electronic device. When a power supply voltage VDDX is in a rising phase, the power-on reset circuit controls the resistance of each resistor unit in a first branch and the resistance of each resistor unit in a second branch, so that the power-on reset circuit has a first equilibrium voltage. When the power supply voltage VDDX is in a falling phase, the power-on reset circuit controls the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch, so that the power-on reset circuit has a second equilibrium voltage, wherein the first equilibrium voltage is greater than the second equilibrium voltage. Thus, when the power supply voltage VDDX is slowly rising or falling, even if the power supply voltage fluctuates upward or downward due to process fluctuations or temperature changes, because the first equilibrium voltage in the rising phase is greater than the second equilibrium voltage in the falling phase, the power supply voltage will not reach the second equilibrium voltage during the rising phase of equilibrium fluctuations, or will not reach the first equilibrium voltage during the falling phase of equilibrium fluctuations, thereby preventing the problem of false triggering or non-triggering of the reset signal. The power-on reset circuit provided by embodiments of the present application can significantly avoid the problem of false triggering or non-triggering of the reset signal due to process fluctuations and temperature changes, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of the structure of a power-on reset circuit provided in an embodiment of the present application;

[0034] Figure 2 A schematic structural diagram of another power-on reset circuit provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the signal output of a Schmitt trigger provided for related technologies;

[0036] Figure 4 A schematic diagram of the signal output by the trigger provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0038] In the description of the embodiments of the present application, "at least one" means one or more, "a plurality of" means two or more, and "multiple times" means two or more, unless otherwise clearly and specifically defined.

[0039] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features.

[0040] In the description of the embodiments of the present application, the character “ / ” generally indicates that the preceding and following associated objects are in an “or” relationship.

[0041] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0042] In the description of the embodiments of the present application, when a component “includes” another component, unless otherwise stated, other components are not excluded, and other components may be further included.

[0043] Traditional MOS (Metal Oxide Semiconductor)-based POR circuits are susceptible to process fluctuations and temperature changes, resulting in reset signal mis-triggering or non-triggering. Related art power-on reset circuits only have a single equilibrium voltage, which remains the same when the power supply voltage is rising and falling. Consequently, as the power supply voltage slowly rises or falls, the circuit's trigger point can easily drift, causing reset signal instability. For example, when the power supply voltage is slowly rising, it reaches the voltage trigger point and enters the reset state. At this point, if noise is introduced due to process fluctuations and temperature changes, the power supply voltage can easily fluctuate upward or downward due to the noise, causing the power supply voltage to fluctuate around the voltage trigger point, making the reset signal extremely unstable and prone to mis-triggering or non-triggering.

[0044] Based on this, the embodiment of the present application provides a power-on reset circuit, referring to Figure 1 and Figure 2 As shown, it includes: a bandgap voltage reference module 1 and an operational amplifier 2.

[0045] refer to Figure 1 and Figure 2 As shown, the bandgap voltage reference module 1 includes a first branch and a second branch; the first branch includes a first PNP transistor Q1, a first resistor unit 11 and a first bias resistor unit 12, the first bias resistor unit 12 is arranged in parallel between the emitter and the collector of the first PNP transistor Q1, the base and the collector of the first PNP transistor Q1 are electrically connected to the ground end, and the first resistor unit 11 is arranged between the power supply and the emitter of the first PNP transistor Q1.

[0046] refer to Figure 1 and Figure 2 As shown, the second branch includes a second PNP transistor Q2, a second resistor unit 13, a second bias resistor unit 14 and a third resistor unit 15. The second resistor unit 13 and the third resistor unit 15 are arranged in series between the power supply and the emitter of the second PNP transistor Q2. The signal input end of the third resistor unit 15 is electrically connected to the second resistor unit 13, and the signal output end of the third resistor unit 15 is electrically connected to the emitter of the second PNP transistor Q2. The base and collector of the second PNP transistor Q2 are electrically connected to the ground end. The second bias resistor unit 14 is arranged in parallel between the signal input end of the third resistor unit 15 and the collector of the second PNP transistor Q2.

[0047] refer to Figure 1 and Figure 2As shown, the negative phase input terminal of the operational amplifier 2 is electrically connected to the emitter of the first PNP transistor Q1 , and the positive phase input terminal of the operational amplifier 2 is electrically connected to the signal input terminal of the third resistor unit 15 .

[0048] refer to Figure 1 and Figure 2 As shown, the bandgap voltage reference module 1 is used to: by controlling the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch, the bandgap voltage reference module has a first equilibrium voltage when the voltage vddx of the power supply is in the rising phase, and has a second equilibrium voltage when the voltage vddx of the power supply is in the falling phase, wherein the first equilibrium voltage is greater than the second equilibrium voltage, wherein the first equilibrium voltage is the voltage of the emitter of the first PNP transistor Q1 when the voltage of the power supply is in the rising phase. V be1 and the voltage at the signal input terminal of the third resistor unit 15 V be2_amp the second equilibrium voltage is when the power supply voltage is in the falling stage, the emitter voltage of the first PNP transistor Q1 and the voltage of the signal input terminal of the third resistor unit 15 is zero when the power supply voltage corresponds to.

[0049] refer to Figure 1 and Figure 2 As shown, the operational amplifier 2 is used to amplify the difference between the voltage at the emitter of the first PNP transistor Q1 and the voltage at the signal input end of the third resistor unit 15 , and output a signal Vin_smt.

[0050] refer to Figure 1 and Figure 2 As shown, the ground terminal can provide a ground voltage vssx.

[0051] In the embodiment of the present application, the first PNP transistor and the second PNP transistor are bipolar junction transistors (BJT). Compared with NPN transistors, PNP transistors are more widely compatible with various CMOS processes, reducing design adjustments caused by different processes.

[0052] In the first branch of the embodiment of the present application, the specific structures of the first resistor unit and the first bias resistor unit are not limited; in the second branch of the embodiment of the present application, the specific structures of the second resistor unit, the second bias resistor unit and the third resistor unit are not limited.

[0053] In the embodiments of the present application, the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch directly affect the magnitude of the equilibrium voltage (i.e., the voltage trigger point). The embodiments of the present application do not limit the specific method for controlling the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch. For example, a portion of the structure of a resistor unit can be configured as a variable resistor, and the remaining portion can be configured as a fixed resistor. By controlling the resistance of the variable resistor, the resistance of the resistor unit can be controlled. Alternatively, a switch can be configured to control a portion of the structure of the resistor unit, thereby controlling the resistance of the resistor unit. Of course, other control methods can also be used, and will not be detailed here.

[0054] In an embodiment of the present application, controlling the resistance of each resistor unit in the first branch can be achieved by separately controlling the first resistor unit and the first bias resistor unit in the first branch, that is, both the first resistor unit and the first bias resistor unit are controllable; or, only the first resistor unit can be controlled, and the resistance of the first bias resistor unit is fixed; or, only the first bias resistor unit can be controlled, and the resistance of the first resistor unit is fixed; this is not limited here.

[0055] In an embodiment of the present application, controlling the resistance value of each resistor unit in the second branch may be achieved by separately controlling the second resistor unit, the second bias resistor unit, and the third resistor unit in the second branch, that is, the second resistor unit, the second bias resistor unit, and the third resistor unit are all controllable; or, only part of the second resistor unit, the second bias resistor unit, and the third resistor unit may be controlled. For example, the second resistor unit and the second bias resistor unit in the second branch may be separately controlled, and the resistance value of the third resistor unit is fixed; this is not limited here.

[0056] In the embodiment of the present application, the first balancing voltage is greater than the second balancing voltage. To further ensure the stability of the reset signal, the difference between the first balancing voltage and the second balancing voltage can be greater than or equal to a preset value. The preset value can be determined based on noise signals generated by process fluctuations and temperature changes. For example, the preset value can be 45mV, 50mV, or 55mV. The specific values ​​of the first balancing voltage and the second balancing voltage need to be determined based on the specific circuit structures of the first branch and the second branch and are not limited here.

[0057] The power-on reset circuit provided in the embodiments of the present application has a hysteresis characteristic. Specifically, when the power supply voltage VDDX is in a rising phase, the power-on reset circuit maintains a first equilibrium voltage by controlling the resistance values ​​of each resistor unit in the first branch and the resistance values ​​of each resistor unit in the second branch. When the power supply voltage VDDX is in a falling phase, the power-on reset circuit maintains a second equilibrium voltage by controlling the resistance values ​​of each resistor unit in the first branch and the resistance values ​​of each resistor unit in the second branch. The first equilibrium voltage is greater than the second equilibrium voltage. Thus, when the power supply voltage VDDX is slowly rising or falling, even if the power supply voltage fluctuates upward or downward due to process fluctuations or temperature changes, because the first equilibrium voltage in the rising phase is greater than the second equilibrium voltage in the falling phase, the power supply voltage will not reach the second equilibrium voltage during the rising phase, or will not reach the first equilibrium voltage during the falling phase. Consequently, the reset signal will not be falsely triggered or not triggered. The power-on reset circuit provided in the embodiments of the present application can significantly avoid the reset signal false triggering or not triggering caused by process fluctuations and temperature changes, thereby improving device reliability.

[0058] In one or more embodiments, in order to reduce the influence of noise on the output signal of the operational amplifier, reference Figure 2 As shown, the power-on reset circuit further includes: a trigger 3 ; the output end of the operational amplifier 2 is electrically connected to the input end of the trigger 3 .

[0059] Trigger 3 is used to:

[0060] When the voltage of the power supply is in the rising stage, when the voltage signal received by the negative input terminal of the operational amplifier 2 is greater than or equal to the voltage signal received by the positive input terminal of the operational amplifier 2, a high-level signal is output. At this time, the voltage of the power supply is less than or equal to the first equilibrium voltage; when the voltage signal received by the negative input terminal of the operational amplifier 2 is less than the voltage signal received by the positive input terminal of the operational amplifier 2, a low-level signal is output. At this time, the voltage of the power supply is greater than the first equilibrium voltage.

[0061] When the voltage of the power supply is in a decreasing stage, when the voltage signal received by the negative input terminal of the operational amplifier 2 is less than the voltage signal received by the positive input terminal of the operational amplifier 2, a low-level signal is output. At this time, the voltage of the power supply is greater than or equal to the second equilibrium voltage; when the voltage signal received by the negative input terminal of the operational amplifier 2 is greater than or equal to the voltage signal received by the positive input terminal of the operational amplifier 2, a high-level signal is output. At this time, the voltage of the power supply is less than the second equilibrium voltage.

[0062] The voltage of the high-level signal is greater than the voltage of the low-level signal. The definitions of high and low levels are not specifically limited here. For example, a signal that fluctuates within a range of ±5% to ±10% of the power supply voltage is generally referred to as a high-level signal, and a signal that fluctuates within a range of ±5% to ±10% of the insulation ground voltage is referred to as a low-level signal. Of course, other definitions of high and low-level signals are possible, and will not be elaborated upon here.

[0063] The embodiments of the present application do not limit the specific structure of the trigger. For example, the trigger may be a Schmitt trigger or an improved Schmitt trigger.

[0064] A resistance control method for the first resistor unit and the first bias resistor unit is provided below.

[0065] The first resistance unit is configured to have a first resistance value under the control of a high-level signal; and is configured to have a second resistance value under the control of a low-level signal; the first resistance value is greater than the second resistance value; the first bias resistance unit is configured to have a third resistance value under the control of a high-level signal; and is configured to have a fourth resistance value under the control of a low-level signal; the third resistance value is less than the fourth resistance value.

[0066] In an embodiment of the present application, the signal output by the trigger is fed back to the first resistor unit. When the signal is a high-level signal, the first resistor unit has a first resistance value; when the signal is a low-level signal, the first resistor unit has a second resistance value, wherein the first resistance value is greater than the second resistance value. Similarly, the signal output by the trigger is fed back to the first bias resistor unit. When the signal is a high-level signal, the first bias resistor unit has a third resistance value; when the signal is a low-level signal, the first bias resistor unit has a fourth resistance value, wherein the third resistance value is less than the fourth resistance value.

[0067] In the embodiment of the present application, the difference range between the first resistance value and the second resistance value is not limited, and the difference range between the third resistance value and the fourth resistance value is not limited.

[0068] Based on the resistance control method of the first resistor unit and the first bias resistor unit described above, to reduce design difficulty, the resistance value of the third resistor unit is fixed; the second bias resistor unit has the same structure as the first bias resistor unit. In this case, the second bias resistor unit and the first bias resistor unit have the same resistance value. Similarly, the second bias resistor unit is configured to have a third resistance value under the control of a high-level signal and a fourth resistance value under the control of a low-level signal; the third resistance value is less than the fourth resistance value.

[0069] To further reduce design difficulty, the resistance of the first bias resistor unit is M times the resistance of the third resistor unit, where M is greater than or equal to 6. For example, M can be 6, 7, 8, 9, 10, 11, 12, or 13. In this case, it can be considered that the resistance of the first bias resistor unit is much greater than the resistance of the third resistor unit.

[0070] It should be noted that the ratio of the resistance value of the second resistor unit to the resistance value of the first resistor unit is related to the ratio of the emitter area of ​​the second PNP transistor to the emitter area of ​​the first PNP transistor; by setting these two ratios, when the voltage of the power supply is the first equilibrium voltage or the second equilibrium voltage, the voltage of the emitter of the first PNP transistor is V be1 and the voltage at the signal input terminal of the third resistor unit V be2_amp The difference is zero, that is, the emitter voltage V be1 and the voltage V at the signal input terminal of the third resistor unit be2_amp same.

[0071] In some embodiments, the second resistance unit and the first resistance unit have the same structure, and the ratio of the resistance value of the second resistance unit to the resistance value of the first resistance unit is 1:1; the emitter area of ​​the second PNP type transistor is N times the emitter area of ​​the first PNP type transistor, and N is greater than 1, and the ratio of the emitter area of ​​the second PNP type transistor to the emitter area of ​​the first PNP type transistor is N:1.

[0072] In some embodiments, the resistance of the second resistance unit is N times the resistance of the first resistance unit, and N is greater than 1, then the ratio of the resistance of the second resistance unit to the resistance of the first resistance unit is N:1; the emitter area of ​​the second PNP-type transistor is the same as the emitter area of ​​the first PNP-type transistor, then the ratio of the emitter area of ​​the second PNP-type transistor to the emitter area of ​​the first PNP-type transistor is 1:1.

[0073] The following provides a specific circuit structure of the first branch and the second branch.

[0074] refer to Figure 1 and Figure 2 As shown, the first resistance unit 11 includes a first switch Msw1, and a first resistor R12 and a second resistor R11 connected in series, and the first resistor R12 and the first switch Msw1 are arranged in parallel; the first resistor R12 is arranged between the power supply and the second resistor R11; the first switch Msw1 is used to maintain an off state under the control of a high-level signal; and maintain an on state under the control of a low-level signal.

[0075] refer to Figure 1 and Figure 2 As shown, the first bias resistor unit 12 includes a second switch Msw2, and a first bias resistor Rsw1 and a second bias resistor Rsw2 connected in series, and the second bias resistor Rsw2 and the second switch Msw2 are arranged in parallel; the second bias resistor Rsw2 is arranged between the first bias resistor Rsw1 and the ground terminal vssx; the second switch Msw2 is used to maintain an on state under the control of a high-level signal; and maintain an off state under the control of a low-level signal.

[0076] refer to Figure 1 and Figure 2 As shown, the second resistance unit 13 includes a third switch Msw3, and a fourth resistor R22 and a fifth resistor R21 connected in series, and the fourth resistor R22 and the third switch Msw3 are arranged in parallel; the fourth resistor R22 is arranged between the power supply and the fifth resistor R21; the third switch Msw3 is used to maintain an off state under the control of a high-level signal; and maintain an on state under the control of a low-level signal.

[0077] refer to Figure 1 and Figure 2 As shown, the second bias resistor unit 14 includes a fourth switch Msw4, and a third bias resistor Rsw3 and a fourth bias resistor Rsw4 connected in series, and the fourth bias resistor Rsw4 and the fourth switch Msw4 are arranged in parallel; the fourth bias resistor Msw4 is arranged between the third bias resistor and the ground terminal; the fourth switch Msw4 is used to maintain an on state under the control of a high-level signal; and maintain an off state under the control of a low-level signal.

[0078] refer to Figure 1 and Figure 2 As shown, the third resistance unit 15 includes a third resistor R3.

[0079] It should be noted that in the first branch and the second branch, the resistance setting of each resistor unit can refer to any of the above-mentioned methods. The first switch Msw1 and the third switch Msw3 are both P-type transistors, and the second switch Msw2 and the fourth switch Msw4 are both N-type transistors. Two setting methods are specifically described below. In the first method, the first bias resistor unit and the second bias resistor unit have the same structure. In this case, the resistance of the first bias resistor Rsw1 is the same as the resistance of the third bias resistor Rsw3, and the resistance of the second bias resistor Rsw2 is the same as the resistance of the fourth bias resistor Rsw4; the first resistor unit and the second resistor unit have the same structure. In this case, the resistance of the first resistor R12 is the same as the resistance of the fourth resistor R22, and the resistance of the second resistor R11 is the same as the resistance of the fifth resistor R21; the emitter area of ​​the second PNP transistor Q2 is N times the emitter area of ​​the first PNP transistor Q1, where N is greater than 1.

[0080] The second type, the first bias resistor unit and the second bias resistor unit have the same structure. In this case, the resistance of the first bias resistor Rsw1 is the same as the resistance of the third bias resistor Rsw3, and the resistance of the second bias resistor Rsw2 is the same as the resistance of the fourth bias resistor Rsw4; the resistance of the second resistor unit is N times the resistance of the first resistor unit, and N is greater than 1. In this case, the resistance of the fifth resistor R21 is N times the resistance of the second resistor R11, and the resistance of the fourth resistor R22 is N times the resistance of the first resistor R12; the emitter area of ​​the second PNP transistor Q2 is the same as the emitter area of ​​the first PNP transistor Q1.

[0081] The following takes the first structure as an example to illustrate the derivation process of the first equilibrium voltage and the second equilibrium voltage.

[0082] refer to Figure 1 and Figure 2 As shown, when the power supply voltage reaches a balanced state, the following formula needs to be satisfied:

[0083]

[0084]

[0085]

[0086]

[0087]

[0088]

[0089]

[0090] in, V be1 is the emitter voltage of the first PNP transistor Q1, V be2_amp is the voltage at the signal input terminal of the third resistor R3, V be2 is the emitter voltage of the second PNP transistor Q2, V T is the thermal voltage, the voltage at the signal input end of the third resistor R3, I c1 is the current flowing into the emitter of the first PNP transistor Q1, I c2 is the current flowing into the emitter of the second PNP transistor Q2, I 1 is the current passing through the first resistor R12, I 2 is the current passing through the fifth resistor R21, Is is the saturation current of the first PNP transistor Q1, R sw is the resistance value of the second bias resistor unit, R 3 is the resistance of the third resistor R3, and N is the ratio of the emitter area of ​​the second PNP transistor Q2 to the emitter area of ​​the first PNP transistor Q1. V T The calculation formula of can be obtained according to relevant technologies and will not be described in detail here.

[0091] According to formula (5), formula (1) and formula (2), we can get:

[0092]

[0093] Substituting formula (4) into formula (8), we can obtain:

[0094]

[0095] According to formula (3) and formula (9), we can get:

[0096]

[0097] Subtracting both sides of formula (6) and formula (7) and performing corresponding calculations yields:

[0098]

[0099] The voltage of the power supply in a balanced state V tp for:

[0100]

[0101]

[0102]

[0103]

[0104]

[0105]

[0106] when R sw >> R 3, formula (12) can be simplified to:

[0107]

[0108]

[0109] Among them, the right side is the standard bandgap unit voltage V bg The calculation formula is

[0110]

[0111] From formula (13), we can get that when the positive temperature coefficient term Can compensate V be2 When the negative temperature coefficient is , formula (13) can achieve temperature balance and has small fluctuations under different process angles. In addition, adjusting The size of the power-on reset circuit can be adjusted V tp The size of the balance voltage can be adjusted.

[0112] In other words, each resistor unit in the first and second branches is not only used to adjust the balance point of the power supply voltage, but also serves as an adjustment element for the transistor temperature compensation effect, ensuring that the circuit can still operate accurately at different temperatures. The power-on reset circuit provided in the embodiment of the present application avoids the drift of the corresponding VDDX flip voltage point due to semiconductor process errors through precise resistor ratio design, achieving process invariance. The combination of the PNP BJT and the resistor network avoids the drift of the corresponding VDDX flip voltage point caused by different temperatures, thereby improving the stability of the system.

[0113] In the embodiment of the present application, when the voltage of the power supply is in the rising stage and the voltage of the power supply is less than or equal to the first equilibrium voltage (that is, the voltage of the power supply is in a balanced state or before reaching a balanced state), the trigger outputs a high-level signal (POR=1). Under the control of the high-level signal, the first switch Msw1 and the third switch Msw3 are disconnected, and the second switch Msw2 and the fourth switch Msw4 are turned on. R sw = R sw1= R sw3 , R 1= R 11 +R 12 , R 2= R 21 +R 22, the first equilibrium voltage can be calculated according to formula (13). When the power supply voltage is in the decreasing phase and the power supply voltage is greater than or equal to the second equilibrium voltage (i.e., the power supply voltage is in equilibrium or before reaching equilibrium), the trigger outputs a low-level signal (POR = 0). Under the control of the low-level signal, the first switch Msw1 and the third switch Msw3 are turned on, and the second switch Msw2 and the fourth switch Msw4 are turned off.

[0114] For example, when N=8, V T ≈0.026v, R sw1 = R sw3 ≈795kohm, R sw2 = R sw4 ≈273kohm, R 11 ≈299kohm, R 12 ≈45kohm, R 21 ≈299kohm, R 22 ≈45kohm, R When 3≈27kohm, we can calculate the first equilibrium voltage vtp_rise = 1.6V and the second equilibrium voltage vtp_fall = 1.45V. The symbol "≈" here indicates an approximate relationship. In analog circuit and chip design, as long as the resistance value is within a certain range of the designed value, it is acceptable.

[0115] It should be noted that R sw Refers to the resistance of the second bias resistor unit. The resistance of the first bias resistor unit is the same as the resistance of the second bias resistor unit. R sw1 Refers to the resistance of the first bias resistor Rsw1, R sw3 Refers to the resistance of the third bias resistor Rsw3, R sw2 Refers to the resistance of the second bias resistor Rsw2, R sw4 refers to the resistance of the fourth bias resistor Rsw4, R 1 refers to the resistance value of the first resistance unit, R 11 Refers to the resistance of the second resistor R11, R 12 refers to the resistance of the first resistor R12, R 2 refers to the resistance of the second resistor unit,R 21 refers to the resistance of the fifth resistor R21, R 22 Refers to the resistance of the fourth resistor R22.

[0116] It should be noted that the derivation process of the second structure is similar to the above, the difference is: Formula (5) is modified to , formula (7) is modified to , the rest of formulas (1) to (4) and (6) remain unchanged. Based on these seven formulas, we can also get formulas (10) and (11). The specific derivation process will not be repeated here.

[0117] To enhance scalability, refer to Figure 2 As shown, the power-on reset circuit also includes an inverter 4; the trigger 3 includes a first P-type transistor M1, a second P-type transistor M2, a third P-type transistor M3, a first N-type transistor M4, a second N-type transistor M5, a third N-type transistor M6, a fourth N-type transistor Mt and a fifth N-type transistor M7.

[0118] refer to Figure 2 As shown, the source of the first P-type transistor M1 is electrically connected to the power supply, the drain of the first P-type transistor M1, the source of the second P-type transistor M2, and the source of the third P-type transistor M3 are electrically connected, the drain of the second P-type transistor M2, the drain of the first N-type transistor M4, the gate of the third P-type transistor M3, and the gate of the third N-type transistor M6 are electrically connected, the drain of the third N-type transistor M6 is electrically connected to the ground terminal, and the source of the first N-type transistor M4, the drain of the second N-type transistor M5, and the drain of the third N-type transistor M6 are electrically connected. The source of the third N-type transistor M6 is electrically connected to the power supply, the source of the second N-type transistor M5, the drain and gate of the fourth N-type transistor Mt, and the drain of the fifth N-type transistor M7 are electrically connected, the sources of the fourth N-type transistor Mt and the fifth N-type transistor M7 are electrically connected to the ground terminal, the gate of the first P-type transistor M1, the gate of the second P-type transistor M2, the gate of the first N-type transistor M4, and the gate of the second N-type transistor M5 are all electrically connected to the output terminal of the operational amplifier 2, and the gate of the fifth N-type transistor M7 is electrically connected to the output terminal of the inverter 4.

[0119] The drain of the second P-type transistor M2 is used as the output terminal of the trigger. The input terminal of the inverter 4 is electrically connected to the drain of the second P-type transistor M2. The inverter 4 is used to invert the signal output by the trigger 3.

[0120] Figure 3 Schematic diagram of the waveforms of the reset signal por and the inverted signal porb of the reset signal output by a conventional Schmitt trigger. Figure 4This is a waveform diagram of the reset signal por and the inverted signal porb of the reset signal output by the Schmitt trigger provided by the present application. The difference between the conventional Schmitt trigger and the Schmitt trigger provided by the embodiment of the present application is that the fourth N-type transistor Mt and the fifth N-type transistor M7 are not provided. Figure 3 As shown in FIG, during the power-on process, the reset signal por and the inverted signal porb of the reset signal are prone to glitch signals (defined by the dotted box A), which may cause the power-on reset function to fail. In order to solve this problem, the present application improves the conventional Schmitt trigger by introducing a fourth N-type transistor Mt and a fifth N-type transistor M7. The fourth N-type transistor Mt is used to raise the flip level of the Schmitt trigger. Figure 4 As shown, the reset signal por can be prevented from being flipped prematurely when the power supply voltage vddx rises / falls and the voltage value is small, thereby preventing the reset signal por and the inverted signal porb of the reset signal from generating spurs.

[0121] based on Figure 2 The power-on reset circuit shown in Figure 1 has branch 1 V be1 and branch 2 V be2_amp It can be used as a decision point for pulling the reset signal por low and the inverted signal porb of the reset signal high.

[0122] Specifically, during the rise or fall of vddx, when V be1 > V be2_amp , the voltage of the reset signal por is high level POR=1, the voltage of the inverted signal porb of the reset signal is low level, PORB=0, indicating that the system is in reset state; when V be1 < V be2_amp , the voltage of the reset signal por is low level POR=0, and the voltage of the inverted signal porb of the reset signal is high level, PORB=1, indicating that the system can exit the reset state and enter the normal working mode.

[0123] refer to Figure 2 As shown in the figure, since the operating state of the operational amplifier and inverter is not fully established when the power supply voltage vddx rises / falls to a lower voltage, it may lead to a high impedance state. Therefore, it can be set as follows Figure 2The first capacitor C1 and the second capacitor C2 are shown, wherein one end of the first capacitor C1 is connected between the operational amplifier 2 and the trigger 3, and the other end is grounded. The second capacitor C2 is connected between the inverter 4 and the trigger 3, and the other end is connected to the power supply. By setting the first capacitor C1 and the second capacitor C2, the voltage value of the corresponding node can be set during the rise / fall process of the power supply voltage vddx, thereby preventing the corresponding circuit node from entering a high-impedance state during the rise / fall process of the power supply voltage vddx, thereby preventing the logic level error of the reset signal por / the inverted phase signal of the reset signal porb, and thus preventing functional failure.

[0124] The present application also provides an electronic device including any of the above power-on reset circuits. The electronic device can significantly avoid the problem of reset signal mis-triggering or non-triggering caused by process fluctuations and temperature changes, and has high reliability.

[0125] The type and application scenarios of the electronic device are not limited. The electronic device can be a component or product used in fields such as smart housing, transportation, smart home, consumer electronics, monitoring, industrial automation, in-cabin detection, and health care. For example, the electronic device can be used in consumer electronics such as 4G or 5G mobile phones, tablets, and personal computers; or it can also be used in fields such as base stations and drones; or it can also be used in fields such as intelligent transportation equipment such as automobiles, bicycles, motorcycles, ships, subways, or trains; or it can also be used in smart home devices such as sweeping robots, televisions, air conditioners, or smart lights; or it can also be used in fields such as in-cabin detection in automobiles, indoor personnel monitoring, and intelligent medical equipment.

[0126] The division of various components above is only for the purpose of clear description. During implementation, they can be combined into one component or some components can be split and decomposed into multiple components. As long as they include the same logical relationship, they are all within the scope of protection of this application.

[0127] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A power-on reset circuit, characterized in that: include: Bandgap voltage reference module and operational amplifier; The bandgap voltage reference module includes a first branch and a second branch; the first branch includes a first PNP-type transistor, a first resistor unit, and a first bias resistor unit, the first bias resistor unit is arranged in parallel between the emitter and the collector of the first PNP-type transistor, the base and the collector of the first PNP-type transistor are electrically connected to the ground terminal, and the first resistor unit is arranged between a power supply and the emitter of the first PNP-type transistor; The second branch includes a second PNP-type transistor, a second resistor unit, a second bias resistor unit, and a third resistor unit, the second resistor unit and the third resistor unit are arranged in series between the power supply and the emitter of the second PNP-type transistor, the signal input end of the third resistor unit is electrically connected to the second resistor unit, the signal output end of the third resistor unit is electrically connected to the emitter of the second PNP-type transistor, the base and collector of the second PNP-type transistor are electrically connected to the ground end, and the second bias resistor unit is arranged in parallel between the signal input end of the third resistor unit and the collector of the second PNP-type transistor; The first bias resistor unit and the second bias resistor unit have the same structure and controllable resistance; the resistance of the third resistor unit is fixed; the resistance of the first bias resistor unit is M times the resistance of the third resistor unit, and M is greater than or equal to 6; The second resistance unit and the first resistance unit have the same structure and controllable resistance, the emitter area of ​​the second PNP-type transistor is N times the emitter area of ​​the first PNP-type transistor, and N is greater than 1; or the resistance values ​​of the second resistance unit and the first resistance unit are controllable, the resistance value of the second resistance unit is N times the resistance value of the first resistance unit, and N is greater than 1; the emitter area of ​​the second PNP-type transistor is the same as the emitter area of ​​the first PNP-type transistor; The negative phase input terminal of the operational amplifier is electrically connected to the emitter of the first PNP transistor, and the positive phase input terminal of the operational amplifier is electrically connected to the signal input terminal of the third resistor unit; The bandgap voltage reference module is configured to: control the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch so that the bandgap voltage reference module has a first equilibrium voltage when the power supply voltage is in a rising phase, and has a second equilibrium voltage when the power supply voltage is in a falling phase, wherein the first equilibrium voltage is greater than the second equilibrium voltage, wherein the first equilibrium voltage is the power supply voltage corresponding to when the power supply voltage is in a rising phase and the difference between the voltage at the emitter of the first PNP transistor and the voltage at the signal input terminal of the third resistor unit is zero; and the second equilibrium voltage is the power supply voltage corresponding to when the power supply voltage is in a falling phase and the difference between the voltage at the emitter of the first PNP transistor and the voltage at the signal input terminal of the third resistor unit is zero; and the first equilibrium voltage and the second equilibrium voltage are adjusted by adjusting the ratio of the resistance of the second resistor unit to the resistance of the second bias resistor unit. The operational amplifier is used to amplify the difference between the voltage of the emitter of the first PNP transistor and the voltage of the signal input end of the third resistor unit.

2. The power-on reset circuit according to claim 1, wherein: The power-on reset circuit further includes: a trigger; the output end of the operational amplifier is electrically connected to the input end of the trigger; The trigger is used to: When the voltage of the power supply is in a rising stage, when the voltage signal received by the negative phase input terminal of the operational amplifier is greater than or equal to the voltage signal received by the positive phase input terminal of the operational amplifier, a high level signal is output; when the voltage signal received by the negative phase input terminal of the operational amplifier is less than the voltage signal received by the positive phase input terminal of the operational amplifier, a low level signal is output; When the voltage of the power supply is in a decreasing stage, when the voltage signal received by the negative input terminal of the operational amplifier is less than the voltage signal received by the positive input terminal of the operational amplifier, the low-level signal is output; when the voltage signal received by the negative input terminal of the operational amplifier is greater than or equal to the voltage signal received by the positive input terminal of the operational amplifier, the high-level signal is output.

3. The power-on reset circuit according to claim 2, wherein: The first resistance unit is configured to have a first resistance value under the control of the high-level signal; and is configured to have a second resistance value under the control of the low-level signal; the first resistance value is greater than the second resistance value; The first bias resistor unit is configured to have a third resistance value under the control of the high-level signal; and is configured to have a fourth resistance value under the control of the low-level signal; and the third resistance value is smaller than the fourth resistance value.

4. The power-on reset circuit according to claim 2 or 3, characterized in that: The first resistor unit includes a first switch, and a first resistor and a second resistor connected in series, the first resistor and the first switch being arranged in parallel; the first resistor being arranged between the power supply and the second resistor; the first switch being configured to remain in an off state under the control of the high-level signal, and to remain in an on state under the control of the low-level signal; The first bias resistor unit includes a second switch, and a first bias resistor and a second bias resistor connected in series, the second bias resistor and the second switch being arranged in parallel; the second bias resistor being arranged between the first bias resistor and the ground terminal; the second switch being configured to remain in an on state under the control of the high-level signal and remain in an off state under the control of the low-level signal; The second resistor unit includes a third switch, and a fourth resistor and a fifth resistor connected in series, wherein the fourth resistor and the third switch are arranged in parallel; the fourth resistor is arranged between the power supply and the fifth resistor; the third switch is configured to remain in an off state under the control of the high-level signal and to remain in a on state under the control of the low-level signal; The second bias resistor unit includes a fourth switch, and a third bias resistor and a fourth bias resistor connected in series, wherein the fourth bias resistor and the fourth switch are arranged in parallel; the fourth bias resistor is arranged between the third bias resistor and the ground terminal; the fourth switch is configured to maintain an on state under the control of the high-level signal and maintain an off state under the control of the low-level signal; The third resistance unit includes a third resistor.

5. The power-on reset circuit according to claim 2, wherein: The power-on reset circuit also includes an inverter; The trigger includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor and a fifth N-type transistor; The source of the first P-type transistor is electrically connected to the power supply, the drain of the first P-type transistor, the source of the second P-type transistor, and the source of the third P-type transistor are electrically connected, the drain of the second P-type transistor, the drain of the first N-type transistor, the gate of the third P-type transistor, and the gate of the third N-type transistor are electrically connected, the drain of the third N-type transistor is electrically connected to the ground terminal, the source of the first N-type transistor, the drain of the second N-type transistor, and the drain of the third N-type transistor are electrically connected, the source of the third N-type transistor is electrically connected to the power supply, the source of the second N-type transistor, the drain and gate of the fourth N-type transistor, and the drain of the fifth N-type transistor are electrically connected, the sources of the fourth N-type transistor and the fifth N-type transistor are electrically connected to the ground terminal, the gates of the first P-type transistor, the second P-type transistor, the first N-type transistor, and the second N-type transistor are all electrically connected to the output terminal of the operational amplifier, and the gate of the fifth N-type transistor is electrically connected to the output terminal of the inverter; The drain of the second P-type transistor is used as the output terminal of the trigger, the input terminal of the inverter is electrically connected to the drain of the second P-type transistor, and the inverter is used to invert the signal output by the trigger.

6. An electronic device, characterized in that: include: The power-on reset circuit according to any one of claims 1 to 5.

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