Digital-to-analog conversion device and method with signal calibration mechanism

Abstract

The invention relates to a digital-to-analog conversion device and method with a signal calibration mechanism. The invention discloses a digital-to-analog conversion device with a signal calibration mechanism. The conversion circuit performs digital-to-analog conversion on an input digital signal to generate an output analog signal. The echo transmission circuit downsamples an echo path through which the output analog signal passes to generate an echo signal. N calibration circuits of the echo calibration circuit take selected data contained in N input parts of an input digital signal as pseudo noise feed-in and a plurality of non-selected data as signal feed-in, map by a plurality of codeword deviation tables and process by a plurality of groups of response coefficients to generate N calibration parts of a calibration signal. The calibration parameter operation circuit generates a plurality of offsets according to the echo signal, converges the response coefficient according to the error signal and the pseudo noise transmission path information from the conversion circuit to the echo transmission circuit, and updates the codeword offset table according to the offsets.

Description

Technical Field

[0001] The present invention relates to a digital-to-analog conversion technology, and more particularly to a digital-to-analog conversion device and method with a signal calibration mechanism. Background Art

[0002] The digital-to-analog converter is an important component for converting a signal from a digital form to an analog form. The digital-to-analog converter can generate analog signals of different sizes by multiplying different digital codes by corresponding conversion gain values.

[0003] However, the digital-to-analog converter often has errors due to the offset of the internal current source, and the mismatch between the signal itself and the signal in the transmission path will cause echo, so the digital-to-analog converter requires various calibration techniques to calibrate the input and output signals to achieve the best conversion result. Summary of the invention

[0004] In view of the problems of the prior art, an object of the present invention is to provide a digital-to-analog conversion device and method with a signal calibration mechanism to improve the prior art.

[0005] The present invention includes a digital-to-analog conversion device with a signal calibration mechanism, comprising: a conversion circuit, an echo transmission circuit, an echo calibration circuit and a calibration parameter operation circuit. The conversion circuit includes a plurality of current sources operating at a first frequency to perform digital-to-analog conversion according to a signal input associated with an input digital signal having a set of input codewords to generate an output analog signal, wherein the input digital signal is sequentially and evenly divided into N input parts, where N is a positive integer greater than 1. The echo transmission circuit performs signal processing on the echo path through which the output analog signal passes, and downsamples to generate an echo signal having a second frequency, wherein the second frequency is 1 / N of the first frequency. The echo calibration circuit includes N calibration circuits operating at a second frequency, respectively allowing selected data contained in one of the N input parts to be fed as pseudo noise and a plurality of non-selected data to be fed as signals, to be mapped by a plurality of codeword deviation tables and processed by a plurality of response coefficients to generate one of the N calibration parts of the calibration signal. The calibration parameter operation circuit operates at a second frequency, and generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signal and path information related to the echo calibration circuit, wherein the echo calibration circuit converges the response coefficient according to the error signal and the pseudo-noise transmission path information from the conversion circuit to the echo transmission circuit, and updates the codeword deviation table according to the offsets.

[0006] The present invention further includes a digital-to-analog conversion method with a signal calibration mechanism, which is applied to a digital-to-analog conversion device, comprising: causing a conversion circuit including a plurality of current sources operating at a first frequency to perform conversion according to a signal input related to an input digital signal having a set of input codewords to generate an output analog signal, wherein the input digital signal is sequentially and evenly divided into N input parts, where N is a positive integer greater than 1; causing an echo transmission circuit to perform signal processing on an echo path through which the output analog signal passes, so as to generate an echo signal having a second frequency by downsampling, wherein the second frequency is 1 / N of the first frequency; causing an echo calibration circuit including a plurality of current sources operating at the second ... The N calibration circuits of the second frequency respectively input selected data contained in one of the N input parts as pseudo noise and a plurality of non-selected data as signals, map them by a plurality of codeword deviation tables and process them by a plurality of response coefficients to generate one of the N calibration parts of the calibration signal; enable the calibration parameter operation circuit operating at the second frequency to generate a plurality of offsets according to an error signal of the echo signal relative to the calibration signal and path information related to the echo calibration circuit; and enable the echo calibration circuit to converge the response coefficient according to the error signal and the pseudo noise transmission path information from the conversion circuit to the echo transmission circuit, and update the codeword deviation table according to the offset.

[0007] The features, implementation and effects of the present invention are described in detail below with reference to the drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram showing a digital to analog conversion device with a signal calibration mechanism according to an embodiment of the present invention;

[0009] Figure 2 A more detailed block diagram of a signal input circuit in one embodiment of the present invention is shown;

[0010] Figure 3A A more detailed block diagram of an echo calibration circuit according to an embodiment of the present invention is shown;

[0011] Figure 3B A more detailed block diagram showing one of the calibration circuits included in the echo calibration circuit according to one embodiment of the present invention; and

[0012] Figure 4 A flowchart of a digital-to-analog conversion method with a signal calibration mechanism according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0013] An object of the present invention is to provide a digital-to-analog conversion device with a signal calibration mechanism. When generating an output analog signal and an echo cancellation analog signal having a first frequency, downsampling is performed so that an internal circuit can operate at a second frequency that is 1 / N of the first frequency, and partial information of the input digital signal itself is fed as pseudo noise, so that calibration is performed according to the echo signal without additionally generating pseudo noise.

[0014] Please refer to Figure 1 . Figure 1 The block diagram of a digital-to-analog conversion device 100 with a signal calibration mechanism in one embodiment of the present invention is shown. The digital-to-analog conversion device 100 includes a signal input circuit 110, a conversion circuit 120, an echo transmission circuit 130, an echo calibration circuit 140 and a calibration parameter calculation circuit 150.

[0015] Please refer to Figure 2 . Figure 2 A more detailed block diagram of the signal input circuit 110 is shown in one embodiment of the present invention.

[0016] The signal input circuit 110 includes N feeding circuits. Figure 2 In the embodiment of FIG. 1 , N is 4, so the signal input circuit 110 includes four feeding circuits 200A- 200D.

[0017] The signal input circuit 110 feeds a signal to the conversion circuit 120 according to the input digital signal IS. Figure 1 As shown, for example, a signal source SS of a transmitter (TX) in a communication system receives an input digital signal IS, and the input digital signal IS is generated by over-sampling an original digital signal (not shown) having an original codeword.

[0018] For example, the original digital signal may be a signal operating at 400 MHz and having a set of original codewords having 64 values ​​such as but not limited to 4, 8, 12, ..., 256. The input digital signal IS may be a signal operating at 1600 MHz and having a set of input codewords having 256 values ​​such as but not limited to 1, 2, 3, ..., 256 by being oversampled by 4 times from the original digital signal.

[0019] The feed circuits 200A-200D of the signal input circuit 110 capture one of the N input parts of the input digital signal IS and output it. More specifically, the four feed circuits 200A-200D capture one of the four input parts IPA-IPD of the input digital signal IS and output it. In one embodiment, the four input parts IPA-IPD can be represented by phases, corresponding to 90 degrees, 180 degrees, 270 degrees, and 360 degrees, respectively, and are Figure 2 They are marked as 090, 180, 270, and 360 respectively after the input parts IPA~IPD.

[0020] The conversion circuit 120 operates at a first frequency, wherein the first frequency is, for example, but not limited to, 1600 MHz. The conversion circuit 120 performs digital-to-analog conversion according to a signal input related to an input digital signal IS having an input codeword to generate an output analog signal OD. The output analog signal OD is a signal actually transmitted to the outside. However, the output analog signal OD may be transmitted by Figure 1 The echo path EP shown leaks to, for example, but not limited to, a receiving circuit (receiver; RX, not shown). In one embodiment, a resistor (not shown) may be provided on the echo path EP for voltage division to achieve an echo cancellation mechanism.

[0021] Figure 1 The echo transmission circuit 130 performs signal processing on the echo path EP to downsample and generate an echo signal ES having a second frequency that is 1 / N of the first frequency. Since the first frequency is 1600 MHz and N is 4 in the above example, the second frequency is 400 MHz. The above signal processing includes, for example, but not limited to, echo response processing and analog-to-digital conversion through downsampling to generate the echo signal ES.

[0022] The aforementioned conversion circuit 120 includes a plurality of current sources (not shown in the figure) to generate analog signals according to the control of corresponding signal feed-in. The current sources may include thermometer-type and binary-controlled current sources. In one embodiment, the current sources include 15 thermometer-type controlled current sources which may be represented as T01 to T15 and 4 binary-controlled current sources which may be represented as B01 to B04, each of which is electrically coupled to a different voltage source according to the control of the input codeword to output one of a positive voltage and a negative voltage.

[0023] In one embodiment, each thermometer-type controlled current source outputs a positive or negative voltage of 1 unit, and the four binary-type controlled current sources sequentially output positive or negative voltages of 1 / 2, 1 / 4, 1 / 8, and 1 / 16 units. Therefore, under the control of the input codeword, 256 values ​​will correspond to the output voltage range from -15.9375 to +15.9375 units.

[0024] For example, when the value of the input code word is 60, the first 12 thermometer-type controlled current sources (T01~T12) will output a negative voltage, the last three thermometer-type controlled current sources (T13~T15) will output a positive voltage, the first, third, and fourth binary-type controlled current sources (B01, B03, B04) will output a positive voltage, and the second binary-type controlled current source (B02) will output a negative voltage, and the final output voltage is -8.5625 units.

[0025] The aforementioned current sources each have a current deviation value, which causes a static mismatch error in the output analog signal. In addition, the inconsistency in the timing of the current source turning on will cause a leading mismatch error in time if it is turned on too early, and a lagging mismatch error in time if it is turned on too late.

[0026] The echo calibration circuit 140 eliminates the static mismatch error, the leading mismatch error, and the lagging mismatch error of each conversion circuit.

[0027] The echo calibration circuit 140 includes N calibration circuits operating at a second frequency, each of which feeds selected data of one of the N input parts as pseudo noise and multiple non-selected data as signals, is mapped by multiple codeword deviation tables and processed by multiple groups of response coefficients to generate one of the N calibration parts of the calibration signal.

[0028] Please also refer to Figure 3A as well as Figure 3B . Figure 3A A more detailed block diagram of the echo calibration circuit 140 is shown in one embodiment of the present invention. Figure 3B A more detailed block diagram of one of the calibration circuits included in the echo calibration circuit 140 according to one embodiment of the present invention is shown.

[0029] Since N is 4 in this embodiment, the echo calibration circuit 140 includes four calibration circuits 145A-145D. Figure 3B The calibration circuit 145A is used as an example for illustration. The calibration circuits 145A-145D correspond to one of the receiving input parts IPA-IPD respectively.

[0030] In one embodiment, the current source of the conversion circuit 120 includes a selected current source and a plurality of non-selected current sources, the selected data corresponds to the selected current source, and the non-selected data corresponds to the non-selected current source, wherein the selected data has a minimum data correlation between the N input parts and between the original codeword relative to the non-selected data.

[0031] In the example of the conversion circuit 120 including 15 thermometer-controlled current sources T01 to T15 and 4 binary-controlled current sources B01 to B04, the binary-controlled current source B01 and the thermometer-controlled current source T08 are most suitable as the selected current source. Taking the binary-controlled current source B01 as the selected current source as an example, the thermometer-controlled current sources T01 to T15 and the binary-controlled current sources B02 to B04 are all used as non-selected current sources.

[0032] Therefore, for the four input parts IPA-IPD with N being 4, the selected data ISA-ISD and the unselected data INA-IND are included respectively. The selected data ISA-ISD all correspond to the binary control current source represented as B01, while the unselected data INA-IND correspond to other current sources.

[0033] The calibration circuits 145A-145D included in the echo calibration circuit 140 respectively input selected data ISA-ISD as pseudo noise and non-selected data INA-IND as signals, thereby generating one of the calibration parts CIA-CID. Figure 3B In the calibration circuit 145A shown in FIG. 1 , the input part IPA serves as the corresponding input part of the calibration circuit 145A, and the calibration part CIA serves as the corresponding calibration part of the calibration circuit 145A.

[0034] The calibration circuit 145A includes a static mapping circuit 300 , a lead time mapping circuit 310 , a delay time mapping circuit 320 , a static response circuit 330 , a lead response circuit 340 , a delay response circuit 350 , and a pseudo noise response circuit 360 .

[0035] The static mapping circuit 300 receives the non-selected data INA corresponding to the input part IPA and maps the non-selected data INA according to the static code word deviation table TSA in the code word deviation table to generate a static mapping signal DSS.

[0036] The advance time mapping circuit 310 receives the non-selected data INA corresponding to the input part IPA and maps the data according to the advance code word deviation table TLA in the code word deviation table to generate the advance time mapping signal DSL.

[0037] The backward time mapping circuit 320 receives the non-selected data INA corresponding to the input part IPA and maps the non-selected data INA according to the backward code deviation table TDA in the code deviation table to generate a backward time mapping signal DSD.

[0038] In the above mapping circuit, each codeword deviation table contains a one-to-one correspondence between multiple codewords and multiple codeword deviation values. The input codeword corresponds to one of the codewords in each codeword deviation table. In the initial state, the deviation values ​​corresponding to all codewords are preset to 0.

[0039] The static response circuit 330 receives the static mapping signal DSS and processes it according to a set of static response coefficients CSA among the plurality of sets of response coefficients to generate a static output calibration signal CLS in the corresponding calibration portion CIA.

[0040] The lead response circuit 340 receives the lead time mapping signal DSL and processes it according to one set of lead response coefficients CLA among the plurality of sets of response coefficients to generate a lead output calibration signal CLL in the corresponding calibration section CIA.

[0041] The lag response circuit 350 receives the lag time mapping signal DSD and processes it according to a set of lag response coefficients CDA among the plurality of sets of response coefficients to generate a lag output calibration signal CDL in the corresponding calibration portion CIA.

[0042] The pseudo noise response circuit 360 receives the selected data ISA corresponding to the input part IPA and processes it according to a set of pseudo noise response coefficients CNA to generate a pseudo noise calibration signal CLN in the corresponding calibration part CIA.

[0043] The calibration circuits 145B-145D may respectively have the same components and architecture as the calibration circuit 145A, so as to process according to the internal static codeword deviation tables TSB-TSD, leading codeword deviation tables TLB-TLD, lagging codeword deviation tables TDB-TDD, static response coefficients CSB-CSD, leading response coefficients CLB-CLD, lagging response coefficients CDB-CDD and pseudo noise response coefficients CNB-CND, and generate calibration parts CIB-CLD, and the calibration parts CIB-CLD include calibration signals corresponding to the calibration part CIA. The relevant details are not repeated here.

[0044] In one embodiment, Figure 1 The digital-to-analog conversion device 100 further includes an error calculation circuit 160 for calculating an error signal DIS of the echo signal ES relative to the calibration portion CIA-CLD.

[0045] In one embodiment, Figure 1 The digital-to-analog conversion device 100 further includes a residual echo cancellation circuit 170 for further canceling the residual echo. The residual echo cancellation circuit 170 includes a residual echo response circuit 180 and a cancellation circuit 190 .

[0046] The residual echo response circuit 180 receives the input digital signal IS and processes it according to a set of residual echo response coefficients CCR to generate a residual echo cancellation signal ECR. The cancellation circuit 190 subtracts the residual echo cancellation signal ECR from the error signal DIS to generate a final error signal FDIS. The residual echo response circuit 180 converges according to the final error signal FDIS.

[0047] The calibration parameter calculation circuit 150 generates a plurality of offsets according to the error signal DIS of the echo signal ES relative to the calibration signal including the calibration parts CIA-CLD and the path information related to the echo calibration circuit 140. In one embodiment, the calibration parameter calculation circuit 150 actually generates the offsets according to the final error signal FDIS processed by the residual echo cancellation circuit 170.

[0048] In one embodiment, the path information is the path delays DL1-DL4 from each response circuit (static response circuit 330, leading response circuit 340, lagging response circuit 350 and pseudo noise response circuit 360) to the calibration parameter calculation circuit 150. Since the processing of these circuits takes time, the calibration parameter calculation circuit 150 needs to trace back the calculated offset to the correct input codeword according to the path delays DL1-DL4.

[0049] In one embodiment, the calibration parameter operation circuit 150 receives the static response coefficients CSA-CSD, the leading response coefficients CLA-CLD, and the lagging response coefficients CDA-CDD of the static response circuit 330, the leading response circuit 340, the lagging response circuit 350, and the pseudo noise response circuit 360 of each calibration circuit 145A-145D, and performs one-dimensional inversion on these response coefficients, multiplies them with the value of the final error signal FDIS, and then accumulates them to generate corresponding inversion error values. The calibration parameter operation circuit 150 further sets each inversion error value to the offset DAA-DAD of the static mapping circuit 300, the leading time mapping circuit 310, and the lagging time mapping circuit 320 of each calibration circuit 145A-145D according to the path delays DL1-DL4.

[0050] It should be noted that the above-mentioned offset generation method is only an example. In other embodiments, the calibration parameter calculation circuit 150 may also generate the offset in other ways.

[0051] The echo calibration circuit 140 can be trained according to the final error signal FDIS and the pseudo noise transmission path information from the conversion circuit 120 to the echo transmission circuit 130 to make each set of response coefficients converge, thereby achieving the purpose of calibrating the conversion circuit 120. The pseudo noise transmission path information can be obtained by feeding and transmitting the selected data ISA-ISD.

[0052] In order to avoid the aforementioned training targets affecting each other, the digital-to-analog conversion device 100 is trained in different stages.

[0053] In the first training stage, each calibration circuit 145A~145D converges the pseudo noise response coefficients CNA~CND of the pseudo noise response circuit 360 according to the echo signal ES, and the static response circuit 330, the leading response circuit 340 and the lagging response circuit 350 set the static response coefficients CSA~CSD, the leading response coefficients CLA~CLD and the lagging response coefficients CDA~CDD according to the converged pseudo noise response coefficients CNA~CND of each calibration circuit 145A~145D.

[0054] The following is a more detailed description of the response coefficient setting.

[0055] In one embodiment, the target calibration circuit of calibration circuits 145A to 145D corresponds to a target input portion in the input portion and corresponds to a converged target pseudo-noise response coefficient, the leading calibration circuit of calibration circuits 145A to 145D is used to receive a leading input portion relative to the target input portion and corresponds to a converged leading pseudo-noise response coefficient, and the lagging calibration circuit of calibration circuits 145A to 145D is used to receive a lagging input portion relative to the target input portion and corresponds to a converged lagging pseudo-noise response coefficient.

[0056] For example, since the calibration circuits 145A-145D sequentially receive the input portions IPA-IPD in a cyclic manner, when the target calibration circuit is the calibration circuit 145B, its corresponding target input portion is the input portion IPB, and the corresponding converged target pseudo noise response coefficient is the pseudo noise response coefficient CBN. The leading calibration circuit will be the calibration circuit 145A, its corresponding leading input portion is the input portion IPA, and the corresponding converged leading pseudo noise response coefficient is CNA. The lagging calibration circuit will be the calibration circuit 145C, its corresponding lagging input portion is the input portion IPC, and the corresponding converged lagging pseudo noise response coefficient is CCN.

[0057] The static response circuit 330 of the target calibration circuit 145B sets the converged target pseudo noise response coefficient CBN as the static response coefficient CSB.

[0058] The lead response circuit 340 of the target calibration circuit 145B sets the lead response coefficient CLB according to the converged target pseudo noise response coefficient CBN and the converged lead pseudo noise response coefficient CNA. In one embodiment, the lead response circuit 340 of the target calibration circuit 145B superimposes the converged target pseudo noise response coefficient CBN with positive and negative inversion on the converged lead pseudo noise response coefficient CNA to set it as the lead response coefficient CLB. Therefore, the lead response coefficient CLB can be expressed as -CBN+CNA.

[0059] The backward response circuit 350 of the target calibration circuit 145A sets the backward response coefficient CDB according to the converged target pseudo noise response coefficient CNA and the converged backward pseudo noise response coefficient CCN. In one embodiment, the backward response circuit 350 of the target calibration circuit 145B superimposes the converged target pseudo noise response coefficient CBN with positive and negative inversion on the converged backward pseudo noise response coefficient CCN to set it as the backward response coefficient CDB. Therefore, the backward response coefficient CDB can be expressed as -CBN+CCN.

[0060] Similarly, when the target calibration circuit is the calibration circuit 145C, and the corresponding converged target pseudo-noise response coefficient is the pseudo-noise response coefficient CCN. The static response circuit 330 of the calibration circuit 145C sets the converged target pseudo-noise response coefficient CBN to the static response coefficient CSB. The leading response circuit 340 of the calibration circuit 145C superimposes the converged target pseudo-noise response coefficient CCN with positive and negative inversion and the converged leading pseudo-noise response coefficient CBN to set it as the leading response coefficient CLC, which can be expressed as -CCN+CBN. The lagging response circuit 350 of the calibration circuit 145C superimposes the converged target pseudo-noise response coefficient CCN with positive and negative inversion and the converged lagging pseudo-noise response coefficient CDN to set it as the lagging response coefficient CDC, which can be expressed as -CCN+CDN.

[0061] In one embodiment, when the target calibration circuit corresponds to the most leading part of the input parts IPA-IPD, the leading response circuit 340 left-shifts the converged leading pseudo noise response coefficients, fills them with 0, and then superimposes them.

[0062] For example, when the target calibration circuit is the calibration circuit 145A, the leading part IPA of the corresponding input part IPA to IPD. The static response circuit 330 of the calibration circuit 145A sets the converged target pseudo noise response coefficient CNA to the static response coefficient CSA. The leading response circuit 340 of the calibration circuit 145A superimposes the converged target pseudo noise response coefficient CNA with positive and negative inversion and the converged leading pseudo noise response coefficient CDN with left shift and 0 complement to set it as the leading response coefficient CLA, which can be expressed as -CNA+[CDN(2:end)0]. The lagging response circuit 350 of the calibration circuit 145A still superimposes the converged target pseudo noise response coefficient CNA with positive and negative inversion and the converged lagging pseudo noise response coefficient CBN to set it as the lagging response coefficient CDA, which can be expressed as -CNA+CBN.

[0063] In one embodiment, when the target calibration circuit corresponds to the most backward part of the input parts IPA-IPD, the backward response circuit 350 subtracts one from the last one of the converged backward pseudo noise response coefficients and then performs superposition.

[0064] For example, when the target calibration circuit is the calibration circuit 145D, the most backward part IPD of the corresponding input part IPA~IPD. The static response circuit 330 of the calibration circuit 145D sets the converged target pseudo noise response coefficient CDN to the static response coefficient CSD. The leading response circuit 340 of the calibration circuit 145D still superimposes the converged target pseudo noise response coefficient CDN with positive and negative inversion and the converged leading pseudo noise response coefficient CCN to set it as the leading response coefficient CLD, which can be expressed as -CDN+CCN. The backward response circuit 350 of the calibration circuit 145D superimposes the converged target pseudo noise response coefficient CDN with positive and negative inversion and the converged backward pseudo noise response coefficient CNA with the last one minus one to set it as the backward response coefficient CDD, which can be expressed as -CDN+[CNA(1:end)-1].

[0065] In the second training phase, each calibration circuit 145A-145D updates one of the static codeword deviation tables TSA-TSD, leading codeword deviation tables TLA-TLD, and lagging codeword deviation tables TDA-TDD according to one of the offsets DAA-DAD associated with each calibration circuit 145A-145D.

[0066] In one embodiment, the deviation values ​​of each current source included in the conversion circuit 120 correspond to different input codewords and have multiple permutations and combinations, so that there is a mapping relationship between the deviation value of the current source and the offset of the input codeword. The calibration parameter operation circuit 150 can first divide the offsets corresponding to different input codewords into multiple groups according to the operating status of each current source in the second training stage, and set each current source as a target current source to further set the corresponding current deviation value operation formula. The current deviation value operation formula is the result of the subtraction operation of two groups, so that the current deviation values ​​of each current source other than the target current source offset each other.

[0067] The calibration parameter operation circuit 150 substitutes the offsets DAA-DAD into the current deviation value calculation formula corresponding to each current source to calculate the current deviation value of the target current source, and then converts the current deviation value of the current source into a plurality of codeword deviation values, so that the corresponding static codeword deviation table TSA-TSD, leading codeword deviation table TLA-TLD, and lagging codeword deviation table TDA-TDD are updated. For the detailed operation process of the calibration parameter operation circuit 150 calculating the current deviation value according to the offsets DAA-DAD and converting it into the codeword deviation value, and then updating the codeword deviation table, please refer to the application case of U.S. patent application No. 17691502. It will not be repeated here.

[0068] In one embodiment, the residual echo response circuit may set the residual echo response coefficient CCR within a preset range, and then the calibration parameter operation circuit 150 performs calculations to reduce the degree of freedom and reduce the interaction on the system. In one embodiment, the lower limit value of the preset range may be -1×10 -2 , the upper limit can be +1×10 -2 However, the present invention is not limited thereto.

[0069] By the above method, the calibration parameter calculation circuit 150 can update the static codeword deviation tables TSA-TSD, the leading codeword deviation tables TLA-TLD, and the lagging codeword deviation tables TDA-TDD associated with each calibration circuit 145A-145D.

[0070] In one embodiment, the conversion circuit 120 may further include a control circuit (not shown) to generate a start-up sequence according to the current deviation values ​​corresponding to the current sources, and then turn on the thermometer-controlled current sources in the start-up sequence according to the input codeword through the thermometer code control method, so that the linearity of these current sources turning on in the start-up sequence is greater than a preset value. The setting of the start-up sequence can be achieved in different ways, which will not be repeated here.

[0071] Therefore, when the digital-to-analog conversion device 100 of the present invention generates an output analog signal and an echo cancellation analog signal having a first frequency, downsampling is performed so that the internal circuit can operate at a second frequency that is 1 / N of the first frequency, and partial information of the input digital signal itself is fed as pseudo noise, so that calibration is performed according to the echo signal without additionally generating pseudo noise.

[0072] It should be noted that in the above embodiment, N is described as 4. However, N can be any positive integer, and is preferably a multiple of 2. The present invention is not limited thereto.

[0073] Please refer to Figure 4 . Figure 4 A flowchart of a digital-to-analog conversion method 400 with a signal calibration mechanism is shown in one embodiment of the present invention.

[0074] In addition to the aforementioned devices, the present invention further discloses a digital to analog conversion method 400, which is applied to, for example, but not limited to Figure 1 In the digital-to-analog conversion device 100. An embodiment of the digital-to-analog conversion method 400 is as follows: Figure 4 As shown, the following steps are included.

[0075] In step S410: the conversion circuit 120 including multiple current sources operating at a first frequency is converted according to a signal input related to an input digital signal IS having a set of input codewords to generate an output analog signal OD, wherein the input digital signal IS is sequentially and evenly divided into N input parts, where N is a positive integer greater than 1.

[0076] In step S420 , the echo transmission circuit 130 performs signal processing on the echo path EP through which the output analog signal OD passes, so as to downsample and generate an echo signal ES having a second frequency, wherein the second frequency is 1 / N of the first frequency.

[0077] In step S430, the N calibration circuits included in the echo calibration circuit 140 and operating at the second frequency respectively input the selected data included in one of the N input parts as pseudo noise and the multiple non-selected data as signals, map them using the multiple codeword deviation tables and process them using the multiple groups of response coefficients to generate one of the N calibration parts of the calibration signal.

[0078] In step S440 , the calibration parameter calculation circuit 150 operating at the second frequency is enabled to generate a plurality of offsets according to the error signal DIS of the echo signal ES relative to the calibration signal and the path information related to the echo calibration circuit 140 .

[0079] In step S450 , the echo calibration circuit 140 is enabled to converge the response coefficient according to the error signal DIS and the pseudo noise transmission path information from the conversion circuit 120 to the echo transmission circuit 130 , and the codeword deviation table is updated according to the offset.

[0080] It should be noted that the above implementation is only an example. In other embodiments, those skilled in the art may make changes without violating the spirit of the present invention.

[0081] In summary, the digital-to-analog conversion device and method with a signal calibration mechanism in the present invention can generate an output analog signal with a first frequency and an echo cancellation analog signal by downsampling so that the internal circuit can operate at a second frequency that is 1 / N of the first frequency, and use part of the information of the input digital signal itself as pseudo noise to feed in, so as to perform calibration according to the echo signal without additionally generating pseudo noise.

[0082] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. A person with ordinary knowledge in the technical field may make changes to the technical features of the present case based on the explicit or implicit content of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be subject to the scope of the patent application defined in this specification.

[0083] Explanation of symbols

[0084] 100: Digital to analog conversion device

[0085] 110:Signal input circuit

[0086] 120:Conversion circuit

[0087] 130: Echo transmission circuit

[0088] 140:Echo calibration circuit

[0089] 150: calibration parameter calculation circuit

[0090] 160: Error calculation circuit

[0091] 170: Residual echo cancellation circuit

[0092] 180: Residual echo response circuit

[0093] 190: Elimination circuit

[0094] 200A~200D: Feeding circuit

[0095] 300: static mapping circuit

[0096] 310: Leading time mapping circuit

[0097] 320: Lag time mapping circuit

[0098] 330: Static response circuit

[0099] 340: Lead Response Circuit

[0100] 350: Lag response circuit

[0101] 360: Pseudo-noise response circuit

[0102] 400:Digital to Analog Conversion Method

[0103] S410~S450: Steps

[0104] CDA~CDD: Lagging response coefficient

[0105] CDL: Lag output calibration signal

[0106] CIA~CID: Calibration part

[0107] CLL: Leading output calibration signal

[0108] CLN: Pseudo Noise Calibration Signal

[0109] CLA~CLD: Leading Response Coefficient

[0110] CLS: static output calibration signal

[0111] CNA~CND: Pseudo-noise response coefficient

[0112] CSA~CSD: Static response coefficient

[0113] DAA~DAD: offset

[0114] DIS: Error signal

[0115] DL1~DL4: path delay

[0116] DSD: Delayed Time Mapped Signal

[0117] DSL: Leading Time Mapping Signal

[0118] DSS: Static Mapping Signal

[0119] ECR: residual echo cancellation signal

[0120] EP: Echo Path

[0121] ES: Echo signal

[0122] FDIS: Final Error Signal

[0123] INA~IND: Non-selected data

[0124] IPA~IPD: Input part

[0125] IS: Input digital signal

[0126] ISA~ISD: Selected data

[0127] OD: Output analog signal

[0128] ON: Pseudo-noise analog signal

[0129] SS:Signal source

[0130] TDA~TDD: Lagging codeword deviation table

[0131] TLA~TLD: Leading Codeword Deviation Table

[0132] TSA~TSD: Static Code Deviation Table

Claims

1. A digital to analog conversion device with a signal calibration mechanism, comprising: A conversion circuit comprising a plurality of current sources operating at a first frequency to perform digital-to-analog conversion according to a signal input associated with an input digital signal having a set of input codewords to generate an output analog signal, wherein the input digital signal is sequentially and evenly divided into N input parts, where N is a positive integer greater than 1; An echo transmission circuit performs signal processing on the echo path through which the output analog signal passes, so as to generate an echo signal having a second frequency by downsampling, wherein the second frequency is 1 / N of the first frequency; an echo calibration circuit, comprising N calibration circuits operating at the second frequency, respectively allowing selected data contained in one of the N input parts to be fed as pseudo noise and a plurality of non-selected data to be fed as signals, mapped by a plurality of codeword deviation tables and processed by a plurality of response coefficients to generate one of the N calibration parts of the calibration signal; as well as The calibration parameter operation circuit operates at the second frequency and generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signal and path information related to the echo calibration circuit, wherein the echo calibration circuit converges the plurality of response coefficients according to the error signal and pseudo noise transmission path information from the conversion circuit to the echo transmission circuit, and updates the plurality of codeword deviation tables according to the offsets.

2. The digital-to-analog conversion device as claimed in claim 1 further comprises a signal input circuit configured to feed a signal to the conversion circuit, comprising N feeding circuits to capture one of the N input parts of the input digital signal for output.

3. The digital-to-analog conversion device as claimed in claim 1, wherein each of the N calibration circuits comprises: A static mapping circuit receives the non-selected data of one of the N input parts of the input digital signal and maps the non-selected data according to the static code word deviation table in the code word deviation table to generate a static mapping signal; A lead time mapping circuit receives the non-selected data of the corresponding input part and maps the non-selected data according to the lead code word deviation table in the code word deviation table to generate a lead time mapping signal; A backward time mapping circuit receives the non-selected data of the corresponding input part and maps the non-selected data according to the backward code word deviation table in the code word deviation table to generate a backward time mapping signal; A static response circuit receives the static mapping signal and processes it according to a set of static response coefficients among the multiple sets of response coefficients to generate a static output calibration signal corresponding to one of the N calibration parts in the calibration signals; A lead response circuit receives the lead time mapping signal and processes it according to a set of lead response coefficients among the plurality of sets of response coefficients to generate a lead output calibration signal of the corresponding calibration part; A backward response circuit receives the backward time mapping signal and processes it according to a set of backward response coefficients among the multiple sets of response coefficients to generate a backward output calibration signal of the corresponding calibration part; as well as The pseudo noise response circuit receives the selected data of the corresponding input part and processes it according to a set of pseudo noise response coefficients to generate a pseudo noise calibration signal of the corresponding calibration part.

4. The digital-to-analog conversion device of claim 3 , wherein in a first training phase, each of the N calibration circuits converges the set of pseudo-noise response coefficients of the pseudo-noise response circuit according to the echo signal, and the static response circuit, the leading response circuit, and the lagging response circuit set the set of static response coefficients, the set of leading response coefficients, and the set of leading response coefficients according to the converged set of pseudo-noise response coefficients of each of the N calibration circuits; and In a second training phase, each of the N calibration circuits updates one of the codeword deviation tables according to one of the offsets associated with each of the N calibration circuits.

5. The digital-to-analog conversion device as claimed in claim 4, wherein the target calibration circuit of the N calibration circuits corresponds to a target input portion of the N input portions and corresponds to a set of converged target pseudo-noise response coefficients, the leading calibration circuit of the N calibration circuits is used to receive a leading input portion relative to the target input portion and corresponds to a set of converged leading pseudo-noise response coefficients, and the lagging calibration circuit of the N calibration circuits is used to receive a lagging input portion relative to the target input portion and corresponds to a set of converged lagging pseudo-noise response coefficients; The static response circuit of the target calibration circuit sets the group of converged target pseudo-noise response coefficients as the group of static response coefficients, the leading response circuit sets the group of leading response coefficients according to the group of converged target pseudo-noise response coefficients and the group of converged leading pseudo-noise response coefficients, and the lagging response circuit sets the group of lagging response coefficients according to the group of converged target pseudo-noise response coefficients and the group of converged lagging pseudo-noise response coefficients.

6. The digital-to-analog conversion device as described in claim 5, wherein the leading response circuit of the target calibration circuit superimposes the group of convergent target pseudo-noise response coefficients with positive and negative inversion on the group of convergent leading pseudo-noise response coefficients to set them as the group of leading response coefficients, and the lagging response circuit superimposes the group of convergent target pseudo-noise response coefficients with positive and negative inversion on the group of convergent lagging pseudo-noise response coefficients to set them as the group of lagging response coefficients.

7. The digital-to-analog conversion device of claim 6, wherein when the target calibration circuit corresponds to the most leading part of the N input parts, the leading response circuit shifts the group of converged leading pseudo noise response coefficients to the left and fills them with 0 and then superimposes them; When the target calibration circuit corresponds to the most backward part of the N input parts, the backward response circuit repeatedly superimposes the last one of the group of converged backward pseudo noise response coefficients minus one.

8. The digital-to-analog conversion device of claim 1, further comprising a residual echo cancellation circuit, comprising: a residual echo response circuit, receiving the input digital signal and processing it according to a set of residual echo response coefficients to generate a residual echo cancellation signal; and A cancellation circuit, subtracting the residual echo cancellation signal from the error signal to generate a final error signal; The residual echo response circuit converges according to the final error signal, and the calibration parameter calculation circuit actually generates the offsets according to the final error signal and path information related to the echo calibration circuit.

9. A digital-to-analog conversion device as described in claim 1, wherein the input digital signal is generated by oversampling an original digital signal having a set of original codewords, the conversion circuit comprises a plurality of current sources, and the current sources comprise a selected current source and a plurality of non-selected current sources, the selected data corresponds to the selected current source, the non-selected data corresponds to the non-selected current sources, wherein the selected data has minimum data correlation between N input parts and between the original codewords relative to the non-selected data.

10. A digital to analog conversion method with a signal calibration mechanism, applied to a digital to analog conversion device, comprising: causing a conversion circuit including a plurality of current sources operating at a first frequency to perform conversion according to a signal input associated with an input digital signal having a set of input codewords to generate an output analog signal, wherein the input digital signal is sequentially and evenly divided into N input parts, where N is a positive integer greater than 1; The echo transmission circuit performs signal processing on the echo path through which the output analog signal passes, so as to generate an echo signal having a second frequency by down-sampling, wherein the second frequency is 1 / N of the first frequency; The N calibration circuits included in the echo calibration circuit and operating at the second frequency respectively input selected data included in one of the N input parts as pseudo noise and a plurality of non-selected data as signals, and perform mapping by a plurality of codeword deviation tables and processing by a plurality of response coefficients to generate one of the N calibration parts of the calibration signal; Enable the calibration parameter operation circuit operating at the second frequency to generate a plurality of offsets according to an error signal of the echo signal relative to the calibration signal and path information related to the echo calibration circuit; as well as The echo calibration circuit is made to converge the plurality of response coefficients according to the error signal and the pseudo noise transmission path information from the conversion circuit to the echo transmission circuit, and the plurality of codeword deviation tables are updated according to the offsets.

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