Low-noise short-offset transient electromagnetic receiving conditioning circuit and receiver

Abstract

The present disclosure relates to a low-noise short-offset transient electromagnetic receiving conditioning circuit and a receiver. The conditioning circuit includes: a first power supply filtering circuit, a second power supply filtering circuit, an active filtering circuit, a power frequency noise suppression circuit, and a low-noise amplification circuit; the first power supply filtering circuit and the second power supply filtering circuit are respectively used to filter the first power supply and the second power supply to reduce noise; the active filtering circuit is used to filter out interference signals; the power frequency noise suppression circuit is used to filter out power frequency noise; the low-noise amplification circuit includes an input-stage amplification circuit, an intermediate-stage amplification circuit, and an output-stage amplification circuit. The above technical solution of the present application sets multiple filtering circuits to filter out noise, which is beneficial to reducing noise.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technologies, and in particular, to a low-noise short-offset transient electromagnetic receiving conditioning circuit and a receiver. Background Art

[0002] The short-offset transient electromagnetic method (SOTEM) has the advantages of large detection depth and strong resolution ability. As a broadband near-source method, to fully exploit the detection potential of the method, it is necessary to break through the bandwidth limitation and achieve a large bandwidth at the receiving end respectively. Under the condition of a large bandwidth, the noise interference is relatively serious. Summary of the Invention

[0003] To overcome the problems existing in the related art, the present disclosure provides a low-noise short-offset transient electromagnetic receiving conditioning circuit and a receiver, so as to solve the problem of relatively serious noise interference under the condition of a large bandwidth in the related art.

[0004] According to the first aspect of the embodiments of the present disclosure, a low-noise short-offset transient electromagnetic receiving conditioning circuit is provided, including: a first power supply filtering circuit, a second power supply filtering circuit, an active filtering circuit, a power frequency noise suppression circuit, and a low-noise amplification circuit. The above-mentioned first power supply filtering circuit and the second power supply filtering circuit are respectively used for filtering the first power supply and the second power supply to reduce noise. The above-mentioned active filtering circuit is used to filter out interference signals. The above-mentioned power frequency noise suppression circuit is used to filter out power frequency noise.

[0005] The above-mentioned low-noise amplification circuit includes: an input stage amplification circuit, an intermediate stage amplification circuit, and an output stage amplification circuit.

[0006] In an implementation manner, the above-mentioned input stage amplification circuit includes: a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode, a ninth triode. A first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor.

[0007] The above-mentioned first triode and the above-mentioned second triode form a current mirror. The emitter of the above-mentioned first triode and the emitter of the above-mentioned second triode are respectively connected to the power supply. The base of the above-mentioned first triode is respectively connected to the base of the above-mentioned second triode, the collector of the above-mentioned third triode, and the collector of the above-mentioned fourth triode.

[0008] The collector of the first triode is connected to the collector of the fourth triode. The base of the third triode is connected to the first end of the first resistor, and the second end of the first resistor is grounded. The base of the fourth triode is connected to the first end of the second resistor, and the second end of the second resistor is grounded. The emitter of the third triode is connected to the emitter of the fifth triode. The emitter of the fourth triode is connected to the emitter of the sixth triode. The base of the fifth triode is connected to the base of the sixth triode. The collector of the fifth triode is respectively connected to the collector of the seventh triode and the base of the ninth triode. The collector of the sixth triode is respectively connected to the collector of the eighth triode and the base of the twelfth triode in the intermediate stage amplifier circuit. The base of the seventh triode is connected to the base of the eighth triode. The emitter of the seventh triode is respectively connected to the first end of the fourth resistor and the first end of the third resistor. The emitter of the eighth triode is respectively connected to the first end of the fifth resistor and the second end of the third resistor. The second ends of the fourth resistor and the fifth resistor are connected to a negative voltage.

[0009] In one embodiment, the intermediate stage amplifier circuit includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a zero resistor, a thirteenth triode, an eleventh triode, and a twelfth triode.

[0010] The first ends of the seventh resistor and the eighth resistor are respectively connected to a positive voltage. The second end of the seventh resistor is respectively connected to the bases of the thirteenth triode and the eleventh triode, and is connected to the collector of the eleventh triode. The emitters of the thirteenth triode and the eleventh triode are connected to a negative voltage. The second end of the eighth resistor is connected to the first end of the ninth resistor, and the second end of the ninth resistor is respectively connected to the second end of the zero resistor and the collector of the twelfth triode. The emitter of the twelfth triode is connected to the first end of the tenth resistor, and the second end of the tenth resistor is connected to a negative voltage.

[0011] In one embodiment, the above output stage amplifier circuit includes: a thirteenth resistor, an eleventh resistor, a twelfth resistor, a fourteenth resistor, a first capacitor, a second capacitor, and a third capacitor. The first end of the thirteenth resistor is connected to a positive voltage. The second end of the thirteenth resistor is respectively connected to the first end of the second capacitor and the first end of the operational amplifier. The second end of the second capacitor is respectively grounded and connected to the first end of the eleventh resistor. The second end of the eleventh resistor is respectively connected to the positive input terminal of the operational amplifier and the first end of the first capacitor. The second end of the first capacitor is respectively connected to the first end of the zero resistor and the second end of the ninth resistor in the intermediate stage amplifier circuit. The first end of the twelfth resistor is connected to the negative input terminal of the operational amplifier, and the second end is respectively grounded and connected to the first end of the third capacitor. The second end of the third capacitor is respectively connected to the second end of the operational amplifier and the first end of the fourteenth resistor. The second end of the fourteenth resistor is connected to a negative voltage.

[0012] In one embodiment, the above first power supply filtering circuit includes: a thirteenth triode. The emitter of the thirteenth triode is respectively connected to the anode of the eighth diode, the anode of the ninth diode, and the first end of the first filtering capacitor. The second end of the first filtering capacitor is grounded. The collector of the thirteenth triode is respectively connected to the cathode of the seventh diode, the first end of the second filtering capacitor, the first end of the seventeenth resistor, the cathode of the seventh diode, and the input power supply. The second end of the seventeenth resistor, the anode of the seventh diode, the second end of the eighteenth resistor, the first end of the third filtering capacitor, and the first end of the fourth filtering capacitor are connected together. The second end of the third filtering capacitor and the second end of the fourth filtering capacitor are connected together and grounded. The base of the thirteenth triode is respectively connected to the cathode of the eighth diode and the first end of the eighteenth resistor.

[0013] In one embodiment, the above second power supply filtering circuit includes: a fourteenth triode. The emitter of the fourteenth triode is respectively connected to the cathode of the eleventh diode, the first end of the fifth filtering capacitor, and the cathode of the twelfth diode. The second end of the fifth filtering capacitor is grounded. The base of the fourteenth triode is respectively connected to the first end of the twentieth resistor and the anode of the eleventh diode. The collector of the fourteenth triode is respectively connected to the first end of the nineteenth resistor, the anode of the twelfth diode, the anode of the twelfth diode, and the first end of the sixth filtering capacitor. The second end of the sixth filtering capacitor is grounded. The cathode of the twelfth diode is respectively connected to the second end of the twentieth resistor, the second end of the nineteenth resistor, the first end of the seventh filtering capacitor, and the first end of the eighth filtering capacitor; the second end of the seventh filtering capacitor and the second end of the eighth filtering capacitor are connected together and grounded.

[0014] In one embodiment, the above power frequency noise suppression circuit includes: an amplifier and a voltage follower;

[0015] The positive input terminals of the above amplifiers are respectively connected to the first ends of the second filter capacitor and the second filter resistor. The second ends of the second filter capacitor are respectively connected to the first ends of the first filter capacitor and the third filter resistor. The second ends of the second filter resistor are respectively connected to the first ends of the third filter capacitor and the first filter resistor. The second ends of the first filter capacitor and the second ends of the first filter resistor are connected together. The second ends of the third filter resistor and the second ends of the third filter capacitor are connected together and connected to the output terminal of the voltage follower. The positive input terminal of the voltage follower is respectively connected to the first ends of the fifth filter resistor and the fourth filter resistor. The second end of the fifth filter resistor is grounded, and the second end of the fourth filter resistor is connected to the output terminal of the above amplifier.

[0016] In one embodiment, the above active filter circuit includes: a first active filter operational amplifier and a second active filter operational amplifier. The output terminal of the first active filter operational amplifier is respectively connected to the first end of the first active filter resistor, the first end of the first active filter capacitor and the inverting input terminal of the first active filter operational amplifier. The second end of the first active filter capacitor is respectively connected to the first ends of the first active filter resistor and the second active filter resistor. The second end of the second active filter resistor is respectively connected to the first end of the second active filter capacitor and the non-inverting input terminal of the first active filter operational amplifier. The output terminal of the second active filter operational amplifier is respectively connected to the first end of the third active filter capacitor and the inverting input terminal of the second active filter operational amplifier. The second end of the third active filter capacitor is respectively connected to the first ends of the third active filter resistor and the fourth active filter resistor. The second end of the fourth active filter resistor is respectively connected to the first end of the fourth active filter capacitor and the non-inverting input terminal of the second active filter operational amplifier.

[0017] In a second aspect, the present application proposes a receiver, including the low-noise short-offset transient electromagnetic receiving signal conditioning circuit described in any one of the above, and further including: a main control board, a connection board and an analog board. The low-noise short-offset transient electromagnetic receiving signal conditioning circuit is arranged on the analog board.

[0018] There is a magnetic coupling isolation module on the connection board, which is respectively connected to the digital signal ports of the analog board and the main control board.

[0019] In some embodiments, a cascaded digital filtering and sampling device is arranged on the main control board, and the cascaded digital filtering and sampling device includes:

[0020] The first FIR filter decimation device, the input end of the first FIR filter decimation device inputs the original data, and the output end outputs the first decimated data with a frequency twice that of the original data.

[0021] The second FIR filter decimation device, the input end of the second FIR filter decimation device inputs the first decimated data, and the output end outputs the second decimated data with a frequency twice that of the first decimated data.

[0022] The third FIR filter decimation device, the input end of the third FIR filter decimation device inputs the second decimated data, and the output end outputs the third decimated data with a frequency twice that of the second decimated data.

[0023] The fourth FIR filter decimation device, the input end of the fourth FIR filter decimation device inputs the third decimated data, and the output end outputs the fourth decimated data with a frequency twice that of the third decimated data.

[0024] The data selector, the input ends of the data selector respectively input the original data, the first decimated data, the second decimated data, the third decimated data and the fourth decimated data.

[0025] The output end of the data selector outputs the finally filtered data.

[0026] The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:

[0027] For the above technical solution of the present application, a low-noise short-offset transient electromagnetic receiving conditioning circuit and a receiver, the conditioning circuit includes a power supply filtering circuit, an active filtering circuit, a power frequency noise suppression circuit and a low-noise amplification circuit; the above power supply filtering circuit is used to filter the power supply to reduce noise; the above active filtering circuit is used to filter out interference signals; the above power frequency noise suppression circuit is used to filter out power frequency noise. The above technical solution of the present application realizes noise filtering.

[0028] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure.

[0030] Figure 1 It is a schematic diagram of a semi-aerial frequency domain electromagnetic method shown according to an exemplary embodiment;

[0031] Figure 2 It is a block diagram of a low-noise short-offset transient electromagnetic receiving signal conditioning circuit shown according to an exemplary embodiment;

[0032] Figure 3 It is a low-noise amplifier circuit diagram shown according to an exemplary embodiment;

[0033] Figure 4 It is a first power supply filtering circuit diagram shown according to an exemplary embodiment;

[0034] Figure 5 It is a second power supply filtering circuit diagram shown according to an exemplary embodiment;

[0035] Figure 6 It is a power frequency noise suppression circuit diagram shown according to an exemplary embodiment;

[0036] Figure 7 It is an active filter circuit diagram shown according to an exemplary embodiment;

[0037] Figure 8 It is a block diagram of the structure of a receiver shown according to an exemplary embodiment;

[0038] Figure 9 It is a cascaded digital filter combination shown according to an exemplary embodiment. Detailed implementation manners

[0039] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all the implementation manners consistent with the present disclosure. On the contrary, they are only examples of the devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0040] It should be noted that all actions of obtaining signals, information, or data in this application are carried out on the premise of complying with the corresponding data protection regulations and policies of the country where the location is located and obtaining the authorization given by the owner of the corresponding device.

[0041] See the appendix Figure 1, the semi-aerial frequency domain electromagnetic method is an artificial active source exploration method that uses ground transmission and aerial reception to explore geological structures. The semi-aerial electromagnetic detection is carried out by the cooperation of two parts: the transmitting system and the receiving system. The specific detection principle is as follows: The electromagnetic transmitter is located on the ground and provides an alternating current to the grounded wire as an excitation source. The changing current will generate a changing magnetic field, which is called the primary field. The underground medium generates eddy currents under the action of the primary field, and the eddy currents will gradually decay over time. The changing eddy currents will generate an induced magnetic field, which is called the secondary field. The unmanned aerial vehicle carries the semi-aerial electromagnetic receiving system in the air and receives the secondary field data through the magnetic field sensor. The magnetic induction coil can convert the changing magnetic field signal into an induced voltage signal. The receiving system first performs signal conditioning such as amplification and filtering on the induced voltage signal through the electronics unit, and then collects and stores the data. Based on the electromagnetic differences between abnormal bodies such as underground mineral resources and the earth, the data stored in the semi-aerial electromagnetic receiving system is processed by forward and inverse modeling, etc. Combining the transmitted waveform and geological exploration experience, the underground structure and the location of the abnormal body are explained and analyzed, so as to achieve the purpose of detecting the deep geological structure. The above receiving system mainly includes two parts: one is the magnetic induction coil, that is, the receiving sensor of the secondary field signal; the other is the receiver, which performs noise reduction, amplification and acquisition on the signals from the sensor. Under the condition of large bandwidth, the noise interference in the receiver is relatively serious.

[0042] Based on this, the present application proposes a low-noise short-offset transient electromagnetic receiving conditioning circuit 1, see the appendix Figure 2 , including: a first power supply filtering circuit 11, a second power supply filtering circuit 12, an active filtering circuit 13, a power frequency noise suppression circuit 14 and a low-noise amplification circuit 15. The above first power supply filtering circuit 11 and second power supply filtering circuit 12 are respectively used to filter the first power supply and the second power supply to reduce noise. The above active filtering circuit 13 is used to filter out interference signals. The above power frequency noise suppression circuit 14 is used to filter out power frequency noise. The above low-noise amplification circuit 15 includes: an input stage amplification circuit, an intermediate stage amplification circuit and an output stage amplification circuit.

[0043] The above technical solutions of the present application, the first power supply filtering circuit, the second power supply filtering circuit, the active filtering circuit, the power frequency noise suppression circuit and the low-noise amplification circuit; are beneficial to eliminating noise.

[0044] In some embodiments, to meet the project requirements of a large and adjustable gain for the amplifier circuit, the low-noise amplifier circuit consists of three-stage amplifier circuits, namely the input-stage amplifier circuit, the intermediate-stage amplifier circuit, and the output-stage amplifier circuit. The noise of the multi-stage amplifier circuit is mainly determined by the input-stage amplifier circuit. By using independent components to build the input-stage amplifier circuit, the internal noise is much lower than that of the integrated operational amplifier. Therefore, a low-noise bipolar junction transistor (BJT) is selected as the core to build the input-stage and intermediate-stage amplifier circuits. In addition, to reduce the common-mode interference caused by DC coupling, the amplifier circuit adopts a differential input form, and two-channel PNP matched transistors MAT03 and two-channel NPN matched transistors MAT12 with extremely low noise power spectral density and high gain-bandwidth product are selected. The matched transistors contain two transistors with extremely similar parameters, and the difference can be ignored. The high matching of the two can reduce the impact on the circuit caused by transistor differences and better realize the function of the differential circuit.

[0045] See the appendix Figure 3, the input stage amplifier circuit includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, and a ninth transistor Q9. A first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The first transistor Q1 and the second transistor Q2 form a current mirror. The emitter of the first transistor Q1 and the emitter of the second transistor Q2 are respectively connected to a power supply. The base of the first transistor Q1 is respectively connected to the base of the second transistor Q2, the collector of the third transistor Q3, and the collector of the fourth transistor Q4. The collector of the first transistor Q1 is connected to the collector of the fourth transistor Q4. The base of the third transistor Q3 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded. The base of the fourth transistor Q4 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded; the emitter of the third transistor Q3 is connected to the emitter of the fifth transistor Q5; the emitter of the fourth transistor Q4 is connected to the emitter of the sixth transistor Q6; the base of the fifth transistor Q5 is connected to the base of the sixth transistor Q6. The collector of the fifth transistor Q5 is connected to the collector of the seventh transistor Q7 and the base of the ninth transistor Q9, respectively. The collector of the sixth transistor Q6 is connected to the collector of the eighth transistor Q8 and the base of the twelfth transistor in the intermediate stage amplifier circuit, respectively. The base of the seventh transistor Q7 is connected to the base of the eighth transistor Q8. The emitter of the seventh transistor Q7 is connected to the first end of the fourth resistor R4 and the first end of the third resistor R3, respectively. The emitter of the eighth transistor Q8 is connected to the first end of the fifth resistor R5 and the second end of the third resistor R3, respectively. A second end of the fourth resistor R4 and a second end of the fifth resistor R5 are connected to a negative voltage.

[0046] When the operating current of MAT03 and MAT12 is maintained above 0.01mA, its noise can remain stable. In order to make the transistor work normally and stably, it is necessary to design a reasonable bias circuit. The voltage source bias circuit is susceptible to factors such as temperature and power supply fluctuations, resulting in the drift of the output voltage, thereby reducing the stability of the bias circuit, and the input end of the amplifier circuit designed by the present invention is directly coupled, and the voltage source will introduce a DC voltage component into the signal, limiting the range of variation of the signal. In addition, the voltage source has limited control over the collector current of the transistor, which is not conducive to suppressing the noise of the circuit. Therefore, the present invention selects a current source to design a bias circuit. Transistor Q1, transistor Q2, transistor Q10, and transistor Q11 constitute a mirror current source, and the high matching of MAT12 and MAT03 transistors just solves the problem that the mirror current source circuit has high requirements for transistor matching.

[0047] The input - stage amplifier circuit is mainly composed of MAT12 (Q3, Q4, Q7, Q8) and MAT03 (Q5, Q6). The input signal acts on the bases of the third transistor Q3 and the fourth transistor Q4. The common - collector amplifier circuit formed by the third transistor Q3 and the fourth transistor Q4 has the characteristics of high input impedance and low output impedance, enhancing the load - driving ability of the whole circuit. The fifth transistor Q5 and the sixth transistor Q6 form a common - base amplifier circuit, which has a high voltage gain and improves the bandwidth of the circuit. The seventh transistor Q7, the eighth transistor Q8, and the ninth transistor Q9 act as active loads, which can transfer the change of the collector current of the fifth transistor Q5, Δic5, to the collector of the sixth transistor Q6. The signal is output from the collector of the sixth transistor Q6, thus realizing differential input and single - ended output. The approximate parameters of the transistors are the same. When a differential - mode signal is input, Δie5 = −Δie6, and Δib5 = Δib6, that is, Δic5 = −Δic6. The base current of the transistor Q9 is very small and can be ignored, so Δic5 = Δic7. When R4 = R5, Δic7 = Δic8, so Δio1 = Δic6−Δic8 = −2Δic5. When a common - mode signal is input, Δic5 = Δic6, and similarly, Δio1 = 0 can be obtained. This shows that the input - stage amplifier circuit can amplify the differential - mode signal and suppress the interference of common - mode signals such as external noise. Adjusting the resistor R3 can eliminate the influence caused by temperature drift and transistor differences.

[0048] In some embodiments, the above - mentioned intermediate - stage amplifier circuit includes: a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a zero - th resistor R0, a thirteenth transistor Q10, an eleventh transistor Q11, and a twelfth transistor Q12. The first ends of the seventh resistor R7 and the eighth resistor R8 are respectively connected to the positive voltage. The second end of the seventh resistor R7 is respectively connected to the base of the thirteenth transistor Q10 and the base of the eleventh transistor, and is connected to the collector of the eleventh transistor Q11. The emitters of the thirteenth transistor Q10 and the eleventh transistor Q11 are connected to the negative voltage. The second end of the eighth resistor R8 is connected to the first end of the ninth resistor R9. The second end of the ninth resistor R9 is respectively connected to the second end of the zero - th resistor R0 and the collector of the twelfth transistor Q12. The emitter of the twelfth transistor Q12 is connected to the first end of the tenth resistor R10, and the second end of the tenth resistor R10 is connected to the negative voltage.

[0049] The intermediate-stage amplifier circuit is a common-emitter amplifier circuit centered around the twelfth triode Q12. The twelfth triode Q12 is an NPN-type transistor with a model number of 2N2222. While amplifying the voltage, a negative feedback resistor R0 is introduced and connected between the input terminal Ui and the collector of Q12 to control the amplification factor of the circuit. The eighth resistor R8 is a large resistor, and the ninth resistor R9 is a small resistor, which are used to roughly adjust and finely adjust the offset voltage respectively, so that the DC component of the twelfth triode Q12 is close to zero.

[0050] In some embodiments, the above output-stage amplifier circuit includes: a thirteenth resistor R13, an eleventh resistor R11, a twelfth resistor R12, a fourteenth resistor R14, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0051] The first end of the above thirteenth resistor R13 is connected to a positive voltage; where the positive voltage is 15V. The second end of the above thirteenth resistor R13 is respectively connected to the first end of the above second capacitor C2 and the first end of the operational amplifier. The second end of the above second capacitor C2 is respectively grounded and the first end of the above eleventh resistor R11. The second end of the above eleventh resistor R11 is respectively connected to the positive input terminal of the above operational amplifier A0 and the first end of the above first capacitor C1. The second end of the above first capacitor C1 is respectively connected to the first end of the zero resistor R0 and the second end of the ninth resistor R9 in the intermediate-stage amplifier circuit. The first end of the above twelfth resistor R12 is connected to the negative input terminal of the above operational amplifier A0, and the second end is respectively grounded and the first end of the above third capacitor C3. The second end of the above third capacitor C3 is respectively connected to the second end of the above operational amplifier A0 and the first end of the above fourteenth resistor R14. The second end of the above fourteenth resistor R14 is connected to a negative voltage. Where the negative voltage is -15V.

[0052] The output-stage amplifier circuit is built around the operational amplifier A0. The integrated operational amplifier chip has excellent low-noise amplification performance and extremely high common-mode rejection ratio, and is particularly suitable for conditioning weak signals. Among them, the first capacitor C1 is a decoupling capacitor used to eliminate the DC bias. The second capacitor C2 and the third capacitor C3 are filter capacitors to reduce the influence of power supply ripple. The thirteenth resistor R13 and the fourteenth resistor R14 are current-limiting resistors to prevent excessive current from damaging the operational amplifier A0 chip. The input bias current of the operational amplifier A0 must have a return path to the ground, and the eleventh resistor R11 and the twelfth resistor R12 provide the ground loop. Rg is an adjustment resistor, and changing its resistance value can achieve adjustable gain of the output-stage amplifier circuit.

[0053] The stability of the power supply system is equally important. If the power supply noise is too large, it will seriously affect the working performance of the system. The present invention uses a ±15V dual power supply for operation. To reduce the ripple of the ±15V voltage, an electronic filter circuit is designed.

[0054] See Appendix Figure 4, the above-mentioned first power supply filtering circuit 11 includes: a thirteenth triode Q13, the emitter of the thirteenth triode Q13 is respectively connected to the anode of an eighth diode D8, the anode of a ninth diode D9, and the first end of a first filtering capacitor C26. The second end of the first filtering capacitor C26 is grounded. The collector of the thirteenth triode Q13 is respectively connected to the cathode of a seventh diode D7, the first end of a second filtering capacitor C23, the first end of a seventeenth resistor R17, the cathode of the seventh diode D7 and the input power supply. The second end of the seventeenth resistor R17, the anode of the seventh diode D7, the second end of an eighteenth resistor R18, the first end of a third filtering capacitor C24 and the first end of a fourth filtering capacitor C25 are connected together. The second end of the third filtering capacitor C24 and the second end of the fourth filtering capacitor C25 are connected together and grounded. The base of the thirteenth triode Q13 is respectively connected to the cathode of the eighth diode and the first end of the eighteenth resistor R18.

[0055] The first power supply is +15V. The first power supply filtering circuit consists of two parts: the first part is a π-type filter, which is composed of the second filtering capacitor C23, the seventeenth resistor R17, and the third filtering capacitor C24, and thus can filter the Vi ripple. The second part is an emitter follower, which is composed of the thirteenth triode Q13, the seventeenth resistor R17, and the eighteenth resistor R18. The seventeenth resistor R17 and the eighteenth resistor R18 are the bias resistors of the thirteenth triode Q13 to stabilize the base potential. Since the current fluctuation input to the base of the thirteenth triode Q13 is small, the output emitter current is also relatively stable. The emitter follower has the function of current amplification, enhancing the load-carrying capacity of the circuit.

[0056] The thirteenth triode Q13, the seventeenth resistor R17, and the third filtering capacitor C24 form a capacitor multiplier, which can be equivalent to a filtering capacitor. Its equivalent capacitance is equivalent to the third filtering capacitor C24 multiplied by the current gain of the triode, significantly increasing the capacitance and improving the filtering effect. The advantage of the capacitor multiplier is that in the case of the same capacitance value, its volume is smaller than that of a real capacitor, and it can well suppress the power supply ripple noise when carrying a load. It is especially suitable for occasions where low-noise DC power supply is required when designing the electronics unit of a short-offset electromagnetic receiving system.

[0057] See the appendix Figure 5, the second power supply filtering circuit 12 includes: a fourteenth triode Q14, the emitter of the fourteenth triode Q14 is respectively connected to the cathode of an eleventh diode D11, the first end of a fifth filtering capacitor C30, and the cathode of a twelfth diode D12. The second end of the fifth filtering capacitor C30 is grounded. The base of the fourteenth triode Q14 is respectively connected to the first end of a twentieth resistor R20 and the anode of the eleventh diode D11. The collector of the fourteenth triode Q14 is respectively connected to the first end of a nineteenth resistor R19, the anode of a twelfth diode D10, the anode of the twelfth diode D12, and the first end of a sixth filtering capacitor C27. The second end of the sixth filtering capacitor C27 is grounded. The cathode of the twelfth diode Q10 is respectively connected to the second end of the twentieth resistor R20. The second end of the nineteenth resistor R19, the first end of a seventh filtering capacitor C28, and the first end of an eighth filtering capacitor C29. The second end of the seventh filtering capacitor C28 and the second end of the eighth filtering capacitor C29 are connected together and grounded.

[0058] See the appendix Figure 6 , when the short offset transient electromagnetic method is used for actual detection, the magnetic induction coil will also superimpose the noise in the target frequency band on the signal. Since the power grid equipment uses alternating current with a frequency of 50 Hz, the target signal often contains 50 Hz power frequency noise, which causes great interference to the later signal processing. Therefore, it is necessary to filter a single frequency point of 50 Hz. The present invention adopts a double-T band-stop filter to filter out the power frequency interference signal and introduces voltage-controlled feedback to make it have excellent frequency selection characteristics and filtering performance. The filter is mainly composed of a frequency selection module, an amplification module, and a feedback module.

[0059] The above-mentioned power frequency noise suppression circuit 14 includes: an amplifier and a voltage follower. The positive input terminal of the above-mentioned amplifier A1 is respectively connected to the first terminal of the second filter capacitor C52 and the first terminal of the second filter resistor R52. The output terminal of the above-mentioned amplifier A1 outputs a voltage U0. The second terminal of the above-mentioned second filter capacitor C52 is respectively connected to the first terminal of the first filter capacitor C51 and the first terminal of the third filter resistor R53. The second terminal of the above-mentioned second filter resistor R52 is respectively connected to the first terminal of the third filter capacitor C53 and the first terminal of the first filter resistor R51. Among them, the first terminal of the first filter resistor R51 inputs a power supply Ui. The second terminal of the above-mentioned first filter capacitor C51 and the second terminal of the above-mentioned first filter resistor R51 are connected together. The second terminal of the above-mentioned third filter resistor R53 and the second terminal of the above-mentioned third filter capacitor C53 are connected together and connected to the output terminal of the voltage follower. The positive input terminal of the above-mentioned voltage follower A2 is respectively connected to the first terminal of the fifth filter resistor R55 and the first terminal of the fourth filter resistor R54. The second terminal of the above-mentioned fifth filter resistor R55 is grounded. The second terminal of the above-mentioned fourth filter resistor R54 is connected to the output terminal of the above-mentioned amplifier A1. A single-T network is composed of R51, R52, and C53 and can be regarded as a low-pass filter. Another single-T network is composed of C51, C52, and R53 and can be regarded as a high-pass filter. By changing the resistance value and capacitance value, the value of the center frequency f_0 of the wave trap, that is, the frequency value to be filtered, can be determined. The output terminal of the amplifier A1 is the output of the wave trap, and the output terminal of the amplifier A1 and the voltage follower A2 form a voltage feedback circuit, feeding back a part of the output signal of the amplifier A1 to the vertical arm of the double-T network to form bootstrap, thereby introducing positive feedback. The fourth filter resistor R54 and the fifth filter resistor R55 are used to determine the value of the positive feedback coefficient m.

[0060] The center frequency f_0 of the wave trap of the present invention is 50 Hz. When the input signal is of other frequencies, its gain is 1. The operational amplifier chip is selected as AD8602, which has the characteristics of being less affected by temperature and having a large dynamic range, and can stably respond to the input signal when powered by a low voltage.

[0061] The bandwidth BW and Q value of the wave trap are respectively:

[0062]

[0063] Among them, BW is the bandwidth, f_H is the upper limit frequency, f_L is the lower limit frequency, f_0 is the center frequency, Q is the ratio of the center frequency to the bandwidth, and m is the positive feedback coefficient.

[0064] If you want the wave trap to have good filtering performance, that is, the wave trap has a narrow bandwidth and a high Q value, then the value of m needs to be taken close to 1. The bandwidth BW of the wave trap is the ratio of the center frequency f_0 to Q. When the center frequency is selected as 50 Hz, its bandwidth can be reduced by increasing the Q value.

[0065] In some embodiments, when the electromagnetic receiving system is operating, the magnetic induction coil will receive signals of all frequencies in the environment, that is, a large amount of noise is mixed in the target signal, including external environmental noise, UAV flight noise, operating noise of electronic components on the circuit board, ripple noise introduced by the battery and power supply, etc., which increases the difficulty of subsequent data processing and analysis and may even directly affect the detection result. In addition, when signals of various frequencies are superimposed in the time domain, the signal amplitude may exceed the maximum receiving voltage of the receiving system, and the noise generated by electronic components is also positively correlated with the size of the frequency band. Therefore, it is necessary to design a suitable filter to limit the bandwidth of the signal conditioning circuit in the receiving system and block interference signals outside a specific frequency range. The passband cut-off frequency of the active low-pass filter circuit is set to 15 kHz, the stopband start frequency is set to 30 kHz, the passband attenuation is 3 dB, and the stopband attenuation is 30 dB. A fourth-order Butterworth low-pass filter circuit is formed in the form of cascading two second-order filters.

[0066] See the appendix Figure 7 As shown in the figure, the above-mentioned active filter circuit 13 includes: a first active filter operational amplifier A61 and a second active filter operational amplifier A62. The output terminal of the first active filter operational amplifier A61 is respectively connected to the first end of a first active filter resistor R63, the first end of a first active filter capacitor C61, and the inverting input terminal of the first active filter operational amplifier. The second end of the first active filter capacitor C61 is respectively connected to the first end of a first active filter resistor R61 and the first end of a second active filter resistor R62. The second end of the second active filter resistor R62 is respectively connected to the first end of a second active filter capacitor C62 and the non-inverting input terminal of the first active filter operational amplifier A61. The output terminal of the second active filter operational amplifier A62 is respectively connected to the first end of a third active filter capacitor C63 and the inverting input terminal of the second active filter operational amplifier A62. The second end of the third active filter capacitor C63 is respectively connected to the first end of a third active filter resistor R61 and the first end of a fourth active filter resistor R64. The second end of the fourth active filter resistor R64 is respectively connected to the first end of a fourth active filter capacitor C64 and the non-inverting input terminal of the second active filter operational amplifier A62.

[0067] In this embodiment, the chip models of the first active filter operational amplifier A61 and the second active filter operational amplifier A62 are NE5532. Two operational amplifiers are integrated inside this chip, which has an extremely low noise level and excellent output driving ability, and the high slew rate of this chip makes the output waveform not easily distorted.

[0068] Second, see the appendix Figure 8, this application proposes a receiver, which includes the low-noise short-offset transient electromagnetic receiving signal conditioning circuit described in one of the above items, and also includes: a main control board, a connection board, and an analog board.

[0069] The low-noise short-offset transient electromagnetic receiving signal conditioning circuit is arranged on the analog board.

[0070] There is a magnetic coupling isolation module on the connection board, which is respectively connected to the digital signal ports of the analog board and the main control board.

[0071] In this embodiment, the interface board is the bridge between the inside and outside of the instrument, and is integrated with a sensor interface, a power supply interface, a communication interface, and an interaction interface. Among them, the sensor interface is mainly a magnetic field sensor interface, and its connection wires are connected to the input ends of the analog channels on the analog board. The power supply interface is responsible for inputting an external 12V power supply, and supplies power to the entire system through a power distribution network. The communication interface and the interaction interface are responsible for the human-computer interaction function, and their internal wiring is connected to a chip with multiple processors (Multiprocessor System-on-Chip, MPSoC) on the main control board. In addition, the interface board also has functions such as overcurrent reverse connection protection and power monitoring. The digital interfaces of the power monitoring chip and the power control chip on the interface board are also connected to the MPSoC on the main control board.

[0072] There are 5 analog channels on the analog board to condition and perform analog-to-digital conversion on the analog signals of the magnetic field components. The signal conditioning circuit mainly includes a low-noise amplification circuit, an active filter circuit, a power frequency noise suppression circuit, etc. The analog-to-digital conversion circuit includes an analog-to-digital converter and its peripheral circuits, and its digital interface is connected to the MPSoC on the main control board through the connection board. The model of the analog-to-digital converter is AD7760, which can output sampled data with a 24-bit precision at a maximum frequency of 2.5 MSPS.

[0073] A magnetic coupling isolation module is arranged on the connection board, which is respectively connected to the digital signal ports of the analog board and the main control board, and is responsible for isolating the digital part and the analog part, cutting off the electrical connection to reduce the interference of the digital part on the analog signal. The analog-to-digital conversion data enters the main control board through the connection board.

[0074] The main control board uses an MPSoC with the model number ZU3EG as the main control chip, which is internally divided into two parts: ARM and FPGA. The two parts have different divisions of labor. The FPGA part is mainly responsible for controlling the analog board for analog-to-digital conversion, receiving and parsing the converted data, receiving and parsing GPS data, calibrating the oven-controlled crystal oscillator, managing the system power supply, and other functions. The ARM part is mainly responsible for the process control, human-computer interaction, data storage, and other functions of the entire acquisition station. The ARM part communicates with the FPGA part through the internal AXI bus of the chip, and realizes functions such as configuring acquisition parameters and controlling the start and stop of acquisition by reading and writing the FPGA registers. The analog-to-digital conversion data is transmitted to the ARM part in the form of a data stream after being parsed by the FPGA part, and is stored in the external hard disk by the ARM part.

[0075] In some embodiments, refer to the appendix Figure 9 , a cascaded digital filter sampling device is provided on the main control board, and the cascaded digital filter sampling device includes:

[0076] A first FIR filter decimation device, the input end of the first FIR filter decimation device inputs the original data, and the output end outputs the first decimated data with a frequency twice that of the original data.

[0077] Among them, the original data input at the input end is the data obtained after AD sampling.

[0078] A second FIR filter decimation device, the input end of the second FIR filter decimation device inputs the first decimated data, and the output end outputs the second decimated data with a frequency twice that of the first decimated data;

[0079] A third FIR filter decimation device, the input end of the third FIR filter decimation device inputs the second decimated data, and the output end outputs the third decimated data with a frequency twice that of the second decimated data;

[0080] A fourth FIR filter decimation device, the input end of the fourth FIR filter decimation device inputs the third decimated data, and the output end outputs the fourth decimated data with a frequency twice that of the third decimated data;

[0081] A data selector, the input ends of the data selector respectively input the original data, the first decimated data, the second decimated data, the third decimated data, and the fourth decimated data;

[0082] The output end of the data selector outputs the finally filtered data.

[0083] Refer to the appendix Figure 7, where each FIR filter decimation device is composed of an FIR filter with a length of 96 and provides 120 dB of attenuation at the Nyquist frequency. Cascade digital filter sampling avoids the spectral aliasing effect during the decimation process and can suppress out-of-band quantization noise generated by the analog-to-digital conversion process. Through the cascade digital filter sampling technology, the original sampling rate range of the analog-to-digital converter from 78 kSPS to 2.5 MSPS is extended to 4.9 kSPS to 2.5 MSPS, while ensuring the acquisition accuracy after the sampling rate is extended, enabling the instrument to be more flexibly applied to electromagnetic exploration in various frequency bands.

[0084] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only considered exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0085] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A receiver, characterized in that: include: Low-noise short-offset transient electromagnetic receiving signal conditioning circuit, main control board, connection board, interface board and simulation board; The low-noise short-offset transient electromagnetic receiving signal conditioning circuit is arranged on the analog board; The connection board is provided with a magnetic coupling isolation module, which is respectively connected to the digital signal ports of the analog board and the main control board; The main control board uses a chip MPSoC with multiple processors as the main control chip, which is internally divided into two parts: ARM and FPGA. The FPGA part is responsible for controlling the analog board to perform analog-to-digital conversion, receiving and parsing conversion data, receiving and parsing GPS data, calibrating the constant temperature crystal oscillator, and managing the system power supply function; The ARM part is responsible for the process control, human-computer interaction, and data storage of the entire acquisition station; The ARM part communicates with the FPGA part through the AXI bus inside the chip, and configures the acquisition parameters and controls the acquisition start and stop functions by reading and writing the FPGA register; The analog-to-digital conversion data is analyzed by the FPGA part and transmitted to the ARM part in the form of a data stream, and is stored in an external hard disk by the ARM part; The analog board has an analog-to-digital conversion circuit; the analog-to-digital conversion circuit is connected to the MPSoC chip with multiple processors on the main control board through the connection board; The interface board is integrated with a magnetic field sensor interface; The magnetic field sensor interface is connected to the analog channel input terminal on the analog board; The low-noise short-offset transient electromagnetic receiving signal conditioning circuit comprises: A first power supply filter circuit, a second power supply filter circuit, an active filter circuit, a power frequency noise suppression circuit and a low noise amplifier circuit; The first power supply filter circuit and the second power supply filter circuit are used to filter the first power supply and the second power supply respectively to reduce noise; The active filter circuit is used to filter out interference signals; The power frequency noise suppression circuit is used to filter out power frequency noise; The low-noise amplifier circuit comprises: an input-stage amplifier circuit, an intermediate-stage amplifier circuit and an output-stage amplifier circuit.

2. The receiver according to claim 1, characterized in that The power frequency noise suppression circuit comprises: an amplifier and a voltage follower; The positive input terminal of the amplifier is connected to the first end of the second filter capacitor and the first end of the second filter resistor respectively; The second end of the second filter capacitor is connected to the first end of the first filter capacitor and the first end of the third filter resistor respectively; The second end of the second filter resistor is connected to the first end of the third filter capacitor and the first end of the first filter resistor respectively; The second end of the first filter capacitor and the second end of the first filter resistor are connected together; The second end of the third filter resistor and the second end of the third filter capacitor are connected together and connected to the output end of the voltage follower; The positive input end of the voltage follower is connected to the first end of the fifth filter resistor and the first end of the fourth filter resistor respectively, the second end of the fifth filter resistor is grounded, and the second end of the fourth filter resistor is connected to the output end of the amplifier; The bandwidth BW and Q value are: BW=f H -f L =4(1-m)f0; Where BW is the bandwidth, f H is the upper frequency limit, f L is the lower limit frequency, f0 is the center frequency, Q is the ratio of the center frequency to the bandwidth, and m is the positive feedback coefficient; The m value is close to 1; When the center frequency is selected as 50Hz, the bandwidth is narrowed by increasing the Q value; The fourth filter resistor and the fifth filter resistor are used to determine the value of the positive feedback coefficient m.

3. The receiver according to claim 1, characterized in that The input stage amplifier circuit comprises: a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode and a ninth triode; a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor; The first transistor and the second transistor form a current mirror; The emitter of the first triode and the emitter of the second triode are respectively connected to a power supply; The base of the first triode is respectively connected to the base of the second triode, the collector of the third triode and the collector of the fourth triode; The collector of the first triode is connected to the collector of the fourth triode; The base of the third transistor is connected to the first end of the first resistor, and the second end of the first resistor is grounded; The base of the fourth transistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; The emitter of the third transistor is connected to the emitter of the fifth transistor; The emitter of the fourth triode is connected to the emitter of the sixth triode; The base of the fifth transistor is connected to the base of the sixth transistor; The collector of the fifth triode is connected to the collector of the seventh triode and the base of the ninth triode respectively; The collector of the sixth triode is respectively connected to the collector of the eighth triode and the base of the twelfth triode in the intermediate stage amplifier circuit; The base of the seventh transistor is connected to the base of the eighth transistor; The emitter of the seventh transistor is connected to the first end of the fourth resistor and the first end of the third resistor respectively; The emitter of the eighth transistor is connected to the first end of the fifth resistor and the second end of the third resistor respectively; The second end of the fourth resistor and the second end of the fifth resistor are connected to a negative voltage.

4. The receiver according to claim 1, characterized in that The intermediate stage amplifier circuit comprises: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a zeroth resistor, a tenth transistor, an eleventh transistor and a twelfth transistor; The first end of the seventh resistor and the first end of the eighth resistor are respectively connected to a positive voltage; The second end of the seventh resistor is connected to the base of the tenth transistor and the eleventh transistor, and is connected to the collector of the eleventh transistor; The emitters of the tenth transistor and the eleventh transistor are connected to a negative voltage; The second end of the eighth resistor is connected to the first end of the ninth resistor, the second end of the ninth resistor is respectively connected to the second end of the zeroth resistor and the collector of the twelfth transistor, the emitter of the twelfth transistor is connected to the first end of the tenth resistor, and the second end of the tenth resistor is connected to a negative voltage.

5. The receiver according to claim 1, characterized in that The output stage amplifier circuit comprises: a thirteenth resistor, an eleventh resistor, a twelfth resistor, a fourteenth resistor, a first capacitor, a second capacitor and a third capacitor; The first end of the thirteenth resistor is connected to a positive voltage; The second end of the thirteenth resistor is connected to the first end of the second capacitor and the first end of the operational amplifier respectively; The second end of the second capacitor is connected to the ground and the first end of the eleventh resistor respectively, and the second end of the eleventh resistor is connected to the positive input end of the operational amplifier and the first end of the first capacitor respectively; The second end of the first capacitor is connected to the first end of the zeroth resistor and the second end of the ninth resistor in the intermediate stage amplifier circuit respectively; The first end of the twelfth resistor is connected to the negative input terminal of the operational amplifier, and the second end is respectively connected to the ground and the first end of the third capacitor; The second end of the third capacitor is respectively connected to the second end of the operational amplifier and the first end of the fourteenth resistor; The second end of the fourteenth resistor is connected to a negative voltage.

6. The receiver according to claim 1, characterized in that The first power supply filter circuit comprises: a thirteenth transistor, the emitter of which is respectively connected to the anode of the eighth diode, the anode of the ninth diode, and the first end of the first filter capacitor; The second end of the first filter capacitor is grounded; The collector of the thirteenth transistor is respectively connected to the cathode of the seventh diode, the first end of the second filter capacitor, the first end of the seventeenth resistor, the cathode of the seventh diode and the input power supply; The second end of the seventeenth resistor, the anode of the seventh diode, the second end of the eighteenth resistor, the first end of the third filter capacitor and the first end of the fourth filter capacitor are connected together; The second end of the third filter capacitor and the second end of the fourth filter capacitor are connected together and grounded; The base of the thirteenth transistor is respectively connected to the cathode of the eighth diode and the first end of the eighteenth resistor.

7. The receiver according to claim 1, characterized in that The second power supply filter circuit comprises: a fourteenth transistor, the emitter of which is respectively connected to the cathode of the eleventh diode, the first end of the fifth filter capacitor, and the cathode of the twelfth diode; The second end of the fifth filter capacitor is grounded; The base of the fourteenth transistor is respectively connected to the first end of the twentieth resistor and the anode of the eleventh diode; The collector of the fourteenth triode is respectively connected to the first end of the nineteenth resistor, the anode of the tenth diode, the anode of the twelfth diode and the first end of the sixth filter capacitor; The second end of the sixth filter capacitor is grounded; The cathode of the tenth diode is respectively connected to the second end of the twentieth resistor, the second end of the nineteenth resistor, the first end of the seventh filter capacitor and the first end of the eighth filter capacitor; the second end of the seventh filter capacitor and the second end of the eighth filter capacitor are connected together and grounded.

8. The receiver according to claim 1, characterized in that The active filtering circuit comprises: a first active filter operational amplifier and a second active filter operational amplifier; The output end of the first active filter operational amplifier is respectively connected to the first end of the first active filter resistor, the first end of the first active filter capacitor and the inverting input end of the first active filter operational amplifier; The second end of the first active filter capacitor is respectively connected to the first end of the first active filter resistor and the first end of the second active filter resistor; The second end of the second active filter resistor is respectively connected to the first end of the second active filter capacitor and the non-inverting input end of the first active filter operational amplifier; The output terminal of the second active filter operational amplifier is respectively connected to the first terminal of the third active filter capacitor and the inverting input terminal of the second active filter operational amplifier; The second end of the third active filter capacitor is connected to the first end of the third active filter resistor and the first end of the fourth active filter resistor respectively; The second end of the fourth active filter resistor is respectively connected to the first end of the fourth active filter capacitor and the non-inverting input end of the second active filter operational amplifier.

9. The receiver according to claim 1, characterized in that The main control board is provided with a cascade digital filter sampling device, and the cascade digital filter sampling device comprises: A first FIR filtering downsampling device, wherein the input end of the first FIR filtering downsampling device inputs original data, and the output end outputs first downsampling data with a frequency twice that of the original data; a second FIR filtering down-sampling device, wherein an input end of the second FIR filtering down-sampling device inputs the first down-sampling data, and an output end of the second FIR filtering down-sampling device outputs second down-sampling data with a frequency twice the frequency of the first down-sampling data; a third FIR filtering down-sampling device, wherein the input end of the third FIR filtering down-sampling device inputs the second down-sampling data, and the output end outputs third down-sampling data having a frequency twice that of the second down-sampling data; a fourth FIR filtering down-sampling device, wherein the third down-sampling data is input into the input end of the fourth FIR filtering down-sampling device, and the fourth down-sampling data having a frequency twice that of the third down-sampling data is output from the output end; a data selector, wherein the input ends of the data selector are respectively input with the original data, the first down-sampled data, the second down-sampled data, the third down-sampled data and the fourth down-sampled data; The output end of the data selector outputs the final filtered data.

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