A communication control method and chip for inter-frame spacing

Abstract

The application discloses a communication control method and a chip for interframe interval, and the communication control method comprises the following steps: step 1, after the last bit of current frame data is sent by a sending device, starting timing and recording an initial time, meanwhile, driving a configuration signal line to be low according to the level condition in the last half bit period of the last bit, controlling the configuration signal line to keep low in a predicted time period, then releasing the configuration signal line to be high resistance, and detecting a receiving interrupt response; step 2, after the sending device detects the receiving interrupt response, keeping timing and detecting a sending request; step 3, after the sending device detects the sending request, the sending device starts to send the frame header of next frame data, and the time interval from the initial time to the current time is determined as the interframe interval.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication control method and chip for inter-frame spacing. Background Technology

[0002] Chinese invention patent application CN201810679019.1 discloses the newly released USB Type-C Power Delivery Protocol (hereinafter referred to as PD protocol), which is based on USB 3.1 and is a power delivery protocol based on the Type-C interface. USB PD can support a maximum power delivery of 100W (20V / 5A) and supports power supply role switching, meeting the power supply needs of most electronic devices. In the USB Type-C interface, USB PD communication uses Biphase Mark Coding (BMC) to transmit data on the CC channel. This method is simple and flexible, has been released as a PD communication standard, and is gradually being widely used. BMC encoding is a phase modulation encoding technique that mixes clock and data for transmission. A key feature of BMC encoding is that the level changes at the beginning of each bit cycle. Within a bit cycle, level changes represent logic; if the level changes in the middle of the bit cycle, it represents logic "1"; otherwise, it represents logic "0". Using BMC encoding allows the transmitting and receiving ends to correctly transmit and receive data using only a single data line, while maintaining good synchronization between the two ends. The PD protocol specifies that the BMC code transmission frequency is 300kHz, that is, each bit period is 3.33µs. Each communication data packet includes a 64-bit preamble as a synchronization header.

[0003] Chinese invention patent application CN201810679019.1 discloses a BMC code adaptive decoding system and method, which focuses on processing the synchronization header signal of BMC signals, including the number of transition edges. Specifically, it adaptively configures the parameters of the decoding threshold according to the BMC data preamble synchronization code, and then analyzes the level transition situation in the middle of a single bit signal according to the decoding threshold to perform corresponding decoding. The decoding performance is improved, but it only solves the problem of frequency deviation at the receiving end. It does not predict the time interval between two adjacent message packets transmitted by the physical layer (including the transmitter and receiver) used to transmit USB power transmission messages, and cannot obtain a stable inter-frame interval (i.e., the time interval between two adjacent message packets). If the inter-frame interval is unstable, it will cause problems such as timing disorder, difficulty in clock synchronization, and severe timeout (the delay time generated when transmitting two adjacent data packets exceeds 2 bit cycles) in the PD protocol communication process, thereby affecting the stability and reliability of communication. Summary of the Invention

[0004] This application discloses a communication control method and chip for inter-frame spacing, and the specific technical solution is as follows:

[0005] A communication control method for inter-frame intervals includes: Step 1, after the transmitting device transmits the last bit of the current frame data, starting a timer and recording the initial time, simultaneously driving a configuration signal line to a low level according to the level of the last half-bit period of the last bit, controlling the configuration signal line to remain at a low level for a predicted time period, then releasing the configuration signal line to a high-impedance state, detecting a receive interrupt response, and then executing Step 2; wherein, the receive interrupt response is an interrupt signal generated by the receiving device after receiving the last bit of the current frame data, triggered by a timer; Step 2, after the transmitting device detects the receive interrupt response, maintaining the timer and detecting a transmission request, and then executing Step 3; wherein... The sending request is a timed signal generated by the transmitting device after detecting the receiving interrupt response, used to send the next frame of data. Step 3: After detecting the sending request, the transmitting device begins sending the frame header of the next frame of data, and simultaneously determines the time interval from the initial time to the current time as the inter-frame interval. The receiving interrupt response and the sending request are used to constrain the time error of the inter-frame interval to be within a controllable time range under different level conditions in the last half-bit period of the last bit. The transmitting device is connected to the receiving device via a configuration signal line. Each frame of data is transmitted between the transmitting and receiving devices in the form of biphase marker encoding.

[0006] Based on steps 1 to 3, this application discloses a communication control method for inter-frame intervals. Starting from the end of the current frame data, it sequentially configures the required timing values ​​by setting the configuration signal line low, detecting the receive interrupt response, and generating the boundary timing corresponding to the transmit request. This allows the inter-frame interval to become a configurable fixed value during the transmission of two frames of data. Therefore, by fixing the time error corresponding to the inter-frame interval, the reliability and efficiency of communication between the transmitting and receiving devices are improved, the bit error rate is reduced, the communication protocol stack design is simplified, and the robustness of the system is enhanced.

[0007] A chip includes a processing unit, a storage unit, and a computer program stored in the storage unit and executable on the processing unit. When executed by the processing unit, the computer program implements the communication control method described above. The chip disclosed in this application is equivalent to generating the receive interrupt response and the transmit request sequentially at fixed trigger times using a pre-configured first target timing time and a second target timing time. Therefore, regardless of the length of the data frame received by the receiving device, and whether the last half-bit period of the last bit is high or low, the time from the completion of data frame reception to the sequential generation of the receive interrupt response and the transmit request is controllable. After the transmit request is generated, a pre-configured time error is formed by timing a third target timing time, and the next frame of data is transmitted only after timing the third target timing time. Therefore, the chip dynamically adjusts according to different situations, making the absolute time error range of the inter-frame interval controllable under various conditions. This achieves improved communication reliability and efficiency between the transmitting and receiving devices, reduced bit error rate, simplified communication protocol stack design, and enhanced system robustness by fixing the time error corresponding to the inter-frame interval. Attached Figure Description

[0008] Figure 1 This is a schematic diagram showing the connection between the transmitting device and the receiving device provided in this application.

[0009] Figure 2 This is a schematic diagram of the data encoding format transmitted in the CC line (configuration signal line) provided in this application.

[0010] Figure 3 This is a waveform diagram of the last half-bit period in the UI aligned to the last bit of the UI when the last bit of the current frame data is 1.

[0011] Figure 4 This is a waveform diagram of the second embodiment of the present application, showing the waveform generated after detecting that the last half bit period of the last bit in the UI aligned with the last bit is high when the last bit of the current frame data is 0.

[0012] Figure 5 This is a waveform diagram of the last half-bit period in the UI aligned to the last bit of the UI when the last bit of the current frame data is 1.

[0013] Figure 6 This is a waveform diagram of the fourth embodiment of the present application, showing the waveform generated when the last half bit period of the UI aligned to the last bit is low when the last bit of the current frame data is 0.

[0014] Figure 7 This is a flowchart illustrating a communication control method for inter-frame spacing provided in this application.

[0015] Figure label:

[0016] tHoldlowBMC: Preset low-level hold time;

[0017] Soft programmable range: Configurable interval range;

[0018] max tEndDriveBMC: The maximum measurement interval of the final edge, which is equal to the maximum value of the prediction time period;

[0019] T1: The time taken by the transmitting device from sending the last bit of the current frame data to detecting the reception interrupt response is recorded as the first target timing time;

[0020] High impedance: High impedance state;

[0021] T2: The time from when the configuration signal line is pulled high until the transmitting device detects the transmission request is recorded as the second target timing time;

[0022] tInterframeGap: The ideal interframe gap, which covers the time period from the final edge of the transmission to the configuration signal line being pulled down from a high-impedance state to a low level;

[0023] tx_message_req: Send a request;

[0024] T3: The time elapsed from when the transmitting device detects the transmission request to when it begins sending the frame header of the next frame of data, recorded as the third target timing time or the preset transition time;

[0025] Peamable for next frame: The transmission readiness status, used to indicate the time period corresponding to the transmission readiness status of the next frame of data;

[0026] UI: Bit period, used to represent the transmission time of one bit. Detailed Implementation

[0027] The present application will be described in further detail below with reference to embodiments and accompanying drawings, but the implementation of the present application is not limited thereto. It should be noted that a frame of data packaged during communication includes three parts: a frame header, a data portion, and a frame trailer. The frame header and trailer contain necessary control information. The frame header is the start of the frame and contains control information such as source address, destination address, and sequence number, used for identifying and synchronizing data. The frame trailer contains checksums or end markers for error detection and frame termination. The data portion contains data packets and is the main content of the frame, containing the actual transmitted data information. The length of this portion can be adjusted according to actual needs. In data communication, a "packet" is contained within a "frame".

[0028] like Figure 1 As shown, a pair of transmitting and receiving devices communicate via the configuration signal line CC. The transmitting device can attach a checksum to the data to be transmitted and transmit the payload, including the checksum, via biphase mark coding (BMC) on CC. The receiving device, by restoring the clock and locking onto a frame of data transmitted by the transmitting device, first detects the frame header, then decodes the received data, including the checksum; then it detects the frame tail and verifies the checksum.

[0029] The CC line (Configuration Channel) is a type of USB Type-C cable. The CC line transmits signals using BMC (Biphase Mark Coding) encoding; one phase change represents logic 0, and two phase changes represent logic 1. The CC line supports pull-up / pull-down resistors and power role monitoring. The interface circuitry within the transmitting device connects to the interface circuitry within the receiving device via the CC1 or CC2 pin of the Type-C line. The transmitting or receiving device simultaneously includes both a transmitter and a receiver, and its application scenario is power transfer communication with mobile terminal devices. Both the transmitting and receiving devices have separate transmitter and receiver ends; when the transmitting device is responsible for sending data, the receiving device is responsible for receiving data; conversely, when the transmitting device is responsible for receiving data, the receiving device is responsible for sending data. The data transmission and reception roles of the transmitting and receiving devices can be interchanged.

[0030] Since hardware timing itself requires a clock, if there are multiple clocks in the circuit, there will be a period error when the same signal crosses from one clock of the transmitting device to another clock (the internal clock of the receiving device). In addition, the time when the hardware starts to recognize the instructions sent by the software is also uncertain. As a result, the time interval between different frames of data (inter-frame interval) cannot be predicted stably. An unstable inter-frame interval will lead to problems such as timing disorder, difficulty in clock synchronization, timeout errors, and increased bit error rate in the USB PD communication process. Therefore, it is necessary to determine the interval between different frames of data through timing. By pre-configuring or dynamically configuring the boundary conditions of the frame tail related levels, an inter-frame interval with a fixed error can be timed during timing detection, which can be used for actual data transmission and communication in the CC line.

[0031] To address the aforementioned technical deficiencies, this application discloses a communication control method for inter-frame intervals. In this application, the entity executing the communication control method can be considered a transmitting device or a software system capable of controlling both the transmitting and receiving devices. The transmitting device is connected to the receiving device via configured signal lines, and the transmitting and receiving devices communicate data using biphase marker encoding. Its application scenarios include power delivery communication. Figure 7 As shown, the communication control method includes:

[0032] Step 1: After the transmitting device has sent the last bit of the current frame data, start timing and record the initial time so that timing begins from the completion of sending the last bit of the current frame data (i.e., the frame tail is sent). From the perspective of signal timing, the initial time can be the moment of the last edge of the last bit of the current frame data; schematically, the initial time is as follows: Figure 3 and Figure 4 As shown by the last falling edge of the last bit of the current frame data, or as... Figure 5 and Figure 6 The timing is shown by the last rising edge of the last bit of the current frame data; simultaneously, the configuration signal line is driven to a low level based on the level condition during the last half-bit period of the last bit, and the configuration signal line is controlled to remain low during the predicted time period. At this time, the moment when the configuration signal line is set to a low level and the time when the configuration signal line remains low can be determined. In order to prevent the length of the data part (payload) in the current frame data and the level condition during the last half-bit period of the last bit from affecting the low-level time of the configuration signal line, step 1 can fix the time when the configuration signal line remains low by timing. Of course, the fixed time is a pre-configured timing value. As long as the fixed time is completed directly after driving the configuration signal line to a low level, the timing can be completed. For example, in step 1, the timing is completed when the time when the configuration signal line remains low reaches the specified time. Figures 3 to 6After the maximum measurement interval maxtEndDriveBMC of the final edge, it enters a high-impedance state, waiting for the transmitting device to detect a receive interrupt response. The maximum measurement interval maxtEndDriveBMC of the final edge is equal to the maximum value of the predicted time period. The preset low-level hold time is as follows: Figures 3 to 6 The waveform diagram shows the square wave width occupied by tHoldlowBMC, which is a configurable time period. Preferably, when the configuration signal line is released to a high-impedance state, the level of the configuration signal line increases from 0V to 3V, but remains below the high level; and the configuration signal line is not driven to transmit data.

[0033] Then, the configuration signal line is released to a high-impedance state. At this time, the configuration signal line is not pulled up or down, and it is in a non-driven state. The receiving device has received a frame of data, so it needs to detect the receive interrupt response and then execute step 2. The receive interrupt response is an interrupt signal generated by a timer after the receiving device has received the last bit of the current frame of data.

[0034] Step 2: After the transmitting device detects a receive interruption response, it maintains a timer and detects a transmission request, then executes Step 3 to begin controlling the transmitting device to send the next frame of data. It is worth noting that the time period from when the transmitting device sends the last bit of the current frame of data to when the receive interruption response is detected is... Figures 3 to 6 The waveform diagram shows that T1 occupies the width of the square wave, which is different from... Figures 3 to 6 The square wave width occupied by tHoldlowBMC in the waveform diagram can be considered as independent time periods. The moment when the received interrupt response is detected is delayed to the rising edge of the high impedance state.

[0035] Since the receiving device triggers an interrupt signal in the software upon completion of data reception, after the transmitting device has transmitted the last bit of the current frame data in step 1, the receiving device triggers the software system to generate the reception interrupt response after receiving the last bit of the current frame data. Upon detecting the reception interrupt response, the transmitting device will start timing the new level state of the configuration signal line. There is an interrupt time interval between the receiving device receiving the last bit of the current frame data and triggering the software system to generate the reception interrupt response. Figures 3 to 6T1 in the waveform diagram; This application pre-configures the interrupt time interval or dynamically adjusts the interrupt time interval according to the real-time signal conditions, so that after the receiving device receives the last bit of the current frame data, it immediately generates the receiving interrupt response by timing the specific interrupt time interval and is detected by the transmitting device. This makes the time from receiving the last bit of the current frame data to triggering / detecting the receiving interrupt response controllable, and is not affected by the high or low level state of the last half bit period of the last bit and the length of the data received by the receiving device.

[0036] After the receive interruption response is detected, a transition time is continued (corresponding to...). Figures 3 to 6 As shown in T2), when timer T2 ends, the software system is triggered to generate a transmission request. Therefore, it can be understood that the transmission request is a request signal for sending the next frame of data generated by a timer trigger after the transmitting device detects the receive interrupt response. It should be noted that after step 2 is executed and before step 3 is executed, which is the period from when the configuration signal line is released to a high impedance state until the transmission request (i.e., the generated request signal for sending the next frame of data) is detected. During this period, as shown in T2, the transmission request is generated. Figures 3 to 6 As shown in the waveform diagram, T2 occupies the width of the square wave, covering the time from the rising edge of the square wave indicated by High impedance to the rising edge of the pulse corresponding to the transmission request tx_message_req. This application pre-configures or dynamically configures this period so that after the subsequent detection of the receive interrupt response, the transmission request is generated immediately after timing this period. This makes the time from detecting the receive interrupt response to generating the transmission request controllable, unaffected by the high / low level state of the last half-bit period of the last bit and the length of the data transmitted by the transmitting device.

[0037] Step 3: After the transmitting device detects a transmission request, it begins sending the header of the next frame of data. Simultaneously, the time interval from the initial moment to the current moment is defined as the inter-frame interval, and the transmitting device sends data according to this interval, which is dynamically adjustable. Specifically, after the transmitting device detects a transmission request, it begins driving the configuration signal line to send data in BMC code format. The time interval between the generation of the transmission request and the detection of the transmission request by the transmitting device includes a pre-configured fixed time error, which is less than or equal to one bit period. This can be understood as the transmitting device starting to send the header of the next frame of data simultaneously with the end of this time interval.

[0038] It is worth noting that the receive interrupt response and the send request are used to constrain the time error of the inter-frame interval to be within a controllable time range under different level conditions in the last half bit period of the last bit. Specifically, the time interval from the initial moment to the moment when the receive interrupt response is detected, and the time interval from the moment the receive interrupt response is detected to the moment when the send request is generated, can be configured as a fixed time period. The time interval from the moment the send request is generated to the moment when the sending device detects the send request (the moment when the sending device starts sending the frame header of the next frame of data) includes a pre-configured fixed time error. Therefore, the controllable time range can be regarded as a timing time period jointly determined by the receive interrupt response, the send request, and the preset transition time.

[0039] Schematic, the time interval from when the sending request is generated to when the sending device detects the sending request, such as Figures 3 to 6 The waveform diagram shows that T3 occupies a square wave width that covers the rising edge of the pulse corresponding to the transmission request tx_message_req to the rising edge of the period from the peamable for next frame. The timing sequentially spans the high impedance and the low-level phases of the configuration signal line (aligned with the edge of the peamable for next frame). For simplicity, the time interval from the generation of the transmission request to the detection of the transmission request by the transmitting device is denoted as the preset transition time. The preset transition time preferably has a time error within one bit period, such as... Figures 3 to 6 The waveform diagram shows the time interval from the last falling edge of the tInterframeGap phase to the last rising edge of the period peamable for next frame in the same attached figure. Figure 3 and Figure 4 Equivalent to the difference obtained by subtracting tInterframeGap from the sum of T1, T2 and T3, this difference is a pre-configured fixed timing value and is less than one bit period; based on this, starting from the generation of the transmission request, the error of the time interval between the transmission of two adjacent frames of data between the transmitting device and the receiving device can be configured as a specific time error value by timing T3, which is a time error that cannot be avoided due to the influence of the clock.

[0040] Schematic, assuming the time error of the inter-frame interval determined in step 3 is limited to one bit period, the inter-frame interval is equal to Figure 3 , Figure 4 , Figure 5 and Figure 6The sum of T1, T2, and T3 in any of the attached figures, but not equal to the ideal interframe gap tInterframeGap; wherein, the square wave waveform occupied by T1, T2, and T3 in the same attached figure covers the time interval required to transmit two adjacent frames of data. If the preset transition time is regarded as a timing period obtained by timing, its timing value can be pre-configured, so the time error allowed by the preset transition time is a controllable error. When the time interval T1 between the initial moment and the moment when the receiving interrupt response is detected, and the time interval T2 between the detection of the receiving interrupt response and the generation of the transmission request are both configured as fixed time periods, the preset transition time can be dynamically adjusted according to different data frame transmission conditions, so that the time error of the interframe gap determined in various cases does not exceed a single bit period, thereby constraining the time error of the interframe gap to be within a controllable time range under different level conditions in the last half bit period of the last bit, and the controllable time range can be one bit period.

[0041] comprehensive Figures 3 to 6 It is understood that by pre-configuring fixed T1 and T2, this application ensures that regardless of the length of the data frame received by the receiving device, or whether the last half-bit period of the last bit is high or low, the time from the completion of data frame reception to the generation of the receive interrupt response and the send request is controllable. After the send request is generated, a pre-configured time error is formed by timing T3, and the next frame of data is sent only after timing T3. Therefore, regardless of the length of a frame of data sent by the sending device or the type of the frame tail (the level condition in the last half-bit period of the last bit), the error from the time the send request is generated by the software to the time the sending device starts sending the next frame of data is controllable. This enables dynamic adjustment based on different situations, making the absolute time error range of the inter-frame interval controllable under various circumstances.

[0042] Based on steps 1 to 3, this application discloses a communication control method for inter-frame intervals. Starting from the end of the current frame data, the required timing values ​​are configured by setting the configuration signal line low, detecting the receive interrupt response, and generating the boundary timing corresponding to the transmission request. This allows the inter-frame interval to become a configurable fixed value when transmitting two frames of data sequentially. From the perspective of the transmitting device: regardless of the length of the transmitted data or the level condition of the last half-bit period of the last bit, the time for keeping the configuration signal line low at the end of the frame is controllable and can be controlled to a fixed value. From the perspective of the receiving device: regardless of the length of the received data or the level condition of the last half-bit period of the last bit, the time between the completion of receiving the current frame data and the detection of the receive interrupt response is controllable and can be controlled to a fixed value. From the perspective of the transmitting device: regardless of the length of a single frame of data or the type of data frame, the time error within the time interval from the generation of the transmission request to the start of transmitting the next frame of data is controllable. In summary, by fixing the time error corresponding to the inter-frame interval, the reliability and efficiency of communication between the transmitting device and the receiving device are improved, the bit error rate is reduced, the communication protocol stack design is simplified, and the robustness of the system is enhanced.

[0043] As one embodiment, in step 1, after driving the configuration signal line to a low level, the time for which the configuration signal line remains at a low level is timed. It is worth noting that after sending the last bit of the current frame data in step 1, if the last half-bit period of the last bit of the current frame data is output as a high level, the configuration signal line is driven to flip from high to low; if the last half-bit period of the last bit of the current frame data is output as a low level, the configuration signal line is first pulled high for one bit period and then flipped low. This achieves pulling the configuration signal line low after the last falling edge of the frame. Based on this, the time for which the configuration signal line remains low is timed starting from the falling edge when the configuration signal line is set to low. To make the time for the configuration signal line to remain low programmable, this embodiment uses a pre-configured fixed timing value, ensuring that the configuration signal line remains low for a fixed timing value at the end of the frame. The fixed timing value is configured as a preset low-level holding time.

[0044] After the timer reaches a preset low-level hold time for the configuration signal line, the timer continues. After the timer reaches a configurable interval for the configuration signal line to remain low, the configuration signal line is released to a high-impedance state to wait for the transmitting device to detect the receive interruption response. The predicted time period includes both the preset low-level hold time and the configurable interval, both of which are configurable time periods. The preset low-level hold time is as follows: Figures 3 to 6 The waveform diagram shows the width of the square wave occupied by tHoldlowBMC, where... Figure 3 and Figure 4 In both cases, the output is pulled low and maintained at the preset low level hold time tHoldlowBMC when the last half bit period of the last bit of the current frame data is high. Figure 5 and Figure 6 When the last half-bit period of the last bit of the current frame data is low, the signal is first pulled high and maintained for one bit period (UI), then pulled low and maintained at the preset low-level hold time (tHoldlowBMC). Then, the timing continues within the configurable interval, meaning the signal can remain low within this interval. The duration the configuration signal line is pulled low at the end of the frame is controllable and can be maintained for the same preset low-level hold time. Based on this, the configurable interval and / or the preset low-level hold time can be dynamically adjusted according to the length of the transmitted data frame and the level of the last bit. The maximum value of the sum of the preset low-level hold time (tHoldlowBMC) and the configurable interval (soft programmable range) can reach [value missing]. Figures 3 to 6 The maximum measurement interval segment max tEndDriveBMC of the final edge is shown in the diagram to ensure that T1 remains constant. Therefore, regardless of whether the last bit of the current frame data is low or high, the preset low-level holding time and the configurable interval segment are timed sequentially only after the configuration signal line is flipped to low. Since the preset low-level holding time and the configurable interval segment can be configured in advance or dynamically adjusted, the inter-frame interval is adjusted to be stable when the transmitting device transmits frame tails with different level states.

[0045] As one embodiment, the communication control method further includes: when the transmitting device detects the receive interruption response, determining the time interval between the initial time and the time when the receive interruption response is detected as a first target timing time; wherein, the sum of the preset low-level hold time and the configurable interval is less than or equal to the first target timing time, such as... Figures 3 to 6As shown, if the first target timing time T1 is timed, the timing time T1 ends after the rising edge of the high impedance state, that is, after timing the configurable interval soft programmable range for a period of time. Therefore, starting from the last edge of the last bit, the sum of the preset low level hold time tHoldlowBMC and the configurable interval soft programmable range is less than or equal to the first target timing time T1.

[0046] It should be noted that when the transmitting device sends the current frame data, the receiving device receives the current frame data through the configuration signal line; the time interval from when the receiving device receives the last bit of the current frame data to when it detects the receiving interrupt response is a configurable time interval, so that the first target timing time remains fixed under different level conditions in the last half bit period of the last bit. Specifically, the first target timing time will cover the preset low level holding time and the time interval from when the sending / receiving of the current frame data is completed to when the receiving interrupt response is detected. The preset low level holding time (corresponding to...) Figures 3 to 6 The time interval from the completion of sending / receiving the current frame data to the detection of the receive interruption response (corresponding to tHoldlowBMC). Figures 3 to 6 The soft programmable range in the first target timing can be dynamically adjusted to keep the timing of the first target timing constant at different levels during the last half-bit period of the last bit.

[0047] It can also be understood that when the transmitting device finishes sending the last bit of the current frame data (i.e., the frame tail signal edge is sent), the receiving device synchronously finishes receiving the last bit of the current frame data. The current time is the initial time, and the timing starts at this time. That is, the timing starts from the initial time and continues until the receiving interruption response is detected. Since the receiving interruption response is triggered at a pre-configured time, the first target timing time is a controllable timing time and can be adjusted to a fixed time.

[0048] Indicatively, the initial time is as follows Figure 3 and Figure 4As shown in the diagram, the last falling edge of the last bit of the current frame data corresponds to the output being high for the last half-bit period of the last bit of the current frame data. The last falling edge of the UI occupied by the last bit of the current frame data is recorded as the initial time. At the initial time, the current frame data is preferably received by the receiving device, and the last falling edge of the UI occupied by the last bit of the current frame data is the falling edge of the last bit shown in the diagram. Then, the timing passes through tHoldlowBMC and the soft programmable range, and then the configuration signal line is released into a high impedance state to wait for the detection of the receive interrupt response. The time interval from the initial time to the rising edge of entering the high impedance state is less than [a certain value]. Figure 3 and Figure 4 T1 in the software can adjust the configurable interval segment soft programmable range through software commands. The sum of tHoldlowBMC and soft programmable range can be adjusted to the maximum measurement interval segment max tEndDriveBMC of the final edge. The maximum measurement interval segment max tEndDriveBMC of the final edge can be further fixed. Here, the final edge can refer to the last falling edge of the UI occupied by the last bit of the current frame data.

[0049] Indicatively, the initial time is as follows Figure 5 and Figure 6 As shown in the diagram, the last rising edge of the last bit of the current frame data corresponds to the output being low for the last half bit period of the last bit of the current frame data. Therefore, the last rising edge of the UI occupied by the last bit of the current frame data is recorded as the initial time. At the initial time, the current frame data is preferably received by the receiving device, and the last rising edge of the UI occupied by the last bit of the current frame data is the rising edge of the last bit shown in the diagram. Then, the time is counted for the high-level bit period UI, the preset low-level hold time tHoldlowBMC, and the configurable interval soft programmable range. Then, the configuration signal line is released to enter the high-impedance state to wait for the detection of the reception interrupt response. The time interval from the initial time to the rising edge of entering the high impedance state is less than [a certain value]. Figure 5 and Figure 6In T1, with both the bit period UI and the preset low-level hold time tHoldlowBMC set to fixed values, the configurable interval soft programmable range is adjusted by software commands. The sum of the bit period UI, the preset low-level hold time tHoldlowBMC, and the configurable interval soft programmable range is adjusted to the maximum measurement interval max tEndDriveBMC of the final edge. The maximum measurement interval max tEndDriveBMC of the final edge can be further fixed. Here, the final edge can refer to the last rising edge of the UI occupied by the last bit of the current frame data.

[0050] In summary, this application designs the time interval between the transmitting device sending the last bit of the current frame data and the receiving device receiving the last bit of the current frame data and detecting the reception interruption response to be software programmable. This ensures that regardless of the data length of the receiving device or the level state of the last bit period, the time interval between the receiving device receiving the last bit of the current frame data and detecting the reception interruption response will not be affected. The size of this time interval can be pre-configured or configured in real time to adapt to the formation of a stable inter-frame interval under different level states of last bit data transmission / reception.

[0051] Based on the above embodiments, the communication control method further includes: in step 2, after the transmitting device detects a receive interrupt response, timing is performed for the configuration signal line to remain in a high impedance state; when the timing reaches the second target timing time, it is determined that the transmission request has been generated; before the transmission request tx_message_req arrives, in step 2, after the transmitting device detects the receive interrupt response, the configuration signal line is already in a high impedance state, the timing phase has moved from the first target timing time T1 to other timing phases, until the transmission request tx_message_req is generated, and the time interval between the end of the timing of the first target timing time T1 and the rising edge of the transmission request tx_message_req is determined as the second target timing time T2. The second target timing time is a configurable time period, allowing the second target timing time to remain fixed under different level conditions within the last half-bit period of the last bit.

[0052] Based on the above embodiments, after the transmission request is generated, the transmission device is guided to enter the transmission preparation state by controlling the configuration signal line from a high impedance state to a low level; after the transmission device crosses the transmission preparation state, the transmission device detects the transmission request to execute step 3; in step 3, the transmission device starts to transmit the frame header of the next frame data by driving the configuration signal line to start transmitting the next frame data, and the time interval between the generation of the transmission request and the start of transmission of the frame header of the next frame data is set as the third target timing time.

[0053] If the timing of the third target is to be calculated, the configuration signal line is pulled down during the timing period, which can be done by a pull-down resistor to 0V to 1V, and the transmitting device is guided into the transmission preparation state when the configuration signal line is pulled down; starting from the generation of the transmission request, the pre-configured timing of the third target is calculated, combined with... Figures 3 to 6 It can be seen that during the timing of the third target timing time T3, the pulse signal corresponding to the sending request tx_message_req, the configuration signal line being set to low level, and the sending preparation state peamable for next frame are timed sequentially until the level of the configuration signal line is detected to be driven to high level again, and the sending preparation state peamable for next frame is timed. This high level is higher than the level output by the configuration signal line in the high impedance state.

[0054] Based on this, after the third target timing period has elapsed, the transmitting device moves beyond the transmission preparation state and begins transmitting the frame header of the next frame of data. Simultaneously, the sum of the first target timing period, the second target timing period, and the third target timing period is determined as the inter-frame interval, which is schematically equivalent to... Figures 3 to 6 The sum of T1, T2, and T3 in any of the attached figures; the time error of the third target timing is configurable, and the time error that the inter-frame interval can reserve is a controllable time error that exists in the inter-frame interval within the third target timing time or within the transmission preparation state. This controllable time error is constrained within one bit period and is equal to a pre-configured fixed value, such as equal to the clock period (3.3us) of the BMC code generated on the CC line.

[0055] It should be noted that the third target timing time is the preset transition time mentioned in the foregoing embodiments, ensuring that the time error of the inter-frame interval is within a controllable time range under different level conditions within the last half-bit period of the last bit. Illustratively, in summary... Figures 3 to 6It is understood that this application can generate the receive interrupt response and the send request at fixed trigger times by pre-configuring or dynamically adjusting the first target timing time T1 and the second target timing time T2. Therefore, regardless of the length of the data frame received by the receiving device, and whether the last half bit period of the last bit is high or low, the time from the completion of data frame reception to the generation of the receive interrupt response and the send request is controllable. After detecting the send request, the third target timing time T3 will be continuously timed before the frame header of the next data frame is sent, forming a fixed time error.

[0056] Therefore, regardless of the length or type of data frames sent, the time error reserved within the third target timing time can be controlled. Thus, the time range required from the generation of the sending request to the start of sending the header of the next frame of data can be predicted and represented by the third target timing time. Therefore, after the third target timing time has elapsed, it can be confirmed when to start sending the next frame of data. Based on the pre-configured fixed first and second target timing times, the inter-frame interval is configured as a fixed time interval. Then, based on this fixed time interval, multiple frames of different lengths or types of data are transmitted sequentially, making the bit error rate controllable and improving the reliability of sending the next frame of data.

[0057] In existing technologies, the third target timing time generally serves as a transition phase within the inter-frame interval, including the sequential transmission of data between two adjacent frames and the transition from software issuing a transmission request to hardware detecting the transmission request. Time errors may exist in both of these phases. Due to these time errors, the third target timing time in existing technologies introduces an uncertain time range relative to the ideal inter-frame interval tInterframeGap illustrated in the diagram. However, step 3 disclosed in this application makes the time error controllable and even negligible, thus not affecting the stability of the inter-frame interval. Therefore, this application overcomes the impact of the uncertain time range on the stability and reliability of data communication caused by reserving a pre-configured time error within the third target timing time.

[0058] Specifically, in step 1, the method of driving the configuration signal line to a low level based on the level of the last half-bit period of the last bit includes: after detecting that the level of the configuration signal line is high during the last half-bit period of the last bit, pulling the level of the configuration signal line down to a low level, so as to drive the configuration signal line to a low level when the falling edge of the last bit arrives, and simultaneously determining that the transmitting device has finished transmitting the last bit of the current frame data, and recording the time of the last falling edge of the last bit as the initial time; in step 1, the transmitting device ensures that the receiving device locks the last bit through the last bit of the current frame data. The last half-bit period of the last bit is high, causing the transmitting device to drive the configuration signal line to pull down to a low level, which not only determines that the transmitting device has finished transmitting the last bit of the current frame data, but also allows the receiving device to receive the last bit of the current frame data, and also establishes the timing start point of the first target timing time (corresponding to the initial time).

[0059] The case where the configuration signal line is high during the last half-bit period of the last bit includes the configuration signal line being high only during the last half-bit period of the last bit, corresponding to... Figure 3 A waveform diagram; or, the case where the level of the configuration signal line is high during one bit period of the last bit includes the configuration signal line being high during the bit period of the last bit, corresponding to... Figure 4 A schematic diagram of the waveform. Indicatively, the initial time is as follows: Figure 3 and Figure 4 As shown in the last falling edge time of the last bit of the current frame data, correspondingly, the last half bit period of the last bit of the current frame data is output as high level. Then, the last falling edge time of the UI occupied by the last bit of the current frame data is recorded as the initial time. At the initial time, the current frame data is preferably received by the receiving device.

[0060] The last bit is the latest bit sent in the end of the current frame data. It should be noted that during data transmission between the sending and receiving devices, the sending device packages data into frames for transmission, and the receiving device, upon receiving the data, parses and processes the frame based on the information in the frame header. After sending the last bit of the current frame data in step 1, if the last half-bit period of the last bit of the current frame data is high, the configuration signal line is driven to flip from high to low to confirm the completion of sending a frame of data. In this way, different types of data can be transmitted efficiently and accurately between different devices. The size of a frame of data can be adjusted according to specific protocols and application requirements, but its structured and standardized design ensures correct data transmission and processing.

[0061] As an example, such as Figure 3 As shown, within the bit period occupied by the last bit of the current frame data, the configuration signal line (CC line) is high only during the last half-bit period of the last bit of the current frame data, indicating that the data in the last bit of the current frame data is logic 1; then... Figure 3 At the falling edge of the last bit shown, the configuration signal line is driven low. Then, the configuration signal line is controlled to maintain a low level for a preset low-level hold time tHoldlowBMC to stabilize the inter-frame interval. A configurable interval segment, soft programmable range, is reserved, and tHoldlowBMC and soft programmable range are set as adjustable time periods. The sum of these two values ​​equals the maximum measurement interval max tEndDriveBMC of the final edge. Then, the configuration signal line is released to a high-impedance state, meaning it is pulled up to 3V (but below high level) after passing max tEndDriveBMC from the falling edge of the last bit, to wait for the receive interrupt response for a sufficiently long time. Then, upon detecting the receive interrupt response, the second target timing time T2 is started until a transmit request tx_message_req is generated. Then, the third target timing time T3 is started to cause the configuration signal line to transition from the high-impedance state to the transmit ready state, peamagable for next. Within the third target timing time T3, after the transmission request tx_message_req is generated, the configuration signal line is controlled to be set to a low level (pulled high to 0V to 1V by a pull-down resistor) to enter the transmission preparation state peamable for next frame; after the timing T3 is completed, the configuration signal line is driven to start transmitting the frame header of the next frame data.

[0062] When the last half-bit period of the last bit (frame tail) of the current frame data is high, regardless of the length of the data frame received by the receiving device, the time from the completion of data frame reception to the generation of the receive interrupt response and the transmission request is controllable; after the transmission request is generated, the third target timing time T3 will be continuously timed until the frame header of the next frame data is sent, forming a fixed inter-frame interval. Combined with... Figure 3It is understood that this application can fix the first target timing time T1 and the second target timing time T2, and then time from the generation of the transmission request to the start of the transmission of the next frame data to calculate the third target timing time T3, which becomes the transition stage in the inter-frame interval, including the sequential transmission of two adjacent frames of data and the transition from the software issuing the transmission request to the hardware detecting the transmission request, at least relative to Figure 3 Even under ideal conditions, the interframe gap tInterframeGap may still introduce time errors. However, step 3 of this application discloses that the time error is controllable and limited to one bit period UI, thus not affecting the stability of the interframe gap. Therefore, when the last half bit period of the frame tail is high, regardless of the length of a frame of data sent by the transmitting device, the error from the time the software-generated sending request to the time the transmitting device starts sending the next frame of data is controllable. Thus, the time error can be dynamically adjusted according to different situations, reducing the time error caused by the transmission of different frame data, and overcoming the impact of the uncertain time range on the stability and reliability of data communication in the prior art.

[0063] It should be noted that in the USB PD (Power Delivery) protocol, the "UI" mentioned in the aforementioned embodiments refers to "Unit Interval". This term originates from the field of communications, particularly digital communications and serial interfaces, and is a unit used to represent time intervals, representing the transmission time of one bit. It can be configured as the clock cycle of the CC line according to the communication protocol, preferably 3.3µs, and can be used as the system's allowable time error.

[0064] As an example two, such as Figure 4 As shown, the configuration signal line (CC line) is high during the bit period occupied by the last bit of the current frame data, indicating that the data in the last bit of the current frame data is logic 0; then... Figure 4At the falling edge of the last bit shown, the configuration signal line is driven low, and then the configuration signal line is controlled to maintain a low level for a preset low-level hold time tHoldlowBMC to maintain the stability of the inter-frame interval. A configurable interval segment, softprogrammable range, is reserved, and tHoldlowBMC and softprogrammable range are set as adjustable time periods, the sum of which equals the maximum measurement interval max tEndDriveBMC of the final edge. Then, the configuration signal line is released to a high impedance state (pulled up to 3V by a pull-up resistor, but below the high level) after passing through max tEndDriveBMC from the falling edge of the last bit, allowing the transmitting device to detect the receive interrupt response for a sufficiently long and controllable period. After detecting the receive interrupt response, the second target timing time T2 continues until a transmit request tx_message_req is generated, at which point the third target timing time T3 begins to be counted, causing the configuration signal line to transition from the high impedance state to the transmit ready state pemable for next. Within the third target timing time T3, after the transmission request tx_message_req is generated, the configuration signal line is controlled to be set to a low level (pulled high to 0V to 1V by a pull-down resistor) to enter the transmission preparation state peamable for next frame. After the timing T3 is completed, the configuration signal line is driven to start transmitting the frame header of the next frame data.

[0065] When the last bit (frame tail) of the current frame data is high for the entire bit period, regardless of the length of the data frame received by the receiving device, the time from the completion of data frame reception to the generation of the receive interrupt response and the transmission request is controllable. After the transmission request is generated, the third target timing time T3 will be continuously timed until the frame header of the next frame data is sent, forming a pre-configured time error, combined with... Figure 4 It is understood that this application can fix the first target timing time T1 and the second target timing time T2, and then time from the generation of the transmission request to the start of the transmission of the next frame data to calculate the third target timing time T3, which becomes the transition stage in the inter-frame interval, including the sequential transmission of two adjacent frames of data and the transition from the software issuing the transmission request to the hardware detecting the transmission request, at least relative to Figure 4Even under ideal conditions, the interframe gap tInterframeGap may still introduce time errors. However, step 3 of this application discloses that the time error is controllable and limited to one bit period UI, thus not affecting the stability of the interframe gap. Therefore, when the frame tail is high for the entire bit period, regardless of the length of a frame of data sent by the transmitting device, the error from the time the software-generated sending request to the time the transmitting device starts sending the next frame of data is controllable. Thus, the time error can be dynamically adjusted according to different situations, reducing the time error caused by the transmission of different frames, and overcoming the impact of the uncertain time range on the stability and reliability of data communication in the prior art.

[0066] It is worth noting that since the high-impedance state is equivalent to an isolation state, it refers to an output state of the circuit that is neither a high level nor a low level. The configuration signal line in the high-impedance state has a level lower than the high level but higher than the low level, thereby stopping the transmission of data on the configuration signal line.

[0067] Specifically, within the first target timing time T1, when the current frame data transmission ends, regardless of whether the last bit of the current frame data is logic 0 or logic 1, as long as the configuration signal line is high for the second half bit period of the last bit of the current frame data, the configuration signal line will be continuously pulled low for a preset low-level holding time tHoldLowBMC and a configurable soft programmable range, and then the configuration signal line will be released to a high-impedance state. That is, a configurable low-level time is added at the end of a data frame before data transmission stops. The configurable soft programmable range is the time interval from when the configuration signal line is held low for the preset low-level holding time tHoldLowBMC until it is released to a high-impedance state. Since the time interval from when the configuration signal line is held low for the preset low-level holding time tHoldLowBMC until it is released to a high-impedance state is configurable, and the receive interrupt response is pre-configured to be generated at the corresponding trigger time, the soft programmable range... The time interval `range` is configurable, therefore the elapsed time from when the configuration signal line is held low for a preset low-level holding time `tHoldLowBMC` until the transmitting device detects the receive interrupt response is configurable. Ultimately, by dynamically adjusting `tHoldLowBMC` and `soft programmable range`, the first target timing time `T1` is adjusted to a fixed value to ensure that, when the configuration signal line is high for the last half-bit period of the last bit of the last bit, the second half-bit period of the last bit of the current frame data is also high to accommodate different data length transmission scenarios.

[0068] On the other hand, in step 1, the method of driving the configuration signal line to a low level based on the level condition of the last half-bit period of the last bit includes: after detecting that the level of the configuration signal line is low during the last half-bit period of the last bit, first pulling the level of the configuration signal line up to a high level, simultaneously determining that the transmitting device has finished transmitting the last bit of the current frame data, and recording the moment of the last rising edge of the last bit as the initial moment, then driving the configuration signal line to remain high for one bit period, and then pulling the level of the configuration signal line down to a low level, thereby delaying the driving of the configuration signal line to a low level by one bit period relative to the last bit of the current frame data; and also delaying the action of driving the configuration signal line to a low level when the level of the configuration signal line is high during the last half-bit period of the last bit by one bit period, forming a time difference of one bit period. Therefore, in conjunction with the design of the aforementioned embodiment, the first target timing time can be fixed according to the different level conditions during the last half-bit period to compensate for the time difference of this bit period; otherwise, combined with the time error during the transmission preparation state, two UI errors would accumulate.

[0069] In this embodiment, after detecting that the level of the configuration signal line is low during the last half-bit period of the last bit, the purpose of first pulling the level of the configuration signal line high and maintaining it for one bit period is: 1. To design a fixed delay time so that it forms a fixed time difference with the last bit when the level is high during the last half-bit period, thereby reducing the time error caused by the low level state; 2. To allow the frame end to end with a high level, and then start the timing of the preset low level hold time tHoldLowBMC by uniformly pulling the level of the configuration signal line low.

[0070] In step 1, the transmitting device ensures that the receiving device locks the last bit of the current frame data by using the last bit. The last half-bit period of the last bit is low, causing the transmitting device to drive the configuration signal line to pull up. This not only determines that the transmitting device has finished transmitting the last bit of the current frame data, but also ensures that the receiving device receives the last bit of the current frame data, and establishes the starting point of the first target timing time (corresponding to the initial time). Illustratively, the initial time is as follows: Figure 5 and Figure 6 As shown in the last rising edge time of the last bit of the current frame data, correspondingly, the last half bit period of the last bit of the current frame data is output as low level. Then, the last rising edge time of the UI occupied by the last bit of the current frame data is recorded as the initial time. At the initial time, the current frame data is preferably received by the receiving device.

[0071] The case where the configuration signal line is low during the last half-bit period of the last bit includes the configuration signal line being low only during the last half-bit period of the last bit, corresponding to... Figure 5 The waveform diagram shows that the value of the last bit is logic 1; or, the case where the level of the configuration signal line is low during one bit period of the last bit includes the configuration signal line being low during the bit period of the last bit, corresponding to... Figure 6 The waveform diagram shows that the last bit in the last position is logic 0.

[0072] The last bit is the latest bit sent in the end of the current frame data. It should be noted that during data transmission between the sending and receiving devices, the sending device packages data into frames for transmission, and the receiving device, upon receiving the data, parses and processes the frames based on the information in the frame header. After sending the last bit of the current frame data in step 1, if the last half-bit period of the last bit of the current frame data is low, the configuration signal line is pulled high and held for one bit period before flipping low. This confirms that the sending device can perform the actions after sending a frame of data, and also helps the sending and receiving devices distinguish between frame ends of different levels.

[0073] As an example three, such as Figure 5 As shown, within the bit period occupied by the last bit of the current frame data, the configuration signal line is low only during the last half-bit period of the last bit of the current frame data, indicating that the last bit of the current frame data is logic 1; then... Figure 5At the rising edge of the last bit shown, the configuration signal line is driven low. Then, the configuration signal line is controlled to maintain a low level for a preset low-level hold time tHoldlowBMC. A configurable interval, soft programmable range, is reserved, and tHoldlowBMC and soft programmable range are set to adjustable time periods. The sum of these two is equal to the maximum measurement interval maxtEndDriveBMC of the final edge. Then, the configuration signal line is released, allowing it to pass through maxtEndDriveBMC from the falling edge of the last bit and then become a high impedance state. This allows the transmitting device to detect the receive interrupt response within a sufficiently long and controllable time period. At this point, the first target timing time T1 has elapsed. The second target timing time T2 continues to be timed until a transmit request tx_message_req is generated. Then, the third target timing time T3 begins to be timed so that the configuration signal line transitions from the high impedance state to the transmit ready state. nextframe; within the third target timing time T3, after the transmission request tx_message_req arrives, the configuration signal line is controlled to be set to low level (pulled high to 0V to 1V by the pull-down resistor) to enter the transmission preparation state peamable for next frame. After the timing T3 is completed, the configuration signal line is driven to start transmitting the frame header of the next frame data.

[0074] In implementation three, when the last half-bit period of the last bit (frame tail) of the current frame data is low, regardless of the length of the data frame received by the receiving device, the time from the completion of data frame reception to the generation of the reception interrupt response and the transmission request is controllable; after the transmission request is generated, the third target timing time T3 will be continuously timed until the frame header of the next frame data is sent, forming a fixed inter-frame interval. Combined with... Figure 5It is understood that this application can fix the first target timing time T1 and the second target timing time T2, and then time from the generation of the sending request to the start of sending the next frame data to calculate the third target timing time T3, which becomes the transition stage in the inter-frame interval, including the sequential transmission of two adjacent frames of data and the transition from the software issuing the sending request to the hardware detecting the sending request; however, step 3 disclosed in this application is controllable in terms of the time error, which is limited to one bit period UI and will not affect the stability of the inter-frame interval; therefore, when the last half bit period of the frame tail is low, compared to the case where the last half bit period of the frame tail is high, regardless of the length of a frame of data sent by the same sending device, the error from the sending request generated by the software to the sending device starting to send the next frame of data is controllable, realizing dynamic adjustment of the time error according to different situations, reducing the time error caused by the transmission of different frame data, and overcoming the impact of the uncertain time range of the prior art on the stability and reliability of data communication.

[0075] As an example four, such as Figure 6 As shown, within the bit period occupied by the last bit of the current frame data, the configuration signal line is low only for one bit period of the last bit of the current frame data, indicating that the last bit of the current frame data is logic 0; then... Figure 6At the rising edge of the last bit shown, the configuration signal line is driven low. Then, the configuration signal line is controlled to maintain a low level for a preset low-level hold time tHoldlowBMC. A configurable interval segment, soft programmable range, is reserved, and tHoldlowBMC and soft programmable range are set as adjustable time periods. The sum of these two is equal to the maximum measurement interval max tEndDriveBMC of the final edge. Then, the configuration signal line is released to a high-impedance state, allowing it to pass through maxtEndDriveBMC from the falling edge of the last bit and then release to a high-impedance state (High impedance). This ensures that the transmitting device detects the receive interrupt response for a sufficiently long and controllable period, while maintaining the first target timing time at a fixed value. Then, the timing of the second target timing time T2 continues until a transmit request tx_message_req is generated. Finally, the timing of the third target timing time T3 begins, causing the configuration signal line to transition from the high-impedance state (High impedance) to the transmit ready state (peamable for next). Within the third target timing time T3, after the transmission request tx_message_req is generated, the configuration signal line is controlled to be set to a low level, entering the transmission preparation state peamable for next frame. After the timing T3 is completed, the configuration signal line is driven to start transmitting the frame header of the next frame of data.

[0076] In implementation four, when the last bit (frame tail) of the current frame data is low for the entire bit period, regardless of the length of the data frame received by the receiving device, the time from the completion of data frame reception to the generation of the reception interrupt response and the transmission request is controllable; after the transmission request is generated, the third target timing time T3 will be continuously timed until the frame header of the next frame data is sent, combined with... Figure 6It is understood that this application can fix the first target timing time T1 and the second target timing time T2, and then time from the generation of the sending request to the start of sending the next frame data to calculate the third target timing time T3, which becomes the transition stage in the inter-frame interval. This includes the sequential transmission of two adjacent frames of data and the transition from the software issuing the sending request to the hardware detecting the sending request. At least compared to the ideal inter-frame interval tInterframeGap, there may be time errors. However, step 3 disclosed in this application makes the time error controllable and limited to one bit period UI, which will not affect the stability of the inter-frame interval. Therefore, when the end of the frame is at a low level for the entire bit period, compared to the end of the frame being at a high level for the entire bit period, regardless of the length of a frame of data sent by the sending device, the error from the sending request generated by the software to the start of sending the next frame of data by the sending device is controllable. Thus, the time error can be dynamically adjusted according to different situations to reduce the time error caused by the transmission of different frames of data, and overcome the impact of the uncertain time range of the prior art on the stability and reliability of data communication.

[0077] Combination Figures 5 to 6 It can be seen that before the tx_message_req request arrives, in step 2, when the transmitting device detects the receive interrupt response, the configuration signal line is released into a high impedance state. At this time, the time interval between the falling edge of the last bit in the diagram and the rising edge of the high impedance state (the moment when the level of the configuration signal line is pulled up) is determined to be less than or equal to the first target timing time T1. Specifically, within the first target timing time T1, when the current frame data ends, regardless of whether the last bit of the current frame data is logic 0 or logic 1, as long as the configuration signal line is low for the second half bit period of the last bit of the current frame data, it is first pulled high and held for one bit period, then the configuration signal line is continuously pulled low for a preset low-level holding time tHoldLowBMC and a configurable soft programmable range, and then the configuration signal line is released into a high impedance state. That is, a controllable low-level time is added at the end of a frame data before the data transmission is stopped, reducing the influence of the level state of the last bit of the current frame data on the first target timing time T1.

[0078] The configurable soft programmable range is the time interval from the time the configuration signal line is held low for a preset low-level holding time tHoldLowBMC until it is released to a high-impedance state. Since this time interval is configurable, and the receive interrupt response is pre-configured to be generated at the corresponding trigger time, the soft programmable range is also configurable. Therefore, the elapsed time from the time the configuration signal line is held low for a preset low-level holding time tHoldLowBMC until the transmitting device detects the receive interrupt response is configurable. Finally, by dynamically adjusting tHoldLowBMC and the soft programmable range, the first target timing time T1 is adjusted to a fixed value. This ensures that, when the configuration signal line is high for the last half-bit period of the last bit of the current frame data, the latter half-bit period of the last bit is also high, accommodating different data length transmission scenarios.

[0079] Based on the above embodiments, in order to constrain the time error of the inter-frame interval to be within a controllable time range under different level conditions in the last half-bit period of the last bit, when the preset low-level hold time is configured to a fixed value, the configurable interval required for timing when the level in the last half-bit period of the last bit is high is smaller than the configurable interval required for timing when the level in the last half-bit period of the last bit is low. This ensures that the first target timing time is configured to a fixed value whether the level in the last half-bit period of the last bit is high or low. Finally, by dynamically adjusting tHoldLowBMC and soft programmable range, the first target timing time T1 is adjusted to a fixed value, so that whether the level of the configuration signal line in the last half-bit period of the last bit is high or low, it is compatible with the last half-bit period of the current frame data being high to handle different data length transmission situations.

[0080] As one embodiment, a method for transmitting each frame of data between a transmitting device and a receiving device in the form of biphase mark encoding includes:

[0081] Firstly, for each frame of data to be transmitted, including the aforementioned current frame data and the next frame data, the specific form of biphase marker encoding exists:

[0082] If the level of the configuration signal line at the beginning of the current bit period jumps once relative to its level in the last half bit period of the previous bit period, then the current bit period is timed and the level of the configuration signal line is detected during the timed period.

[0083] If the level of the configuration signal line changes only once in the middle of the current bit period, then the data transmitted in the current bit period is identified as logic 1, corresponding to... Figure 2 The high level indicated at Data in.

[0084] Corresponding to Figure 2 In this context, the current bit period is the second bit period UI, and the level of the configuration signal line is represented by BMC. If the level of the configuration signal line changes only once in the middle of the current bit period within the second bit period UI, the level of the configuration signal line will first remain high in the first half of the bit period and then remain low in the second half of the bit period.

[0085] Corresponding to Figure 2 In this context, the current bit period is the 4th bit period UI, and the level of the configuration signal line is represented by BMC. If the level of the configuration signal line changes only once in the middle of the current bit period within the 4th bit period UI, the level of the configuration signal line will first remain low in the first half of the bit period and then remain high in the second half of the bit period.

[0086] If the level of the configuration signal line does not change during the current bit period, the data transmitted during the current bit period is identified as logic 0, corresponding to... Figure 2 The low level indicated at Data in.

[0087] Corresponding to Figure 2 In this context, the current bit period is the first bit period UI, and the level of the configuration signal line is represented by BMC. If the level of the configuration signal line does not change within the first bit period UI, the level of the configuration signal line remains low.

[0088] Corresponding to Figure 2 In this context, the current bit period is the 3rd bit period UI, and the level of the configuration signal line is represented by BMC; if the level of the configuration signal line does not change within the 3rd bit period UI, the level of the configuration signal line remains high.

[0089] Because the biphase marker encoding inverts the level at the beginning of each bit cycle, logic can be represented by level changes within a bit cycle. If the level inverts in the middle of the bit cycle, it represents logic 1; otherwise, it represents logic 0. Therefore, by checking whether there is a level inversion within one bit cycle at the end of each bit, logic 0 and 1 can be distinguished.

[0090] It should be noted that the Biphasic Marking (BMC) encoding is a physical layer signaling scheme for transmitting USB power transfer messages. This encoding assumes a dedicated DC connection, identified as the CC line, for transmitting PD messages. Biphasic Marking is a version of Manchester encoding (see [IEC 60958-1]). In BMC, there is a transition at the beginning of each bit time (UI), and a second transition in the middle of the UI when a 1 is transmitted. BMC is effectively DC balanced (each 1 is DC balanced, two consecutive 0s are DC balanced, regardless of the number of 1s in between). It has finite parallax (limited to 1 bit, so a very low DC level).

[0091] According to the definition in Chapter 4, Section 2 of the IEC 60958-1:2021 standard, each bit to be transmitted is represented by a symbol containing two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. If the bit to be transmitted is logic 0, the second state of the symbol is the same as the first state; however, if the bit is logic 1, it will be different. In short, within a CLOCK cycle, a level transition indicates a 1, and no level transition indicates a 0. Encoding 0 results in only one transition at the very beginning of the UI (the transition can be from low to high, or from high to low), remaining unchanged during the UI period. Encoding 1 results in a transition not only at the beginning of the UI but also in the middle of the UI.

[0092] This application also discloses a chip, which includes a processing unit, a storage unit, and a computer program stored on the storage unit and executable on the processing unit. When the computer program is executed by the processing unit, it implements the communication control method as described above.

[0093] PD (Power Delivery) is a fast charging technology that can bring a battery to or near full charge within 1-5 hours. It is commonly used for traction batteries that need to be fully charged in a short time. A PD chip is a chip with fast charging functionality, typically used as a chip module in a power adapter. The chip disclosed in this application can be used as a PD chip. A communication protocol is established between the mobile terminal and the power adapter. The power adapter adjusts its output voltage and current in real time according to the mobile terminal's requests, and adjusts and controls various components of the system. Therefore, the stability and reliability of the communication between the mobile terminal and the power adapter directly affect the stability and safety of the charging process; hence, the PD chip is needed to execute the aforementioned communication control method.

[0094] Establishing a communication protocol between the mobile terminal and the power adapter may involve verifying the interface between two PD chips. The CC (Channel Configuration) line is used to configure the power supply to the two connected devices. USB PD uses BMC (Biphase Mark Code) for transmission. The aforementioned transmitting device is the power supply device (e.g., the power adapter), and the receiving device is the powered device.

[0095] By executing steps 1 to 3 of the aforementioned communication control method, starting from the end of the current frame data, the chip sequentially sets the configuration signal line to a low level, detects the receive interrupt response, and generates the corresponding boundary timing for the send request, thus configuring the required timing values ​​in a fixed / dynamic manner. In this way, when transmitting two frames of data in succession, the inter-frame interval becomes a configurable fixed value.

[0096] The chip disclosed in this application is equivalent to generating the receive interrupt response and the send request at fixed trigger times by pre-configured first and second target timing times. Therefore, regardless of the length of the data frame received by the receiving device, and whether the last half bit period of the last bit is high or low, the time from the completion of data frame reception to the generation of the receive interrupt response and the send request is controllable. After the send request is generated, a pre-configured time error is formed by timing a third target timing time, and the next frame of data is sent only after timing the third target timing time. Therefore, from the perspective of the transmitting device: regardless of the length of the transmitted data and the level condition within the last half-bit period of the last bit, the time for which the configuration signal line is kept low at the end of the frame is controllable and can be controlled to a fixed value; from the perspective of the receiving device: regardless of the length of the received data and the level condition within the last half-bit period of the last bit, the time between the completion of receiving the current frame data and the detection of the receiving interrupt response is controllable and can be controlled to a fixed value; from the perspective of the transmitting device: regardless of the length of the transmitted single frame data or the type of data frame, the time error existing from the generation of the transmission request to the start of transmitting the next frame data is controllable and can be controlled to a fixed value. In summary, the chip dynamically adjusts according to different situations to make the absolute time error range of the inter-frame interval controllable under various conditions. By fixing the time error corresponding to the inter-frame interval, the reliability and efficiency of communication between the transmitting and receiving devices are improved, the bit error rate is reduced, the communication protocol stack design is simplified, and the robustness of the system is enhanced.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A communication control method of an interframe space, characterized by, The method comprises the following steps: Step 1: after the sending device sends the last bit of the current frame data, starting timing and recording the initial time, and driving the configuration signal line to be low according to the level of the last half bit period of the last bit, and controlling the configuration signal line to remain low within a predicted time period, and then releasing the configuration signal line to be high impedance, and detecting a receiving interrupt response, and then executing Step 2; wherein the receiving interrupt response is an interrupt signal triggered by timing after the receiving device receives the last bit of the current frame data; Step 2: after the sending device detects the receiving interrupt response, keeping timing and detecting a sending request, and then executing Step 3; wherein the sending request is a request signal for sending the next frame data triggered by timing after the sending device detects the receiving interrupt response; Step 3: after the sending device detects the sending request, the sending device starts sending the header of the next frame data, and determines the time interval from the initial time to the current time as the inter-frame interval; Wherein, the receiving interrupt response and the sending request are used to constrain the time error of the inter-frame interval within a controllable time range under different levels of the last half bit period of the last bit; Wherein, the sending device is connected with the receiving device through the configuration signal line; and the sending device and the receiving device transmit each frame of data in the form of double-phase mark encoding.

2. The communication control method according to claim 1, characterized by, In Step 1, after driving the configuration signal line to be low, timing the time of keeping the configuration signal line low; After timing the time of keeping the configuration signal line low to reach the preset low level keeping time, keeping timing, and after timing the time of keeping the configuration signal line low to reach the configurable interval segment, releasing the configuration signal line to be high impedance to wait for detecting the receiving interrupt response; Wherein, the predicted time period comprises a preset low level keeping time and a configurable interval segment, and the preset low level keeping time and the configurable interval segment are both configurable time periods.

3. The communication control method according to claim 2, characterized by, The communication control method further comprises: When the sending device detects the receiving interrupt response, determining the time interval from the initial time to the time of detecting the receiving interrupt response as a first target timing time; Wherein, the sum of the preset low level keeping time and the configurable interval segment is less than or equal to the first target timing time; when the sending device sends the current frame data, the receiving device receives the current frame data through the configuration signal line; and the time interval from the time when the receiving device receives the last bit of the current frame data to the time of detecting the receiving interrupt response is a configurable time period, so that the first target timing time remains fixed under different levels of the last half bit period of the last bit.

4. The communication control method of claim 3, wherein In the step 2, after the sending device detects the receiving interrupt response, the time for which the configuration signal line remains in the high impedance state is timed; when the time for which the configuration signal line remains in the high impedance state reaches a second target timing time, it is determined that the sending request has been generated; wherein the second target timing time is a configurable time period, and the second target timing time remains fixed under different levels of the last half bit period of the last bit.

5. The communication control method of claim 4, wherein After the sending request is generated, the configuration signal line is controlled to be set from the high impedance state to the low level, so as to guide the sending device to enter the sending preparation state; after the sending device crosses the sending preparation state, the sending device detects the sending request to perform step 3; In step 3, the start of the sending device to send the header of the next frame data is realized by driving the configuration signal line to start sending the next frame data, and the time interval between the generation of the sending request and the start of the sending device to send the header of the next frame data is set as a third target timing time, so that the sum of the first target timing time, the second target timing time and the third target timing time is determined as the interframe interval, wherein the time error of the third target timing time is configurable, and the time error of the interframe interval is within a controllable time range under different levels of the last half bit period of the last bit.

6. The communication control method of claim 3, wherein The method for driving the configuration signal line to be set to the low level according to the level of the last half bit period of the last bit comprises: After detecting that the level of the configuration signal line in the last half bit period of the last bit is the high level, the level of the configuration signal line is pulled down to the low level, so as to drive the configuration signal line to be set to the low level when the falling edge of the last bit comes, and determine that the sending device has sent the last bit of the current frame data, and record the time of the last falling edge of the last bit as the initial time; Wherein, the last bit is the latest one bit position in the frame tail of the current frame data.

7. The communication control method of claim 6, wherein The method for driving the configuration signal line to be set to the low level according to the level of the last half bit period of the last bit comprises: After detecting that the level of the configuration signal line in the last half bit period of the last bit is the low level, the level of the configuration signal line is first pulled up to the high level, and it is determined that the sending device has sent the last bit of the current frame data, and the time of the last rising edge of the last bit is recorded as the initial time, then the configuration signal line is driven to remain in the high level for one bit period, and then the level of the configuration signal line is pulled down to the low level; Wherein, the last bit is the latest one bit position in the frame tail of the current frame data.

8. The communication control method of claim 7, wherein In the case that the preset low level holding time is configured as a fixed value, the configurable interval section required to be timed out in the case that the level in the last half bit period of the last bit is high is less than the configurable interval section required to be timed out in the case that the level in the last half bit period of the last bit is low, so that the first target timing time is configured as a fixed value in the case that the level in the last half bit period of the last bit is high or low.

9. The communication control method of claim 1, wherein The method for transmitting each frame of data in the form of bi-phase mark encoding between a transmitting device and a receiving device comprises: If the level of the configuration signal line at the beginning of the current bit period jumps once relative to the level of the configuration signal line in the last half bit period of the previous bit period, the current bit period is timed and the level of the configuration signal line is detected during the timing; If it is detected that the level of the configuration signal line jumps once in the middle of the current bit period in the current bit period, the data transmitted in the current bit period is identified as logic 1; the case that the level of the configuration signal line jumps once in the middle of the current bit period in the current bit period is that the level of the configuration signal line is high in the first half bit period and low in the second half bit period; or the case that the level of the configuration signal line jumps once in the middle of the current bit period in the current bit period is that the level of the configuration signal line is low in the first half bit period and high in the second half bit period; If it is detected that the level of the configuration signal line does not jump in the current bit period, the data transmitted in the current bit period is identified as logic 0; the case that the level of the configuration signal line does not jump in the current bit period in the current bit period is that the level of the configuration signal line is high or low.

10. A chip, characterized by The chip comprises a processing unit, a storage unit, and a computer program stored on the storage unit and executable on the processing unit, and the computer program is executed by the processing unit to implement the communication control method according to any one of claims 1 to 9.

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