Acceleration method and device for post quantum cryptography algorithm

Abstract

The invention provides an acceleration method and device for a post quantum cryptography algorithm, and is applied to the technical field of information security. The method comprises the steps of determining a target polynomial needing to be calculated by adopting polynomial multiplication in a lattice password under the condition that the post-quantum cryptographic algorithm is the lattice password; determining the number of turns of transformation operation according to the number of points of the target polynomial and a butterfly transformation unit in each turn; and determining an input point interval and a node subscript of a calculation node in each butterfly transformation unit in each round according to the number of rounds, and carrying out parallel calculation on points of the target polynomial based on the butterfly transformation units.

Description

Technical Field

[0001] The present invention relates to the field of information security technology, and in particular to a method and device for accelerating a post-quantum cryptographic algorithm. Background Art

[0002] With the continuous development of quantum computing technology, data protection has entered the era of quantum security. The cornerstone of information security is cryptographic technology, and breakthroughs in quantum computing will bring great challenges to public key cryptography widely used in modern cryptography. Like the Shor algorithm, it can efficiently solve some number theory problems with the help of quantum computers, and these problems are precisely the underlying mathematical problems that public key cryptography algorithms such as RSA and elliptic curve cryptography rely on. This means that in the quantum era, the existing public key cryptography system is likely to undergo major changes and reshaping, so exploring how to maintain the security of cryptography under the potential threat of quantum computers has become a key issue that needs to be solved urgently.

[0003] Post-Quantum Cryptography (PQC) focuses on designing cryptographic algorithms that can still guarantee security even in the face of quantum computer attacks in the future. It is usually built on the basis of some more difficult mathematical problems, such as lattice-based cryptographic algorithms, hash function-based cryptographic algorithms, and encoding-based cryptographic algorithms. Among them, lattice cryptography is very representative and belongs to the mainstream technical route in the post-quantum cryptography family. Its security comes from the difficult problems in the lattice.

[0004] For lattice cryptography, the computational speed of polynomial multiplication plays a decisive role, which directly affects the overall performance of the lattice cryptography algorithm. Therefore, how to improve the computational speed of polynomial multiplication has become an urgent problem to be solved. Summary of the invention

[0005] The present invention provides a method and device for accelerating a post-quantum cryptographic algorithm, so as to solve the problem of how to improve the calculation speed of polynomial multiplication.

[0006] The present invention provides an acceleration method for a post-quantum cryptographic algorithm, comprising: when the post-quantum cryptographic algorithm is a lattice cryptography, determining a target polynomial in the lattice cryptography that needs to be calculated by polynomial multiplication; determining the number of rounds of transformation operations and butterfly transformation units in each round according to the number of points of the target polynomial; determining the input point interval and node subscript of a calculation node in each butterfly transformation unit in each round according to the number of rounds, and performing parallel calculation on the points of the target polynomial based on the butterfly transformation units.

[0007] According to a method for accelerating a post-quantum cryptographic algorithm provided by the present invention, the number of points of the target polynomial is The step of determining the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial comprises: determining the number of rounds of transformation operations according to the number of points of the target polynomial Determine the number of rounds of transformation operation as , determine the number of butterfly transform units in each round as .

[0008] According to a method for accelerating a post-quantum cryptographic algorithm provided by the present invention, the step of determining the input point interval and node subscript of a computing node in each butterfly transformation unit in each round according to the number of rounds comprises: In rounds, the input point interval of the computing node in each butterfly transformation unit is determined to be , the node subscript interval is ;in, .

[0009] According to a method for accelerating a post-quantum cryptographic algorithm provided by the present invention, the method further includes: determining the node scale after recursive decomposition in each round according to the number of points of the target polynomial.

[0010] According to a method for accelerating a post-quantum cryptographic algorithm provided by the present invention, the parallel calculation of the points of the target polynomial based on the butterfly transformation unit includes: using a graphics processor to parallel calculate the points of the target polynomial, and one butterfly transformation unit corresponds to one thread block of the graphics processor.

[0011] The present invention also provides an acceleration device for a post-quantum cryptographic algorithm, comprising the following modules: a processing module; the processing module is used to determine, when the post-quantum cryptographic algorithm is a lattice cipher, a target polynomial that needs to be calculated by polynomial multiplication in the lattice cipher; determine the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial; determine the input point interval and node subscript of the calculation node in each butterfly transformation unit in each round according to the number of rounds, and perform parallel calculations on the points of the target polynomial based on the butterfly transformation units.

[0012] According to an acceleration device for a post-quantum cryptographic algorithm provided by the present invention, the number of points of the target polynomial is The processing module is used to calculate the number of points of the target polynomial according to the number of points of the target polynomial. Determine the number of rounds of transformation operation as , determine the number of butterfly transform units in each round as .

[0013] According to an acceleration device for a post-quantum cryptographic algorithm provided by the present invention, the processing module is used in the In rounds, the input point interval of the computing node in each butterfly transformation unit is determined to be , the node subscript interval is ;in, .

[0014] According to an acceleration device for a post-quantum cryptographic algorithm provided by the present invention, the processing module is used to determine the node scale after each round of recursive decomposition according to the number of points of the target polynomial.

[0015] According to an acceleration device for a post-quantum cryptographic algorithm provided by the present invention, the processing module is used to use a graphics processor to perform parallel calculations on the points of the target polynomial, and one butterfly transformation unit corresponds to one thread block of the graphics processor.

[0016] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, an acceleration method for a post-quantum cryptographic algorithm as described above is implemented.

[0017] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a method for accelerating a post-quantum cryptographic algorithm as described in any one of the above.

[0018] The present invention also provides a computer program product, comprising a computer program, which, when executed by a processor, implements a method for accelerating a post-quantum cryptographic algorithm as described above.

[0019] The acceleration method and device of the post-quantum cryptographic algorithm provided by the present invention can determine the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial; determine the input point interval and node subscript of the computing node in each butterfly transformation unit in each round according to the number of rounds, and perform parallel calculations on the points of the target polynomial based on the butterfly transformation units. Since the points of the target polynomial can be calculated in parallel, the efficiency of fast number theory transformation can be improved, thereby realizing the acceleration of the post-quantum cryptographic algorithm based on lattice cryptography. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1It is a flow chart of the acceleration method of the post-quantum cryptographic algorithm provided by the present invention; Figure 2 It is a schematic diagram of the acceleration method of the post-quantum cryptographic algorithm provided by the present invention; Figure 3 It is a schematic diagram of the structure of the acceleration device of the post-quantum cryptographic algorithm provided by the present invention; Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] It should be noted that, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0024] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0025] In order to facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and order of execution.

[0026] The basic concepts involved in the embodiments of the present application are described in detail below.

[0027] Modulo operation: Modulo operation is a kind of operation relationship expression within the range of integers. ,if Can be Divisible by , which means and Divide by The remainders obtained are the same, which is called modulo For example, , because 7-1=6 is divisible by 3, the remainders when divided by 3 are both 1.

[0028] Euler function: Euler function For positive integers Defined as follows: it counts the number of Among the positive integers, The number of positive integers that are coprime (i.e., their greatest common factor is 1). For example, , there are 2 positive integers less than or equal to 6 and coprime with 6, 1 and 5, so .

[0029] Order: For two integers and ( are mutually prime and ), there is a smallest positive integer , so that Established, this is called mold The order is denoted as For example, if , , we can calculate , and 3 is the smallest positive integer that satisfies this condition, so the order of 2 modulo 7 is .

[0030] Primitive root: when an integer , are mutually prime, and mold The order equal When Model For example, for prime numbers , , and it was found that , so 2 is a primitive root modulo 5.

[0031] The nature of the original root: When is a prime number, the primitive root has a special property, that is, if Model The original root of The results are different from each other. Lower, original root The values ​​generated are all different from each other. For example, for prime numbers , primitive root 3, calculation , , etc. These results vary.

[0032] Referring to the properties of the unit root in the Fast Fourier Transform (FFT), the primitive root in the Fast Number Theoretic Transform (NTT) also satisfies the periodicity, symmetry and halving of the primitive root. Using these properties, the NTT algorithm can also realize recursive decomposition like FFT.

[0033] Selection of primitive roots and moduli: In order to realize the recursive decomposition of NTT, the modulus The format should be Table 1 shows some optional primitive roots and moduli.

[0034] Table 1

[0035] Fast Number Theoretic Transform (NTT): The basic principle and execution process of fast number theoretic transform are basically the same as those of fast Fourier transform, but FFT needs to use double type for calculation, which will cause precision error when a large number of operations are performed. NTT is a transformation algorithm in the sense of modulus in the integer domain, which is better than FFT in terms of calculation accuracy. Replace with the roots of unity formed by primitive roots on the modulo domain , the transformation in the complex domain is converted to the modular domain, thereby achieving an improvement in calculation accuracy.

[0036] According to the periodicity, symmetry and halving of primitive roots, the fast number theory The transformation of a point is decomposed into two The transformation of the point, if is a power of 2, and the algorithm complexity is In the above recursive process, starting from the top, the array is split layer by layer, and the smallest granularity calculation result is generated at the bottom layer, and then the final result is formed layer by layer. The process of separating the subscripts requires additional storage space, which increases the space complexity.

[0037] In order to reduce space complexity, special operations are performed layer by layer from the bottom result to the top. This operation is called butterfly operation, which can convert a sequence in place into , its space complexity is In order to implement the butterfly operation, the sequence subscript needs to be bit reversed, as shown below: After converting the original sequence elements by bit reversal, NTT operations can be performed layer by layer in a loop. The algorithm complexity is , the space complexity is .

[0038] The embodiments of the present application describe some exemplary embodiments for the purpose of explanation. It should be understood that the present application can be implemented in other ways that are not specifically shown in the drawings.

[0039] like Figure 1 As shown, the embodiment of the present application provides a method for accelerating a post-quantum cryptographic algorithm, and the method for accelerating a post-quantum cryptographic algorithm can be applied to an acceleration device for a post-quantum cryptographic algorithm. The method for accelerating a post-quantum cryptographic algorithm can include S101-S103: S101. When the post-quantum cryptographic algorithm is a lattice cryptographic algorithm, an acceleration device for the post-quantum cryptographic algorithm determines a target polynomial that needs to be calculated by polynomial multiplication in the lattice cryptographic algorithm.

[0040] Post-quantum cryptographic algorithms are designed to resist attacks from quantum computers. Lattice cryptography is a representative type of cryptography in the post-quantum cryptography family and is currently the mainstream post-quantum cryptographic algorithm technology route. The speed of polynomial multiplication is the key to the performance of lattice cryptographic algorithms. The acceleration device of the post-quantum cryptographic algorithm can first determine the target polynomial that needs to be calculated by polynomial multiplication in the lattice cryptography.

[0041] S102. The acceleration device of the post-quantum cryptographic algorithm determines the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial.

[0042] Optionally, the number of points of the target polynomial is , the acceleration device of the post-quantum cryptographic algorithm can be based on the number of points of the target polynomial Determine the number of rounds of transformation operation as , determine the number of butterfly transform units in each round as .

[0043] Specifically, fast number theoretic transformations are algorithms that speed up polynomial multiplication. The target polynomial of points, where The fast number theory transformation can be divided into Round transformation operation, each round has In each round, the calculations between different butterfly transform units can be carried out in parallel.

[0044] For example, Figure 2 As shown, Take the target polynomial of 8 points as an example. The 8 points are , the whole can be divided into Round-trip operation, including wheel, Wheel and In each round, there are The calculations between the four butterfly transform units can be carried out in parallel in each round.

[0045] S103. The acceleration device of the post-quantum cryptographic algorithm determines the input point interval and node subscript of the computing node in each butterfly transformation unit in each round according to the number of rounds, and performs parallel calculation on the points of the target polynomial based on the butterfly transformation unit.

[0046] Optionally, the acceleration device of the post-quantum cryptographic algorithm can determine the node scale after each round of recursive decomposition according to the number of points of the target polynomial.

[0047] Specifically, in each round of fast number theory transformation, we can define the module The remaining series The primitive root of subunit is , also called the rotation factor, where yes The original root, is a prime number, Divisible The rotation factor for each round is ,in, , It refers to the node size after recursive decomposition of this round, and its value is halved with each level of recursion.

[0048] It should be noted that Indicates A primitive root, At the same time, because of the mathematical properties of primitive roots, only half of the primitive roots are needed to calculate all the remaining roots of unity, so the value range is .

[0049] For example, continue to refer to Figure 2 ,exist round, which corresponds to the bottom layer of recursive decomposition, so the node size ,Right now , so the rotation factor of this round is ;exist round, the node size of this round is twice that of the previous round, so ,Right now , so the rotation factor of this round is and ;exist round, which corresponds to the top level of recursive decomposition, so the node size ,Right now , so the rotation factor of this round is .

[0050] Optionally, the acceleration device of the post-quantum cryptographic algorithm can be In rounds, the input point interval of the computing node in each butterfly transformation unit is determined to be , the node subscript interval is ; in, .

[0051] For example, continue to refer to Figure 2 ,exist round, the distance between the two input points of each butterfly transformation unit is points, the node subscript interval is For example, the input point of the first butterfly transformation unit in round 2 is and , the middle interval For these three points, the interval between node subscript 0 and node subscript 4 is 4. The interval between the two input points of each butterfly transform unit is 1 point, and the node subscript interval is 2. For example, the input point of the first butterfly transform unit is and , the middle interval At this point, the interval between node subscript 0 and node subscript 2 is 2. In round 0, the interval between the two input points of each butterfly transform unit is 0 points, and the node subscript interval is 1. For example, the input point of the first butterfly transform unit in round 0 is and , the node subscript interval is 1. By parallel calculation of 8 input points, the corresponding 8 outputs can be obtained respectively .

[0052] Optionally, the acceleration device of the post-quantum cryptographic algorithm can use a graphics processor to perform parallel calculations on the points of the target polynomial, and one butterfly transformation unit corresponds to one thread block of the graphics processor.

[0053] Specifically, a graphics processing unit (GPU) is a microprocessor specifically designed to handle graphics and image-related tasks. Regarding GPU programming mode, there are three important concepts, namely grid, block, and thread, which correspond to the device, streaming multiprocessor (SM), and core at the GPU structural level. The smallest unit of GPU operation is thread. Multiple threads can form a block, and multiple blocks executing the same program can form a grid. Multiple blocks share a cache, so communication between blocks can be regarded as a fully connected mode.

[0054] The accelerator of the post-quantum cryptographic algorithm can split the fast number theory transformation according to the operation iteration rounds, parallelize the same calculation operation in each round, and then regard each SM in the graphics processor as a computing node for parallel calculation, and distribute the parallelized operations to different SMs according to the rules. The specific distribution rules are: Step 1: Determine the unit for parallel computing in each round, which corresponds to Selected , by these Parallel calculations are performed in this round. Indicates the subscript interval of the input nodes of the butterfly transformation unit during this round of transformation.

[0055] Step 2: Determine the input nodes of each round by calculating the node index. The input points of the butterfly transformation unit are separated by points, that is, the node subscript interval is .

[0056] Step 3: Determine the calculation parameters for each round , ,in It refers to the node size after recursive decomposition of this round, and its value is halved with each level of recursion.

[0057] It should be noted that the parallel fast number theory transformation parallelizes the computational operations of each iteration round, and its complexity is a constant, that is, , a total of logn rounds of recursive iterations are performed using the binary search method, so the complexity is .

[0058] In the embodiment of the present application, the number of rounds of transformation operations and the butterfly transformation units in each round can be determined according to the number of points of the target polynomial; the input point interval and node subscript of the calculation node in each butterfly transformation unit in each round are determined according to the number of rounds, and the points of the target polynomial are calculated in parallel based on the butterfly transformation units. Since the points of the target polynomial can be calculated in parallel, the efficiency of fast number theory transformation can be improved, thereby realizing the acceleration of the post-quantum cryptographic algorithm based on lattice cryptography.

[0059] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. In order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiment disclosed herein, the embodiment of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0060] It should be noted that the device in the embodiment of the present application includes a virtual device and a physical device. The virtual device can be an acceleration device for the post-quantum cryptographic algorithm, and the physical device can include an electronic device, a computer storage medium, and a computer program product.

[0061] The acceleration method of the post-quantum cryptographic algorithm provided in the embodiment of the present application can be performed by an acceleration device of the post-quantum cryptographic algorithm, or a control module for accelerating the post-quantum cryptographic algorithm in the acceleration device of the post-quantum cryptographic algorithm. In the embodiment of the present application, the acceleration method of the post-quantum cryptographic algorithm performed by the acceleration device of the post-quantum cryptographic algorithm is taken as an example to illustrate the acceleration device of the post-quantum cryptographic algorithm provided in the embodiment of the present application.

[0062] It should be noted that the embodiment of the present application can divide the functional modules of the acceleration device of the post-quantum cryptographic algorithm according to the above method example. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. Optionally, the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation.

[0063] like Figure 3 As shown, an embodiment of the present application provides an acceleration device 300 for a post-quantum cryptographic algorithm. The acceleration device 300 for a post-quantum cryptographic algorithm includes: a processing module 301. The processing module 301 is used to determine the target polynomial that needs to be calculated by polynomial multiplication in the lattice cipher when the post-quantum cryptographic algorithm is a lattice cipher; determine the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial; determine the input point interval and node subscript of the calculation node in each butterfly transformation unit in each round according to the number of rounds, and perform parallel calculations on the points of the target polynomial based on the butterfly transformation units.

[0064] Optionally, the number of points of the target polynomial is The processing module 301 is used to calculate the number of points of the target polynomial Determine the number of rounds of transformation operation as , determine the number of butterfly transform units in each round as .

[0065] Optionally, the processing module 301 is used to In rounds, the input point interval of the computing node in each butterfly transformation unit is determined to be , the node subscript interval is ;in, .

[0066] Optionally, the processing module 301 is used to determine the node scale after each round of recursive decomposition according to the number of points of the target polynomial.

[0067] Optionally, the processing module 301 is used to use a graphics processor to perform parallel calculations on points of the target polynomial, and one butterfly transformation unit corresponds to one thread block of the graphics processor.

[0068] In the embodiment of the present application, the number of rounds of transformation operations and the butterfly transformation units in each round can be determined according to the number of points of the target polynomial; the input point interval and node subscript of the calculation node in each butterfly transformation unit in each round are determined according to the number of rounds, and the points of the target polynomial are calculated in parallel based on the butterfly transformation units. Since the points of the target polynomial can be calculated in parallel, the efficiency of fast number theory transformation can be improved, thereby realizing the acceleration of the post-quantum cryptographic algorithm based on lattice cryptography.

[0069] Figure 4 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 4As shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430 and a communication bus 440, wherein the processor 410, the communication interface 420 and the memory 430 communicate with each other through the communication bus 440. The processor 410 may call the logic instructions in the memory 430 to execute the acceleration method of the post-quantum cryptographic algorithm, the method comprising: when the post-quantum cryptographic algorithm is a lattice cipher, determining the target polynomial that needs to be calculated by polynomial multiplication in the lattice cipher; determining the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial; determining the input point interval and node subscript of the calculation node in each butterfly transformation unit in each round according to the number of rounds, and performing parallel calculation on the points of the target polynomial based on the butterfly transformation unit.

[0070] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0071] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the acceleration method of the post-quantum cryptographic algorithm provided by the above methods, the method comprising: when the post-quantum cryptographic algorithm is a lattice cipher, determining the target polynomial that needs to be calculated by polynomial multiplication in the lattice cipher; determining the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial; determining the input point interval and node subscript of the calculation node in each butterfly transformation unit in each round according to the number of rounds, and performing parallel calculations on the points of the target polynomial based on the butterfly transformation unit.

[0072] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements an acceleration method for executing a post-quantum cryptographic algorithm provided by the above methods, the method comprising: when the post-quantum cryptographic algorithm is a lattice cipher, determining a target polynomial in the lattice cipher that requires polynomial multiplication calculation; determining the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial; determining the input point interval and node subscript of the calculation node in each butterfly transformation unit in each round according to the number of rounds, and performing parallel calculations on the points of the target polynomial based on the butterfly transformation units.

[0073] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0074] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for accelerating a post-quantum cryptographic algorithm, characterized in that: include: In the case where the post-quantum cryptographic algorithm is a lattice cryptography, determining a target polynomial that needs to be calculated by polynomial multiplication in the lattice cryptography; Determining the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial; The input point interval and node subscript of the calculation node in each butterfly transformation unit in each round are determined according to the number of rounds, and the points of the target polynomial are calculated in parallel based on the butterfly transformation unit.

2. The acceleration method of the post-quantum cryptographic algorithm according to claim 1, characterized in that: The number of points of the target polynomial is , the determining the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial includes: According to the number of points of the target polynomial Determine the number of rounds of transformation operation as , determine the number of butterfly transform units in each round as .

3. The acceleration method of the post-quantum cryptographic algorithm according to claim 2, characterized in that: The step of determining the input point interval and node subscript of the computing node in each butterfly transformation unit in each round according to the number of rounds includes: In the In rounds, the input point interval of the computing node in each butterfly transformation unit is determined to be , the node subscript interval is ; in, .

4. The acceleration method of the post-quantum cryptographic algorithm according to claim 2, characterized in that: The method further comprises: The node scale after each round of recursive decomposition is determined according to the number of points of the target polynomial.

5. The acceleration method of the post-quantum cryptographic algorithm according to any one of claims 1 to 4, characterized in that: The performing parallel calculation on the points of the target polynomial based on the butterfly transformation unit comprises: A graphics processor is used to perform parallel calculations on the points of the target polynomial, and one butterfly transformation unit corresponds to one thread block of the graphics processor.

6. An acceleration device for a post-quantum cryptographic algorithm, characterized in that: include: Processing module; The processing module is used to determine, when the post-quantum cryptographic algorithm is a lattice cryptography, a target polynomial that needs to be calculated by polynomial multiplication in the lattice cryptography; determine the number of rounds of transformation operations and the butterfly transformation units in each round according to the number of points of the target polynomial; determine the input point interval and node subscript of the calculation node in each butterfly transformation unit in each round according to the number of rounds, and perform parallel calculation on the points of the target polynomial based on the butterfly transformation units.

7. The acceleration device for the post-quantum cryptographic algorithm according to claim 6, characterized in that: The number of points of the target polynomial is The processing module is used to calculate the number of points of the target polynomial according to the number of points of the target polynomial. Determine the number of rounds of transformation operation as , determine the number of butterfly transform units in each round as .

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the acceleration method of the post-quantum cryptographic algorithm as described in any one of claims 1 to 5 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the acceleration method of the post-quantum cryptographic algorithm as claimed in any one of claims 1 to 5 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the acceleration method of the post-quantum cryptographic algorithm as claimed in any one of claims 1 to 5 is implemented.

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