Performance prediction method and device for multi-channel parallel MCC fragmentation

Abstract

The invention relates to a multi-channel parallel MCC fragment performance prediction method and device, and the method comprises the steps: obtaining an MCC fragment combination set which comprises a plurality of MCC fragment combinations, and each MCC fragment combination comprises a plurality of links; for each link in the plurality of links of each MCC fragment combination, based on the parameters of the MCC fragment combination, performing time delay estimation through a time delay estimation model to obtain a periodic average time delay of each link; and for each link in the plurality of links of each MCC fragment combination, based on the parameters of the MCC fragment combination, performing bandwidth estimation through a bandwidth estimation model to obtain the bandwidth of each link. Rapid estimation of MCC fragment combination performance is realized, and meanwhile, time resources and test manpower resources are saved.

Description

Technical Field

[0001] The present disclosure relates to the field of coexistence technology, and in particular to a performance prediction method and device for multi-channel parallel MCC slices. Background Art

[0002] In the related technology, MCC (Multi-channel concurrent) technology is a technology used for coexistence, which allows the WiFi chip to handle multiple tasks at the same time, such as the TDD (Time Division Duplexing) technology of WiFi and P2P (peer-to-peer). WiFi and P2P cannot work at the same time, so WiFi and P2P work in time-sharing and need to switch channels.

[0003] Currently, user usage scenarios are complex and changeable. In MCC scenarios, the bandwidth and latency required for different applications are different. There are many time-sharing allocation combinations, and it is difficult to find a suitable time-sharing combination for related scenarios. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the present disclosure provides a performance prediction method and device for MCC slices.

[0005] According to a first aspect of an embodiment of the present disclosure, a performance prediction method for an MCC slice is provided, including:

[0006] Acquire an MCC slice combination set, where the MCC slice combination set includes multiple MCC slice combinations, and the MCC slice combination includes multiple links;

[0007] For each link in the multiple links of each of the MCC slice combinations, based on the parameters of the MCC slice combination, a delay estimation model is used to perform delay estimation to obtain a period average delay of each link;

[0008] For each link in the multiple links of each MCC slice combination, bandwidth estimation is performed through a bandwidth estimation model based on parameters of the MCC slice combination to obtain a bandwidth of each link.

[0009] In some implementations, obtaining the MCC slice combination set includes:

[0010] Determining a prediction interval and a preset step time of the MCC slice combination;

[0011] Based on the prediction interval of the MCC slice combination and the preset step time, an MCC slice combination set is acquired.

[0012] In some implementations, the delay estimation is performed based on the parameters of the MCC slice combination through a delay estimation model to obtain the period average delay of each link; including:

[0013] Based on platform-related hardware parameters and parameters of the MCC slice combination, obtain the total delay of success during the wake-up period of each link, the maximum number of delay detection particles expected to be successful during the wake-up period, the total delay of successful round trips during the sleep period, and the maximum number of delay detection particles expected to be successful during the sleep period;

[0014] Based on the total delay during the wake-up period within the cycle, the expected maximum number of successful delay detection particles during the wake-up period within the cycle, the total delay of successful round trips during the sleep period within the cycle, and the expected maximum number of successful delay detection particles during the sleep period within the cycle, delay estimation is performed through a delay estimation model to obtain the periodic average delay of each link.

[0015] In some implementations, the platform-related hardware parameters include a channel switching overhead of the platform, and the obtaining of the maximum number of delay detection nodes expected to succeed during the wake-up period within the cycle of each link based on the platform-related hardware parameters and the parameters of the MCC slice combination includes:

[0016] Based on the intra-cycle wake-up time of the link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detection nodes expected to succeed during the intra-cycle wake-up period is obtained.

[0017] In some implementations, the obtaining, based on platform-related hardware parameters and parameters of the MCC slice combination, a total delay for successful wake-up during a period of each link includes:

[0018] Based on the delay of the link in the current channel and the maximum number of delay detection nodes expected to be successfully detected during the wake-up period in the cycle, the total delay of success during the wake-up period in the cycle is obtained.

[0019] In some implementations, the obtaining, based on platform-related hardware parameters and parameters of the MCC slice combination, a maximum number of delay detections expected to be successful during the sleep period within the cycle of each link includes:

[0020] Based on the peak delay of the link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detections expected to be successful during the sleep period within the cycle is obtained.

[0021] In some implementations, obtaining the total delay of successful round trips during the sleep period within the cycle of each link based on the platform-related hardware parameters and the parameters of the MCC slice combination includes:

[0022] Based on the expected maximum number of successful delay detections during the sleep period within the cycle, the peak delay of the link, the delay round-trip detection interval and the penalty delay, the total delay of successful round-trips during the sleep period within the cycle of each link is obtained; wherein the penalty delay refers to the instantaneous delay increase time caused by the surge in data volume during wake-up from waiting to execution.

[0023] In some implementations, the performing bandwidth estimation based on the parameters of the MCC slice combination through a bandwidth estimation model to obtain the bandwidth of each link includes:

[0024] Based on platform-related hardware parameters and parameters of the MCC shard combination, obtain the maximum wake-up duration per second of each link and an estimated value of the highest throughput that can be achieved in an actual environment;

[0025] Based on the maximum wake-up duration per second of each link and the estimated value of the highest throughput that can be achieved in the actual environment, bandwidth estimation is performed through a bandwidth estimation model to obtain the bandwidth of each link.

[0026] In some implementations, the platform-related hardware parameters include a channel switching overhead of the platform, and the obtaining, based on the platform-related hardware parameters and the parameters of the MCC slice combination, the maximum wake-up duration per second of each link includes:

[0027] Based on the maximum number of running cycles per second, the wake-up time of the link within the cycle and the channel switching overhead of the platform, the maximum wake-up duration per second of each link is obtained.

[0028] In some implementations, obtaining an estimated value of a maximum throughput that can be achieved in an actual environment based on platform-related hardware parameters and parameters of the MCC slice combination includes:

[0029] Based on the proportion of the highest throughput in a clean environment within the highest physical transmission rate and the proportion of the highest throughput in the actual environment within the highest throughput in the clean environment, an estimated value of the highest throughput that can be achieved in the actual environment is obtained; wherein the highest throughput in the clean environment refers to the highest actual transmission rate with basically no retransmission after removing the underlying protocol overhead, and the highest throughput in the actual environment refers to the highest actual transmission rate with a certain amount of retransmission after removing the underlying protocol overhead.

[0030] According to a second aspect of an embodiment of the present disclosure, a performance prediction device for an MCC slice is provided, including:

[0031] A slice acquisition module, configured to acquire an MCC slice combination set, wherein the MCC slice combination set includes a plurality of MCC slice combinations, and the MCC slice combination includes a plurality of links;

[0032] A delay estimation module, configured to perform delay estimation for each link of the multiple links of each MCC slice combination through a delay estimation model based on the parameters of the MCC slice combination to obtain a period average delay of each link;

[0033] The bandwidth estimation module is used to perform bandwidth estimation on each link of the multiple links of each MCC slice combination through a bandwidth estimation model based on the parameters of the MCC slice combination to obtain the bandwidth of each link.

[0034] In some implementations, the fragment acquisition module is specifically configured to:

[0035] Determining a prediction interval and a preset step time of the MCC slice combination;

[0036] Based on the prediction interval of the MCC slice combination and the preset step time, an MCC slice combination set is acquired.

[0037] In some implementations, the delay estimation module performs delay estimation based on the parameters of the MCC slice combination through a delay estimation model to obtain the period average delay of each link; and is used to:

[0038] Based on platform-related hardware parameters and parameters of the MCC slice combination, obtain the total delay of success during the wake-up period of each link, the maximum number of delay detection particles expected to be successful during the wake-up period, the total delay of successful round trips during the sleep period, and the maximum number of delay detection particles expected to be successful during the sleep period;

[0039] Based on the total delay during the wake-up period within the cycle, the expected maximum number of successful delay detection particles during the wake-up period within the cycle, the total delay of successful round trips during the sleep period within the cycle, and the expected maximum number of successful delay detection particles during the sleep period within the cycle, delay estimation is performed through a delay estimation model to obtain the periodic average delay of each link.

[0040] In some implementations, the platform-related hardware parameters include a channel switching overhead of the platform, and the delay estimation module obtains the maximum number of delay detections expected to be successful during the wake-up period within the cycle of each link based on the platform-related hardware parameters and the parameters of the MCC slice combination; used to:

[0041] Based on the intra-cycle wake-up time of the link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detection nodes expected to succeed during the intra-cycle wake-up period is obtained.

[0042] In some implementations, the delay estimation module obtains the total delay of a successful wake-up period within the cycle of each link based on platform-related hardware parameters and parameters of the MCC slice combination; and is used to:

[0043] Based on the delay of the link in the current channel and the maximum number of delay detection nodes expected to be successfully detected during the wake-up period in the cycle, the total delay of success during the wake-up period in the cycle is obtained.

[0044] In some implementations, when the delay estimation module obtains the maximum number of delay detections expected to be successful during the sleep period within the cycle of each link based on the platform-related hardware parameters and the parameters of the MCC slice combination, it is used to:

[0045] Based on the peak delay of the link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detections expected to be successful during the sleep period within the cycle is obtained.

[0046] In some implementations, the delay estimation module obtains the total delay of successful round trips during the sleep period within the cycle of each link based on platform-related hardware parameters and parameters of the MCC slice combination, and is used to:

[0047] Based on the expected maximum number of successful delay detection nodes during the sleep period within the cycle, the peak delay of the link, the delay round-trip detection interval and the penalty delay, the total delay of successful round-trip during the sleep period within the cycle of each link is obtained; wherein the penalty delay.

[0048] In some implementations, the bandwidth estimation module performs bandwidth estimation through a bandwidth estimation model based on the parameters of the MCC slice combination to obtain the bandwidth of each link, and is used to:

[0049] Based on platform-related hardware parameters and parameters of the MCC shard combination, obtain the maximum wake-up duration per second of each link and an estimated value of the highest throughput that can be achieved in an actual environment;

[0050] Based on the maximum wake-up duration per second of each link and the estimated value of the highest throughput that can be achieved in the actual environment, bandwidth estimation is performed through a bandwidth estimation model to obtain the bandwidth of each link.

[0051] In some implementations, the platform-related hardware parameters include a channel switching overhead of the platform, and the bandwidth estimation module obtains the maximum wake-up duration per second of each link based on the platform-related hardware parameters and the parameters of the MCC slice combination, and is used to:

[0052] Based on the maximum number of running cycles per second, the wake-up time of the link within the cycle and the channel switching overhead of the platform, the maximum wake-up duration per second of each link is obtained.

[0053] In some implementations, when the bandwidth estimation module obtains an estimated value of the highest throughput that can be achieved in an actual environment based on platform-related hardware parameters and parameters of the MCC slice combination, it is used to:

[0054] Based on the ratio of the highest throughput in the clean environment to the highest physical transmission rate and the ratio of the highest throughput in the actual environment to the highest throughput in the clean environment, an estimated value of the highest throughput that can be achieved in the actual environment is obtained.

[0055] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, including:

[0056] at least one processor; and

[0057] a memory communicatively connected to the at least one processor; wherein,

[0058] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the performance prediction method of the MCC slice described in the first aspect above.

[0059] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, comprising:

[0060] The storage medium stores a computer program, and when the computer program is executed by the processor, the performance prediction method of the MCC slice described in the first aspect is implemented.

[0061] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0062] The bidirectional estimated delay of the MCC slice combination is obtained through the delay estimation model, and the bidirectional estimated bandwidth of the MCC slice combination is obtained through the bandwidth estimation model, thereby realizing rapid estimation of the performance of the MCC slice combination and saving time resources and testing human resources.

[0063] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0065] Figure 1 It is a topology diagram for performance evaluation of MCC slice combination in related technology.

[0066] Figure 2The present invention is a flowchart of a method for predicting performance of an MCC slice according to an exemplary embodiment.

[0067] Figure 3 is a model diagram of MCC slice combination according to an example.

[0068] Figure 4 The present invention is a flowchart of a method for predicting performance of an MCC slice according to another exemplary embodiment.

[0069] Figure 5 The figure is a flow chart of a method for predicting performance of an MCC slice according to another exemplary embodiment.

[0070] Figure 6 The figure is a flow chart of a method for predicting performance of an MCC slice according to another exemplary embodiment.

[0071] Figure 7 It is a block diagram of a performance prediction device for an MCC slice according to an exemplary embodiment.

[0072] Figure 8 It is a block diagram of a device according to an exemplary embodiment. DETAILED DESCRIPTION

[0073] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0074] In related technologies, MCC time-sharing combinations generally use test latency and bandwidth, and then check whether the results meet business expectations, and decide whether to use the MCC time-sharing combination based on the test results. However, in scenarios with more business demands, multiple time-sharing combinations and testing and result analysis on different platforms consume a lot of resources.

[0075] The performance evaluation of MCC time-sharing in related technologies requires Figure 1The topology shown in the figure uses the ping packet used to test the network connection and the network performance test tool iperf to perform performance testing and obtain data. The entire topology includes the connection of the test PC, router, DUT (device under test), auxiliary machine, mobile phone responsible for capturing different data packet software, and other devices. The topology is complex and the access sequence of each device is complex. Although the above topology can truly test the performance of two links in different MCC time-sharing, due to the complexity of the overall test topology, the difficulty of practical operation, and the trouble of obtaining test data, it will consume too much manpower and time under a large number of MCC time-sharing tests, and the final result is that it is difficult to obtain time-sharing performance data and consumes too much resources.

[0076] In order to solve the above problems, the embodiments of the present application provide a performance prediction method and device for MCC slices.

[0077] Figure 2 is a flow chart showing a method for predicting performance of an MCC slice according to an exemplary embodiment. Figure 2 As shown, the performance prediction method of MCC slices can be used in electronic devices, including the following steps.

[0078] In step S201, an MCC slice combination set is obtained, where the MCC slice combination set includes multiple MCC slice combinations, and the MCC slice combination includes multiple links.

[0079] First of all, it should be explained that slicing means time division. Taking the coexistence of WLAN (Wireless Local Area Network) and P2P as an example, the MCC slicing combination is explained. The MCC slicing combination (50:50) means that WLAN and P2P each occupy 50ms.

[0080] As an implementation manner, a prediction interval and a preset step time of the MCC slice combination are determined; based on the prediction interval and the preset step time of the MCC slice combination, an MCC slice combination set is acquired.

[0081] Taking WLAN and P2P coexistence as an example, assuming that the prediction interval of the MCC slice combination is set to 25-50, and the preset step time is 5ms. With 5ms as the step, the MCC slice combinations that can be obtained include (25:30, 25:35, 25:40..), or vice versa, the MCC slice combinations that can be obtained include (30:25, 35:25, 40:25..).

[0082] In step S202, for each link in the multiple links of each MCC slice combination, delay estimation is performed through a delay estimation model based on the parameters of the MCC slice combination to obtain a period average delay of each link.

[0083] As an example, Figure 3 As shown, the model of the MCC slice combination includes a first link (Link A) and a second link (Link B), and the two links work on two channels respectively. The parameters of the MCC slice combination may include the following parameters:

[0084] P: one time-sharing cycle time;

[0085] SccLat(A): the delay of LinkA in the current channel;

[0086] SccLat(B): the delay of LinkB in the current channel;

[0087] T(P, A): the wake-up time of LinkA during period P, and the sleep time of LinkB during period P (in this embodiment, within one cycle, the wake-up time of LinkA is equal to the sleep time of LinkB, T(P, A)+T(P, B)=P);

[0088] T(P,B): PT(P,A), the wake-up time of LinkB during P, and the sleep time of LinkA during P.

[0089] ProbeInt: delay round-trip detection interval. For example, assume that 10 (ms) is used as the delay round-trip detection interval.

[0090] As an implementation method, the parameters of the first link in the platform-related hardware parameters and the parameters of the MCC slice combination are input into the delay estimation model to obtain the periodic average delay of the first link. The parameters of the second link in the platform-related hardware parameters and the parameters of the MCC slice combination are input into the delay estimation model to obtain the periodic average delay of the second link.

[0091] In this embodiment, the platform-related hardware parameters include the channel switching overhead of the platform. Before performance prediction, it is necessary to obtain the channel switching overhead SwitchCons(Platform) of the current platform Platform. The channel switching overhead of the platform can be obtained through testing.

[0092] Taking the coexistence of WLAN and P2P as an example, WLAN and P2P cannot work at the same time and need to work in two channels in time-sharing, so channel switching is required. Channel switching affects the latency and bandwidth of data transmission, so it is necessary to obtain the platform-related hardware parameters of the current platform, including channel switching overhead.

[0093] This embodiment uses a delay estimation model to estimate the delays of multiple links of the MCC slice combination, which saves manpower and is highly efficient.

[0094] In step S203, for each link in the multiple links of each MCC slice combination, bandwidth estimation is performed through a bandwidth estimation model based on the parameters of the MCC slice combination to obtain the bandwidth of each link.

[0095] As an implementation method, the parameters of the first link in the platform-related hardware parameters and the MCC slice combination parameters are input into the bandwidth estimation model to obtain the bandwidth of the first link. The parameters of the second link in the platform-related hardware parameters and the MCC slice combination parameters are input into the bandwidth estimation model to obtain the bandwidth of the second link.

[0096] This embodiment uses a bandwidth estimation model to estimate the bandwidth of multiple links of the MCC slice combination, which saves manpower and is highly efficient.

[0097] This embodiment establishes a model on the MCC shard combination, and predicts the corresponding bandwidth and delay for different MCC shard combinations through the delay prediction model and the bandwidth prediction model, which serves as a data system estimation solution for the entire time-sharing combination, and is 665% faster than the manual estimation solution.

[0098] The performance prediction method of MCC slices in the embodiment of the present application obtains the bidirectional estimated delay of the MCC slice combination through the delay estimation model, and obtains the bidirectional estimated bandwidth of the MCC slice combination through the bandwidth estimation model, thereby realizing the rapid estimation of the performance of the MCC slice combination set, so that more suitable MCC slice combinations in different business scenarios can be efficiently found, while saving time resources and testing human resources.

[0099] The following describes in detail the implementation method of performing delay estimation based on the parameters of the MCC slice combination in step S202 through the delay estimation model to obtain the period average delay of each link.

[0100] Figure 4 is a flow chart showing a method for predicting performance of an MCC slice according to another exemplary embodiment. Figure 4 As shown, the following steps are included.

[0101] In step S401, based on the intra-cycle wake-up time of the link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detection nodes expected to succeed during the intra-cycle wake-up period is obtained.

[0102] This embodiment is described by taking delay estimation of LinkA as an example.

[0103] As a specific implementation method, based on the intra-cycle wake-up time of the first link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detection nodes (ActiveTotalNum) expected to be successful during the intra-cycle wake-up of the first link is obtained by the following formula.

[0104]

[0105] Among them, ActiveTotalNum (T (P, A)) is the number of delay detection nodes that are expected to be successfully completed during the wake-up period of LinkA during the P period (that is, the maximum number of delay detection nodes that are expected to be successfully completed during the wake-up period).

[0106] Similarly, the ActiveTotalNum of the second link can be obtained by transforming the link through the above formula based on the wake-up time within the cycle of the second link, the channel switching overhead of the platform, and the delay round-trip detection interval.

[0107] In step S402, based on the link delay in the current channel and the maximum number of delay detections expected to be successful during the wake-up period within the cycle, the total delay of the successful wake-up period within the cycle is obtained.

[0108] As a specific implementation method, based on the latency of the first link in the current channel and the expected maximum number of successful latency detections during the wake-up period within the cycle of the first link, the total latency (ActiveTotalLat) of successful wake-up during the cycle of the first link is obtained by the following formula.

[0109] ActiveTotalLat(T(P,A))=SccLat(A)*ActiveTotalNum(T(P,A)

[0110] Among them, ActiveTotalLat(T(P,A)): the total latency during the successful wake-up period within the cycle of LinkA during period P.

[0111] In step S403, based on the peak delay of the link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detection nodes expected to be successful during the sleep period within the cycle is obtained.

[0112] As a specific implementation method, based on the peak delay of the first link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detection nodes (InactiveTotalNum) expected to be successful during the sleep period within the cycle of the first link is obtained by the following formula.

[0113]

[0114] Among them, InactiveTotalNum (T (P, A)): during period P, the number of delay detections that can be successfully performed during the sleep period of LinkA (that is, the maximum number of delay detections that can be successfully performed during the sleep period);

[0115] MccMaxLat(T(P,A)): The peak latency of LinkA during period P.

[0116] In step S404, the total delay of successful round trips during the sleep period of each link is obtained based on the expected maximum number of successful delay detections during the sleep period, the peak delay of the link, the delay round-trip detection interval, and the penalty delay; wherein the penalty delay refers to the instantaneous delay increase time caused by the surge in data volume during the wake-up period from waiting to execution.

[0117] As a specific implementation method, based on the expected maximum number of successful delay detection nodes during the sleep period of the first link, the peak delay of the first link, the delay round-trip detection interval, and the penalty delay, the total delay (InactiveTotalLat) of successful round trips during the sleep period of the first link is obtained by the following formula:

[0118]

[0119] Where, N = InactiveTotalNum(T(P,A)),

[0120] f(n)=(MccMaxLat(T(P,A))-(n-1)*ProbeInt+MccLatPen(x)),

[0121] InactiveTotalLat(T(P,A)): The total latency of successful round trips during the sleep period of LinkA during period P;

[0122] MccLatPen(x): Penalty delay. The change from Pending->Go causes an instantaneous increase in loading during wake-up, which may lead to incast (i.e., the instantaneous delay caused by the surge in data volume during wake-up from waiting to execution). For example, the penalty delay x is 1 <x<3(ms)。

[0123] In step S405, based on the total delay during the successful wake-up period within the cycle, the expected maximum number of successful delay detections during the wake-up period within the cycle, the total delay of successful round trips during the sleep period within the cycle, and the expected maximum number of successful delay detections during the sleep period within the cycle, the delay estimation model is used to perform delay estimation to obtain the periodic average delay of each link.

[0124] That is, through steps S401-S404, based on the platform-related hardware parameters and the parameters of the MCC slice combination, the total delay of success during the wake-up period, the maximum delay detection number of particles expected to be successful during the wake-up period, the total delay of successful round trips during the sleep period, and the maximum delay detection number of particles expected to be successful during the sleep period are obtained for each link. Then, based on the total delay of success during the wake-up period, the maximum delay detection number of particles expected to be successful during the wake-up period, the total delay of successful round trips during the sleep period, and the maximum delay detection number of particles expected to be successful during the sleep period, the average delay of the cycle (MccAvgLat) of each link is obtained.

[0125] As a specific implementation method, based on the total successful delay during the wake-up period of the first link, the expected maximum number of successful delay detection nodes during the wake-up period of the first link, the total successful round-trip delay during the sleep period of the first link, and the expected maximum number of successful delay detection nodes during the sleep period of the first link, the cycle average delay of the first link is obtained by the following formula.

[0126]

[0127] Where, MccAvgLat(T(P,A)) is the cycle average delay of LinkA during period P.

[0128] The performance prediction method of MCC slices in the embodiment of the present application implements a delay estimation model, and the two-way estimated delay of the MCC slice combination can be obtained through the delay estimation model.

[0129] The following describes in detail the implementation method of performing bandwidth estimation based on the platform-related hardware parameters and the parameters of the MCC slice combination in step S203 by using the bandwidth estimation model to obtain the bandwidth of each link.

[0130] Figure 5 is a flow chart showing a method for predicting performance of an MCC slice according to another exemplary embodiment. Figure 5 As shown, the following steps are included.

[0131] In step S501, based on the maximum number of running cycles per second, the wake-up time of the link within the cycle and the channel switching overhead of the platform, the maximum wake-up time per second of each link is obtained.

[0132] This embodiment is described by taking bandwidth estimation of LinkA as an example.

[0133] As a specific implementation method, based on the maximum number of running cycles per second (PeriodNum), the wake-up time within the cycle of the first link and the channel switching overhead of the platform, the maximum wake-up time per second (ActiveTime) of the first link is obtained by the following formula.

[0134] ActiveTime(T(P,A))=PeriodNum(P)*(T(P,A)-SwitchCons(Platform))

[0135] Among them, ActiveTime (T (P, A)): the actual duration that LinkA can wake up per second (that is, the maximum wake-up duration of LinkA per second); PeriodNum (P) is the maximum number of operating periods P per second, in this example PeriodNum (P) = 1000 / P.

[0136] In step S502, based on the ratio of the highest throughput in the clean environment to the highest physical transmission rate and the ratio of the highest throughput in the actual environment to the highest throughput in the clean environment, an estimated value of the highest throughput that can be achieved in the actual environment is obtained.

[0137] As a specific implementation method, the maximum physical transmission rate (PeakPhyRate) supported by the current negotiation is obtained, and the maximum throughput of the clean environment is obtained based on the proportion of the maximum throughput of the clean environment within the maximum physical transmission rate and the maximum physical transmission rate; based on the maximum throughput of the clean environment and the proportion of the maximum throughput of the actual environment within the maximum throughput of the clean environment, an estimated value (ReachableRate) of the maximum throughput that can be achieved in the actual environment is obtained.

[0138] As an example, PeakPhyRate(pro, bw, nss): the highest physical transmission rate (phyrate) currently supported by the negotiation, for example, select the 2 groups with the highest current usage scenarios;

[0139] AX, 80M, 2:1201;

[0140] AC, 80M, 2:866;

[0141] SccPeakTput (PeakPhyRate): Maximum throughput (Tput) in a clean environment;

[0142] It should be noted that the maximum throughput in a clean environment refers to the maximum actual transmission rate with almost no retransmission after removing the underlying protocol overhead. The maximum throughput in an actual environment refers to the maximum actual transmission rate with certain retransmission after removing the underlying protocol overhead.

[0143] For example, the maximum throughput of the clean environment may account for 75% of the maximum physical transmission rate, and the maximum throughput of the actual environment may account for 60% of the maximum throughput of the clean environment.

[0144] ReachableRate(SccPeakTput): The estimated value of the highest throughput that can be achieved in the actual environment

[0145] In step S503, the bandwidth of each link is obtained based on the maximum wake-up duration per second of each link and the estimated value of the highest throughput that can be achieved in the actual environment.

[0146] That is to say, through the above steps S501-S502, the parameters based on the platform-related hardware parameters and the MCC slice combination are implemented to obtain the maximum wake-up time per second of each link and the estimated value of the highest throughput that can be achieved in the actual environment; then based on the maximum wake-up time per second of each link and the estimated value of the highest throughput that can be achieved in the actual environment, the bandwidth of each link is obtained.

[0147] As a specific implementation method, based on the maximum wake-up time per second of the first link and the estimated value of the highest throughput that can be achieved in the actual environment, the bandwidth MaxActiveTput of the first link is obtained by the following formula:

[0148] MaxActiveTput=ActiveTime*ReachableRate

[0149] Among them, MaxActiveTput is the actual maximum throughput that can be achieved by the link per second, that is, the bandwidth of the link.

[0150] In this embodiment, the highest throughput that a link can actually achieve per second is the bandwidth of the link.

[0151] The performance prediction method for MCC slices in the embodiment of the present application implements a bandwidth estimation model, and the bidirectional estimated bandwidth of the MCC slice combination can be obtained through the bandwidth estimation model.

[0152] As a specific example, Figure 6 is a flow chart of a method for predicting performance of an MCC slice according to another exemplary embodiment. Figure 6 As shown, the following steps are included.

[0153] In step S601, platform-related hardware parameters are input.

[0154] In step S602, the parameters of the next MCC slice combination that needs to be estimated are obtained.

[0155] In step S603, the delay estimation model is used to perform delay estimation on the current MCC slice combination to obtain a delay estimation result for each link.

[0156] In step S604, bandwidth estimation is performed on the current MCC slice combination using a bandwidth estimation model to obtain a bandwidth estimation result for each link.

[0157] In step S605, the parameters of the current MCC slice combination and the delay estimation result and the bandwidth estimation result are saved.

[0158] In step S606, it is determined whether there is a next MCC slice combination that needs to be estimated. If yes, the process jumps to step S602; if no, the process jumps to step S607.

[0159] In step S607, the parameters of all MCC slice combinations as well as the delay estimation results and the bandwidth estimation results are output.

[0160] Optionally, you can generate an MCC performance estimate report for the corresponding platform, and you can also visualize the estimated data for the MCC shard combination.

[0161] The performance prediction method of MCC slices in the embodiment of the present application obtains the bidirectional estimated delay of the MCC slice combination through the delay estimation model, and obtains the bidirectional estimated bandwidth of the MCC slice combination through the bandwidth estimation model, thereby realizing the rapid estimation of the performance of the MCC slice combination set, so that more suitable MCC slice combinations in different business scenarios can be efficiently found, while saving time resources and testing human resources.

[0162] Figure 7 FIG. 1 is a block diagram of a performance prediction device for an MCC slice according to an exemplary embodiment. Figure 7 The device includes a fragment acquisition module 701, a delay estimation module 702 and a bandwidth estimation module 703.

[0163] in,

[0164] A slice acquisition module 701 is used to acquire an MCC slice combination set, where the MCC slice combination set includes multiple MCC slice combinations, and the MCC slice combination includes multiple links;

[0165] The delay estimation module 702 is used to estimate the delay of each link in the multiple links of each MCC slice combination through the delay estimation model based on the parameters of the MCC slice combination to obtain the period average delay of each link;

[0166] The bandwidth estimation module 703 is used to perform bandwidth estimation for each link in the multiple links of each MCC slice combination through a bandwidth estimation model based on the parameters of the MCC slice combination to obtain the bandwidth of each link.

[0167] In some implementations, the fragment acquisition module 701 is specifically configured to:

[0168] Determine the prediction interval and preset step time of the MCC shard combination;

[0169] Based on the prediction interval and the preset step time of the MCC shard combination, an MCC shard combination set is obtained.

[0170] In some implementations, the delay estimation module 702 performs delay estimation based on the parameters of the MCC slice combination through a delay estimation model to obtain a period average delay of each link; and is used to:

[0171] Based on the platform-related hardware parameters and the parameters of the MCC slice combination, obtain the total delay of success during the wake-up period of each link, the maximum number of delay detections expected to be successful during the wake-up period, the total delay of successful round trips during the sleep period, and the maximum number of delay detections expected to be successful during the sleep period;

[0172] Based on the total delay during the wake-up period within the cycle, the expected maximum number of successful delay detections during the wake-up period within the cycle, the total delay of successful round trips during the sleep period within the cycle, and the expected maximum number of successful delay detections during the sleep period within the cycle, the delay is estimated through the delay estimation model to obtain the cycle average delay of each link.

[0173] In some implementations, the platform-related hardware parameters include the channel switching overhead of the platform, and the delay estimation module 702 obtains the maximum number of delay detections expected to be successful during the wake-up period of each link based on the platform-related hardware parameters and the parameters of the MCC slice combination; used to:

[0174] Based on the intra-cycle wake-up time of the link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detection nodes expected to succeed during the intra-cycle wake-up period is obtained.

[0175] In some implementations, the delay estimation module 702 obtains the total delay of the successful wake-up period within the cycle of each link based on the platform-related hardware parameters and the parameters of the MCC slice combination; and is used to:

[0176] Based on the link latency in the current channel and the expected maximum number of successful latency detections during the wake-up period within the cycle, the total latency of successful wake-up during the cycle is obtained.

[0177] In some implementations, when the delay estimation module 702 obtains the maximum number of delay detections expected to succeed during the sleep period of each link in a cycle based on platform-related hardware parameters and parameters of the MCC slice combination, it is used to:

[0178] Based on the peak latency of the link, the channel switching overhead of the platform, and the latency round-trip detection interval, the maximum number of latency detections expected to be successful during the sleep period within the cycle is obtained.

[0179] In some implementations, the delay estimation module 702 obtains the total delay of successful round trips during the sleep period of each link within the cycle based on platform-related hardware parameters and parameters of the MCC slice combination, for:

[0180] Based on the expected maximum number of successful delay detections during the sleep period within the cycle, the peak delay of the link, the delay round-trip detection interval and the penalty delay, the total delay of successful round-trips during the sleep period within the cycle of each link is obtained; among which, the penalty delay.

[0181] In some implementations, the bandwidth estimation module 703 performs bandwidth estimation based on the parameters of the MCC slice combination through the bandwidth estimation model to obtain the bandwidth of each link, and is used to:

[0182] Based on the platform-related hardware parameters and the parameters of the MCC shard combination, obtain the maximum wake-up time per second of each link and the estimated value of the highest throughput that can be achieved in the actual environment;

[0183] Based on the maximum wake-up time per second of each link and the estimated value of the highest throughput that can be achieved in the actual environment, the bandwidth estimation model is used to estimate the bandwidth and obtain the bandwidth of each link.

[0184] In some implementations, the platform-related hardware parameters include the channel switching overhead of the platform. When the bandwidth estimation module 703 obtains the maximum wake-up duration per second of each link based on the platform-related hardware parameters and the parameters of the MCC slice combination, it is used to:

[0185] Based on the maximum number of running cycles per second, the wake-up time of the link within the cycle, and the channel switching overhead of the platform, the maximum wake-up time per second of each link is obtained.

[0186] In some implementations, when the bandwidth estimation module 703 obtains an estimated value of the highest throughput that can be achieved in an actual environment based on platform-related hardware parameters and parameters of the MCC slice combination, it is used to:

[0187] Based on the proportion of the highest throughput in a clean environment within the highest physical transmission rate and the proportion of the highest throughput in the actual environment within the highest throughput in the clean environment, an estimated value of the highest throughput that can be achieved in the actual environment is obtained; wherein the highest throughput in the clean environment refers to the highest actual transmission rate with basically no retransmission after removing the underlying protocol overhead, and the highest throughput in the actual environment refers to the highest actual transmission rate with a certain amount of retransmission after removing the underlying protocol overhead.

[0188] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0189] The performance prediction device of the MCC slices in the embodiment of the present application obtains the two-way estimated delay of the MCC slice combination through the delay estimation model, and obtains the two-way estimated bandwidth of the MCC slice combination through the bandwidth estimation model, thereby realizing the rapid estimation of the performance of the MCC slice combination set, so that more suitable MCC slice combinations in different business scenarios can be efficiently found, while saving time resources and testing human resources.

[0190] Figure 8 1 is a block diagram of an apparatus 1800 for performance prediction of MCC slices according to an exemplary embodiment. For example, the apparatus 1800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0191] Reference Figure 8 , the device 1800 may include one or more of the following components: a processing component 1802 , a memory 1804 , a power component 1806 , a multimedia component 1808 , an audio component 1810 , an input / output (I / O) interface 1812 , a sensor component 1814 , and a communication component 1816 .

[0192] The processing component 1802 generally controls the overall operation of the device 1800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1802 may include one or more processors 1820 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 1802 may include one or more modules to facilitate interaction between the processing component 1802 and other components. For example, the processing component 1802 may include a multimedia module to facilitate interaction between the multimedia component 1808 and the processing component 1802.

[0193] The memory 1804 is configured to store various types of data to support operations on the device 1800. Examples of such data include instructions for any application or method operating on the device 1800, contact data, phone book data, messages, pictures, videos, etc. The memory 1804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0194] The power component 1806 provides power to the various components of the device 1800. The power component 1806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device 1800.

[0195] The multimedia component 1808 includes a screen that provides an output interface between the device 1800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1808 includes a front camera and / or a rear camera. When the device 1800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0196] The audio component 1810 is configured to output and / or input audio signals. For example, the audio component 1810 includes a microphone (MIC), and when the device 1800 is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 1804 or sent via the communication component 1816. In some embodiments, the audio component 1810 also includes a speaker for outputting audio signals.

[0197] I / O interface 1812 provides an interface between processing component 1802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0198] The sensor assembly 1814 includes one or more sensors for providing various aspects of the status assessment of the device 1800. For example, the sensor assembly 1814 can detect the open / closed state of the device 1800, the relative positioning of components, such as the display and keypad of the device 1800, the sensor assembly 1814 can also detect the position change of the device 1800 or a component of the device 1800, the presence or absence of user contact with the device 1800, the orientation or acceleration / deceleration of the device 1800, and the temperature change of the device 1800. The sensor assembly 1814 can include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 1814 can also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1814 can also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0199] The communication component 1816 is configured to facilitate wired or wireless communication between the device 1800 and other devices. The device 1800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 1816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0200] In an exemplary embodiment, the device 1800 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to perform the above-mentioned methods.

[0201] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1804 including instructions, and the instructions can be executed by a processor 1820 of the device 1800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0202] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed in this disclosure. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0203] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A performance prediction method for multi-channel parallel MCC slices, characterized in that: include: Acquire an MCC slice combination set, where the MCC slice combination set includes multiple MCC slice combinations, and the MCC slice combination includes multiple links; For each link in the multiple links of each of the MCC slice combinations, based on the parameters of the MCC slice combination, a delay estimation model is used to perform delay estimation to obtain a period average delay of each link; For each link in the multiple links of each MCC slice combination, bandwidth estimation is performed through a bandwidth estimation model based on parameters of the MCC slice combination to obtain a bandwidth of each link.

2. The method according to claim 1, characterized in that The obtaining of the MCC slice combination set includes: Determining a prediction interval and a preset step time of the MCC slice combination; Based on the prediction interval of the MCC slice combination and the preset step time, an MCC slice combination set is acquired.

3. The method according to claim 1, characterized in that The delay estimation based on the parameters of the MCC slice combination is performed through a delay estimation model to obtain the period average delay of each link; including: Based on platform-related hardware parameters and parameters of the MCC slice combination, obtain the total delay of success during the wake-up period of each link, the maximum number of delay detection particles expected to be successful during the wake-up period, the total delay of successful round trips during the sleep period, and the maximum number of delay detection particles expected to be successful during the sleep period; Based on the total delay during the wake-up period within the cycle, the expected maximum number of successful delay detection particles during the wake-up period within the cycle, the total delay of successful round trips during the sleep period within the cycle, and the expected maximum number of successful delay detection particles during the sleep period within the cycle, delay estimation is performed through a delay estimation model to obtain the periodic average delay of each link.

4. The method according to claim 3, characterized in that: The platform-related hardware parameters include the channel switching overhead of the platform, and the parameters based on the platform-related hardware parameters and the MCC slice combination are used to obtain the maximum number of delay detection nodes expected to be successful during the wake-up period within the cycle of each link; including: Based on the intra-cycle wake-up time of the link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detection nodes expected to succeed during the intra-cycle wake-up period is obtained.

5. The method according to claim 4, characterized in that The step of obtaining the total delay of a successful wake-up period within a cycle of each link based on the platform-related hardware parameters and the parameters of the MCC slice combination includes: Based on the delay of the link in the current channel and the maximum number of delay detection nodes expected to be successfully detected during the wake-up period in the cycle, the total delay of success during the wake-up period in the cycle is obtained.

6. The method according to claim 3, characterized in that: The obtaining, based on platform-related hardware parameters and parameters of the MCC slice combination, a maximum number of delay detections expected to be successful during the sleep period within the cycle of each link, includes: Based on the peak delay of the link, the channel switching overhead of the platform, and the delay round-trip detection interval, the maximum number of delay detections expected to be successful during the sleep period within the cycle is obtained.

7. The method according to claim 6, characterized in that The obtaining, based on platform-related hardware parameters and parameters of the MCC slice combination, a total delay of successful round trips during the sleep period within the cycle of each link, comprises: Based on the expected maximum number of successful delay detections during the sleep period within the cycle, the peak delay of the link, the delay round-trip detection interval and the penalty delay, the total delay of successful round-trips during the sleep period within the cycle of each link is obtained; wherein the penalty delay refers to the instantaneous delay increase time caused by the surge in data volume during wake-up from waiting to execution.

8. The method according to claim 1, characterized in that The step of performing bandwidth estimation based on the parameters of the MCC slice combination through a bandwidth estimation model to obtain the bandwidth of each link includes: Based on platform-related hardware parameters and parameters of the MCC shard combination, obtain the maximum wake-up duration per second of each link and an estimated value of the highest throughput that can be achieved in an actual environment; Based on the maximum wake-up duration per second of each link and the estimated value of the highest throughput that can be achieved in the actual environment, bandwidth estimation is performed through a bandwidth estimation model to obtain the bandwidth of each link.

9. The method according to claim 8, characterized in that The platform-related hardware parameters include a channel switching overhead of the platform, and the maximum wake-up duration per second of each link is obtained based on the platform-related hardware parameters and the parameters of the MCC slice combination, including: Based on the maximum number of running cycles per second, the wake-up time of the link within the cycle and the channel switching overhead of the platform, the maximum wake-up duration per second of each link is obtained.

10. The method according to claim 8, characterized in that The obtaining of an estimated value of the highest throughput that can be achieved in an actual environment based on platform-related hardware parameters and the parameters of the MCC shard combination includes: Based on the proportion of the highest throughput in a clean environment within the highest physical transmission rate and the proportion of the highest throughput in the actual environment within the highest throughput in the clean environment, an estimated value of the highest throughput that can be achieved in the actual environment is obtained; wherein the highest throughput in the clean environment refers to the highest actual transmission rate with basically no retransmission after removing the underlying protocol overhead, and the highest throughput in the actual environment refers to the highest actual transmission rate with a certain amount of retransmission after removing the underlying protocol overhead.

11. A performance prediction device for a multi-channel parallel MCC slice combination, characterized in that: include: A slice acquisition module, configured to acquire an MCC slice combination set, wherein the MCC slice combination set includes a plurality of MCC slice combinations, and the MCC slice combination includes a plurality of links; A delay estimation module, configured to perform delay estimation for each link of the multiple links of each MCC slice combination through a delay estimation model based on the parameters of the MCC slice combination to obtain a period average delay of each link; The bandwidth estimation module is used to perform bandwidth estimation on each link of the multiple links of each MCC slice combination through a bandwidth estimation model based on the parameters of the MCC slice combination to obtain the bandwidth of each link.

12. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that: include: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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