Image sensor, analog-to-digital converter and successive approximation register analog-to-digital converter

Abstract

The invention relates to an image sensor, an analog-to-digital converter and a successive approximation register analog-to-digital converter. A system may include an analog-to-digital converter (ADC) including a capacitive digital-to-analog converter (CDAC). A multi-sampling circuit may be used to sample an input signal to the ADC at different times. The multi-sampling circuit may include a sampling capacitor that forms at least part of the CDAC.

Description

Technical Field

[0001] The present disclosure relates generally to systems having analog-to-digital converters (ADCs), and more particularly to ADCs in image sensors or imaging systems. Background Art

[0002] Image sensors are often used in electronic systems or electronic devices to generate image data. In a typical arrangement, the image sensor includes an image sensor array having active image sensor pixels. Based on control signals received along a control path, the active image sensor pixels generate image signals in response to incident light. The generated image signals are read out along a readout path and used to generate one or more image frames that can be used in the electronic system.

[0003] The image signal generated by the pixel is an analog signal converted to digital data by the ADC during a readout operation. To mitigate some types of noise, such as random telegraph signal (RTS) noise, the image sensor may perform correlated multi-sampling (CMS) to sample the signal at multiple points in time and average the samples to reduce the adverse effects or artifacts caused by the noise. Because multiple samples are typically averaged in the digital domain, performing CMS may reduce the frame rate due to the additional ADC conversions required for the multiple samples. Summary of the invention

[0004] According to a first aspect, an image sensor is provided, comprising: an image sensor pixel array; and a pixel readout circuit coupled to the image sensor pixel array, wherein the pixel readout circuit comprises a successive approximation register analog-to-digital converter, and wherein the successive approximation register analog-to-digital converter comprises a correlated multi-sampling circuit.

[0005] According to a second aspect, an analog-to-digital converter is provided, the analog-to-digital converter having an input terminal, the input terminal receiving an analog signal for conversion, the analog-to-digital converter comprising: a capacitive digital-to-analog converter; a comparator, the comparator coupled to the capacitive digital-to-analog converter; a control logic circuit, the control logic circuit coupled to the comparator and the capacitive digital-to-analog converter; and a plurality of sampling switches, each of the plurality of sampling switches coupling the capacitive digital-to-analog converter to the input terminal.

[0006] According to a third aspect, a successive approximation register analog-to-digital converter is provided, the successive approximation register analog-to-digital converter comprising: a capacitive digital-to-analog converter; a comparator, the comparator coupled to the capacitive digital-to-analog converter; a control logic circuit, the control logic circuit coupled to the comparator and the capacitive digital-to-analog converter; and a plurality of coupling capacitors, each of the plurality of coupling capacitors coupling the capacitive digital-to-analog converter to an input terminal of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of an illustrative system with one or more image sensors according to some embodiments.

[0008] Figure 2 is a schematic diagram of an illustrative image sensor circuit according to some embodiments.

[0009] Figure 3 is a schematic diagram of an exemplary analog-to-digital converter circuit according to some implementations.

[0010] Figure 4 is a schematic diagram of an illustrative capacitive digital-to-analog converter circuit for use in an analog-to-digital converter circuit, according to some implementations.

[0011] Figure 5 is a schematic diagram of an illustrative analog-to-digital converter circuit configured to perform correlated multi-sampling according to some embodiments.

[0012] Figure 6 is a schematic diagram of an illustrative correlated multiple sampling circuit integrated with a capacitive digital-to-analog converter circuit, according to some implementations.

[0013] Figure 7 is an illustrative timing diagram for sampling an input signal for correlated multiple sampling according to some implementations. DETAILED DESCRIPTION

[0014] An electronic system and / or device may include one or more image sensors that gather incident light to capture an image. An image sensor may include one or more arrays of image sensor pixels. A pixel in an image sensor may include a photosensitive element, such as a photodiode, that converts incident light into an image signal. An image sensor may have any number (e.g., hundreds or thousands or more) of pixels. A typical image sensor may, for example, have hundreds of thousands or millions of pixels (e.g., several megapixels). An image sensor may include control circuitry (e.g., circuitry for operating image pixels) and readout circuitry for reading out an image signal that corresponds to the charge generated by the photosensitive element.

[0015] Figure 1 is a functional block diagram of an illustrative imaging system, such as an electronic device, that uses an image sensor to capture images. Figure 1The imaging system 10 may be a portable electronic device such as a camera, a cellular telephone, a tablet computer, a webcam, a camcorder, a video surveillance system, an automotive imaging system, a video gaming system with imaging capabilities, an augmented reality and / or virtual reality system, an unmanned aerial system (such as a drone), an industrial system, or any other desired imaging system or device that captures image data.

[0016] Camera module 12 (sometimes referred to as an imaging module) may be used to convert incident light into digital image data. Camera module 12 may include one or more lenses 14 and one or more image sensors 16. When capturing an image, light from a scene may be focused onto each image sensor 16 by one or more lenses 14. Image sensor 16 may include circuitry for converting analog pixel image signals into corresponding digital image data that is provided to storage and processing circuitry 18 via path 15. Path 15 may include a wired communication path containing conductive signal traces, vias, wires, or other conductive structures, and / or may include a wireless communication path implemented using wireless communication circuitry.

[0017] The storage and processing circuitry 18 may include one or more integrated circuits, each of which serves a data storage function and / or a data calculation or processing function. As an example, the one or more integrated circuits may include an image processing circuit (such as a digital signal processor), an application specific integrated circuit, a general purpose processor, a microprocessor, a microcontroller, a storage device (such as a random access memory and a non-volatile memory), and / or other types of integrated circuits having a processor and / or a memory.

[0018] Storage and processing circuitry 18 may be implemented using components separate from the camera module and / or components forming part of the camera module. As one example, storage and processing circuitry 18 may be implemented using circuitry forming part of an integrated circuit that includes image sensor 16 or an integrated circuit within camera module 12. When storage and processing circuitry 18 is included on an integrated circuit different from that of image sensor 16, the integrated circuit having storage and processing circuitry 18 may be stacked or packaged vertically relative to the integrated circuit having image sensor 16.

[0019] Processing circuitry 18 may be used to process and store image data that has been acquired by camera module 12. As examples, an image processing engine on processing circuitry 18, an imaging mode selection engine on processing circuitry 18, and / or other types of processing engines on processing circuitry 18 may process image data captured by camera module 12. If desired, processing circuitry 18 may provide processed image data to external equipment (such as a computer, external display, or other device) using wired and / or wireless communication pathways.

[0020] like Figure 2As shown, image sensor 16 may include a pixel array, such as pixel array 20 including image sensor pixels 22 arranged in rows and columns (sometimes referred to herein as image pixels or pixels). A row of pixels or a column of pixels may sometimes be collectively referred to herein as a row of pixels. Image sensor 16 may include control and processing circuitry 24 (sometimes referred to herein as control circuitry 24) that controls the operation of pixel array 20. Pixel array 20 may include, for example, hundreds or thousands of rows and hundreds or thousands of columns of image sensor pixels 22. If desired, pixel array 20 may be provided with a filter array having multiple visible color filter elements or invisible filter elements (each filter element corresponds to a respective pixel), thereby allowing a single image sensor to sample light of different colors or different wavelength groups.

[0021] Image sensor pixels 22 may be formed in a semiconductor substrate using complementary metal oxide semiconductor (CMOS) technology or charge coupled device (CCD) technology or any other suitable photosensitive device technology. Image sensor pixels 22 may be front side illuminated (FSI) image sensor pixels or back side illuminated (BSI) image sensor pixels.

[0022] Control circuitry 24 may be coupled to pixel control circuitry, such as row control circuitry 26, which includes a row driver that provides control signals to pixel array 20, and may be coupled to pixel readout circuitry, such as column readout and control circuitry 28, which reads out signals from pixel array 20.

[0023] Row control circuitry 26 may receive a row address and / or a signal indicating a row address from control circuitry 24, and supply corresponding row control signals (such as a reset control signal, an anti-blooming control signal, a row selection control signal, a charge transfer control signal, a dual conversion gain control signal, and a readout control signal) to pixels 22 through conductive lines or conductive paths 30 (such as pixel row control paths). Specifically, each pixel row may receive different control signals through corresponding multiple control paths, so that each pixel row is coupled to multiple conductive paths 30. One or more conductive lines or conductive paths 32 (such as pixel column readout paths) may be coupled to each column of pixels 22. Conductive paths 32 may be used to read out image signals from pixels 22 and to supply bias signals (such as bias currents or bias voltages) to pixels 22. As an example, when performing a pixel readout operation, a pixel row in pixel array 20 may be selected using row control circuitry 26, and image signals generated by selected image pixels 22 in the pixel row may be read out along conductive paths 32.

[0024] Column readout circuitry 28 may receive image signals (such as analog pixel values ​​generated by pixels 22) via conductive paths 32. Column readout circuitry 28 may include memory or buffer circuitry for temporarily storing calibration signals (such as reset level signals, reference level signals, and / or other non-image signals) read out from array 20 and for temporarily storing image level signals read out from array 20, amplifier circuitry or multiplier circuitry (such as amplifier circuitry 34 provided per column), analog-to-digital converter (ADC) circuitry (ADC circuitry 36 provided per column), bias circuitry, latch circuitry for selectively enabling or disabling portions of column readout circuitry 28, or other circuitry coupled to one or more columns of pixels in array 20 for operating pixels 22 and / or for reading out image signals from pixels 22.

[0025] Although in Figure 2 In the example of FIG. 3 , amplifier circuit 34 and ADC circuit 36 ​​are shown as being external to readout circuit 28, but this is merely illustrative. Amplifier circuit 34 and ADC circuit 36 ​​may form part of readout circuit 28. If desired, amplifier circuit 34 may be omitted and / or other amplifier circuits may be placed elsewhere in readout circuit 28, such as downstream of ADC circuit 36. Figure 2 In the example of , one or more amplifiers of amplifier circuitry 34 may be configured to receive an analog image signal from image pixel array 20 and amplify the analog image signal. Depending on the application and the configuration of image sensor 16, the analog image signal may include data from a single column of pixels 22, or amplifier circuitry 34 may receive analog image signals from multiple columns of pixels 22. ADC circuitry 36 may receive the (amplified) analog image signal and may perform an analog-to-digital conversion operation on the analog image signal to generate digital image data (sometimes referred to as a digital pixel value or digital pixel data). The digital image data may be transmitted to (other portions of) column control and readout circuitry 28 for processing operations and / or readout operations. Readout circuitry 28 may supply the (processed) digital pixel data from pixels 22 in one or more pixel columns to control and processing circuitry 24 and / or processor 18 ( Figure 1 ) for further processing and / or storage.

[0026] Figure 3 is a schematic diagram of an exemplary analog-to-digital converter (ADC) circuit 36 ​​(sometimes referred to herein as ADC 36) configured to convert an analog input signal Vin into digital output data Dout. As an example, the ADC may be included in an image sensor (such as Figure 2 image sensor 16) or substantially included in Figure 1Although described herein in the context of an image sensor and / or an imaging system, the ADC may be implemented in any other suitable device or system. In the illustrative example of an imaging system, the ADC 36 may receive data from the image pixel array 20 ( Figure 2 ) is an analog signal. ADC 36 may receive an analog image signal as an input analog signal Vin. Input signal Vin may be an analog signal from and / or generated by one or more pixels 22 in image pixel array 22, such as a signal received via column line 32. ADC 36 may convert input analog image signal Vin into digital image data Dout, which may be provided to downstream readout and / or processing circuitry (such as other portions of readout circuitry 28).

[0027] exist Figure 3 In the example of , ADC 36 may be a successive approximation register (SAR) ADC (sometimes referred to as a successive approximation ADC). SAR ADC 36 may use a binary search algorithm implemented using a digital-to-analog converter (DAC) 40, a comparator 42, and a successive approximation register (SAR) control logic 44 in ADC 36 to perform analog-to-digital conversion. As an illustrative example, a configuration is described herein in which a binary-based search or approximation configuration is implemented by SAR ADC 36. If desired, SAR ADC 36 and components therein may generally implement any type of successive approximation or search configuration, including a non-binary-based (i.e., non-radix-2) search or approximation configuration, such as a sub-2radix (sometimes referred to as a sub-radix-2) approximation, to perform analog-to-digital conversion.

[0028] Although in Figure 3 Not explicitly shown in the example of , ADC 36 may also include other components or circuits, such as a clock circuit, a timing control circuit that supplies timing control signals to one or more of the DAC 40, the comparator 42, one or more auto-zero switches coupled between an input terminal and an output terminal of the comparator 42, the SAR control logic 44, switches and / or other components of the ADC 36, and / or other circuits that support analog-to-digital conversion operations performed by ADC 36.

[0029] DAC 40 (sometimes referred to herein as DAC circuit 40) may include a portion to function as a sample and hold circuit for input signal Vin. Specifically, an input terminal of ADC 36 that receives signal Vin may be coupled to DAC 40, or more specifically, to a sample and hold portion of DAC 40, via switch 46. Switch 46 may be activated or placed in a conductive state using control signal Vsamp to sample the voltage of signal Vin onto DAC 40, and may be deactivated or placed in a non-conductive state using control signal Vsamp to hold the sampled voltage of signal Vin at DAC 40.

[0030] DAC 40 may hold (thereby storing) a sampled voltage of signal Vin and use the sampled voltage to generate one or more output voltages Vdac on path 48 for binary or non-binary based search operations. Path 48 may be coupled to a first terminal of comparator 42, such as Figure 3 In order to generate one or more output voltages Vdac based on the voltage of the input signal Vin, the DAC 40 may receive and use one or more reference voltages VREF (such as a first reference voltage and a second reference voltage less than the first reference voltage) and one or more control signals from the SAR control logic circuit 44. A reference voltage terminal supplying a reference voltage VCM (such as a common mode voltage) may be coupled to a second voltage terminal (such as a common mode voltage) of the comparator 42. Figure 3 If desired, reference voltage VCM may be the same as the low reference voltage received by DAC 40.

[0031] The voltage Vdac generated based on the same sampled voltage of the input signal Vin can be compared successively with a reference voltage VCM (such as a reference ground voltage or an offset voltage) using a comparator 42. Each voltage Vdac can be changed successively, allowing a successive approximation to be compared with the reference voltage VCM. Each comparison can further narrow the range of possible digital values ​​of the sampled voltage of the signal Vin, wherein the number of comparisons determines the bit resolution of the digital output of the analog-to-digital conversion.

[0032] Specifically, the comparator 42 may compare the magnitude of each voltage Vdac with the magnitude of the voltage VCM. The output of the comparator 42 may be a signal provided to the SAR control logic 44 (sometimes referred to herein as the SAR control logic circuit 44 or the control logic circuit 44) using a path 50 coupled between the output terminal of the comparator 42 and the control logic circuit 44. The output signal of the comparator 42 may have a value indicating which of the voltages Vdac or VCM is greater (or smaller). As an example, if the voltage Vdac is greater than the voltage VCM, the comparator output signal may be driven to a logic high ("1") level, and if the voltage Vdac is less than the voltage signal VCM, the comparator output signal may be driven to a logic low ("0") level, or vice versa.

[0033] Figure 3 SAR control logic 44 in ADC 36 may include digital logic circuits (such as combinational logic circuits, such as one or more Boolean logic circuits), sequential logic circuits (such as one or more latches or registers), and / or any other suitable components for operating ADC 36 in a desired manner. Specifically, control logic circuit 44 may track the comparison results of comparator 42 and update the control signal provided to DAC 44 along path 52. The updated control signal received by DAC 40 along path 52 may adjust the voltage Vdac output by DAC 42 accordingly. Each comparison operation performed by comparator 42 (based on the corresponding Vdac of the same sampled input voltage) may resolve a single bit of the corresponding digital output of the sampled input voltage, starting with the most significant bit and ending with the least significant bit. After the desired number of bits are resolved for the digital output of the analog-to-digital conversion operation for the appropriate number of comparisons, control logic circuit 44 may output all of the resolved bits at the output terminal of ADC 36 as the entire digital output Dout.

[0034] Figure 3 The configuration of ADC 36 in FIG. 3 is merely illustrative. If necessary, ADC 36 may have other suitable configurations.

[0035] DAC 40 may be implemented using a capacitive DAC (CDAC) including one or more capacitor banks, each of which contains a plurality of capacitors. Figure 4 An exemplary configuration of ADC 36 including capacitive DAC 40 is shown in the example of FIG. Figure 4 As shown, the capacitive DAC 40 may include a plurality of capacitors 60. Figure 4Six exemplary capacitors 60 are shown in the example of FIG, but this is merely exemplary. Capacitive DAC 40 may include any suitable number of capacitors, depending on the desired bit resolution of the digital output of ADC 36. Specifically, each capacitor may be used to resolve a given bit in the digital output of ADC 36. In this way, when a greater number of capacitors are provided, more bits may be resolved, resulting in a higher bit of the digital output.

[0036] exist Figure 4 In the example of , capacitor 60-1 may have a capacitance of 1*C or C, capacitor 60-2 may have a capacitance of 2*C (i.e., the capacitance of capacitor 60-1 times two), capacitor 60-3 may have a capacitance of 4*C (i.e., the capacitance of capacitor 60-1 times four), capacitor 60-4 may have a capacitance of 8*C (i.e., the capacitance of capacitor 60-1 times eight), capacitor 60-5 may have a capacitance of 16*C (i.e., the capacitance of capacitor 60-1 times sixteen), and capacitor 60-6 may have a capacitance of 32*C (i.e., the capacitance of capacitor 60-1 times thirty-two). In this 6-bit configuration, capacitor 60-6 may be used to resolve the most significant bit of the digital output of ADC 36, capacitor 60-5 may be used to resolve the second most significant bit of the digital output of ADC 36, capacitor 60-4 may be used to resolve the third most significant bit of the digital output of ADC 36, and so on. Capacitor 60-1 may be used to resolve the least significant bit of the digital output of ADC 36.

[0037] Figure 4 The example of is merely illustrative, in which the capacitor 60 in the CDAC 40 is implemented with a binary scaling capacitor (e.g., 1*C, 2*C, 4*C, etc.). If desired, the capacitor 60 may have a non-binary scaling capacitor, such as a capacitor that supports a sub-2 radix approximation scheme. As an illustrative example, the CDAC 40 may have one or more capacitors 60, each having a capacitance of 1.1*C, 1.2*C, 1.4*C, 1.9*C, 3.6*C, 6.9*C, and / or 13C to support a sub-2 radix approximation scheme.

[0038] Each capacitor 60 may have a commonly connected first terminal at the top plate, and may have a second terminal at the bottom plate that is independently connected to a first voltage supply terminal (such as voltage supply terminal 66 that supplies reference voltage VREFHI) or a second voltage supply terminal (such as voltage supply terminal 64 that supplies reference voltage VREFLO). If desired, the second terminal of each capacitor 60 may also assume a third state in which it is disconnected from both voltage supply terminals. In a configuration where an additional voltage supply terminal for supplying other reference voltages is provided, the second terminal of each capacitor may be coupled to the additional supply terminal.

[0039] Specifically, the switch circuits 62-1, 62-2, 62-3, 62-4, 62-5, and 62-6 may each include one or more switches that couple the second terminal of the corresponding capacitor 60 to the terminal 66 or the terminal 64 and / or decouple the second terminal of the corresponding capacitor 60 from both the terminals 64 and 66. The SAR control logic circuit 44 may be configured to connect the corresponding path 52 ( Figure 3 ) supplies corresponding control signals to each switch in the switch circuits 62-1, 62-2, 62-3, 62-4, 62-5 and 62-6. Adjustment of these control signals can adjust the output voltage Vdac of the DAC 40 to perform a binary search operation when resolving each bit of the digital output.

[0040] like Figure 4 As shown, the common terminal (at its top plate) of capacitor 60 may be coupled to the inverting terminal of comparator 42 via coupling capacitor 68. An input terminal of ADC 40 that receives an analog signal for analog-to-digital conversion may be coupled to a common terminal between capacitor 68 and each capacitor 60 via switch 46.

[0041] The input voltage Vin may be sampled using switch 46 onto a common terminal of capacitor 60 located between coupling capacitor 68 and capacitor 60. After sampling, ADC 36 may perform a binary search operation in a bit-by-bit manner to generate a digital output Dout for the input voltage Vin. The binary search operation may include multiple iterations of switching switches in switch circuit 62 and comparing the changing DAC output voltage Vdac to a reference voltage VCM.

[0042] In some illustrative configurations described herein as examples, image sensor 16 may perform correlated multi-sampling (CMS) on the image data read out from each pixel 22. For example, performing correlated multi-sampling may reduce undesirable artifacts caused by noise, such as random telegraph signal (RTS) noise. However, performing correlated multi-sampling may generally require periodically sampling and reading out the same image signal (output from a particular pixel or group of pixels) in the time domain and subsequently processing it multiple times by readout circuitry 28. When performing CMS operations in the digital domain, this may undesirably reduce the frame rate because additional ADC conversions are required to convert each sample of the same image signal.

[0043] Therefore, it may be desirable to provide correlated multi-sampling circuitry for image sensor 16 while maintaining high frame rates, minimizing line times, reducing power consumption, and maintaining and / or improving other performance metrics.

[0044] Figure 5An exemplary embodiment of ADC 36 is shown, which is configured to perform analog processing on an input analog signal (such as from pixel 22 ( Figure 2 )'s pixel output signal) is correlated multi-sampling. Figure 5 The ADC 36 in the embodiment may include a comparator 42, a control logic circuit 44, supply voltage terminals 64 and 66, paths 48, 50 and 52, an input terminal of the ADC 36 receiving an input signal Vin, an output terminal of the ADC 36 outputting a digital output Dout, and the previously combined Figure 3 and Figure 4 Other elements described above. These previously described elements may provide Figure 3 and Figure 4 The same functions as described and / or can be combined with Figure 3 and Figure 4 Configure in the same way as described.

[0045] Additionally, ADC 36 may include a plurality of circuit portions 70 (sometimes referred to herein as slices 70) that are each coupled to a same input terminal of ADC 36 that receives input signal Vin. These plurality of circuit portions 70 may collectively form a correlated multi-sampling circuit for ADC 36. Specifically, the correlated multi-sampling circuit may be integrated with a capacitive DAC circuit of ADC 36.

[0046] Although in Figure 5 In the example of FIG. 3 , N circuit portions 70-1, ..., 70-N are shown, but any suitable number of circuit portions 70 may be included in ADC 36. The number of circuit portions 70 may be equal to the number of expected samples of the same input signal taken over time. In other words, for N-sample CMS operation, N circuit portions 70 may be provided in ADC 36.

[0047] The same components may be included in each circuit portion 70. Figure 5 An exemplary configuration of circuit portion 70-N is shown in and explicitly described herein. The other circuit portions 70-(N-1), 70-(N-2), ..., 70-1 may each have the same elements as described in conjunction with circuit portion 70-N, unless otherwise described herein.

[0048] like Figure 5As shown, circuit portion 70-N may include sampling switch 46-N coupling an input terminal of ADC 36 to terminal 72-N. Each of circuit portions 70-N, 70-(N-1), ..., 70-1 may include independently controllable sampling switch 46. In other words, switch 46-N of circuit portion 70-N may receive control signal Vsamp[N], switch 46-(N-1) of circuit portion 70-(N-1) may receive control signal Vsamp[N-1], ..., switch 46-1 of circuit portion 70-1 may receive control signal Vsamp[1].

[0049] Circuit portion 70-N may include a coupling capacitor 68-N coupling terminal 72-N to terminal 76-N. Each of circuit portions 70-N, 70-(N-1), ..., 70-1 may include different coupling capacitors 68 (instances). In order to maintain the uniformity of circuit portions 70-N, 70-(N-1), ..., 70-1, different coupling capacitors 68 may be configured to have the same capacitance. If necessary, one or more coupling capacitors may have a capacitance different from the capacitance of one or more other coupling capacitors. Circuit portion output terminal 76 may be a common or shared terminal. In other words, terminals 76-N, 76-(N-1), ..., 76-1 may be electrically connected or short-circuited to each other. The common terminal 76 may be coupled to the inverting terminal of comparator 42 via path 48.

[0050] Circuit portion 70-N may include sampling capacitor 60-N coupling terminal 72-N to terminal 74-N. Each of circuit portions 70-N, 70-(N-1), ..., 70-1 may include a different (instance of) sampling capacitor 60. To maintain uniformity of circuit portions 70-N, 70-(N-1), ..., 70-1, different sampling capacitors 60 may be configured to have the same capacitance. If desired, one or more sampling capacitors may have a capacitance that is different from the capacitance of one or more other sampling capacitors.

[0051] The sampling capacitors 60-N, 60-(N-1), . . . , 60-1 used to perform CMS may use the same capacitors (such as Figure 4 The sampling capacitors 60-N, 60-(N-1), ..., 60-1 can each store a corresponding sample (sampled voltage) of the same input signal during a sampling operation of the ADC 36. Specifically, the terminals 72-N, 72-(N-1), ..., 72-1 can store N different samples of the same input signal taken at different times. The charge sharing CMS operation can occur on the terminals 72-N, 72-(N-1), ..., 72-1, for example, via capacitive coupling with the common output terminal 76.

[0052] The sampling capacitors 60-N, 60-(N-1), ..., 60-1 may then be used to perform a binary search operation as part of the capacitive DAC circuit of the ADC 36. Thus, the switch circuit 62 including one or more switches may be used in combination with Figure 4 The described approach couples each sampling capacitor 60 to either voltage supply terminal 64 or voltage supply terminal 66 , or decouples each sampling capacitor 60 from both voltage supply terminals to perform a binary search operation.

[0053] As an example with respect to circuit portion 70-N, terminal 74-N may be coupled to voltage supply terminal 66 supplying reference voltage VREFHI via switch 62-NA, and may be coupled to voltage supply terminal 64 supplying reference voltage VREFLO via switch 62-NB. Switch circuit 62 including switches 62-NA and 62NB may be controlled by a control signal received from control logic circuit 44 via path 52. The control signal received by switch 62-NA may be an inverted version of the control signal received by switch 62-NA, so that at most only one of voltage terminals 64 and 66 is connected to capacitor 60-N. Circuit portions 70-N, 70-(N-1), ..., 70-1 may include different (instances of) switch circuit 62 that couple corresponding sampling capacitor 60 to terminals 64 and 66. As an example, switch circuit 62 of each circuit portion 70 may include two switches that receive corresponding control signals from control logic circuit 44 via path 52. If desired, any suitable number of switches may be used to perform the switching function of switch circuit 62.

[0054] The state of the switch circuit 62 of each circuit portion 70 may be switched during a binary search operation that occurs following correlated multiple sampling of the same input analog signal to generate different DAC output voltages Vdac for comparison at the comparator 42. Each comparison result output by the comparator 42 along the path 50 is used to inform the state of the switch circuit 62 of each circuit portion 70 to generate a subsequent value of the voltage Vdac for subsequent comparison at the comparator 42.

[0055] Combined with Figure 5By configuring in the manner described, a correlated multi-sampling (CMS) circuit can be integrated into the ADC 36. Specifically, the CMS circuit can be integrated into the capacitive DAC circuit without affecting the binary search operation. In addition, the ADC 36 can utilize charge sharing to perform the CMS operation, which eliminates the need to perform a separate ADC conversion operation for each sample, thereby reducing the readout time or line time, increasing the frame rate and reducing power consumption. In addition, the CMS operation performed by the ADC 36 can mitigate noise artifacts attributable to any noise source preceding the capacitive DAC circuit in the ADC 36, such as those attributable to preceding amplifiers and / or buffer circuits.

[0056] Figure 6 is a schematic diagram of eight illustrative circuit portions 70 (sometimes referred to as 8-sample CMS circuits) integrated into the capacitive DAC circuit of the 6-bit SAR ADC 36 . Figure 6 The exemplary circuit portions 70-8, 70-7, ..., 70-1 shown may be implemented as Figure 5 Circuit parts 70-N, ..., 70-1 in.

[0057] like Figure 6 As shown, the capacitive DAC circuit 40 may include a plurality of capacitors 60 that also serve as sampling capacitors for the CMS circuit. Although the capacitors of the DAC circuit 40 may desirably have distinct capacitances (e.g., Figure 4 ), it may be desirable to have a more uniform capacitance distribution for the sampling capacitors of different circuit portions 70 of the CMS circuit. Thus, some of the capacitors 60 in the DAC circuit 40 may be combined to implement the sampling capacitors for a given circuit portion 70 of the CMS circuit, while one or more of the capacitors 60 in the DAC circuit 40 may be split or implemented as multiple parallel capacitors to implement multiple sampling capacitors for multiple circuit portions 70 of the CMS circuit.

[0058] exist Figure 6 In the example of FIG. 1 , circuit portion 70-1 of the CMS circuit may include a sampling capacitor formed using multiple capacitors of DAC circuit 40, such as capacitor 60-1 having a capacitance of 1*C, capacitor 60-2 having a capacitance of 2*C, and capacitor 60-3 having a capacitance of 4*C. Thus, the effective or combined capacitance of the sampling capacitors for circuit portion 70-1 of the CMS circuit may be 7*C. Circuit portion 70-2 of the CMS circuit may include a sampling capacitor formed using a single capacitor of DAC circuit 40, such as capacitor 60-4 having a capacitance of 8*C.

[0059] exist Figure 6 In the example, combined with Figure 4The exemplary capacitor 60-5 depicted as having a capacitance of 16*C may be split into parallel coupled capacitors 60-5A and 60-5B, each having a capacitance of 8*C. Circuit portion 70-3 of the CMS circuit may include a sampling capacitor formed using a single split capacitor of the DAC circuit 40, such as capacitor 60-5A having a capacitance of 8*C. Circuit portion 70-4 of the CMS circuit may include a sampling capacitor formed using a single split capacitor of the DAC circuit 40, such as capacitor 60-5B having a capacitance of 8*C.

[0060] exist Figure 6 In the example, combined with Figure 4 The exemplary capacitor 60-6 described with a capacitance of 32*C may be split into parallel coupled capacitors 60-5A, 60-6B, 60-6C, and 60-6D, each having a capacitance of 8*C. Circuit portion 70-5 of the CMS circuit may include a sampling capacitor formed using a single split capacitor of the DAC circuit 40, such as capacitor 60-6A having a capacitance of 8*C. Circuit portion 70-6 of the CMS circuit may include a sampling capacitor formed using a single split capacitor of the DAC circuit 40, such as capacitor 60-6B having a capacitance of 8*C. Circuit portion 70-7 of the CMS circuit may include a sampling capacitor formed using a single split capacitor of the DAC circuit 40, such as capacitor 60-6C having a capacitance of 8*C. Circuit portion 70-8 of the CMS circuit may include a sampling capacitor formed using a single split capacitor of the DAC circuit 40, such as capacitor 60-6D having a capacitance of 8*C.

[0061] Configured in this manner (eg, by splitting and / or combining capacitors), the capacitors in DAC circuit 40 may more effectively form sampling capacitors for the CMS circuit. Figure 6 In the example of , the relative weights of each sample of the input analog signal applied to circuit portions 70-8, 70-7, 70-6, 70-5, 70-4, 70-3, 70-2, and 70-1 are 8, 8, 8, 8, 8, 8, and 7, respectively. Other suitable weights may be applied to one or more samples if desired. In particular, a more uneven set of weights or a completely uniform set of weights may be used by including additional sampling capacitors of the CMS circuit that are not part of DAC circuit 40 and / or by not using one or more capacitors of DAC circuit 40.

[0062] Although Figure 6 The capacitor scaling configuration shown in FIG. 1 is more similar to a binary capacitance scaling scheme (eg, corresponding to Figure 4 ), but this is for illustration only. In general, you can adjust Figure 6The capacitance scaling configuration of capacitor 60 in and the corresponding split capacitance may be used to implement any suitable capacitance scaling scheme, such as a capacitance scaling scheme that supports sub-2 radix approximation operations or generally other non-binary based approximation operations.

[0063] The sampling switch 46-8 can be controlled by the control signal Vsamp[8] to sample the input voltage for the pixel output signal onto the terminal 72-8 at a first time. The sampling switch 46-7 can be controlled by the control signal Vsamp[7] to sample the input voltage for the same pixel output signal onto the terminal 72-7 at a second time. The sampling switch 46-6 can be controlled by the control signal Vsamp[6] to sample the input voltage for the same pixel output signal onto the terminal 72-6 at a third time. The sampling switch 46-5 can be controlled by the control signal Vsamp[5] to sample the input voltage for the same pixel output signal onto the terminal 72-5 at a fourth time. The sampling switch 46-4 can be controlled by the control signal Vsamp[4] to sample the input voltage for the same pixel output signal onto the terminal 72-4 at a fifth time. The sampling switch 46-3 can be controlled by the control signal Vsamp[3] to sample the input voltage for the same pixel output signal onto the terminal 72-3 at a sixth time. Sampling switch 46-2 may be controlled by control signal Vsamp[2] to sample the input voltage of the same pixel output signal onto terminal 72-2 at a seventh time. Sampling switch 46-1 may be controlled by control signal Vsamp[1] to sample the input voltage of the same pixel output signal onto terminal 72-1 at an eighth time. Samples of the same input signal taken at different times may capture temporal variations, such as those caused by noise and / or attributable to undesirable artifacts. The charge sharing CMS operation performed at ADC 36 using these eight samples may reduce the effects of these temporal variations.

[0064] Figure 7 is an exemplary timing diagram showing how control signals Vsamp[8], Vsamp[7], Vsamp[6], Vsamp[5], Vsamp[4], Vsamp[3], Vsamp[2], and Vsamp[1] may be successively de-asserted to sample the same pixel output signal at different times. Figure 7 In the example of , corresponding switches 46 controlled by the control signal may all be activated at time t0 to electrically connect the same input terminal of ADC 36 to the corresponding terminal 72. At the falling edge of each control signal, the corresponding switch 46 controlled by the control signal may be deactivated, causing the sample to be held or stored at the disconnected terminal 72. In this way, ADC 36 may obtain multiple samples of the same input analog signal.

[0065] After the last control signal Vsamp[1] is disabled, the ADC 36 may perform a binary search operation to iteratively resolve each bit of the digital output corresponding to the input analog signal. Figure 6 , the control signal from the control logic 44 can be used to selectively control the switch circuits 62-6, 62-5, 62-4, 62-3, 62-2 and 62-1 to connect the capacitors 60-6, 60-5, 60-4, 60-3, 60-2 and 60-1 to the voltage terminal 64 or the voltage terminal 64, thereby combining Figure 4 and Figure 6 The described approach performs a binary search operation.

[0066] Various embodiments of exemplary ADC circuits and imaging systems containing ADC circuits have been described.

[0067] As a first example, an image sensor may include: an image sensor pixel array; and a pixel readout circuit coupled to the image sensor pixel array. The pixel readout circuit may include a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may include a correlated multi-sampling (CMS) circuit. The SAR ADC may include a capacitive digital-to-analog converter (CDAC). The CMS circuit may include a plurality of sampling switches coupling an input terminal of the SAR ADC to the CDAC. The CDAC may include a plurality of capacitors. Each of the plurality of sampling switches may couple an input terminal of the SAR ADC to at least one of the plurality of capacitors.

[0068] In some exemplary configurations described herein, in addition to the CDAC having a capacitor bank, the SAR ADC may also include a comparator coupled to the DAC and a control logic circuit coupled to the DAC. The CMS circuit may be formed at least in part using the capacitor bank of the DAC. The CMS circuit may include a plurality of coupling capacitors that couple the capacitor bank to the comparator. The CMS circuit may include a plurality of sampling switches that couple the input terminal of the SAR ADC to the capacitor bank. The plurality of coupling capacitors may be coupled to a first input terminal of the comparator, and a voltage terminal that supplies a reference voltage may be coupled to a second input terminal of the comparator. The digital-to-analog converter may include a switch circuit that couples the capacitor bank to a first voltage terminal that supplies a first reference voltage and a second voltage terminal that supplies a second reference voltage. The control logic circuit may be configured to provide a control signal to the switch circuit. The control logic circuit may be coupled to an output terminal of the comparator, and may be configured to generate a control signal based on a comparator output signal on the output terminal of the comparator. The control logic circuit may be configured to generate a digital output at the output terminal of the SAR ADC.

[0069] As a second example, an analog-to-digital converter (ADC) may have an input terminal for receiving an analog signal for analog-to-digital conversion. The ADC may include a capacitive digital-to-analog converter (CDAC), a comparator coupled to the CDAC, a control logic circuit coupled to the comparator and the CDAC, and a plurality of sampling switches each coupling the CDAC to an input terminal of the ADC. The capacitive digital-to-analog converter may include a capacitor bank having a plurality of capacitors. Each of the plurality of sampling switches may be coupled to at least one of the plurality of capacitors. The capacitive digital-to-analog converter may include a switching circuit that couples the capacitor bank to a first voltage terminal for supplying a first reference voltage and a second voltage terminal for supplying a second reference voltage. Each of the plurality of sampling switches is coupled to an input terminal of the comparator via a corresponding coupling capacitor. The coupling capacitors that couple the plurality of sampling switches to the input terminal of the comparator may have the same capacitance. The input terminal of the comparator may be an inverting terminal of the comparator, and the non-inverting terminal of the comparator may be coupled to a voltage terminal for supplying a reference voltage.

[0070] As a third example, a successive approximation register analog-to-digital converter (SAR ADC) may include a capacitive digital-to-analog converter (CDAC), a comparator coupled to the CDAC, a control logic circuit coupled to the comparator and the CDAC, and a plurality of coupling capacitors each coupling the CDAC to an input terminal of the comparator. The CDAC may include a capacitor bank having a first capacitor and a second capacitor having the same capacitance. A first coupling capacitor of the plurality of coupling capacitors may be coupled to the first capacitor. A second coupling capacitor of the plurality of coupling capacitors may be coupled to the second capacitor. The SAR ADC may also include a plurality of sampling switches, each sampling switch coupling an input terminal of the SAR ADC to a corresponding coupling capacitor of the plurality of coupling capacitors. A first sampling switch of the plurality of sampling switches may be coupled to the first capacitor. A second sampling switch of the plurality of sampling switches may be coupled to the second capacitor.

[0071] Those skilled in the art will appreciate that exemplary embodiments of the present invention may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the present invention.

[0072] The above contents are merely exemplary, and various modifications may be made to the described embodiments. The above embodiments may be implemented individually or in any combination.

Claims

1. An image sensor, comprising: Image sensor pixel array; and A pixel readout circuit is coupled to the image sensor pixel array, wherein the pixel readout circuit includes a successive approximation register analog-to-digital converter, and wherein the successive approximation register analog-to-digital converter includes a correlated multi-sampling circuit.

2. The image sensor of claim 1 , wherein the SAR ADC comprises a capacitive DAC, and the CMS circuit comprises a plurality of sampling switches coupling an input terminal of the SAR ADC to the capacitive DAC.

3. The image sensor of claim 2 , wherein the capacitive digital-to-analog converter comprises a plurality of capacitors, and wherein each of the plurality of sampling switches couples the input terminal of the successive approximation register analog-to-digital converter to at least one of the plurality of capacitors.

4. The image sensor of claim 1 , wherein the successive approximation register analog-to-digital converter comprises a digital-to-analog converter having a capacitor bank, a comparator coupled to the digital-to-analog converter, and a control logic circuit coupled to the digital-to-analog converter, and wherein the correlated multi-sampling circuit is at least partially formed using the capacitor bank of the digital-to-analog converter. 5 . The image sensor of claim 4 , wherein the correlated multi-sampling circuit comprises a plurality of coupling capacitors coupling the capacitor bank to the comparator. 6 . The image sensor of claim 5 , wherein the correlated multi-sampling circuit comprises a plurality of sampling switches coupling an input terminal of the successive approximation register analog-to-digital converter to the capacitor bank. 7 . The image sensor according to claim 5 , wherein the plurality of coupling capacitors are coupled to a first input terminal of the comparator, and wherein a voltage terminal supplying a reference voltage is coupled to a second input terminal of the comparator.

8. The image sensor of claim 5, wherein the digital-to-analog converter comprises a switching circuit that couples the capacitor group to a first voltage terminal that supplies a first reference voltage and to a second voltage terminal that supplies a second reference voltage, and wherein the control logic circuit is configured to provide a control signal to the switching circuit. 9 . The image sensor of claim 8 , wherein the control logic circuit is coupled to an output terminal of the comparator and is configured to generate the control signal based on a comparator output signal at the output terminal of the comparator. 10 . The image sensor of claim 9 , wherein the control logic circuit is configured to generate a digital output at the output terminal of the successive approximation register analog-to-digital converter.

11. An analog-to-digital converter, the analog-to-digital converter having an input terminal, the input terminal receiving an analog signal for conversion, the analog-to-digital converter comprising: Capacitive digital-to-analog converter; a comparator coupled to the capacitive digital-to-analog converter; a control logic circuit coupled to the comparator and the capacitive digital-to-analog converter; and A plurality of sampling switches each couples the capacitive digital-to-analog converter to the input terminal.

12. The analog-to-digital converter of claim 11, wherein the capacitive digital-to-analog converter comprises a capacitor bank having a plurality of capacitors, and wherein each sampling switch of the plurality of sampling switches is coupled to at least one capacitor of the plurality of capacitors. 13 . The analog-to-digital converter of claim 12 , wherein the capacitive digital-to-analog converter comprises a switch circuit that couples the capacitor group to a first voltage terminal that supplies a first reference voltage and a second voltage terminal that supplies a second reference voltage. 14 . The analog-to-digital converter of claim 11 , wherein each sampling switch of the plurality of sampling switches is coupled to an input terminal of the comparator via a corresponding coupling capacitor. 15 . The analog-to-digital converter of claim 14 , wherein the coupling capacitors coupling the plurality of sampling switches to the input terminals of the comparators have the same capacitance. 16 . The analog-to-digital converter according to claim 15 , wherein the input terminal of the comparator is an inverting terminal of the comparator, and wherein a non-inverting terminal of the comparator is coupled to a voltage terminal supplying a reference voltage.

17. A successive approximation register analog-to-digital converter, the successive approximation register analog-to-digital converter comprising: Capacitive digital-to-analog converter; a comparator coupled to the capacitive digital-to-analog converter; a control logic circuit coupled to the comparator and the capacitive digital-to-analog converter; and A plurality of coupling capacitors each couple the capacitive digital-to-analog converter to an input terminal of the comparator.

18. The successive approximation register analog-to-digital converter of claim 17 , wherein the capacitive digital-to-analog converter comprises a capacitor group having a first capacitor and a second capacitor having the same capacitance, wherein a first coupling capacitor of the plurality of coupling capacitors is coupled to the first capacitor, and wherein a second coupling capacitor of the plurality of coupling capacitors is coupled to the second capacitor.

19. The successive approximation register analog-to-digital converter according to claim 18, further comprising: A plurality of sampling switches each couples an input terminal of the successive approximation register analog-to-digital converter to a corresponding coupling capacitor of the plurality of coupling capacitors. 20 . The successive approximation register analog-to-digital converter of claim 19 , wherein a first sampling switch of the plurality of sampling switches is coupled to the first capacitor, and wherein a second sampling switch of the plurality of sampling switches is coupled to the second capacitor.

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