Layout pattern of static random access memory

Abstract

A layout pattern of a static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions and a plurality of gate structures on the substrate. Each diffusion region includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region. Each gate structure spans the plurality of diffusion regions to form a plurality of transistors. The plurality of gates includes a first gate. The first gate includes a first L-shaped portion. The first L-shaped portion spans the first diffusion region and the fifth diffusion region to form a first pull-down transistor (PD1). The first diffusion region and the fifth diffusion region are adjacent and directly contact each other.

Description

TECHNICAL FIELD

[0001] The present application relates to a static random access memory (SRAM), and more particularly, to a static random access memory (SRAM) layout pattern with body contact. BACKGROUND

[0002] In an embedded static random access memory (embedded SRAM), there is a logic circuit and a static random access memory connected to the logic circuit. The static random access memory itself is a kind of volatile memory cell, that is, when the power supplied to the static random access memory disappears, the stored data will be erased at the same time. The static random access memory stores data by using the conduction state of the transistor in the memory cell. The design of the static random access memory is based on the intercoupling transistor, there is no problem of capacitor discharge, it does not need to be charged constantly to keep the data from being lost, that is, it does not need to make memory update action, which is different from the dynamic random access memory (DRAM) which is also a kind of volatile memory, which stores data by using the charged state of the capacitor. The access speed of the static random access memory is quite fast, so it is used as cache memory and the like in computer systems. SUMMARY

[0003] A layout pattern of a static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions located on the substrate, each diffusion region including a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region, and an eighth diffusion region, each diffusion region arranged along a first direction (Y direction), a plurality of gate structures located on the substrate, each gate structure extending along a second direction (X direction) and crossing the plurality of diffusion regions to form a plurality of transistors, wherein the plurality of transistors include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first access transistor PG1, and a second access transistor PG2, wherein the plurality of gate structures include a first gate structure, wherein the first gate structure includes a first L-shaped portion, the first L-shaped portion crossing the first diffusion region and the fifth diffusion region and forming the first pull-down transistor PD1, wherein the first diffusion region and the fifth diffusion region are adjacent to and directly contact each other.

[0004] The present application features an improved layout pattern of a static random-access memory (SRAM), wherein some additional diffusion regions are located adjacent to the original diffusion regions, the additional diffusion regions have a conductive type opposite to that of the original diffusion regions, and the gate structures are designed in an L shape or a T shape (as viewed from the top). In this way, the charges accumulated under the gate structures can be discharged through the diffusion regions and then released through the contact structures, so as to avoid affecting the electrical properties of the transistors and improve the product yield. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 A circuit diagram of an SRAM cell;

[0006] Figure 2 A layout pattern of a static random-access memory (SRAM) cell;

[0007] Figure 3 A cross-sectional structure of a transistor;

[0008] Figure 4 A layout pattern of a static random-access memory (SRAM) cell according to a first preferred embodiment of the present application;

[0009] Figure 5 A layout pattern of a static random-access memory (SRAM) cell according to a second preferred embodiment of the present application; Figure 4 An enlarged schematic view of a gate structure G1 and the surrounding area;

[0010] Figure 6 A layout pattern of a static random-access memory (SRAM) cell according to a second preferred embodiment of the present application;

[0011] Figure 7Layout of a static random access memory (SRAM) cell according to a third preferred embodiment of the invention;

[0012] Figure 8 According to Figure 7 Enlarged schematic view of the middle gate structure G2 and the surrounding area;

[0013] Figure 9 Layout of a static random access memory (SRAM) cell according to a fourth preferred embodiment of the invention;

[0014] Figure 10 Layout of a static random access memory (SRAM) cell according to a fifth preferred embodiment of the invention;

[0015] Figure 11 Layout of a static random access memory (SRAM) cell according to a sixth preferred embodiment of the invention.

[0016] Legend

[0017] 10: static random access memory cell

[0018] 12: substrate

[0019] 12A: silicon layer

[0020] 12B: insulating layer

[0021] 12C: silicon layer

[0022] 14: gate dielectric layer

[0023] 16: depletion region

[0024] 18: region

[0025] 19: shallow trench isolation

[0026] 20: base contact

[0027] 22: base contact

[0028] 24: base contact

[0029] D: diffusion region

[0030] D1: diffusion region (first diffusion region)

[0031] D2: diffusion region (second diffusion region)

[0032] D3: diffusion region (third diffusion region)

[0033] D4: diffusion region (fourth diffusion region)

[0034] D5: diffusion region (fifth diffusion region)

[0035] D6: diffusion region (sixth diffusion region)

[0036] D7: diffusion region (seventh diffusion region)

[0037] D8: diffusion region (eighth diffusion region)

[0038] G: gate structure

[0039] G1: gate structure (first gate)

[0040] G2: gate structure (second gate)

[0041] G3: gate structure (third gate)

[0042] G4: gate structure (fourth gate)

[0043] G2A: long side portion

[0044] G2B: short side portion

[0045] Sr: source

[0046] Dr: drain

[0047] O: center point

[0048] R: region

[0049] R1: region

[0050] P1: first L-shaped portion

[0051] P1A: long side portion

[0052] P1B: short side portion

[0053] P2: second L-shaped portion

[0054] P2A: long side portion

[0055] P2B: short side portion

[0056] V: contact pillar DETAILED DESCRIPTION

[0057] In order to enable the person skilled in the art to further understand the present application, the preferred embodiments of the present application are listed below, and the constitution and effects of the present application are described in detail with the help of the accompanying drawings.

[0058] For the convenience of explanation, the drawings of the present application are only schematic and are non-detailed in scale so as to facilitate the understanding of the present application. The relative positions of the elements in the drawings described in the present application are intended to mean the relative positions of the objects, and thus can be reversed to present the same components, which should all be within the scope of the present application.

[0059] The present application provides a layout pattern of an embedded static random access memory (embedded SRAM). Please refer to Figure 1 , Figure 1 A circuit diagram of an SRAM cell is shown. In the present embodiment, an SRAM cell 10 is preferably composed of a first pull-up device PU1, a second pull-up device PU2, a first pull-down device PD1, a second pull-down device PD2, a first pass gate device PG1, and a second pass gate device PG2 to form a flip-flop, wherein the first pull-up device PU1 and the second pull-up device PU2, the first pull-down device PD1 and the second pull-down device PD2 form a latch so that data can be latched at a storage node N1 or N2. In addition, the first pull-up device PU1 and the second pull-up device PU2 are used as active loads, which can also be replaced by general resistors as pull-up devices, in which case it is a four-device SRAM (4T-SRAM). In the present embodiment, a source region of each of the first pull-up device PU1 and the second pull-up device PU2 is electrically connected to a voltage source Vcc, and a source region of each of the first pull-down device PD1 and the second pull-down device PD2 is electrically connected to a voltage source Vss.

[0060] In an embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 of the SRAM cell 10 are composed of P-type metal oxide semiconductor (PMOS) transistors, and the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1 and the second access transistor PG2 are composed of N-type metal oxide semiconductor (NMOS) transistors, but the present application is not limited thereto. The first pull-up transistor PU1 and the first pull-down transistor PD1 together form an inverter, and the series connection of the first pull-up transistor PU1 and the first pull-down transistor PD1 has two ends coupled to a voltage source Vcc and a voltage source Vss, respectively. Similarly, the second pull-up transistor PU2 and the second pull-down transistor PD2 form another inverter, and the series connection of the second pull-up transistor PU2 and the second pull-down transistor PD2 also has two ends coupled to the voltage source Vcc and the voltage source Vss, respectively. The two inverters are coupled to each other to store data.

[0061] In addition, at the storage node N1, the gates of the second pull-down transistor PD2 and the second pull-up transistor PU2 and the drain of the first pull-down transistor PD1, the first pull-up transistor PU1 and the first access transistor PG1 are electrically connected, respectively. Similarly, at the storage node N2, the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1 and the drain of the second pull-down transistor PD2, the second pull-up transistor PU2 and the second access transistor PG2 are electrically connected, respectively. The gates of the first access transistor PG1 and the second access transistor PG2 are coupled to a word line (Word Line) WL, respectively, and the sources of the first access transistor PG1 and the second access transistor PG2 are coupled to corresponding bit lines (Bit Line) BL1 and BL2, respectively.

[0062] The SRAM cell 10 described above includes six transistors, and thus can also be referred to as a six-transistor static random access memory (6T-SRAM). However, the SRAM cell of the present application is not limited to using a 6T-SRAM, and other SRAM patterns with more transistors, such as an 8T-SRAM and a 10T-SRAM, can also be used as the SRAM cell of the present application. In addition, the above-described transistors can also include other combinations of P-type transistors and N-type transistors.

[0063] Figure 2This is a layout diagram of a static random access memory (SRAM) cell. In this embodiment, the static random access memory cell 10 is located in a region R and disposed on a substrate 12, such as a silicon-on-insulator (SOI) substrate. The substrate 12 has multiple diffusion regions D arranged in parallel with each other, and each diffusion region D is surrounded by a shallow trench isolation (not shown).

[0064] Furthermore, the substrate 12 includes a plurality of gate structures G, and each of the above transistors (including the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, and the second access transistor PG2) includes a gate structure G that spans over at least one diffusion region D and constitutes each transistor.

[0065] like Figure 2 As shown, to clearly define the positions of each gate structure G and diffusion region D, the gate structure G is divided into gate structure G1, gate structure G2, gate structure G3, and gate structure G4, and the diffusion region D is also divided into diffusion region D1, diffusion region D2, diffusion region D3, and diffusion region D4. Gate structure G1 spans diffusion region D2 to form pull-up transistor PU1; gate structure G1 spans diffusion region D1 to form pull-down transistor PD1; gate structure G2 spans diffusion region D1 to form access transistor PG1; gate structure G3 spans diffusion region D3 to form pull-up transistor PU2; gate structure G3 spans diffusion region D4 to form pull-down transistor PD2; and gate structure G4 spans diffusion region D4 to form access transistor PG2. It can be understood that gate structures G1, G2, G3, and G4 all belong to gate structure G, while diffusion regions D1, D2, D3, and D4 all belong to diffusion region D.

[0066] In this invention, the diffusion regions D1, D2, D3, and D4 are preferably arranged along a first direction (e.g., the Y-axis direction), while the gate structures G1, G2, G3, and G4 are elongated structures, all arranged along a second direction (e.g., the X-axis direction). Preferably, the first direction and the second direction are perpendicular to each other.

[0067] Within region R, there are also multiple metal layers (not shown) and contact pillars V. These metal layers and contact pillars V are primarily used to electrically connect transistors to other components, such as word lines, bit lines, voltage sources, or to connect memory nodes as an interconnect structure for transistors. The metal layers and contact pillars V are made of, for example, metal, and may have the same material. For the sake of brevity in the accompanying drawings, Figure 2 The location of the metal layer is not shown in the image, but for clarity, it is included here. Figure 2 The diagram clearly shows the connections between each component, including transistors, memory nodes, word lines, bit lines, and voltage sources.

[0068] In addition, in Figure 2 the embodiments, since the first pull-down transistor PD1, the second pull-down transistor PD2 and the first access transistor PG1, the second access transistor PG2 are composed of N-type metal oxide semiconductor transistors, the diffusion regions D across which are also N-type doped diffusion regions. In contrast, since the first pull-up transistor PU1, the second pull-up transistor PU2 are composed of P-type metal oxide semiconductor transistors, the diffusion regions D across which are also P-type doped diffusion regions. That is, as shown in Figure 2 , the diffusion region D1 and the diffusion region D4 are N-type diffusion regions, and the diffusion region D2 and the diffusion region D3 are P-type diffusion regions. In Figure 2 , the N-type doped regions are denoted by "N+", and the P-type doped regions are denoted by "P+".

[0069] Applicants have found that when a transistor is formed on a silicon-on-insulator (SOI) substrate, some charges can accumulate under the gate structure and be trapped, and cause electrical instability. In more detail, Figure 3 a cross-sectional structure of a transistor is shown. As shown in Figure 3 , the substrate 12 is an SOI substrate, which includes a silicon layer 12A, an insulating layer 12B and a silicon layer 12C stacked from bottom to top, a gate structure G is located on the substrate 12, and the gate structure G and the substrate 12 include a gate dielectric layer 14 therebetween, the source Sr and the drain Dr are respectively included in the substrate on both sides of the gate structure, and a shallow trench isolation (STI) 19 is located outside the source Sr and the drain Dr. A depletion region 16 is included under the gate structure G and between the source Sr and the drain Dr. However, a region 18 is located between the depletion region 16 and the insulating layer 12B under the depletion region 16, and some charges can accumulate in the region 18, but the charges cannot be discharged from the region 18, and the charges accumulated in the region 18 can affect the electrical properties of the transistor.

[0070] To solve the above problems, the present application provides several improved layout patterns of static random access memories, by adding a part of diffusion regions and changing the shape of the gate structure, so that the charges accumulated under the gate structure can be released, thus avoiding the problem of the above-mentioned charge accumulation under the gate structure. For more details, please refer to the following paragraphs.

[0071] Figure 4 A layout diagram of a static random access memory (SRAM) cell of a first preferred embodiment of the present application is shown. As shown in Figure 4 , and Figure 2The embodiment shown in the figure is different from the above-mentioned embodiment. More specifically, Figure 2 The embodiment shown in the figure is different from the above-mentioned embodiment. More specifically, Figure 5 The embodiment shown in the figure is different from the above-mentioned embodiment. More specifically, Figure 4 The embodiment shown in the figure is different from the above-mentioned embodiment. More specifically, Figure 5 The embodiment shown in the figure is different from the above-mentioned embodiment. More specifically, Figure 5 The embodiment shown in the figure is different from the above-mentioned embodiment. More specifically,

[0072] In the embodiment, the diffusion regions D5-D8 are respectively located beside the diffusion regions D1-D4, and the electrical properties of the diffusion regions D5-D8 are opposite to those of the adjacent diffusion regions D1-D4. For example, if the diffusion region D1 is N-type, then the diffusion region D5 adjacent to the diffusion region D1 is P-type. Similarly, in the embodiment, the diffusion regions D5 and D8 are P-type, and the diffusion regions D6 and D7 are N-type.

[0073] The first pull-down transistor PD1 is taken as an example. Since the gate structure of the first pull-down transistor PD1 spans the diffusion region D2 which is N-type, for the first pull-down transistor D1, the source Sr and the drain Dr are N-type, and correspondingly, P-type charges will accumulate in the region directly below the gate and be confined by the N-type source Sr and drain Dr. If the P-type charges are not removed, they will be confined in the region directly below the gate in the embodiment shown in the figure. However, through the improved design of the present application, as shown in the figure, Figure 2 The embodiment shown in the figure is different from the above-mentioned embodiment. More specifically, Figure 4As shown, the P-type charge directly below the gate structure of the first pull-down transistor PD1 can flow out through the P-type diffusion region D5, and then connect to the Vss contact structure through the metal silicide layer (not shown) formed on the surface of the diffusion regions D1 to D8, thus releasing the charge. Similarly, the N-type charge accumulated directly below the gate structure of the first pull-up transistor PU1 will also flow out through the N-type diffusion region D6, and then connect to the Vcc contact structure through the metal silicide layer (not shown), thus releasing the charge. The second pull-up transistor PU2 and the second pull-down transistor PD2 are in the same manner, and their accumulated charges can flow out through the diffusion regions D7 and D8, respectively. Since the second pull-up transistor PU2 and the second pull-down transistor are symmetrical patterns along the center point O of the first pull-up transistor PU1 and the first pull-down transistor PD1, they will not be described again here. Therefore, the Vss contact structure and Vcc contact structure described here can be used as the body contact of the pull-down transistor (PD1, PD2) and the pull-up transistor (PU1, PU2), respectively, and their function is to release the charge accumulated in the substrate.

[0074] Figure 4 In the layout design, the accumulated charge of the first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, and the second pull-down transistor PD2 can be released. However, in the applicant's actual experience, the charge accumulation of pull-down transistors PD1 and PD2 is more severe than that of pull-up transistors PU1 and PU2. Therefore, in other embodiments of the present invention, the layout design may be carried out only for releasing the accumulated charge of the first pull-down transistor PD1 and the second pull-down transistor PD2.

[0075] Figure 6 This is a layout diagram of a static random access memory (SRAM) cell according to a second preferred embodiment of the present invention. In this embodiment, most of the structures are the same as described above. Figure 4 The embodiments shown are the same, and the identical parts will not be repeated. The difference between this embodiment and the previous embodiments is that it does not include diffusion regions D6 and D7, and the second L-shaped portion P2 of gate structure G1 and gate structure G3 is not designed as L-shaped. Therefore, in this embodiment, only the accumulated charge of the first pull-down transistor PD1 and the second pull-down transistor PD2 is released. However, compared with the above embodiments, this invention has advantages such as simpler structure, easier fabrication, and smaller footprint.

[0076] Figure 7 This is a layout diagram of a static random access memory (SRAM) cell according to a third preferred embodiment of the present invention. In this embodiment, most of the structures are the same as described above. Figure 4The embodiments shown are the same, and the same parts are not repeated. However, the embodiment differs from the above embodiments in that, from a top view, the gate structure G2 and the gate structure G4 are designed to be T-shaped, and in more detail, Figure 8 The layout pattern of the static random access memory (SRAM) cell of the present application is shown in FIG. 1. The embodiment shown is the same as the above embodiments, and the same parts are not repeated. However, the embodiment differs from the above embodiments in that, from a top view, the gate structure G2 and the gate structure G4 are designed to be T-shaped, and in more detail, Figure 8 The layout pattern of the static random access memory (SRAM) cell of the present application is shown in FIG. 1. The embodiment shown is the same as the above embodiments, and the same parts are not repeated. However, the embodiment differs from the above embodiments in that, from a top view, the gate structure G2 and the gate structure G4 are designed to be T-shaped, and in more detail, Figure 6 The layout pattern of the static random access memory (SRAM) cell of the present application is shown in FIG. 1. The embodiment shown is the same as the above embodiments, and the same parts are not repeated. However, the embodiment differs from the above embodiments in that, from a top view, the gate structure G2 and the gate structure G4 are designed to be T-shaped, and in more detail, Figure 9 As shown, the gate structure G2 is taken as an example to illustrate that the gate structure G2 is T-shaped, has a long side portion G2A and a short side portion G2B, the long side portion G2A extends along the X-axis direction and is located on the diffusion region D1, and the short side portion G2B extends along the Y-axis direction and is located on the diffusion region D5. In this way, the accumulated charge under the gate structures of the first access transistor PG1 and the second access transistor PG2 can also be released.

[0077] The accumulated charge (P-type charge) under the gate structures of the first access transistor PG1 and the second access transistor PG2 can flow out of the diffusion region D5 and the diffusion region D8, respectively, through the design of the embodiment, and a bulk contact 20 is formed on the diffusion region D5 and the diffusion region D8 in the embodiment, the bulk contact 20 is similar to the contact pillar V and is electrically connected to the diffusion region D5, so that the accumulated charge of the first access transistor PG1 and the second access transistor PG2 can be released through the bulk contact 20.

[0078] The static random access memory cells 10 described in the embodiments can be arranged in an array. Adjacent static random access memory cells 10 can share a part of the diffusion region. For example, Figure 7 The region R shown is a static random access memory cell, and another adjacent region R1 to the left of the region R has another static random access memory cell, wherein the diffusion region D5 of the static random access memory cell of the region R is actually equal to the diffusion region D8 of the static random access memory cell of the region R1.

[0079] The following provides other embodiments of the present application, the layout patterns of which are improved based on the above embodiments, wherein most of the elements can be the same as described in the above embodiments, and the same elements are denoted by the same reference numerals and are not repeated.

[0080] Figure 10 The layout pattern of the static random access memory (SRAM) cell of the present application is shown in FIG. 1. The embodiment shown is the same as the above embodiments, and the same parts are not repeated. However, the embodiment differs from the above embodiments in that, from a top view, the gate structure G2 and the gate structure G4 are designed to be T-shaped, and in more detail, Figure 9The third embodiment is the same as the fourth embodiment, but the difference between the third embodiment and the fourth embodiment is that a substrate contact 22 is further included in the diffusion region D5, the substrate contact 22 is similar to the contact pillar V, is electrically connected to the diffusion region D5, and is located beside the first pull-down transistor PD1, so that the accumulated charge of the pull-down transistor (PD1 or PD2) can be released through the substrate contact 22. In the above embodiment, the charge of the pull-down transistor (PD1 or PD2) is released through the metal silicide formed on the surface of the diffusion region after the Vss contact structure is connected, but the conductivity of the metal silicide can be poor due to the missing of the manufacturing process, at which time the substrate contact 22 can be added, and such a structure can enable the access transistor (PG1 and PG2) and the pull-down transistor (PD1 or PD2) to each include the substrate contact 20 and the substrate contact 22, so that the charge can be released more effectively.

[0081] Figure 11 The layout diagram of a static random access memory (SRAM) cell of a fifth preferred embodiment of the present application is shown. Most of the elements of the present embodiment are the same as those of the fourth embodiment. Figure 9 The fourth embodiment is the same as the fourth embodiment, but the difference between the third embodiment and the fourth embodiment is that the diffusion region D5 is divided into different regions, and more specifically, the diffusion regions D5 included in the access transistor (PG1 and PG2) and the pull-down transistor (PD1 or PD2) are not directly connected to each other, and the access transistor (PG1 and PG2) releases the charge through the substrate contact 20, and the pull-down transistor (PD1 or PD2) releases the charge through the substrate contact 22 or the Vss contact structure. Such a change form also belongs to the scope covered by the present application.

[0082] Figure 5 The layout diagram of a static random access memory (SRAM) cell of a sixth preferred embodiment of the present application is shown. Most of the elements of the present embodiment are the same as those of the fourth embodiment. Figure 4 The fourth embodiment is the same as the fourth embodiment, but the difference between the third embodiment and the fourth embodiment is that the diffusion region D5 is divided into different regions, and more specifically, the diffusion regions D5 included in the access transistor (PG1 and PG2) and the pull-down transistor (PD1 or PD2) are not directly connected to each other, and the access transistor (PG1 and PG2) releases the charge through the substrate contact 20, and the pull-down transistor (PD1 or PD2) releases the charge through the substrate contact 22 or the Vss contact structure. Such a change form also belongs to the scope covered by the present application.

[0083] In light of the above description and drawings, the present application provides a layout pattern of a static random-access memory (SRAM), which includes a substrate 12, a plurality of diffusion regions D1-D8 located on the substrate, each diffusion region including a first diffusion region D1, a second diffusion region D2, a third diffusion region D3, a fourth diffusion region D4, a fifth diffusion region D5, a sixth diffusion region D6, a seventh diffusion region D7, and an eighth diffusion region D8, each diffusion region being arranged along a first direction (Y direction). A plurality of gate structures G is located on the substrate, each gate structure G extending along a second direction (X direction) and crossing the plurality of diffusion regions D1-D8 to form a plurality of transistors, wherein the plurality of transistors includes a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1), and a second access transistor (PG2), wherein the plurality of gates includes a first gate G1, wherein the first gate G1 includes a first L-shaped portion P1, the first L-shaped portion P1 crossing the first diffusion region D1 and the fifth diffusion region D5 and forming the first pull-down transistor (PD1), wherein the first diffusion region D1 and the fifth diffusion region D5 are adjacent and directly contact (for example Figure 6 as shown in the embodiment).

[0084] In some embodiments of the present application, wherein the first L-shaped portion P1 includes a short side portion P1B and a long side portion P1A, wherein the short side portion P1B of the first L-shaped portion P1 is arranged along the first direction (Y direction), and the long side portion P1A of the first L-shaped portion P1 is arranged along the second direction (X direction).

[0085] In some embodiments of the present application, wherein the short side portion P1B of the first L-shaped portion P1 is located on the fifth diffusion region D5, and the long side portion P1A of the first L-shaped portion P1 is located on the first diffusion region D1.

[0086] In some embodiments of the present application, wherein the first gate G1 includes a second L-shaped portion P2, the second L-shaped portion P2 crossing the second diffusion region D2 and the sixth diffusion region D6 and forming the first pull-up transistor (PU1), wherein the second diffusion region D2 and the sixth diffusion region D6 are adjacent and directly contact (for example ​ as shown in the embodiment).

[0087] In some embodiments of the present application, wherein the second L-shaped portion P2 includes a short side portion P2B and a long side portion P2A, wherein the short side portion P2B of the second L-shaped portion P2 is arranged along the first direction (Y direction), and the long side portion P2A of the second L-shaped portion P2 is arranged along the second direction (X direction).

[0088] In some embodiments of the application, the long side portion P1A of the first L-shaped portion P1 and the long side portion P2A of the second L-shaped portion P2 are aligned with each other in the second direction (X direction).

[0089] In some embodiments of the application, the short side portion P2B of the second L-shaped portion P2 is located on the sixth diffusion region D6, and the long side portion P2A of the second L-shaped portion P2 is located on the second diffusion region D2.

[0090] In some embodiments of the application, the plurality of gates G includes a second gate G2, the second gate G2 spans the first diffusion region D1 and the fifth diffusion region D5 and constitutes a first access transistor (PG1), wherein the second gate G2 has a T-shaped profile (e.g. as shown in the embodiment) from a top view. ​

[0091] In some embodiments of the application, the second gate G2 has a short side portion G2B and a long side portion G2A, wherein the short side portion G2B of the second gate G2 is arranged along the first direction (Y direction), and the long side portion G2A of the second gate G2 is arranged along the second direction (X direction).

[0092] In some embodiments of the application, the short side portion G2B of the second gate G2 is located on the fifth diffusion region D5, and the long side portion G2A of the second gate G2 is located on the first diffusion region D1.

[0093] In some embodiments of the application, a substrate contact 20 is further included, located on the fifth diffusion region D5 and electrically connected with the fifth diffusion region D5.

[0094] In some embodiments of the application, the first diffusion region D1, the fourth diffusion region D4, the sixth diffusion region D6 and the seventh diffusion region D7 comprise a first conductivity type (e.g. N type), and the second diffusion region D2, the third diffusion region D3, the fifth diffusion region D5 and the eighth diffusion region D8 comprise a second conductivity type (e.g. P type).

[0095] In some embodiments of the application, the first conductivity type (e.g. N type) and the second conductivity type (e.g. P type) are different.

[0096] In some embodiments of the application, the substrate 12 comprises an SOI substrate.

[0097] In some embodiments of the application, a third gate G3 is further included, the third gate G3 spans the third diffusion region D3 and the seventh diffusion region D7 and constitutes a second pull-up transistor (PU2), wherein the third diffusion region D3 and the seventh diffusion region D7 are adjacent and directly contact. ​

[0098] In some embodiments of the present application, the third gate G3 straddles the fourth diffusion D4 and the eighth diffusion D8 and forms a second pull-down transistor (PD2), wherein the fourth diffusion D4 is adjacent to and directly contacts the eighth diffusion D8.

[0099] In some embodiments of the present application, the first gate G1 and the third gate G3 are symmetric with respect to a center point O.

[0100] In some embodiments of the present application, the plurality of gates includes a fourth gate G4, the fourth gate G4 straddles the fourth diffusion D4 and the eighth diffusion D8 and forms a second access transistor (PG2), wherein the fourth gate G4 has a T-shaped profile from a top view.

[0101] In some embodiments of the present application, the second gate G2 and the fourth gate G4 are symmetric with respect to a center point O.

[0102] In some embodiments of the present application, the layout pattern of the static random access memory is arranged adjacent to (e.g., in regions R and R1, respectively) another layout pattern of a static random access memory, and the fifth diffusion D5 of the layout pattern of the static random access memory directly contacts an eighth diffusion D8 of the layout pattern of another static random access memory.

[0103] The present application features an improved layout pattern of a static random access memory, which includes some additional diffusion regions adjacent to the original diffusion regions, the additional diffusion regions have opposite conductivity types from the original diffusion regions, and the gate structures are designed to be L-shaped or T-shaped (from a top view). In this way, the charges accumulated under the gate structures can be discharged through the diffusion regions and then released through the contact structures, so as to avoid affecting the electrical properties of the transistors and improve product yield.

[0104] The above descriptions are only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application should be covered by the scope of the present application.

Claims

1. A layout pattern for static random-access memory (SRAM), comprising: Base; Multiple diffusion regions are located on the substrate, each of which includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region, and an eighth diffusion region, and each of the diffusion regions is arranged along a first direction (Y direction); Multiple gate structures are located on the substrate, each gate structure extends along the second direction (X direction) and spans the multiple diffusion regions to form multiple transistors, wherein the multiple transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1), and a second access transistor (PG2). in, The plurality of gates includes a first gate, wherein the first gate includes a first L-shaped portion, the first L-shaped portion spanning the first diffusion region and the fifth diffusion region and forming the first pull-down transistor (PD1), wherein the first diffusion region and the fifth diffusion region are adjacent to and in direct contact. The first gate includes a second L-shaped portion that spans the second diffusion region and the sixth diffusion region and forms the first pull-up transistor (PU1), wherein the second diffusion region is adjacent to and in direct contact with the sixth diffusion region.

2. The layout pattern of the static random access memory as claimed in claim 1, wherein the first L-shaped portion includes a short side portion and a long side portion, wherein the short side portion of the first L-shaped portion is arranged along the first direction (Y direction), and the long side portion of the first L-shaped portion is arranged along the second direction (X direction).

3. The layout pattern of the static random access memory as described in claim 2, wherein the short side of the first L-shaped portion is located on the fifth diffusion region, and the long side of the first L-shaped portion is located on the first diffusion region.

4. The layout pattern of the static random access memory as claimed in claim 1, wherein the second L-shaped portion includes a short side portion and a long side portion, wherein the short side portion of the second L-shaped portion is arranged along the first direction (Y direction), and the long side portion of the second L-shaped portion is arranged along the second direction (X direction).

5. The layout pattern of the static random access memory as claimed in claim 4, wherein the long side portion of the first L-shaped portion and the long side portion of the second L-shaped portion are aligned with each other in the second direction (X direction).

6. The layout pattern of the static random access memory as claimed in claim 1, wherein the short side of the second L-shaped portion is located on the sixth diffusion region, and the long side of the second L-shaped portion is located on the second diffusion region.

7. The layout pattern of the static random access memory as described in claim 1, wherein, The plurality of gates includes a second gate that spans the first diffusion region and the fifth diffusion region and constitutes the first access transistor (PG1), wherein the second gate has a T-shaped profile when viewed from a top view.

8. The layout pattern of the static random access memory as claimed in claim 7, wherein the second gate has a short side portion and a long side portion, wherein the short side portion of the second gate is arranged along the first direction (Y direction) and the long side portion of the second gate is arranged along the second direction (X direction).

9. The layout pattern of the static random access memory as claimed in claim 8, wherein the short side portion of the second gate is located on the fifth diffusion region, and the long side portion of the second gate is located on the first diffusion region.

10. The layout pattern of the static random access memory as claimed in claim 7, further comprising a substrate contact located on the fifth diffusion region and electrically connected to the fifth diffusion region.

11. The layout pattern of the static random access memory as claimed in claim 1, wherein the first diffusion region, the fourth diffusion region, the sixth diffusion region and the seventh diffusion region include a first conductivity type, and the second diffusion region, the third diffusion region, the fifth diffusion region and the eighth diffusion region include a second conductivity type.

12. The layout pattern of the static random access memory as claimed in claim 11, wherein the first conductivity type is different from the second conductivity type.

13. The layout pattern of the static random access memory as claimed in claim 1, wherein the substrate includes an SOI substrate.

14. The layout pattern of the static random access memory as claimed in claim 1, further comprising a third gate, the third gate spanning the third diffusion region and the seventh diffusion region and forming the second pull-up transistor (PU2), wherein the third diffusion region and the seventh diffusion region are adjacent and in direct contact.

15. The layout pattern of the static random access memory as claimed in claim 14, wherein the third gate spans the fourth diffusion region and the eighth diffusion region and forms the second pull-down transistor (PD2), wherein the fourth diffusion region and the eighth diffusion region are adjacent to and in direct contact.

16. The layout pattern of the static random access memory as claimed in claim 15, wherein the first gate and the third gate are symmetrical about each other along the center point.

17. The layout pattern of the static random access memory as claimed in claim 1, wherein the plurality of gates includes a second gate and a fourth gate, the fourth gate spanning the fourth diffusion region and the eighth diffusion region and constituting the second access transistor (PG2), wherein, in a top view, the fourth gate has a T-shaped profile.

18. The layout pattern of the static random access memory as claimed in claim 17, wherein the second gate and the fourth gate are symmetrical about each other along the center point.

19. The layout pattern of a static random access memory as claimed in claim 1, wherein the layout pattern of the static random access memory is arranged adjacent to the layout pattern of another static random access memory, and the fifth diffusion region of the layout pattern of the static random access memory is in direct contact with the eighth diffusion region of the layout pattern of the other static random access memory.

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