Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate which is provided with a plurality of active regions which are arranged at intervals in a first direction; patterning the substrate to form a plurality of grooves extending from the top surface of the substrate to the inside of the substrate, the grooves being in one-to-one correspondence with the active regions, and the grooves exposing part of the active regions; sequentially forming a first side wall layer and a second side wall layer on the side wall of the groove; forming a bit line contact layer at least filling the rest part of the groove; a bit line column extending in the second direction is formed, the bit line column is in contact connection with the at least one bit line contact layer, the bit line column and the at least one bit line contact layer in contact connection with the bit line column form a bit line structure, and the first direction intersects with the second direction. The embodiment of the invention is at least beneficial to improving the yield of the formed bit line structure so as to improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a memory component used to store programs and various data information. DRAM usually includes capacitors and transistors connected to the capacitors. The capacitors are used to store charges representing stored programs and various data information. The transistors are switches that control the inflow and release of charges from the capacitors. When writing data, the word line gives a high level, the transistor is turned on, and the bit line charges the capacitor; when reading data, the word line also gives a high level, the transistor is turned on, the capacitor is discharged, and the bit line obtains a read signal.

[0003] However, with the continuous development of semiconductor structure manufacturing technology, the semiconductor structure process node is continuously reduced, so that the size of each functional structure in the semiconductor structure is gradually reduced, and the spacing between each functional structure is gradually reduced. In order to achieve the reduction of the size of each functional structure, higher requirements are put forward for the process of preparing it, making it more difficult to control the size accuracy of each functional structure. Moreover, as the spacing between each functional structure is gradually reduced, the residues formed by various preparation processes in the reduced spacing are more difficult to be removed, thus making the performance of each functional structure unstable. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the yield of the formed bit line structure, so as to improve the electrical performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, wherein the substrate has a plurality of active areas arranged at intervals along a first direction; performing patterning on the substrate to form a plurality of grooves extending from the top surface of the substrate to the inside of the substrate, the grooves corresponding to the active areas one by one, and the grooves exposing portions of the active areas; forming a first sidewall layer and a second sidewall layer in sequence on the sidewalls of the grooves; forming a bitline contact layer that at least fills the remaining portions of the grooves; forming a bitline column extending along a second direction, the bitline column being in contact with and connected to at least one of the bitline contact layers, and the bitline column and at least one of the bitline contact layers in contact with it constitute a bitline structure, and the first direction and the second direction intersect.

[0006] In some embodiments, the step of forming the bit line contact layer includes: forming the bit line contact layer that fills the remaining portion of the groove, the bit line contact layer and the groove corresponding one to one; the step of forming the bit line column includes: forming the bit line column that is in contact with and connected to a plurality of the bit line contact layers arranged at intervals along the second direction, the bit line column and the plurality of the bit line contact layers in contact with and connected to it constitute a bit line structure.

[0007] In some embodiments, the step of forming the bit line contact layer includes: forming the bit line contact layer that fills the remaining portions of the plurality of grooves arranged at intervals along the second direction, the bit line contact layer being also located on the top surface of the substrate and extending along the second direction; the step of forming the bit line column includes: forming the bit line column on a side of the bit line contact layer away from the substrate, the bit line column and the bit line contact layer in contact with it constituting a bit line structure.

[0008] In some embodiments, the step of forming the groove includes: forming the groove whose width gradually decreases in the first direction along a direction in the substrate pointing toward the top surface of the substrate.

[0009] In some embodiments, in the step of forming the groove, the manufacturing method also includes: forming a first dielectric layer on the top surface of the substrate, and the groove is surrounded by the substrate and the first dielectric layer; the step of forming the first sidewall layer and the second sidewall layer includes: forming a first sidewall film, and the first sidewall film conformally covers the inner wall of the groove and the top surface of the first dielectric layer; forming a second sidewall film, and the second sidewall film conformally covers the surface of the first sidewall film away from the substrate; using the first dielectric layer as an etching stop layer, etching back the first sidewall film and the second sidewall film, removing the first sidewall film and the second sidewall film located on the top surface of the substrate and the bottom surface of the groove, and the remaining first sidewall film serves as the first sidewall layer, and the remaining second sidewall film serves as the second sidewall layer.

[0010] In some embodiments, in the step of forming the groove, the manufacturing method also includes: forming a first dielectric layer and a second dielectric layer stacked on the top surface of the substrate, and the groove is surrounded by the substrate, the first dielectric layer and the second dielectric layer; the step of forming the first sidewall layer includes: forming a first sidewall film, the first sidewall film conformally covering the inner wall of the groove and the top surface of the second dielectric layer; using the second dielectric layer as an etching stop layer, etching back the first sidewall film to remove the first sidewall film located on the top surface of the second dielectric layer and on the bottom surface of the groove; removing the first sidewall film located on the side wall of the first dielectric layer, and the remaining first sidewall film serves as the first sidewall layer.

[0011] In some embodiments, the first sidewall layer and part of the active area together form a first sub-recess; the step of forming the second sidewall layer includes: forming a second sidewall film, the second sidewall film conformally covering the inner wall of the first sub-recess, the top surface of the second dielectric layer and the top surface of the first sidewall layer; using the second dielectric layer as an etch stop layer, etching back the second sidewall film, removing the second sidewall film located on the top surface of the second dielectric layer and the bottom surface of the first sub-recess, and the remaining second sidewall film and part of the active area together form a second sub-recess; forming a third dielectric layer, the second dielectric layer fills the second sub-recess; the removing of the first sidewall film located on the sidewall of the first dielectric layer includes: using the first dielectric layer as an etch stop layer, removing the second dielectric layer and etching the first sidewall film and the second sidewall film to remove the first sidewall film and the second sidewall film located on the sidewall of the second dielectric layer, and the remaining second sidewall film serves as the second sidewall layer.

[0012] In some embodiments, the second sidewall layer and part of the active area together form a third sub-recess; the step of forming the bit line contact layer includes: forming a bit line contact film, the bit line contact film fills the third sub-recess and is located on the top surface of the first dielectric layer; using the top surface of the first sidewall layer as an etching stop layer, and planarizing the bit line contact film to form a plurality of the bit line contact layers arranged at intervals along the second direction.

[0013] In some embodiments, the second sidewall layer and a portion of the active area together form a third sub-recess; the step of forming the bit line contact layer includes: forming a bit line contact film, the bit line contact film filling the third sub-recess and being located on the top surface of the first dielectric layer; performing a patterning process on the bit line contact film to remove the bit line contact film located on the top surface of the first dielectric layer to form the bit line contact layer extending along the second direction, the bit line contact layer filling a plurality of the third sub-recesses spaced apart along the second direction.

[0014] In some embodiments, the step of forming the bit line pillar includes: forming the bit line pillar along the first direction to cover at least a portion of the top surface of the bit line contact layer.

[0015] In some embodiments, after forming the bit line column, the manufacturing method further includes: forming a first side wall layer located on the side wall of the bit line column, the first side wall layer is also at least located on the top surface of the first side wall layer; forming a second side wall layer located on a side of the first side wall layer away from the bit line column, the second side wall layer is also located on the top surface of the second side wall layer.

[0016] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, comprising: a substrate having a groove, the groove extending from the top surface of the substrate into the substrate, and the groove and the active area correspond one-to-one and expose a portion of the active area; a first sidewall layer, covering the sidewall of the groove; a second sidewall layer, covering a side of the first sidewall layer away from the sidewall of the groove; a bit line contact layer, filling at least the remaining portion of the groove; a bit line column extending along a second direction, the bit line column being in contact with and connected to at least one of the bit line contact layers, and the bit line column and at least one of the bit line contact layers in contact with it constitute a bit line structure, and the first direction and the second direction intersect.

[0017] In some embodiments, the bit line contact layer and the groove correspond one to one, the bit line column is in contact with and connected to a plurality of the bit line contact layers arranged at intervals along the second direction, and a bit line column and a plurality of the bit line contact layers in contact with and connected to it constitute a bit line structure; and / or, the bit line contact layer extends along the second direction and fills the remaining parts of the plurality of the grooves arranged at intervals along the second direction, and a bit line column and a bit line contact layer in contact with and connected to it constitute a bit line structure.

[0018] In some embodiments, along a direction from the bit line pillar to the bit line contact layer, a width of the bit line contact layer in the first direction gradually decreases.

[0019] In some embodiments, the semiconductor structure further includes: a first sidewall layer, located on the sidewall of the bitline column and at least on the top surface of the first sidewall layer; a second sidewall layer, located on a side of the first sidewall layer away from the bitline column and on the top surface of the second sidewall layer.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0021] In the step of forming a bit line structure, a bit line contact layer at least partially embedded in the substrate and in contact with the active area is first formed, and a first side wall layer and a second side wall layer are formed between the side wall of the groove and the bit line contact layer to prevent the bit line contact layer from contacting the substrate except for the active area in contact with it; then a bit line column extending along the second direction is formed, so that the bit line column and at least one bit line contact layer in contact with it constitute a bit line structure. Thus, on the one hand, before forming the bit line contact layer, the first side wall layer and the second side wall layer have been formed in the groove, which is conducive to avoiding the short circuit phenomenon between the bit line contact layer and other conductive structures formed on the substrate subsequently, such as the capacitor structure, that is, the first side wall layer and the second side wall layer can effectively avoid the unnecessary electrical connection phenomenon between the bit line contact layer and other conductive structures formed on the substrate subsequently; on the other hand, the bit line contact layer and the bit line pillar are prepared separately, so that when preparing the bit line pillar, no unnecessary impact will be caused on the already formed bit line contact layer, and it is conducive to forming a larger bit line contact layer, thereby facilitating the improvement of the alignment accuracy between the bit line pillar and the bit line contact layer, and the improvement of the contact area between the bit line pillar and the bit line contact layer, so as to reduce the contact resistance between the bit line pillar and the bit line contact layer. Therefore, by forming the first side wall layer and the second side wall layer first, then forming the bit line contact layer, and then forming the bit line pillar, it is conducive to improving the yield of the formed bit line structure, so as to improve the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 to Figure 2 A schematic cross-sectional structure diagram corresponding to each step in a method for forming a bit line structure;

[0024] Figure 3 A flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figures 4 to 29 A schematic diagram of the cross-sectional structures corresponding to each step in a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] As known from the background technology, the electrical performance of semiconductor structures needs to be improved.

[0027] After analysis, it is found that the process commonly used to prepare the bit line structure currently includes the following steps:

[0028] Figure 1 to Figure 2 Schematic diagram of the cross-sectional structure corresponding to each step in a method for forming a bit line structure. Figure 1 The substrate 10 includes an active area 11, a shallow trench isolation structure 16, and a substrate 17 supporting the active area 11 and the shallow trench isolation structure 16. A groove 12 exposing the active area 11 is formed in the substrate 10. The active area 11 and the groove 12 correspond to each other one by one. Moreover, along the direction Z, the groove 12 presents an inverted trapezoidal morphology that is wide at the top and narrow at the bottom. An initial bit line contact layer 13 is formed to fill the groove 12. An initial bit line layer 14 is formed on the side of the initial bit line contact layer 13 away from the substrate 10. It can be understood that, along the direction Z from the initial bit line layer 14 to the initial bit line contact layer 13, the thickness of the initial bit line contact layer 13 located on the top surface 10a of the substrate is lower than the thickness of the initial bit line contact layer 13 located in the groove 12, that is, the thickness of the initial bit line contact layer 13 in the direction Z is uneven.

[0029] Combined with reference Figure 1 and Figure 2 The initial bit line contact layer 13 and the initial bit line layer 14 are patterned together to form a plurality of bit line structures 15 arranged at intervals along the first direction X. In the step of etching the initial bit line contact layer 13, the depth of etching the initial bit line contact layer 13 on the top surface 10a of the substrate is lower than the depth of etching the initial bit line contact layer 13 in the groove 12, resulting in the problem of uneven etching when etching the initial bit line contact layer 13, which is easy to reduce the etching accuracy and thus reduce the yield of the formed bit line structure. In addition, in the step of etching the bit line contact layer 13 to form the bit line structure 15, since the groove 12 presents an inverted trapezoidal morphology that is wide at the top and narrow at the bottom, the etching rate of the bit line contact layer 13 is reduced, and it is easy to form etching residues in the re-exposed groove 12. For example, the bit line contact layer 13 that should have been removed is not removed. When an isolation layer is subsequently formed in the re-exposed groove 12, the etching residues will destroy the isolation and protection effect of the isolation layer on the bit line structure 15. For example, when a capacitor structure is subsequently formed between adjacent bit line structures 15, the bit line structure 15 is easily electrically connected to the capacitor structure through the etching residues, that is, the etching residues are likely to cause a short circuit in the bit line structure 15.

[0030] It should be noted that Figure 1 and Figure 2 The active region 11 and the substrate 17 are separated by a dotted line.

[0031] Therefore, the problem of etching non-uniformity in the step of forming the bit line structure 15 and the problem of etching residues in the groove 12 caused by etching need to be solved.

[0032] The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, on the one hand, before forming the bit line contact layer, the first side wall layer and the second side wall layer have been formed in the groove, which is conducive to avoiding the short circuit phenomenon between the bit line contact layer and other conductive structures subsequently formed on the substrate, such as the capacitor structure, that is, the first side wall layer and the second side wall layer can effectively avoid the unnecessary electrical connection phenomenon between the bit line contact layer and other conductive structures subsequently formed on the substrate; on the other hand, the bit line contact layer and the bit line pillar are prepared separately, so that when preparing the bit line pillar, no unnecessary impact is caused on the already formed bit line contact layer, and it is conducive to forming a larger bit line contact layer, thereby facilitating the improvement of the alignment accuracy between the bit line pillar and the bit line contact layer, and the improvement of the contact area between the bit line pillar and the bit line contact layer, so as to reduce the contact resistance between the bit line pillar and the bit line contact layer. Therefore, by forming the first side wall layer and the second side wall layer first, then forming the bit line contact layer, and then forming the bit line pillar, it is conducive to improving the yield of the formed bit line structure, so as to improve the electrical performance of the semiconductor structure.

[0033] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0034] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 3 A flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figures 4 to 29 The cross-sectional structure diagram corresponding to each step in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure is shown in FIG. Figures 1 to 29 All are schematic diagrams of local cross-sectional structures of semiconductor structures.

[0035] refer to Figures 3 to 29 , the manufacturing method of the semiconductor structure comprises the following steps:

[0036] S101: Combined with reference Figure 4 and Figure 5, providing a substrate 100, wherein the substrate 100 has a plurality of active regions 110 arranged at intervals along a first direction X.

[0037] It should be noted that Figure 4 FIG. 1 is a top view showing the relative position relationship between the active region 110 in the substrate and the subsequently formed bit lines BL and word lines WL in the semiconductor structure. Figure 5 For the substrate 100 along Figure 4 The first cross-sectional direction AA1 is a schematic diagram of a local cross-sectional structure, and the first cross-sectional direction AA1 is a first direction X, that is, the extension direction of the word line WL. It can be understood that Figure 4 The bit line BL and word line WL drawn in FIG. 1 are only used to illustrate the relative position relationship between the bit line BL, word line WL and active area 110 in the top view. Figure 1 There is no restriction on the internal structure of the bit line BL and the word line WL, and there is no restriction on the three-dimensional positional relationship among the bit line BL, the word line WL and the active area 110. In addition, in order to clearly illustrate the relative positional relationship among the active area 110, the bit line BL and the word line WL in the top view, the bit line BL and the word line WL are both drawn in perspective.

[0038] In some embodiments, reference Figure 5 , there is a shallow trench isolation structure 108 between adjacent active regions 110. It is understandable that the substrate 100 may further include a supporting portion 118 supporting the active region 110 and the shallow trench isolation structure 108. It should be noted that, Figure 5 The active area 110 and the support portion 118 are separated by a dotted line.

[0039] In some embodiments, reference Figure 4 , the multiple active regions 110 are not only arranged at intervals along the first direction X and the second direction Y, but also the two adjacent groups of active regions arranged at intervals along the second direction Y are staggered in the first direction X, the extension direction U of the active regions 110, the first direction X and the second direction Y intersect each other, and the extension direction U of the active regions 110, the first direction X and the second direction Y are located in the same plane. It can be understood that the multiple active regions 110 arranged at intervals along the second direction Y are regarded as a column, and along the first direction X, the adjacent two columns are staggered, and the arrangement of the two columns separated by one column is the same.

[0040] It should be noted that, in actual applications, the multiple active regions 110 may also be arranged in an array along the first direction X and the second direction Y or in other arrangements. The arrangement of the multiple active regions 110 may be adjusted according to actual needs and is not limited here. Figure 4 The arrangement shown is an example, and the subsequent process steps of the bit line contact layer and the bit line pillar are described in detail.

[0041] S102: Combined with reference Figure 5 to Figure 6 The substrate 100 is patterned to form a plurality of grooves 120 extending from the top surface 100 a of the substrate into the substrate 100 . The grooves 120 correspond to the active areas 110 one by one, and the grooves 120 expose a portion of the active area 110 .

[0042] It can be understood that the grooves 120 correspond to the active areas 110 one by one, and the active areas 110 are Figure 4 When arranged in the arrangement shown in FIG. Figure 4 In practical applications, when the active regions are arranged in an array along the first direction X and the second direction Y, the grooves are also arranged in an array along the first direction X and the second direction Y.

[0043] refer to Figure 4 In FIG. 4b, along the extension direction U of the active region 110 itself, the active region 110 includes a first portion 130, a second portion 140 and a third portion 150 arranged in sequence. Figure 4 and Figure 6 The groove 120 is surrounded by the second portion 140. It can be understood that, for each active area 110, the second portion 140 is in contact with a bit line BL, and a partial area in the first portion 130 and a partial area in the third portion 150 are respectively opposite to two word lines WL.

[0044] It should be noted that, in conjunction with the reference Figure 4 and Figure 6 , in the plurality of active regions 110 Figure 4 When the arrangement shown is Figure 6 In the cross-sectional view along the first cross-sectional direction AA1, only the second portion 140 of a portion of the active area 110 can be schematically shown, and the other active areas 110 are Figure 5 The first portion 130 or the third portion 150 of the active region 110 is shown in FIG. Figure 6 Only a portion of the groove 120 surrounded by the second portion 140 is shown schematically. In an actual top view, the second portion 140 in each active region 110 surrounds a groove 120 .

[0045] In some embodiments, reference Figure 6 The step of forming the groove 120 may include: forming the groove 120 whose width gradually decreases in the first direction X in a direction Z pointing to the inside of the substrate 100 along the top surface 100 a of the substrate.

[0046] In some embodiments, reference Figure 6The bottom surface 120a of the groove can not only expose the second portion 140 in the active area 110, but also expose part of the shallow trench isolation structure 108, and along the direction Z, the orthographic projection area of ​​the groove 120 on the substrate top surface 100a gradually decreases, that is, the groove 120 presents a top-wide and bottom-narrow morphology. In this way, it is beneficial to form a bit line contact layer presenting a top-wide and bottom-narrow morphology based on the groove 120 in the subsequent process.

[0047] It should be noted that, in practical applications, the bottom surface of the groove may also only expose the second portion of the active area.

[0048] The process steps for forming the above-mentioned groove 120 include at least the following two embodiments:

[0049] In some embodiments, reference Figure 7 and Figure 8 In the step of forming the groove 120, the manufacturing method may further include: forming a first dielectric layer 106 on the top surface 100a of the substrate, and the groove 120 is surrounded by the substrate 100 and the first dielectric layer 106. It can be understood that the first dielectric layer 106 can be used as an etching stop layer for subsequently forming the first sidewall layer and the second sidewall layer.

[0050] In some embodiments, the steps of forming the groove 120 and the first dielectric layer 106 may include: Figure 7 , before the substrate 100 is patterned to form the groove 120, a first dielectric film 166 is formed on the top surface 100a of the substrate and the active area; Figure 7 and Figure 8 In the step of patterning the substrate 100 , the first dielectric film 166 is also patterned, and the remaining first dielectric film 166 serves as the first dielectric layer 106 to form a groove 120 surrounded by the substrate 100 and the first dielectric layer 106 .

[0051] In other embodiments, reference Fig. 9 In the step of forming the groove 120, the manufacturing method may further include: forming a stacked first dielectric layer 106 and a second dielectric layer 116 on the top surface 100a of the substrate, wherein the groove 120 is surrounded by the substrate 100, the first dielectric layer 106 and the second dielectric layer 116. It is understood that the second dielectric layer 116 may be used as an etching stop layer for subsequently forming the first sidewall layer and the second sidewall layer.

[0052] In some embodiments, the step of forming the groove 120, the first dielectric layer 106 and the second dielectric layer 116 may include: before patterning the substrate 100 to form the groove 120, forming a stacked first dielectric film (not shown) and a second dielectric film (not shown) on the top surface 100a of the substrate and the active area; in the step of patterning the substrate 100, the first dielectric film and the second dielectric film are also patterned, and the remaining first dielectric film serves as the first dielectric layer 106, and the remaining second dielectric film serves as the second dielectric layer 116, so as to form the groove 120 surrounded by the substrate 100, the first dielectric layer 106 and the second dielectric layer 116.

[0053] In the above two embodiments, the material of the first dielectric layer 106 may be polysilicon, and the material of the second dielectric layer 116 may be silicon oxide.

[0054] S103: Reference Figures 8 to 17 , a first sidewall layer 101 and a second sidewall layer 102 are sequentially formed on the groove sidewall 120 b.

[0055] It can be understood that before forming the bit line contact layer, the first side wall layer 101 and the second side wall layer 102 are first formed in the groove 120, which can prevent the subsequently formed bit line contact layer from contacting the substrate 100 except the active area 110 connected to it, and is beneficial to avoid the short circuit between the subsequently formed bit line contact layer and other conductive structures subsequently formed on the substrate 100, such as the capacitor structure. That is, the first side wall layer 101 and the second side wall layer 102 can effectively avoid unnecessary electrical connection between the subsequently formed bit line contact layer and other conductive structures subsequently formed on the substrate 100.

[0056] It can be understood that after the first sidewall layer 101 and the second sidewall layer 102 are formed, the remaining part of the groove 120 is surrounded by the second sidewall layer 102 and the groove 120, and the subsequently formed bit line contact layer fills the remaining part of the groove 120. In this way, the first sidewall layer 101 and the second sidewall layer 102 are first formed in sequence on the groove sidewall 120b, and the second sidewall layer 102 and the groove 120 are used to jointly define the formation space of the bit line contact layer. There is no need to etch the bit line contact layer located in the groove 120 to reserve space for forming the first sidewall layer 101 and the second sidewall layer 102. That is, there is no need to etch the bit line contact layer located in the groove 120, which is beneficial to improving the yield of the formed bit line contact layer and avoiding the formation of etching residues in the groove 120 that affect the electrical properties of the finally formed semiconductor structure.

[0057] The formation of the first sidewall layer 101 and the second sidewall layer 102 includes at least the following embodiments.

[0058] In some embodiments, reference Figure 8 In the step of forming the groove 120 , a first dielectric layer 106 is also formed on the top surface of the substrate 100 , and the groove 120 is surrounded by the substrate 100 and the first dielectric layer 106 .

[0059] On this basis, forming the first sidewall layer 101 and the second sidewall layer 102 may include the following steps:

[0060] refer to Fig.10 , forming a first sidewall film 111, the first sidewall film 111 conformally covers the inner wall of the groove 120 and the top surface of the first dielectric layer 106; forming a second sidewall film 112, the second sidewall film 112 conformally covers the surface of the first sidewall film 111 away from the substrate 100.

[0061] Combined with reference Figure 10 to Figure 11 , using the first dielectric layer 106 as an etching stop layer, the first sidewall film 111 and the second sidewall film 112 are etched back to remove the first sidewall film 111 and the second sidewall film 112 located on the top surface 100a of the substrate and the bottom surface 120a of the groove, and the remaining first sidewall film 111 serves as the first sidewall layer 101, and the remaining second sidewall film 112 serves as the second sidewall layer 102.

[0062] In other embodiments, reference Fig. 9 In the step of forming the groove 120 , a first dielectric layer 106 and a second dielectric layer 116 are stacked and formed on the top surface of the substrate 100 . The groove 120 is surrounded by the substrate 100 , the first dielectric layer 106 and the second dielectric layer 116 .

[0063] On this basis, forming the first sidewall layer 101 may include the following steps:

[0064] refer to Fig.12 , forming a first sidewall film 111 , the first sidewall film 111 conformally covers the inner wall of the groove 120 and the top surface of the second dielectric layer 116 .

[0065] Combined with reference Fig.12 and Fig.13 , using the second dielectric layer 116 as an etching stop layer, the first sidewall film 111 is etched back to remove the first sidewall film 111 located on the top surface of the second dielectric layer 116 and the bottom surface 120 a of the groove.

[0066] It should be noted that the reference Figures 13 to 17 , the first sidewall film 111 located on the sidewall of the second dielectric layer 116 will be removed later, and the remaining first sidewall film 111 will serve as the first sidewall layer 101 .

[0067] In some embodiments, the step of removing the first sidewall film 111 located on the sidewall of the second dielectric layer 116 can be completed during the step of forming the first sidewall layer 101 and the step of forming the second sidewall layer 102 , which is described in detail below.

[0068] refer to Fig.13 The first sidewall layer 101 and a portion of the active area 110 together form a first sub-recess 130; forming the second sidewall layer 102 may include the following steps:

[0069] Combined with reference Fig.13 and Fig.14 , forming a second sidewall film 112 , the second sidewall film 112 conformally covers the inner wall of the first sub-groove 130 , the top surface of the second dielectric layer 116 and the top surface of the first sidewall layer 101 .

[0070] Combined with reference Fig.14 and Fig.15 , using the second dielectric layer 116 as an etching stop layer, the second sidewall film 112 is etched back to remove the second sidewall film 112 located on the top surface of the second dielectric layer 116 and the bottom surface of the first sub-recess 130 , and the remaining second sidewall film 112 and a portion of the active area 110 together form a second sub-recess 140 .

[0071] Combined with reference Fig.15 and Fig.16 , a third dielectric layer 126 is formed, and the third dielectric layer 126 fills the second sub-groove 140 .

[0072] Combined with reference Fig.16 and Fig.17 The step of removing the first sidewall film 111 located on the sidewall of the second dielectric layer 116 may include: using the first dielectric layer 106 as an etching stop layer, removing the second dielectric layer 116 and etching the first sidewall film 111 and the second sidewall film 112 to remove the first sidewall film 111 and the second sidewall film 112 located on the sidewall of the second dielectric layer 116, and the remaining second sidewall film 112 serves as the second sidewall layer 102, and the remaining first sidewall film 111 serves as the first sidewall layer 101.

[0073] In some embodiments, the steps of removing the second dielectric layer 116 and etching the first sidewall film 111 and the second sidewall film 112 include: first, using the second dielectric layer 116 as an etching stop layer, removing the third dielectric layer 126 located on the top surface of the second dielectric layer 116, and the remaining third dielectric layer 126 is located in the second sub-recess 140; then, using the first dielectric layer 106 as an etching stop layer, removing the remaining third dielectric layer 126, the second dielectric layer 116, and the first sidewall film 111 and the second sidewall film 112 located on the sidewalls of the second dielectric layer 116.

[0074] Continue to refer Fig.17, remove the remaining third dielectric layer 126 to expose the groove bottom surface 120a.

[0075] In some embodiments, the material of the third dielectric layer 126 may be a spin-coatable dielectric.

[0076] In the above two embodiments, the material of the first sidewall film 111 may be silicon nitride, and the material of the second sidewall film 112 may be silicon oxide. Therefore, the material of the first sidewall layer 101 is silicon nitride, and the material of the second sidewall layer 102 is silicon oxide. The first sidewall layer 101 and the second sidewall layer 102 cooperate with each other, which is beneficial to improving the insulation effect between the subsequently formed bit line contact layer and the substrate 100 except the active area 110 in contact with it, and is beneficial to providing a better support effect for the subsequently formed bit line contact layer.

[0077] It should be noted that, in the following description, the groove 120 is surrounded by the substrate 100, the first dielectric layer 106 and the second dielectric layer 116. Fig. 9 As shown, the first side wall layer 101 and the second side wall layer 102 are finally formed as shown in FIG. Fig.17 The figure is an example, and the subsequent process steps are described in detail. In practical applications, the groove 120 can be the groove 120 described in any of the above embodiments, and the first sidewall layer 101 and the second sidewall layer 102 finally formed can also be as Fig.11 shown.

[0078] S104: Reference Figures 17 to 20 as well as Fig.24 , forming at least the groove 120 (reference Fig. 9 ) The remaining portion of the bit line contact layer 103.

[0079] In some embodiments, the material of the bit line contact layer 103 may be a semiconductor material such as polysilicon. By setting the material of the bit line contact layer 103 to be a semiconductor material such as polysilicon, the interface state of the contact surface between the finally formed bit line structure and the active area 110 can be reduced, thereby reducing the possibility of abnormalities occurring when transmitting electrical signals between the active area 110 and the bit line structure.

[0080] S105: Reference Figure 20 to Figure 23 as well as Fig.25 , forming a bit line column 104 extending along the second direction Y, the bit line column 104 is in contact with at least one bit line contact layer 103, and the bit line column 104 and at least one bit line contact layer 103 in contact with it constitute a bit line structure 105, the first direction X and the second direction Y intersect.

[0081] It can be understood that since the bit line contact layer 103 and the bit line pillar 105 are prepared in steps, and the groove 105 presents a morphology that is wide at the top and narrow at the bottom, it is beneficial for the bit line contact layer 103 formed based on the groove 120 to present a morphology that is wide at the top and narrow at the bottom. Therefore, after the bit line contact layer 103 is formed, when the bit line pillar 104 is formed, it is beneficial to reduce the difficulty of alignment between the bit line pillar 104 and the bit line contact layer 103, so as to improve the alignment accuracy between the bit line pillar 104 and the bit line contact layer 103, and it is beneficial to increase the contact area between the bit line pillar 104 and the bit line contact layer 103, so as to reduce the contact resistance between the bit line pillar 104 and the bit line contact layer 103, thereby helping to improve the conductive performance of the bit line structure 105.

[0082] It is understandable that, based on different requirements, the bit line contact layer 103 can only fill the groove 120, or it can fill the groove 120 and also be located in a partial area of ​​the substrate top surface 100a. Based on the difference in the bit line contact layer 103, the connection relationship between the bit line column 104 and the bit line contact layer 103 is also different, and the formed bit line structure 105 is also different.

[0083] The process steps of forming the bit line contact layer 103 and the bit line pillar 104 are described in detail below through two embodiments.

[0084] In some embodiments, reference Figures 17 to 19 The step of forming the bit line contact layer 103 may include: forming the bit line contact layer 103 filling the remaining portion of the groove 120 , the bit line contact layer 103 and the groove 120 corresponding to each other one by one.

[0085] In some embodiments, reference Fig.17 , the second sidewall layer 102 and a portion of the active area 110 together enclose a third sub-recess 150; the step of forming the bit line contact layer 103 that only fills the remaining portion of the recess 120 may include: referring to Fig.18 , forming a bit line contact film 113, the bit line contact film 113 fills the third sub-groove 150 and is located on the top surface of the first dielectric layer 106; combined with reference Figure 18 to Figure 19 The top surface of the first sidewall layer 101 is used as an etching stop layer to planarize the bit line contact film 113 to form a plurality of bit line contact layers 103 arranged at intervals along the second direction Y. It can be understood that one bit line contact layer 103 corresponds to one active area 110 .

[0086] refer to Figure 20 to Figure 23 as well as Fig.25 The step of forming a bit line pillar 104 may include: forming a bit line pillar 104 that is in contact with and connected to a plurality of bit line contact layers 103 arranged at intervals along the second direction Y, wherein the bit line pillar 104 and the plurality of bit line contact layers 103 in contact with and connected to the bit line pillar 104 constitute a bit line structure 105.

[0087] In some embodiments, reference Fig.21 , Fig.23 or Fig.25 , the step of forming the bitline pillar 104 may include: forming the bitline pillar 104 covering at least a portion of the top surface of the bitline contact layer 103 along the first direction X. It is understood that the orthographic projection area of ​​the bitline pillar 104 on the substrate top surface 100a may be less than or equal to the orthographic projection area of ​​the bitline contact layer 103 on the substrate top surface 100a, that is, the orthographic projection of the bitline pillar 104 on the substrate top surface 100a is located in the orthographic projection of the bitline contact layer 103 on the substrate top surface 100a. In other words, along the first direction X, the bitline pillar 104 having a width less than or equal to the maximum width of the bitline contact layer 103 is formed.

[0088] This is beneficial in ensuring a larger contact area between the bit line contact layer 103 and the bit line column 104 while ensuring that the subsequently formed isolation layer completely covers the exposed surface of the bit line structure 105, and in preventing the isolation layer from being pierced when the capacitor contact hole is subsequently formed between adjacent bit line structures 105, so as to prevent the capacitor contact hole from exposing the bit line structure 105 and causing a short circuit between the subsequently formed capacitor structure and the bit line structure 105.

[0089] In some embodiments, the step of forming the bit line pillar 104 may include: referring to Fig. 20 , a diffusion barrier film 114, a conductive film 124 and an isolation film 134 are sequentially stacked on a surface formed by the bit line contact layer 103, the first side wall layer 101, the second side wall layer 102 and the substrate top surface 100a; Fig. 20 and Fig.21 The diffusion barrier film 114, the conductive film 124 and the isolation film 134 are patterned to form a plurality of diffusion barrier layers 144 arranged at intervals along the first direction X, a plurality of conductive layers 154 arranged at intervals along the first direction X and a plurality of isolation layers 164 arranged at intervals along the first direction X. A diffusion barrier layer 144, a conductive layer 154 and an isolation layer 164 constitute a bit line pillar 104.

[0090] It can be understood that the bit line contact layer 103 has been prepared before the diffusion barrier film 114, the conductive film 124 and the isolation film 134 are formed. Therefore, in the step of patterning the diffusion barrier film 114, the conductive film 124 and the isolation film 134, the bit line contact layer 103 will not be etched, so that no etching residue will be formed in the groove 120, and only the diffusion barrier film 114, the conductive film 124 and the isolation film 134 need to be patterned to form the bit line column 104, that is, in the step of patterning, the etching depth of each area is not much different, which is beneficial to improve the etching uniformity in the step of patterning, thereby helping to improve the yield of the formed bit line column 104, so as to ultimately improve the yield of the formed bit line structure 105.

[0091] In addition, the diffusion barrier layer 144 is provided to prevent the elements in the conductive layer 154 from diffusing into the bit line contact layer 103, thereby preventing the performance of the bit line contact layer 103 from being affected. In some embodiments, the material of the diffusion barrier layer 144 may be titanium nitride.

[0092] In some embodiments, the conductive layer 154 may be made of metal materials such as tungsten. It is understood that setting the conductive layer 154 to be made of metal materials is beneficial to improving the transmission rate of the bit line structure 105 as a whole to transmit electrical signals.

[0093] In some embodiments, the isolation layer 164 may be made of insulating materials such as silicon nitride.

[0094] In some embodiments, in conjunction with reference Fig.19 and Fig. 20 After forming the bit line contact layer 103 and before forming the bit line pillar 104, for example, before forming the diffusion barrier film 114, the conductive film 124 and the isolation film 134, the first dielectric layer 106 is removed. In this way, the bit line pillar 104 formed subsequently is in contact with the bit line contact layer 103, and the other part of the bit line pillar 104 is in contact with the substrate top surface 100a; continue to combine with reference Fig.19 and Fig. 20 , a seventh dielectric layer 176 is formed at the removed first dielectric layer 106; in combination with reference Fig. 20 and Fig.21 The diffusion barrier film 114 , the conductive film 124 , and the isolation film 134 are patterned to form a plurality of bit line pillars 104 arranged at intervals along the first direction X.

[0095] In other embodiments, in combination with reference Fig.19 and Fig. 22After forming the bit line contact layer 103 and before forming the bit line pillar 104, for example, before forming the diffusion barrier film 114, the conductive film 124 and the isolation film 134, the first dielectric layer 106 is not removed, and in the subsequent step of patterning the diffusion barrier film 114, the conductive film 124 and the isolation film 134, the first dielectric layer 106 is also patterned. Fig.23 In addition to being in contact with the bit line contact layer 103, the formed bit line pillar 104 also has a first dielectric layer 106 between the other part of the bit line pillar 104 and the top surface 100a of the substrate. Fig.23 A seventh dielectric layer 176 is further formed between the remaining first dielectric layer 106 and the first sidewall layer 101. It should be noted that the first dielectric layer 106 is a conductive material, such as polysilicon, and the material of the seventh dielectric layer 176 may be silicon oxide.

[0096] In other embodiments, reference Fig.17 , Fig.18 and Fig.24 The step of forming the bit line contact layer 103 includes: forming the bit line contact layer 103 filling the remaining parts of the plurality of grooves 120 arranged at intervals along the second direction Y, the bit line contact layer 103 is also located on the top surface of the substrate 100 and extends along the second direction Y;

[0097] In some embodiments, reference Fig.17 , the second sidewall layer 102 and a portion of the active area 110 together enclose a third sub-recess 150; the step of forming the bit line contact layer 103 filling the remaining portions of the plurality of recesses 120 arranged at intervals along the second direction Y may include: combining with reference Fig.17 and Fig.18 , forming a bit line contact film 113, the bit line contact film 113 fills the third sub-groove 150 and is located on the top surface of the first dielectric layer 106; combined with reference Fig.18 and Fig.24 The bit line contact film 113 is patterned to remove the bit line contact film 113 located on the top surface of the first dielectric layer 106 to form a bit line contact layer 103 extending along the second direction Y, wherein the bit line contact layer 103 fills a plurality of third sub-grooves 150 arranged at intervals along the second direction Y.

[0098] exist Fig.24 Based on the bit line contact layer 103 shown in FIG. 1 , the steps of forming the bit line pillar 104 include: referring to Fig.25 A bit line pillar 104 is formed on a side of the bit line contact layer 103 away from the substrate 100 , and the bit line pillar 104 and the bit line contact layer 103 in contact with the bit line pillar 104 constitute a bit line structure 105 .

[0099] In some embodiments, before forming the bitline pillars 104, a seventh dielectric layer 176 is formed between adjacent bitline contact layers 103. It should be noted that the method of forming the seventh dielectric layer 176 and the bitline pillars 104 is the same as or corresponds to the above embodiment, and is not described in detail here.

[0100] In some embodiments, the step of providing the substrate 100 may include: referring to Fig.26 , providing a substrate 190, the substrate 190 having a plurality of active regions 110 arranged at intervals along a first direction X and a shallow trench isolation structure 108 located between adjacent active regions 110; a fourth dielectric layer 136, a fifth dielectric layer 146 and a sixth dielectric layer 156 are stacked on the substrate 190. It can be understood that, referring to Figure 26 to Figure 27 In the step of patterning the base 100 , the active area 110 , the fourth dielectric layer 136 , the fifth dielectric layer 146 and the sixth dielectric layer 156 in the substrate 190 are all patterned to form a groove 120 .

[0101] In some embodiments, the fourth dielectric layer 136 and the sixth dielectric layer 156 are made of the same material and different from the material of the fifth dielectric layer 146. For example, the fourth dielectric layer 136 and the sixth dielectric layer 156 can be made of silicon oxide, and the fifth dielectric layer 146 can be made of silicon nitride.

[0102] It should be noted that Fig.26 and Fig. 27 In the figure, only three dielectric layers stacked on the substrate 190, namely the fourth dielectric layer 136, the fifth dielectric layer 146 and the sixth dielectric layer 156 are taken as an example. In actual applications, the number of dielectric layers stacked on the substrate 190 and the materials of the dielectric layers can be set according to actual needs.

[0103] It should be noted that the following Fig.21 The semiconductor structure shown is an example, and the subsequent process steps are described in detail. In practical applications, the bit line pillar 104 can also be as follows Fig.24 or Fig.25 shown.

[0104] In some embodiments, reference Fig.21 , Figure 28 to Figure 29 After the bit line pillar 104 is formed, the manufacturing method may further include the following steps:

[0105] refer to Fig.28 , forming a first sidewall spacer 107 located on the sidewall of the bit line pillar 104, and the first sidewall spacer 107 is also at least located on the top surface 101a of the first sidewall layer.

[0106] In some embodiments, the orthographic projections of the bitline pillar 104 and the bitline contact layer 103 on the substrate top surface 100a overlap, and the first spacer layer 107 may be located only on the first sidewall layer top surface 101a, or the first spacer layer 107 may be located on the first sidewall layer top surface 101a and on a portion of the substrate top surface 100a. In other embodiments, the orthographic projection of the bitline pillar 104 on the substrate top surface 100a is located in the orthographic projection of the bitline contact layer 103 on the substrate top surface 100a, and the orthographic projection area of ​​the bitline pillar 104 on the substrate top surface 100a is smaller than the orthographic projection area of ​​the bitline contact layer 103 on the substrate top surface 100a, that is, a portion of the top surface of the bitline contact layer 103 is not covered by the bitline pillar 104, and the first spacer layer 107 is located on the top surface 101a of the first sidewall layer and is also located on the top surface of the bitline contact layer 103 that is not covered by the bitline pillar 104.

[0107] It should be noted that no matter what the positional relationship between the bit line pillar 104 and the bit line contact layer 103 is, the first side wall layer 107 and the first side wall layer 101 are in contact and connected, so that the side wall of the bit line structure 105 can be jointly covered by the first side wall layer 107 and the first side wall layer 101 to ensure the protection effect of the bit line structure 105, and to improve the insulation effect between the bit line structure 105 and the subsequently formed capacitor structure, so as to avoid the capacitor structure and the bit line structure 105 being electrically connected when the capacitor structure is subsequently formed.

[0108] Continue to refer Fig.28 , forming a second spacer 117 located on the side of the first spacer 107 away from the bit line pillar 104, and the second spacer 117 is also located on the top surface of the second sidewall layer 102. The material of the first spacer 107 can be silicon oxide, and the material of the second spacer 117 can be silicon nitride.

[0109] In other embodiments, reference Fig.29, a first spacer layer 107, a second spacer layer 117 and a third spacer layer 127 are sequentially formed on the sidewall of the bit line pillar 104, the first spacer layer 107 is located on the sidewall of the bit line pillar 104 and at least on the top surface 101a of the first sidewall layer, the second spacer layer 117 is located on the side of the first spacer layer 107 away from the bit line pillar 104, and the third spacer layer 127 can also be formed as a third spacer layer 127 located on the side of the second spacer layer 117 away from the first spacer layer 107. The combined spacer layer composed of the first spacer layer 107, the second spacer layer 117 and the third spacer layer 127 is conducive to improving the insulation effect between the bit line structure 105 and the capacitor structure formed subsequently, and effectively avoiding short circuits between adjacent bit line structures 105. The materials of the first spacer layer 107 and the third spacer layer 127 can be silicon nitride, and the material of the second spacer layer 117 can be silicon oxide. It can be understood that, on the one hand, the two silicon nitride layers are beneficial to improving the supporting strength of the combined sidewall layer to the bit line structure 105, avoiding the collapse of the bit line structure 105, so as to improve the yield of the formed bit line structure 105. On the other hand, the middle silicon oxide layer is beneficial to improving the overall dielectric constant of the combined sidewall layer, so as to improve the insulation effect between the bit line structure 105 and the subsequently formed capacitor structure.

[0110] It should be noted that Figure 4 The bit line BL in the Fig.28 The combined structure of the midline structure 105, the first spacer layer 107 and the second spacer layer 117 can also be regarded as Fig.29 A combined structure of the midline structure 105 , the first spacer layer 107 , the second spacer layer 117 and the third spacer layer 127 .

[0111] To summarize, in the step of forming the bit line structure 105, a bit line contact layer 103 is first formed which is at least partially embedded in the substrate 100 and in contact with the active area 110, and a first side wall layer 101 and a second side wall layer 102 are formed between the groove side wall 120b and the bit line contact layer 103 to prevent the bit line contact layer 103 from contacting the substrate 100 other than the active area 110 in contact with it; then a bit line column 104 extending along the second direction Y is formed, so that the bit line column 104 and at least one bit line contact layer 103 in contact with it constitute the bit line structure 105. In this way, on the one hand, before forming the bit line contact layer 103, the first side wall layer 101 and the second side wall layer 102 have been formed in the groove 120, which is conducive to avoiding the short circuit between the bit line contact layer 103 and other conductive structures subsequently formed on the substrate 100, such as the capacitor structure, that is, the first side wall layer 101 and the second side wall layer 102 can effectively avoid the unnecessary electrical connection between the bit line contact layer 103 and other conductive structures subsequently formed on the substrate 100; on the other hand, the bit line contact layer 103 and the bit line pillar 104 are prepared separately, so that when preparing the bit line pillar 104, there will be no unnecessary impact on the already formed bit line contact layer 103, and it is conducive to forming a larger bit line contact layer 103, so as to improve the alignment accuracy between the bit line pillar 104 and the bit line contact layer 103, and to increase the contact area between the bit line pillar 104 and the bit line contact layer 103, so as to reduce the contact resistance between the bit line pillar 104 and the bit line contact layer 103. Therefore, the process steps of first forming the first sidewall layer 101 and the second sidewall layer 102, then forming the bitline contact layer 103, and then forming the bitline pillar 104 are beneficial to improving the yield of the formed bitline structure 105, so as to improve the electrical performance of the semiconductor structure.

[0112] Another embodiment of the present disclosure further provides a semiconductor structure, which is formed by the manufacturing method provided in the above embodiment. The semiconductor structure provided in another embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above embodiment will not be repeated here.

[0113] refer to Fig.21 , Fig.23 or Fig.25 The semiconductor structure includes: a groove 120 (reference Figure 6) of a substrate 100, a groove 120 extending from a top surface 100a of the substrate into the substrate 100, and the groove 120 corresponds to an active area 110 one by one and exposes a portion of the active area 110; a first sidewall layer 101, covering the sidewall of the groove 120; a second sidewall layer 102, covering a side of the first sidewall layer 101 away from the sidewall of the groove 120; a bit line contact layer 103, at least filling the remaining portion of the groove 120; a bit line column 104 extending along a second direction Y, the bit line column 104 being in contact with and connected to at least one bit line contact layer 103, and the bit line column 104 and the at least one bit line contact layer 103 in contact with it constitute a bit line structure 105, and the first direction X and the second direction Y intersect.

[0114] It can be understood that the contact connection relationship between the bit line pillar 104 and the bit line contact layer 103 includes at least the following three embodiments.

[0115] In some embodiments, reference Fig.21 or Fig.23 , the bit line contact layer 103 and the groove 120 (reference Figure 6 ), the bit line pillars 104 are in contact and connected with a plurality of bit line contact layers 103 arranged at intervals along the second direction Y, and a bit line pillar 104 and the plurality of bit line contact layers 103 in contact and connected therewith constitute a bit line structure 105.

[0116] In other embodiments, reference Fig.25 The bit line contact layer 103 is along the second direction Y (reference Figure 4 ) extends and fills a plurality of grooves 120 arranged at intervals along the second direction Y (reference Figure 6 ), a bit line pillar 104 and a bit line contact layer 103 in contact therewith constitute a bit line structure 105. It can be understood that the bit line contact layer 103 corresponds to a plurality of grooves 120 arranged at intervals along the second direction Y.

[0117] In some other embodiments, according to actual needs, part of the bitline contact layers and the grooves can be made to correspond one to one, that is, part of the bitline pillars and the multiple bitline contact layers in contact with them constitute a bitline structure; and the remaining part of the bitline contact layers can extend along the second direction, that is, a bitline pillar and a bitline contact layer in contact with it constitute a bitline structure.

[0118] In some embodiments, reference Fig.21 , Fig.23 or Fig.25, along the direction from the bit line pillar 104 to the bit line contact layer 103, the width of the bit line contact layer 103 in the first direction X gradually decreases. In this way, it is beneficial to increase the contact area between the bit line pillar 104 and the bit line contact layer 103, thereby facilitating the reduction of the difficulty of alignment between the bit line pillar 104 and the bit line contact layer 103, thereby improving the alignment accuracy between the bit line pillar 104 and the bit line contact layer 103, and reducing the contact resistance between the bit line pillar 104 and the bit line contact layer 103, thereby facilitating the improvement of the conductive performance of the bit line structure 105.

[0119] In some embodiments, the orthographic projection of the bit line pillar 104 on the substrate top surface 100a is located in the orthographic projection of the bit line contact layer 103 on the substrate top surface 100a, and the orthographic projection area of ​​the bit line pillar 104 on the substrate top surface 100a is less than or equal to the orthographic projection area of ​​the bit line contact layer 103 on the substrate top surface 100a.

[0120] In some embodiments, reference Fig.28 The semiconductor structure may further include: a first sidewall layer 107, located on the sidewall of the bit line pillar 104, and at least located on the top surface of the first sidewall layer 101; a second sidewall layer 117, located on a side of the first sidewall layer 107 away from the bit line pillar 104, and also located on the top surface of the second sidewall layer 102.

[0121] It should be noted that the first sidewall layer 107 is at least located on the top surface of the first sidewall layer 101 and includes at least the following three embodiments.

[0122] In some embodiments, reference Fig.28 The orthographic projections of the bit line pillar 104 and the bit line contact layer 103 on the substrate top surface 100 a overlap, and the first spacer layer 107 may be located only on the first sidewall layer top surface 101 a .

[0123] In some other embodiments, the orthographic projections of the bit line pillar 104 and the bit line contact layer 103 on the substrate top surface 100 a coincide with each other, and the first spacer layer 107 may be located on the first sidewall layer top surface 101 a and on a portion of the substrate top surface 100 a .

[0124] In some other embodiments, the orthographic projection of the bit line pillar 104 on the top surface 100a of the substrate is located in the orthographic projection of the bit line contact layer 103 on the top surface 100a of the substrate, and the orthographic projection area of ​​the bit line pillar 104 on the top surface 100a of the substrate is smaller than the orthographic projection area of ​​the bit line contact layer 103 on the top surface 100a of the substrate, that is, part of the top surface of the bit line contact layer 103 is not covered by the bit line pillar 104, then the first side wall layer 107 is located on the top surface 101a of the first side wall layer and also on the top surface of the bit line contact layer 103 not covered by the bit line pillar 104.

[0125] In some embodiments, reference Fig.29On the premise that the sidewalls of the bit line pillar 104 are sequentially covered by the first spacer layer 107 and the second spacer layer 117 , the semiconductor structure may further include: a third spacer layer 127 located on a side of the second spacer layer 117 away from the first spacer layer 107 .

[0126] In summary, the first sidewall layer 101 and the second sidewall layer 102 are conducive to avoiding the short circuit phenomenon between the bit line contact layer 103 and other conductive structures, such as capacitor structures, formed on the substrate 100 later, that is, the first sidewall layer 101 and the second sidewall layer 102 can effectively avoid the unnecessary electrical connection phenomenon between the bit line contact layer 103 and other conductive structures formed on the substrate 100 later. Moreover, compared with the size of the bit line pillar 104, the size of the bit line contact layer 103 can be larger, which is conducive to improving the alignment accuracy between the bit line pillar 104 and the bit line contact layer 103, and is conducive to improving the contact area between the bit line pillar 104 and the bit line contact layer 103, so as to reduce the contact resistance between the bit line pillar 104 and the bit line contact layer 103. Therefore, it is conducive to improving the yield of the bit line structure 105, so as to improve the electrical performance of the semiconductor structure.

[0127] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a plurality of active regions arranged at intervals along a first direction; Performing a patterning process on the substrate to form a plurality of grooves extending from the top surface of the substrate to the inside of the substrate, wherein the grooves correspond to the active areas one by one, and the grooves expose a portion of the active areas; sequentially forming a first side wall layer and a second side wall layer on the side wall of the groove; forming a bit line contact layer that at least fills the remaining portion of the groove; A bit line column extending along a second direction is formed, wherein the bit line column is in contact with at least one of the bit line contact layers, and the bit line column and the at least one of the bit line contact layers in contact with the bit line column constitute a bit line structure, wherein the first direction intersects with the second direction.

2. The manufacturing method according to claim 1, characterized in that: The step of forming the bit line contact layer comprises: forming the bit line contact layer filling the remaining portion of the groove, wherein the bit line contact layer corresponds to the groove one by one; The step of forming the bit line pillar comprises: The bit line pillar is formed to be in contact with and connected to the plurality of bit line contact layers arranged at intervals along the second direction. The bit line pillar and the plurality of bit line contact layers in contact with and connected to the bit line pillar constitute a bit line structure.

3. The manufacturing method according to claim 1, characterized in that: The step of forming the bit line contact layer comprises: forming the bit line contact layer filling the remaining parts of the plurality of grooves arranged at intervals along the second direction, wherein the bit line contact layer is also located on the top surface of the substrate and extends along the second direction; The step of forming the bit line pillar comprises: The bit line pillar is formed on a side of the bit line contact layer away from the substrate. The bit line pillar and the bit line contact layer in contact with the bit line pillar constitute a bit line structure.

4. The manufacturing method according to claim 1, characterized in that: The step of forming the groove includes: forming the groove whose width gradually decreases in the first direction along the top surface of the substrate and in a direction pointing into the substrate.

5. The manufacturing method according to any one of claims 1 to 4, characterized in that: The step of forming the groove further includes: forming a first dielectric layer on the top surface of the substrate, wherein the groove is surrounded by the substrate and the first dielectric layer; The steps of forming the first sidewall layer and the second sidewall layer include: forming a first sidewall film, wherein the first sidewall film conformally covers the inner wall of the groove and the top surface of the first dielectric layer; forming a second sidewall film, wherein the second sidewall film conformally covers a surface of the first sidewall film away from the substrate; The first dielectric layer is used as an etching stop layer, and the first sidewall film and the second sidewall film are etched back to remove the first sidewall film and the second sidewall film located on the top surface of the substrate and the bottom surface of the groove, and the remaining first sidewall film serves as the first sidewall layer, and the remaining second sidewall film serves as the second sidewall layer.

6. The manufacturing method according to any one of claims 1 to 4, characterized in that: The step of forming the groove further includes: forming a first dielectric layer and a second dielectric layer stacked on the top surface of the substrate, wherein the groove is surrounded by the substrate, the first dielectric layer and the second dielectric layer; The step of forming the first sidewall layer comprises: forming a first sidewall film, wherein the first sidewall film conformally covers the inner wall of the groove and the top surface of the second dielectric layer; Using the second dielectric layer as an etching stop layer, etching back the first sidewall film to remove the first sidewall film located on the top surface of the second dielectric layer and the bottom surface of the groove; The first sidewall film located on the sidewall of the second dielectric layer is removed, and the remaining first sidewall film serves as the first sidewall layer.

7. The manufacturing method according to claim 6, characterized in that: The first sidewall layer and a portion of the active area together form a first sub-recess; The step of forming the second sidewall layer comprises: forming a second sidewall film, wherein the second sidewall film conformally covers the inner wall of the first sub-groove, the top surface of the second dielectric layer and the top surface of the first sidewall layer; Using the second dielectric layer as an etching stop layer, etching back the second sidewall film to remove the second sidewall film located on the top surface of the second dielectric layer and the bottom surface of the first sub-recess, and the remaining second sidewall film and a portion of the active area together form a second sub-recess; forming a third dielectric layer, wherein the second dielectric layer completely fills the second sub-groove; The removing of the first sidewall film located on the sidewall of the second dielectric layer includes: using the first dielectric layer as an etching stop layer, removing the second dielectric layer, and etching the first sidewall film and the second sidewall film to remove the first sidewall film and the second sidewall film located on the sidewall of the second dielectric layer, and the remaining second sidewall film serves as the second sidewall layer.

8. The manufacturing method according to claim 7, characterized in that: The second sidewall layer and part of the active area together form a third sub-recess; the step of forming the bit line contact layer comprises: A bit line contact film is formed, which fills the third sub-recess and is located on the top surface of the first dielectric layer; the top surface of the first sidewall layer is used as an etching stop layer, and the bit line contact film is planarized to form a plurality of the bit line contact layers arranged at intervals along the second direction.

9. The manufacturing method according to claim 7, characterized in that: The second sidewall layer and part of the active area together form a third sub-recess; the step of forming the bit line contact layer comprises: A bit line contact film is formed, the bit line contact film fills the third sub-groove and is located on the top surface of the first dielectric layer; the bit line contact film is patterned to remove the bit line contact film located on the top surface of the first dielectric layer to form the bit line contact layer extending along the second direction, the bit line contact layer fills the plurality of third sub-grooves spaced apart along the second direction.

10. The manufacturing method according to claim 1, characterized in that: The step of forming the bit line pillar includes: forming the bit line pillar along the first direction to cover at least a portion of the top surface of the bit line contact layer.

11. The manufacturing method according to claim 1, characterized in that: After forming the bit line pillar, the method further includes: forming a first spacer layer located on the side wall of the bit line pillar, wherein the first spacer layer is also at least located on the top surface of the first sidewall layer; A second spacer layer is formed on a side of the first spacer layer away from the bit line pillar, and the second spacer layer is also located on a top surface of the second sidewall layer.

12. A semiconductor structure, characterized in that: include: A substrate having a groove, wherein the groove extends from the top surface of the substrate into the substrate, and the groove corresponds to the active area one by one and exposes a portion of the active area; A first sidewall layer, covering the sidewall of the groove; A second sidewall layer, covering a side of the first sidewall layer away from the sidewall of the groove; A bit line contact layer at least fills the remaining portion of the groove; A bit line pillar extends along a second direction, the bit line pillar is in contact with at least one of the bit line contact layers, and the bit line pillar and the at least one of the bit line contact layers in contact with the bit line pillar constitute a bit line structure, and the first direction and the second direction intersect.

13. The semiconductor structure according to claim 12, characterized in that: The bit line contact layers and the grooves correspond to each other one by one, the bit line pillars are in contact with and connected to a plurality of the bit line contact layers arranged at intervals along the second direction, and a bit line pillar and a plurality of the bit line contact layers in contact with and connected to it constitute a bit line structure; and / or, The bit line contact layer extends along the second direction and fills the remaining parts of the plurality of grooves arranged at intervals along the second direction. A bit line column and a bit line contact layer in contact with the bit line column constitute a bit line structure.

14. The semiconductor structure according to claim 12 or 13, characterized in that: Along the direction from the bit line pillar to the bit line contact layer, the width of the bit line contact layer in the first direction gradually decreases.

15. The semiconductor structure according to claim 12 or 13, characterized in that: Also includes: A first sidewall layer, located on the sidewall of the bit line pillar, and at least located on the top surface of the first sidewall layer; The second sidewall layer is located on a side of the first sidewall layer away from the bit line pillar and is also located on a top surface of the second sidewall layer.

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