Semiconductor devices and their manufacturing methods, memory systems

Abstract

This application provides a semiconductor device and a method for manufacturing the same, as well as a memory system, comprising: a plurality of channel structures extending along a first direction, the channel structures including a first channel end and a second channel end opposite to each other in the first direction; a first gate extending along the first direction, located between adjacent channel structures, and the first gate including a first gate top surface and a first gate bottom surface opposite to each other in the first direction, the first gate top surface being close to the first channel end; and a second gate extending along the first direction, located on the side of the channel structure opposite to the first gate in a second direction, and the second gate including a second gate top surface and a second gate bottom surface opposite to each other in the first direction, the second gate bottom surface being close to the second channel end, wherein in the first direction, the second gate top surface is located on the side of the first gate top surface near the first channel end, and the first gate bottom surface is located on the side of the second gate bottom surface near the second channel end, and the first direction intersects the second direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method, and a memory system. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is an important type of memory. A DRAM storage cell mainly consists of a storage capacitor and a transistor connected in series with the storage capacitor. The storage capacitor stores data, and the transistor controls the storage of data within the capacitor.

[0003] Currently, the storage density of dynamic random access memory (DRAM) needs to be further improved, and how to increase the storage density of DRAM is a technical problem that needs to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and its manufacturing method, as well as a storage system, which is beneficial to improving the storage density of semiconductor devices.

[0005] In a first aspect, this application provides a semiconductor device, comprising:

[0006] A plurality of channel structures extending along a first direction, the channel structures including a first channel end and a second channel end opposite to each other in the first direction;

[0007] A first gate extending along the first direction is located between adjacent channel structures, and the first gate includes a first gate top surface and a first gate bottom surface opposite each other in the first direction, the first gate top surface being close to the first channel end; and

[0008] The second gate extends along the first direction and is located on the side of the channel structure opposite to the first gate in the second direction. The second gate includes a second gate top surface and a second gate bottom surface opposite to each other in the first direction. The second gate bottom surface is close to the second channel end. In the first direction, the second gate top surface is located on the side of the first gate top surface close to the first channel end, and the first gate bottom surface is located on the side of the second gate bottom surface close to the second channel end. The first direction intersects the second direction.

[0009] In some embodiments, in the first direction, the second gate bottom surface is located on the side of the first gate top surface close to the first gate bottom surface.

[0010] In some embodiments, in the second direction, the top surface of the first gate is aligned with the bottom surface of the second gate.

[0011] In some embodiments, in the first direction, the second gate bottom surface is located on the side of the first gate top surface away from the first gate bottom surface.

[0012] In some embodiments, it also includes:

[0013] A first bottom insulating portion, in the first direction, is located on the side of the bottom surface of the first gate away from the top surface of the first gate and is in contact with the bottom surface of the first gate; and

[0014] The second bottom insulating portion, in the first direction, is located on the side of the bottom surface of the second gate away from the top surface of the second gate and is in contact with the bottom surface of the second gate, and the size of the second bottom insulating portion in the first direction is larger than the size of the first bottom insulating portion in the first direction.

[0015] In some embodiments, the second bottom insulating portion includes an insulating core and a protective layer, the protective layer covering the sidewalls of the insulating core and the bottom wall of the insulating core away from the second gate, the material of the insulating core being different from the material of the protective layer.

[0016] In some embodiments, it also includes:

[0017] A first top insulating portion, in the first direction, is located on the side of the first gate top surface away from the first gate bottom surface and is in contact with the first gate top surface; and

[0018] The second top insulating portion, in the first direction, is located on the side of the second gate top surface away from the second gate bottom surface and is in contact with the second gate top surface, and the size of the second top insulating portion in the first direction is smaller than the size of the first top insulating portion in the first direction.

[0019] In some embodiments, a plurality of first gates and a plurality of second gates are arranged alternately and at intervals along the second direction, and the first gates and the second gates also extend along a third direction, which intersects the first direction and the second direction;

[0020] The first gate is offset from the second gate at its opposite ends in the third direction.

[0021] In some embodiments, the dimension of the first gate in the third direction is different from the dimension of the second gate in the third direction.

[0022] In some embodiments, the first gate includes a first gate end and a second gate end that are upwardly opposite to the third party;

[0023] The second gate includes a third gate end and a fourth gate end that are opposite to the third gate end, the third gate end being close to the first gate end;

[0024] The semiconductor device further includes:

[0025] At least one first gate contact is connected to the first gate terminal of at least one first gate; and

[0026] At least one second gate contact is connected to the third gate terminal of at least one second gate.

[0027] In some embodiments, in two adjacent first gates, the first gate end of one first gate is connected to one first gate contact, and the second gate end of the other first gate is connected to the other first gate contact.

[0028] In two adjacent second gates, the third gate terminal of one second gate is connected to a second gate contact, and the fourth gate terminal of the other second gate is connected to the other second gate contact.

[0029] In some embodiments, the first gate includes a first gate end and a second gate end that are upwardly opposite to the third party;

[0030] The second gate includes a third gate end and a fourth gate end that are opposite to the third gate end, the third gate end being close to the first gate end;

[0031] The semiconductor device further includes:

[0032] At least one first gate contact is connected to the first gate terminal of at least one first gate; and

[0033] At least one second gate contact is connected to the fourth gate terminal of at least one second gate.

[0034] In some embodiments, the first gate terminals of two adjacent first gates are respectively connected to two first gate contacts, and the fourth gate terminals of two adjacent second gates are respectively connected to two second gate contacts.

[0035] Secondly, this application also provides a method for manufacturing a semiconductor device, the method comprising:

[0036] Multiple active pillars are formed extending along a first direction, the active pillars including a first end and a second end opposite to each other in the first direction;

[0037] A first gate extending along the first direction is formed between adjacent active pillars, the first gate including a first gate top surface and a first gate bottom surface opposite each other in the first direction, the first gate top surface being close to the first end; and

[0038] A second gate is formed extending along the first direction. The second gate is located on the side of the active post opposite to the first gate in the second direction. The second gate includes a second gate top surface and a second gate bottom surface opposite to each other in the first direction. The second gate bottom surface is close to the second end. In the first direction, the second gate top surface is located on the side of the first gate top surface close to the first end, and the first gate bottom surface is located on the side of the second gate bottom surface close to the second end. The first direction intersects the second direction.

[0039] In some embodiments of a semiconductor device manufacturing method, forming a plurality of active pillars extending along a first direction includes:

[0040] A first groove and a second groove are formed, which are arranged along the second direction and extend along the third direction. The first groove and the second groove intersect with the plurality of active lines. The first groove and the second groove are staggered at their opposite ends in the third direction. The third direction intersects with the first direction and the second direction.

[0041] The formation of a first gate extending along the first direction between adjacent active pillars includes: filling a first conductive layer in the first groove;

[0042] A portion of the first conductive layer near the first end is removed, and the remaining first conductive layer forms the first initial gate.

[0043] A portion of the first initial gate near the second end is removed, and the remaining portion of the first initial gate forms the first gate.

[0044] In some embodiments of a method for manufacturing a semiconductor device, the method further includes: filling a dielectric layer into the plurality of said recesses;

[0045] The removal of a portion of the first initial gate near the second end includes:

[0046] The second surface of the semiconductor layer is thinned to expose the dielectric layer, and a thinned third surface is formed.

[0047] An opening is formed in the dielectric layer to expose the first initial gate, the opening being recessed from the third surface toward the first surface;

[0048] The portion of the first initial gate near the second end is removed through the opening.

[0049] In some embodiments of a method for manufacturing a semiconductor device, the method further includes: forming a first bottom insulating portion on the first gate near the second end through the opening.

[0050] In some embodiments of a method for manufacturing a semiconductor device, before filling the first conductive layer into the first groove, the method further includes:

[0051] A sacrificial layer is formed in the first groove and the second groove;

[0052] A protective layer is formed covering the sacrificial layer in the second groove; and

[0053] Remove the sacrificial layer from the first groove.

[0054] In some embodiments of a semiconductor device manufacturing method, forming a second gate extending along the first direction includes:

[0055] Remove the protective layer and the sacrificial layer in the second groove;

[0056] A second bottom insulating portion is formed in the second groove, the dimension of the second bottom insulating portion in the first direction being smaller than the depth of the second groove; and

[0057] The second gate is formed on the second bottom insulating portion.

[0058] Thirdly, this application also provides a storage system, comprising:

[0059] Memory, including the semiconductor devices described in any of the above embodiments; and

[0060] A controller, connected to the memory, is used to control the memory.

[0061] The beneficial effects of some embodiments of this application include: in the second direction, the first gate and the second gate are respectively located on opposite sides of the channel structure. In the first direction, the top surface of the second gate is located on the side of the top surface of the first gate near the end of the first channel, and the bottom surface of the first gate is located on the side of the bottom surface of the second gate near the end of the second channel. With this design, at least a portion of the first gate is offset from the second gate in the first direction, and each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction, that is, each of the first gate and the second gate can control portions of two adjacent channel structures in the second direction to be in a conducting or cut-off state. Moreover, based on the fact that each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction, the dimensions of the first gate and the second gate in the second direction can be smaller, that is, it is beneficial to miniaturize the dimensions of the first gate and the second gate in the second direction, which is beneficial to increasing the number of the first gate, the second gate, and the channel structure, thereby increasing the storage density of the semiconductor device and improving the performance of the semiconductor device. Attached Figure Description

[0062] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this application;

[0063] Figure 2A This is a planar schematic diagram showing the formation of multiple active lines and a dielectric layer in a semiconductor layer in some embodiments of this application;

[0064] Figure 2B for Figure 2A A schematic diagram of the cross-sectional structure taken by the AA tangent;

[0065] Figure 2C This is a planar schematic diagram of a first groove and a second groove intersecting with multiple active lines in some embodiments of this application;

[0066] Figure 2D This is a planar schematic diagram showing the formation of a first groove and a second groove intersecting with multiple active lines in some other embodiments of this application;

[0067] Figure 2E For along Figure 2C A schematic diagram of the cross-sectional structure taken by the BB tangent;

[0068] Figure 3A This is a cross-sectional structural diagram of the sacrificial layer formed in the first and second grooves in some embodiments of this application;

[0069] Figure 3B This is a cross-sectional structural diagram showing the formation of a protective layer covering the sacrificial layer in the second groove and the removal of the sacrificial layer in the first groove in some embodiments of this application.

[0070] Figure 3C This is a cross-sectional structural diagram of a first conductive layer formed in a first groove in some embodiments of this application;

[0071] Figure 3D This is a schematic cross-sectional view of a first initial gate formed in a first groove in some embodiments of this application;

[0072] Figure 3E This is a schematic cross-sectional view of a first top insulating portion formed in a first groove on a first initial gate in some embodiments of this application;

[0073] Figure 3F This is a cross-sectional structural diagram showing the removal of the protective layer and the sacrificial layer in the second groove in some embodiments of this application;

[0074] Figure 3G This is a cross-sectional structural diagram of a second bottom insulating portion formed in a second groove in some embodiments of this application;

[0075] Figure 3H This is a cross-sectional structural diagram of a second bottom insulating portion formed in a second groove in some other embodiments of this application;

[0076] Figure 3I This is a schematic cross-sectional view of the second gate insulating layer and the second conductive layer formed in the second groove in some embodiments of this application;

[0077] Figure 3J This is a schematic diagram of the planar structure forming the second gate and the second top insulating portion in some embodiments of this application;

[0078] Figure 3K For along Figure 3J A schematic diagram of the cross-sectional structure intercepted by the CC tangent;

[0079] Figure 3L For along Figure 3J A schematic diagram of the cross-sectional structure taken by the DD tangent;

[0080] Figure 3M This is a schematic diagram of a planar structure in some embodiments of this application, showing the thinning of the second surface of a semiconductor layer to form a third surface;

[0081] Figure 3N For along Figure 3M A schematic diagram of the cross-sectional structure taken by the EE tangent;

[0082] Figure 3O For along Figure 3M A schematic diagram of the cross-sectional structure taken by the FF tangent;

[0083] Figure 3PThis is a schematic diagram of a planar structure forming an opening exposing the first initial gate and the second bottom insulating portion in some embodiments of this application;

[0084] Figure 3Q For along Figure 3P A schematic diagram of the cross-sectional structure taken by the GG tangent;

[0085] Figure 3R For along Figure 3P A schematic diagram of the cross-sectional structure taken by the HH tangent;

[0086] Figure 3S This is a schematic cross-sectional view of a first gate formed by etching back through an opening in some embodiments of this application, and forming a first bottom insulating portion.

[0087] Figure 3T This is a schematic cross-sectional view of the insulating filler layer forming the filling opening in some embodiments of this application;

[0088] Figure 3U This is a cross-sectional structural schematic diagram of a semiconductor device in some other embodiments of this application;

[0089] Figure 3V This is a cross-sectional structural schematic diagram of a semiconductor device in some other embodiments of this application;

[0090] Figure 4A This is a cross-sectional schematic diagram of the first gate, second gate, channel structure, first gate contact, and second gate contact in some embodiments of this application;

[0091] Figure 4B This is a cross-sectional schematic diagram of the first gate, second gate, channel structure, first gate contact, and second gate contact in some other embodiments of this application;

[0092] Figure 5 This is a block diagram of a storage system according to some embodiments of this application;

[0093] Figure 6 This is a block diagram of a storage system according to other embodiments of this application;

[0094] Figure 7 This is a block diagram of an electronic device according to some embodiments of this application.

[0095] The attached figures are labeled as follows:

[0096] z, first direction; y, second direction; x, third direction;

[0097] 10, Semiconductor layer; 10a, First surface; 10b, Second surface; 10c, First groove; 10d, Second groove; 101, Recess; 102, Active line; 103, Active pillar; 1031, First end; 1032, Second end; 1033, First electrode; 1034, Second electrode; 1035, Channel structure; 10351, First channel end; 10352, Second channel end; 10e, Third surface; 10f, Opening;

[0098] 111, dielectric layer; 112, first gate insulating layer; 113, second gate insulating layer;

[0099] 121, Mask pattern; 122, Sacrificial layer; 123, Protective layer; 124, Insulating filler layer;

[0100] 131, First conductive layer; 132, First initial gate; 133, First gate; 133a, First gate top surface; 133b, First gate bottom surface; 1331, First gate terminal; 1332, Second gate terminal; 134, Second conductive layer; 135, Second gate; 135a, Second gate top surface; 135b, Second gate bottom surface; 1351, Third gate terminal; 1352, Fourth gate terminal;

[0101] 141, First top insulating part; 1411, First air gap; 142, Second bottom insulating part; 1421, Insulating core part; 1422, Protective layer; 1423, Second air gap; 143, Second top insulating part; 144, First bottom insulating part;

[0102] 151, First gate contact; 152, Second gate contact;

[0103] 100, Semiconductor device; 200, Memory; 300, Controller; 400, Storage system; 500, Electronic device; 600, Host. Detailed Implementation

[0104] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0105] Please refer to Figure 1 The diagram shown is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this application. The method for manufacturing a semiconductor device includes the following steps:

[0106] Step S101: Form a plurality of active pillars extending along a first direction, wherein the active pillars include a first end and a second end opposite to each other in the first direction;

[0107] Step S102: A first gate extending along a first direction is formed between adjacent active pillars. The first gate includes a first gate top surface and a first gate bottom surface opposite each other in the first direction, with the first gate top surface close to the first end; and

[0108] Step S103: Form a second gate extending along a first direction. The second gate is located on the side of the active pillar away from the first gate in the second direction. The second gate includes a second gate top surface and a second gate bottom surface opposite to each other in the first direction. The second gate bottom surface is close to the second end. In the first direction, the second gate top surface is located on the side of the first gate top surface close to the first end, and the first gate bottom surface is located on the side of the second gate bottom surface close to the second end. The first direction intersects the second direction.

[0109] In some embodiments of this application, the above method is used to form a first gate and a second gate on both sides of the active pillar in the second direction. In the first direction, the top surface of the second gate is located on the side of the top surface of the first gate near the first end, and the bottom surface of the first gate is located on the side of the bottom surface of the second gate near the second end. Therefore, at least a portion of the first gate is offset from the second gate in the first direction, and each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction. That is, each of the first gate and the second gate can control portions of two adjacent channel structures in the second direction to be in a conducting or cut-off state. Moreover, based on the fact that each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction, the dimensions of the first gate and the second gate in the second direction can be smaller, which is beneficial for the miniaturization (scalability) of the dimensions of the first gate and the second gate in the second direction, and for increasing the number of the first gate and the second gate in the second direction, thereby increasing the storage density of the semiconductor device and improving the performance of the semiconductor device.

[0110] The manufacturing method of the above-mentioned semiconductor device will be described in detail below with reference to specific embodiments.

[0111] First, please refer to Figures 2A to 2E As shown, step S101 is performed: forming a plurality of active pillars 103 extending along the first direction z, the active pillars 103 including a first end 1031 and a second end 1032 opposite to each other in the first direction z.

[0112] In some embodiments, please refer to Figures 2A to 2EAs shown, forming a plurality of active pillars 103 extending along the first direction z includes: forming a plurality of recesses 101 in the semiconductor layer 10; the remaining semiconductor layer 10 includes a plurality of active lines 102 extending along the first direction z; the recesses 101 are recessed from a first surface 10a to a second surface 10b of the semiconductor layer 10; the first surface 10a and the second surface 10b are disposed opposite each other in the first direction z; and

[0113] A first groove 10c and a second groove 10d are formed, which are spaced apart along the second direction y and extend along the third direction x. The first groove 10c and the second groove 10d intersect with multiple active lines 102. The remaining active lines 102 form multiple active pillars 103. The two ends of the first groove 10c in the third direction x are offset from the two ends of the second groove 10d in the third direction x. The third direction x intersects with the first direction z and the second direction y.

[0114] In some embodiments, refer to Figure 2A and Figure 2B As shown, forming a plurality of recesses 101 in the semiconductor layer 10 includes: providing a semiconductor layer 10, the semiconductor layer 10 including a first surface 10a and a second surface 10b disposed opposite to each other in a first direction z; and

[0115] A portion of the semiconductor layer 10 is removed to form a plurality of recesses 101 extending along the first direction z and the second direction y and arranged along the third direction x. The remaining semiconductor layer 10 includes a plurality of active lines 102 extending along the first direction z and the second direction y and arranged at intervals along the third direction x. One active line 102 is located between two adjacent recesses 101. The recesses 101 are recessed from the first surface 10a to the second surface 10b.

[0116] In some embodiments, the material of the semiconductor layer 10 includes a single-element semiconductor material, which includes, but is not limited to, single-crystal silicon. Specifically, the semiconductor layer 10 includes a silicon wafer.

[0117] In some embodiments, any two of the first direction z, the second direction y, and the third direction x are perpendicular to each other, but are not limited thereto.

[0118] In some embodiments, the shape of the recess 101 along the cross-section parallel to the first direction z and the third direction x is rectangular, inverted trapezoidal, or other shape. The shape of the active line 102 along the cross-section parallel to the first direction z and the third direction x is rectangular, trapezoidal, or other shape. For example, the shape of the recess 101 along the cross-section parallel to the first direction z and the third direction x is rectangular; correspondingly, the shape of the active line 102 along the cross-section parallel to the first direction z and the third direction x is also rectangular.

[0119] In some embodiments, removing a portion of the semiconductor layer 10 includes: forming a mask pattern 121 on a first surface 10a of the semiconductor layer 10; using the mask pattern 121 as a mask, etching the semiconductor layer 10 to obtain a plurality of recesses 101.

[0120] In some embodiments, please continue to refer to Figure 2A and Figure 2B As shown, after forming a plurality of recesses 101, the method for manufacturing a semiconductor device further includes filling a dielectric layer 111 into the plurality of recesses 101.

[0121] In some embodiments of this application, the dielectric layer 111 isolates the plurality of active lines 102 from each other. The material of the dielectric layer 111 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0122] In some embodiments, please refer to Figure 2C , Figure 2D and Figure 2E As shown, forming a first groove 10c and a second groove 10d arranged along the second direction y and extending along the third direction x includes: removing a portion of the active line 102 and a portion of the dielectric layer 111 to form a first groove 10c and a second groove 10d arranged along the second direction y. The remaining active line 102 includes a plurality of active pillars 103 arranged in an array along the second direction y and the third direction x and extending along the first direction z.

[0123] In some embodiments of this application, the two opposite ends of the first groove 10c in the third direction x are staggered with the two opposite ends of the second groove 10d in the third direction x, so as to better distinguish the first groove 10c and the second groove 10d, and form different gates in the first groove 10c and the second groove 10d respectively. Moreover, when the different gates are led out separately, the process window for the lead-out structure of the different gates is larger.

[0124] In some embodiments, refer to Figure 2C As shown, both the first groove 10c and the second groove 10d are straight lines. The dimension of the first groove 10c along the third direction x is larger than the dimension of the second groove 10d along the third direction x. The opposite ends of the first groove 10c along the third direction x are located on both sides of the second groove 10d along the third direction x.

[0125] In some embodiments, refer to Figure 2DAs shown, the dimensions of the first groove 10c along the third direction x are the same as the dimensions of the second groove 10d along the third direction x. One end of the first groove 10c along the third direction x is adjacent to one end of the second groove 10d along the third direction x, and the other end of the first groove 10c along the third direction x is adjacent to the other end of the second groove 10d along the third direction x. One end of the first groove 10c along the third direction x protrudes beyond one end of the second groove 10d along the third direction x, and the other end of the second groove 10d along the third direction x protrudes beyond the other end of the first groove 10c along the third direction x.

[0126] In some embodiments, refer to Figure 2C and Figure 2D As shown, a plurality of first grooves 10c and a plurality of second grooves 10d are arranged alternately and at intervals along the second direction y in a one-to-one manner, but are not limited thereto.

[0127] In some embodiments, refer to Figure 2C and Figure 2E As shown, the dimensions of the first groove 10c along the first direction z and the second groove 10d along the first direction z can be the same, and the dimensions of the first groove 10c along the second direction y and the second groove 10d along the second direction y can also be the same, so as to simultaneously form the first groove 10c and the second groove 10d, simplifying the manufacturing process of semiconductor devices. In other embodiments, the dimensions of the first groove 10c along the second direction y and the second groove 10d along the second direction y can also be different, and the dimensions of the first groove 10c along the first direction z and the second groove 10d along the first direction z can also be different.

[0128] In some embodiments, refer to Figure 2E As shown, since multiple first grooves 10c and multiple second grooves 10d intersect with multiple active lines 102, the remaining active lines 102 include multiple active pillars 103. The multiple active pillars 103 are arranged in an array along a second direction y and a third direction x, and extend along a first direction z. A first groove 10c is disposed between two adjacent rows of active pillars 103 arranged along the second direction y, and a second groove 10d is disposed between two adjacent rows of active pillars 103 arranged along the second direction y. A row of active pillars 103 includes multiple active pillars 103 arranged side-by-side along the third direction x. Each active pillar 103 includes a first end 1031 and a second end 1032 opposite each other in the first direction z. The first end 1031 is away from the second surface 10b, and the second end 1032 is close to the second surface 10b.

[0129] In some embodiments, refer to Figure 3A and Figure 3BAs shown, after forming a first groove 10c and a second groove 10d arranged along a second direction y and extending along a third direction x, the method of manufacturing a semiconductor device further includes: forming a sacrificial layer 122 in the first groove 10c and the second groove 10d; forming a protective layer 123 covering the sacrificial layer 122 in the second groove 10d; and removing the sacrificial layer 122 in the first groove 10c.

[0130] In some embodiments of this application, before forming the first gate 133 in the first recess 10c, a sacrificial layer 122 is formed in the second recess 10d, and a protective layer 123 is formed covering the sacrificial layer 122 in the second recess 10d. Using this method, when the sacrificial layer 122 in the first recess 10c is removed, the protective layer 123 protects the sacrificial layer 122 in the second recess 10d, ensuring that the sacrificial layer 122 in the second recess 10d remains intact when the sacrificial layer 122 in the first recess 10c is removed.

[0131] In some embodiments, the material of the sacrificial layer 122 includes, but is not limited to, spin-on carbon (SOC). The material of the protective layer 123 includes an insulating material, which includes, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0132] Next, perform step S102 as described above, referring to... Figures 3C to 3V As shown, a first gate 133 extending along the first direction z is formed between adjacent active pillars 103. The first gate 133 includes a first gate top surface 133a and a first gate bottom surface 133b opposite to each other in the first direction z. The first gate top surface 133a is close to the first end 1031.

[0133] In some embodiments, refer to Figure 3C As shown, before forming a first gate 133 extending along the first direction z between adjacent active pillars 103, the method for manufacturing a semiconductor device further includes forming a first gate insulating layer 112 on the trench wall of a first recess 10c. Specifically, the first gate insulating layer 112 is located on the trench wall of the first recess 10c and covers a protective layer 123 and a mask pattern 121.

[0134] In some embodiments, the material of the first gate insulating layer 112 is the same as that of the protective layer, but is not limited thereto. In some embodiments, the semiconductor layer 10 is subjected to a high-temperature oxidation process to form the first gate insulating layer 112 on the trench wall of the first trench 10c. In other embodiments, the first gate insulating layer 112 is formed using a thin-film deposition process. The material of the first gate insulating layer 112 includes oxides, including but not limited to silicon oxide.

[0135] In some embodiments, refer to Figure 3C and Figure 3D As shown, forming a first gate 133 extending along the first direction z between adjacent active pillars 103 includes: filling a first conductive layer 131 in a first groove 10c; removing a portion of the first conductive layer 131 near the first end 1031, with the remaining first conductive layer 131 forming a first initial gate 132.

[0136] Specifically, a first conductive layer 131 covering the first gate insulating layer 112 is formed using a thin film deposition process, and the portion of the first conductive layer 131 located in the first groove 10c fills the first groove 10c; then, a portion of the first conductive layer 131 is etched away, and the remaining first conductive layer 131 is the first initial gate 132.

[0137] In some embodiments of this application, a first conductive layer 131 is filled in the first groove 10c, and a portion of the first conductive layer 131 near the first end 1031 is etched away, leaving the remaining first conductive layer 131 to form a first initial gate 132. This method facilitates the alignment of multiple first initial gates 132 near the first end 1031 of the active pillar 103, meaning that the ends of multiple first initial gates 132 near the first end 1031 are located in a plane parallel to the second direction y. Furthermore, using an etching process to form the first initial gate 132 simplifies the manufacturing process of the first gate 133. In addition, filling the first groove 10c with the first conductive layer 131 allows for more efficient use of the space in the second direction y to set the first gate 133, facilitating the miniaturization of the first gate 133 in the second direction y.

[0138] In some embodiments, the material of the first conductive layer 131 includes metallic and non-metallic conductive materials. Metals include, but are not limited to, at least one of tungsten, aluminum, and copper. Non-metallic conductive materials include, but are not limited to, titanium nitride.

[0139] In some embodiments, refer to Figure 3E and Figure 3H As shown, after forming the first initial gate 132, the method for manufacturing the semiconductor device includes forming a first top insulating portion 141 filling a first recess 10c on the first initial gate 132. The material of the first top insulating portion 141 includes an insulating material, including but not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, the material of the first top insulating portion 141 includes silicon oxide to simplify the fabrication process of the first top insulating portion 141.

[0140] In some embodiments, refer to Figure 3EAs shown, the first top insulating portion 141 has a first air gap 1411 inside. The first air gap 1411 can improve the coupling effect between the two channel structures 1035 adjacent to the first top insulating portion 141 in the second direction y (hereinafter referred to as coupling effect), that is, it can improve the row hammer problem of the semiconductor device. In other embodiments, a first isolation portion (not shown) may also be formed on the first initial gate 132, and a first conductive shielding structure (not shown) located in the first groove 10c may be formed on the first isolation portion. The first conductive shielding structure is connected to a ground voltage or a constant voltage, which can also improve the coupling effect between adjacent channel structures 1035.

[0141] In other embodiments, reference is made to Figure 3H As shown, the interior of the first top insulating part 141 may also lack the first air gap 1411 or have a small number of air gaps.

[0142] Finally, refer to Figures 3F to 3L As shown, by performing the above step S103, a second gate 135 extending along the first direction z is formed. The second gate 135 is located on the side of the active pillar 103 facing away from the first gate 133 in the second direction y. The second gate 135 includes a second gate top surface 135a and a second gate bottom surface 135b opposite to each other in the first direction z. The second gate bottom surface 135b is close to the second end 1032. In the first direction z, the second gate top surface 135a is located on the side of the first gate top surface 133a close to the first end 1031, and the first gate bottom surface 133b is located on the side of the second gate bottom surface 135b close to the second end 1032. The first direction z intersects with the second direction y.

[0143] In some embodiments, refer to Figures 3F to 3L As shown, forming a second gate 135 extending along the first direction z includes: removing the protective layer 123 and the sacrificial layer 122 in the second groove 10d; forming a second bottom insulating portion 142 in the second groove 10d, the size of the second bottom insulating portion 142 in the first direction z being smaller than the depth of the second groove 10d; and forming a second gate 135 on the second bottom insulating portion 142.

[0144] Reference Figure 3G and Figure 3H As shown, the second bottom insulating portion 142 includes an insulating core 1421 and a protective layer 1422. The protective layer 1422 covers the sidewalls and bottom wall of the insulating core 1421, with the bottom wall of the insulating core 1421 close to the bottom of the second groove 10d. The material of the insulating core 1421 is different from the material of the protective layer. Specifically, the material of the insulating core 1421 includes, but is not limited to, silicon oxide, and the material of the protective layer 1422 includes, but is not limited to, silicon nitride.

[0145] It should be noted that during the formation of the second bottom insulating part 142, the protective layer 1422 protects the active post 103.

[0146] In some embodiments, refer to Figure 3G As shown, a second air gap 1423 is present inside the second bottom insulating portion 142. The second air gap 1423 improves the coupling effect between the two channel structures 1035 adjacent to the second bottom insulating portion 142, that is, it can further improve the hammer effect of the semiconductor device. Wherein, the second air gap 1423 is located inside the insulating core portion 1421. In other embodiments, a second conductive shielding structure (not shown) may also be formed in the second groove 10d, and a second isolation portion (not shown) is provided between the second conductive shielding structure and the active pillar 103. Connecting the second conductive shielding structure to a ground potential or a constant voltage can also improve the coupling effect between adjacent channel structures 1035.

[0147] In other embodiments, reference is made to Figure 3H As shown, the interior of the second bottom insulating part 142 may also lack the second air gap 1423 or have a small number of air gaps.

[0148] In some embodiments, refer to Figure 3G and Figure 3H As shown, after the second bottom insulating portion 142 is formed, the mask pattern 121 is removed.

[0149] In some embodiments, refer to Figure 3I As shown, before forming the second gate 135 on the second bottom insulating portion 142, the semiconductor device manufacturing method further includes forming a second gate insulating layer 113 on the sidewall of the second recess 10d and on the second bottom insulating portion 142. The second gate insulating layer 113 serves to isolate the second gate 135 from the active pillar 103. The material of the second gate insulating layer 113 includes, but is not limited to, oxide materials such as silicon oxide.

[0150] In some embodiments, refer to Figures 3I to 3K As shown, forming a second gate 135 on a second bottom insulating portion 142 includes: forming a second conductive layer 134, the second conductive layer 134 covering and filling the second gate insulating layer 113 in the second groove 10d, the second conductive layer 134 also covering the top surface of the first top insulating portion 141 away from the first initial gate 132 and the end surface of the active pillar 103 away from the second surface 10b; removing a portion of the second conductive layer 134, the remaining second conductive layer 134 in the second groove 10d constitutes the second gate 135.

[0151] In some embodiments, removing a portion of the second conductive layer 134 includes: removing the second conductive layer 134 outside the second groove 10d using a chemical machine polishing process, and further removing a portion of the second conductive layer 134 within the second groove 10d using an etching process, to form the second gate 135. Using both chemical machine polishing and etching processes to remove portions of the second conductive layer 134 to form the second gate 135 simplifies the manufacturing process of the second gate 135, thereby simplifying the manufacturing process of the semiconductor device.

[0152] In some embodiments, when the second conductive layer 134 outside the second groove 10d is removed by chemical machine polishing, the second gate insulating layer 113 outside the second groove 10d and the portion of the first top insulating portion 141 protruding from the active post 103 can also be removed simultaneously.

[0153] It should be noted that in some related technologies, the gate fabrication requires a punching process, which is quite difficult. In this application, however, the second gate 135 is formed using thin film deposition, chemical mechanical polishing, and etching processes, making the fabrication of the second gate 135 much simpler.

[0154] The second gate 135 includes a second gate top surface 135a and a second gate bottom surface 135b that are opposite each other in the first direction z. The second gate bottom surface 135b is in contact with the second bottom insulating portion 142.

[0155] In some embodiments, the material of the second conductive layer 134 includes metallic and non-metallic conductive materials. Metals include, but are not limited to, at least one of tungsten, aluminum, and copper. Non-metallic conductive materials include, but are not limited to, titanium nitride.

[0156] In some embodiments, the sum of the dimensions of the second gate 135 in the first direction z and the dimensions of the second bottom insulating portion 142 in the first direction z is less than the depth of the second groove 10d.

[0157] In some embodiments, refer to Figures 3J to 3L As shown, after forming the second gate 135, the method for manufacturing the semiconductor device further includes forming a second top insulating portion 143 that fills the second groove 10d on the second gate 135. The second top insulating portion 143 is used to isolate the second gate 135 from other structures and provides protection for the second gate 135.

[0158] In some embodiments, the material of the second top insulating portion 143 is the same as the material of the first top insulating portion 141. The dimension of the first top insulating portion 141 in the first direction z is larger than the dimension of the second top insulating portion 143 in the first direction z, which facilitates at least a portion of the first gate 133 being misaligned with the second gate 135 in the first direction.

[0159] In some embodiments, please refer to Figure 3J and Figure 3K As shown, after forming the second top insulating portion 143, the semiconductor device manufacturing method further includes: performing ion doping treatment on the first end 1031 of the active pillar 103 to form a first electrode 1033; and forming a capacitor (not shown) connected to the first electrode 1033.

[0160] In some embodiments, refer to Figures 3M to 3O As shown, after forming the capacitor, removing a portion of the first initial gate 132 near the second end 1032 includes: thinning the second surface 10b of the semiconductor layer 10 to expose the dielectric layer 111, and forming a thinned third surface 10e. The surface of the dielectric layer 111 and the surface of the semiconductor layer 10 together constitute the third surface 10e.

[0161] In some embodiments of this application, the second surface 10b of the semiconductor layer 10 is thinned to expose the dielectric layer 111, and a thinned third surface 10e is formed to facilitate the formation of an opening 10f on the third surface 10e to expose the first initial gate 132. The first initial gate 132 is then etched back to form the first gate 133.

[0162] In some embodiments, refer to Figures 3P to 3R As shown, after forming the third surface 10e, removing a portion of the first initial gate 132 near the second end 1032 further includes: forming an opening 10f in the dielectric layer 111 to expose the first initial gate 132, the opening 10f being recessed from the third surface 10e toward the first surface 10a; and removing a portion of the first initial gate 132 near the second end 1032 through the opening 10f, the remaining first initial gate 132 constituting the first gate 133.

[0163] The first gate 133 includes a first gate top surface 133a and a first gate bottom surface 133b opposite to each other in the first direction z. The first gate top surface 133a is in contact with the first top insulating portion 141. The second gate top surface 135a is located on the side of the first gate top surface 133a closer to the first electrode 1033, and the first gate bottom surface 133b is located on the side of the second gate bottom surface 135b away from the first electrode 1033.

[0164] In some embodiments of this application, after thinning the second surface 10b of the semiconductor layer 10, a third surface 10e is formed. Next, an opening 10f is formed on the third surface 10e toward the first surface 10a, located in the dielectric layer 111 and exposing the first initial gate 132. Finally, the first initial gate 132 is etched back. This method ensures that the first gate bottom surfaces 133b of the plurality of first gates 133 are aligned, thereby better ensuring that the dimensions of the plurality of first gates 133 in the first direction z are controllable and uniform.

[0165] In some embodiments, each opening 10f extends along a second direction y and exposes a first initial gate 132 and a second bottom insulating portion 142. A plurality of second openings 10f are spaced apart along a third direction x. Along the third direction x, a row of active posts 103 is disposed between adjacent second openings 10f, the row of active posts 103 comprising a plurality of active posts 103 arranged side-by-side along the second direction y.

[0166] In some embodiments, refer to Figure 3S As shown, the method for manufacturing a semiconductor device further includes forming a first bottom insulating portion 144 on a first gate 133 near a second end 1032 through an opening 10f. The first bottom insulating portion 144 contacts the bottom surface 133b of the first gate and fills the space between the first gate 133 and the semiconductor layer 10 to isolate the first gate 133 and the semiconductor layer 10.

[0167] It should be noted that, referring to Figure 3T As shown, an insulating filler layer 124 is formed using a thin film deposition process. The insulating filler layer 124 includes a first bottom insulating portion 144, and a portion of the insulating filler layer 124 also fills an opening 10f. The insulating filler layer 124 covers a second bottom insulating portion 142.

[0168] In some embodiments, the material of the insulating filler layer 124 is the same as the material of the dielectric layer. Specifically, the material of the insulating filler layer 124 includes, but is not limited to, silicon oxide.

[0169] In some embodiments, please continue to refer to Figure 3S As shown, after forming the first bottom insulating portion 144, the semiconductor device manufacturing method further includes: performing ion doping treatment on the second end 1032 of the active pillar 103 to form a second electrode 1034, with the remaining active pillar 103 forming a channel structure 1035; and forming a bit line (not shown) connected to the second electrode 1034.

[0170] It should be noted that one of the first electrode 1033 and the second electrode 1034 is the source electrode, and the other of the first electrode 1033 and the second electrode 1034 is the drain electrode. The channel structure 1035 includes a first channel end 10351 and a second channel end 10352 opposite to each other in the first direction z. The first channel end 10351 is adjacent to and in contact with the first electrode 1033, and a plurality of second channel ends 10352 are adjacent to and in contact with the second electrode 1034.

[0171] In some embodiments, refer to Figure 4A and Figure 4B As shown, the method for manufacturing a semiconductor device further includes: forming a first gate contact 151 connected to a first gate 133; and forming a second gate contact 152 connected to a second gate 135.

[0172] In some embodiments, the first gate contact 151 and the second gate contact 152 are located on the same side of the plurality of channel structures 1035, so as to simultaneously form the first gate contact 151 and the second gate contact 152, simplifying the manufacturing process of the semiconductor device. For example, the first gate contact 151 and the second gate contact 152 are located on the side of the second electrode 1034 away from the first electrode 1033.

[0173] Reference Figure 4A and Figure 4B As shown, the first gate 133 includes a first gate terminal 1331 and a second gate terminal 1332 opposite to each other in the third direction x. The second gate 135 includes a third gate terminal 1351 and a fourth gate terminal 1352 opposite to each other in the third direction x. The third gate terminal 1351 is close to the first gate terminal 1331. The first gate terminal 1331 and the third gate terminal 1351 are offset from each other, and the fourth gate terminal 1352 is offset from the second gate terminal 1332.

[0174] In some embodiments, refer to Figure 4A As shown, at least one first gate contact 151 is connected to the first gate terminal 1331 of at least one first gate 133. At least one second gate contact 152 is connected to the third gate terminal 1351 of at least one second gate 135. In two adjacent first gates 133, the first gate terminal 1331 of one first gate 133 is connected to one first gate contact 151, and the second gate terminal 1332 of the other first gate 133 is connected to the other first gate contact 151. In two adjacent second gates 135, the third gate terminal 1351 of one second gate 135 is connected to one second gate contact 152, and the fourth gate terminal 1352 of the other second gate 135 is connected to the other second gate contact 152. With this design, the process windows for both the first gate contact 151 and the second gate contact 152 are relatively large, further reducing the manufacturing difficulty of the semiconductor device.

[0175] In other embodiments, reference is made to Figure 4B As shown, at least one first gate contact 151 is connected to the first gate terminal 1331 of at least one first gate 133, and at least one second gate contact 152 is connected to the fourth gate terminal 1352 of at least one second gate 135. The first gate terminals 1331 of two adjacent first gates 133 are respectively connected to the two first gate contacts 151, and the fourth gate terminals 1352 of two adjacent second gates 135 are respectively connected to the two second gate contacts 152. With this design, the process windows for both the first gate contacts 151 and the second gate contacts 152 are relatively large, further reducing the manufacturing difficulty of the semiconductor device.

[0176] In some embodiments of this application, a first groove 10c and a second groove 10d intersecting with multiple active lines 102 are formed. A first conductive layer 131 is formed in the first groove 10c, and the first conductive layer 131 is etched to form a first gate 133. A second conductive layer 134 is formed in the second groove 10d, and the second conductive layer 134 is etched to form a second gate 135. Therefore, both the first gate 133 and the second gate 135 are formed by etching the conductive layer, simplifying the manufacturing process of the first gate 133 and the second gate 135 and reducing the manufacturing process of the semiconductor device. Moreover, using the semiconductor device manufacturing method of this application, the dimensions of the first gate 133 and the second gate 135 in the second direction y can be smaller, which is beneficial to increasing the number of the first gate 133, the second gate 135, and the channel structure 1035, thereby improving the storage density of the semiconductor device. Furthermore, the first air gap 1411 can improve the coupling effect between two adjacent channel structures 1035 in the second direction y, and the second air gap 1423 can also improve the coupling effect between two adjacent channel structures 1035 in the second direction y.

[0177] In some related technologies, a gate conductive layer is formed on the sidewalls and bottomwalls of the groove, and the gate conductive layer is broken by a punching process to form two gate lines. Due to the difficulty of the punching process, the manufacturing difficulty of semiconductor devices is relatively greater.

[0178] In some embodiments, refer to Figure 3S , Figure 3U and Figure 3VAs shown, the second gate top surface 135a is located on the side of the first gate top surface 133a near the first channel end 10351, and the first gate bottom surface 133b is located on the side of the second gate bottom surface 135b near the second channel end 10352. With this design, at least a portion of the first gate 133 is offset from the second gate 135 in the first direction z. Each of the first gate 133 and the second gate 135 can be shared by two adjacent channel structures 1035 in the second direction y. That is, each of the first gate 133 and the second gate 135 can control whether a portion of two adjacent channel structures 1035 in the second direction y is in a conducting state or a cut-off state.

[0179] This application also provides a semiconductor device prepared by the above-mentioned semiconductor device manufacturing method, which is described below in conjunction with... Figure 3S , Figure 3U , Figure 3V , Figure 4A as well as Figure 4B The semiconductor device described in this application is described.

[0180] The semiconductor device includes multiple channel structures 1035, multiple first gates 133, multiple second gates 135, a first bottom insulating portion 144, a second bottom insulating portion 142, a first top insulating portion 141, a second top insulating portion 143, a first gate contact 151, a second gate contact 152, a first gate insulating layer 112, and a second gate insulating layer 113.

[0181] Multiple channel structures 1035 extend along a first direction z and are arranged in an array along a second direction y and a third direction x. Each channel structure 1035 includes a first channel end 10351 and a second channel end 10352 opposite to each other in the first direction z. The first channel end 10351 of the channel structure 1035 is connected to and in contact with a first electrode 1033. The second channel end 10352 of the channel structure 1035 is connected to and in contact with a second electrode 1034. One of the first electrode 1033 and the second electrode 1034 is the source electrode, and the other of the first electrode 1033 and the second electrode 1034 is the drain electrode.

[0182] Specifically, any two of the first direction z, the second direction y, and the third direction x intersect each other. However, this is not a limitation.

[0183] A plurality of first gates 133 extend along a first direction z and a third direction x. The plurality of first gates 133 are spaced apart along a second direction y. One first gate 133 is located between two adjacent rows of channel structures 1035 in the second direction y. Each first gate 133 includes a first gate top surface 133a and a first gate bottom surface 133b opposite each other in the first direction z, with the first gate top surface 133a near the first channel end 10351. A first gate insulating layer 112 is disposed between the first gate 133 and the sidewall of the channel structure 1035.

[0184] A plurality of second gates 135 extend along a first direction z and a third direction x. The plurality of second gates 135 are spaced apart along a second direction y. One second gate 135 is located on the side of the channel structure 1035 facing away from the first gate 133 in the second direction y, and another second gate 135 is located between two adjacent rows of channel structures 1035 in the second direction y. A second gate insulating layer 113 is disposed between the second gate 135 and the sidewall of the channel structure 1035. The second gate 135 includes a second gate top surface 135a and a second gate bottom surface 135b opposite each other in the first direction z, with the second gate bottom surface 135b close to the second channel end 10352.

[0185] In some embodiments, a plurality of first gates 133 and a plurality of second gates 135 are arranged alternately and at intervals along a second direction y in a one-to-one manner.

[0186] In some embodiments, for adjacent first gate 133 and second gate 135, in the first direction z, the top surface 135a of the second gate is located on the side of the top surface 133a of the first gate near the first channel end 10351, and the bottom surface 133b of the first gate is located on the side of the bottom surface 135b of the second gate near the second channel end 10352. With this design, at least a portion of the first gate 133 is offset from the second gate 135 in the first direction z, and each of the first gate 133 and the second gate 135 can be shared by two adjacent channel structures 1035 in the second direction y, that is, each of the first gate 133 and the second gate 135 can control a portion of two adjacent channel structures 1035 in the second direction y to be in a conducting state or a cut-off state.

[0187] In some embodiments, refer to Figure 3S As shown, in the first direction z, the bottom surface 135b of the second gate is located on the side of the top surface 133a of the first gate close to the bottom surface 133b. With this design, in the first direction z, a portion of the first gate 133 is offset from the second gate 135. Moreover, when a voltage is applied to the channel structure 1035 between the adjacent first gate 133 and second gate 135, the current when the channel structure 1035 is turned on will be larger.

[0188] In other embodiments, reference is made to Figure 3U As shown, in the second direction y, the top surface 133a of the first gate and the bottom surface 135b of the second gate are aligned.

[0189] It should be noted that, referring to Figure 3U As shown, the alignment in this application is within a certain process error range.

[0190] In other embodiments, reference is made to Figure 3V As shown, in the first direction z, the bottom surface 135b of the second gate is located on the side of the top surface 133a of the first gate away from the bottom surface 133b. With this design, the first gate 133 and the second gate 135 are completely offset from each other.

[0191] It should be noted that, for Figure 3V In the semiconductor device shown, when the first gate 133 and the second gate 135 are completely staggered in the first direction z, the region of the channel structure 1035 in which neither the voltage of the first gate 133 nor the second gate 135 can act on the channel structure 1035 can be doped to reduce the resistance of the region and ensure that the channel structure 1035 is turned on by the adjacent first gate 133 and second gate 135.

[0192] For the semiconductor device of this application, a gate group is used as the basic unit of control, thereby controlling the conduction of a channel structure 1035. A gate group includes one set of gate pairs adjacent in the second direction y and another set of gate pairs. One set of gate pairs includes an adjacent first gate 133 and a second gate 135, and the other set of gate pairs includes another adjacent first gate 133 and another adjacent second gate 135, with one second gate 135 disposed adjacent to the other first gate 133. Therefore, a gate group includes two first gates 133 and two second gates 135.

[0193] In some embodiments of this application, a method for controlling a gate group includes: connecting a second gate 135 and a first gate 133 to a second gate on-state voltage and a first gate on-state voltage, respectively; and connecting the first gate 133 and the second gate 135 to a first gate off-state voltage and a second gate off-state voltage, respectively. Using this control method, the channel structure 1035 between the second gate 135 and the first gate 133 is turned on.

[0194] In some embodiments, refer to Figure 4A and Figure 4BAs shown, the two ends of the first gate 133 on the third direction x are offset from the two ends of the second gate 135 on the third direction x, so that the process window of the first gate contact 151 connected to the first gate 133 and the second gate contact 152 connected to the second gate 135 is large enough, simplifying the manufacturing process of the semiconductor device.

[0195] Specifically, the first gate 133 includes a first gate terminal 1331 and a second gate terminal 1332 opposite to each other in the third direction x. The second gate 135 includes a third gate terminal 1351 and a fourth gate terminal 1352 opposite to each other in the third direction x, with the third gate terminal 1351 close to the first gate terminal 1331. The first gate terminal 1331 and the third gate terminal 1351 are offset from each other, and the fourth gate terminal 1352 and the second gate terminal 1332 are offset from each other.

[0196] In some embodiments, refer to Figure 4A As shown, at least one first gate contact 151 is connected to the first gate terminal 1331 of at least one first gate 133. At least one second gate contact 152 is connected to the third gate terminal 1351 of at least one second gate 135. In two adjacent first gates 133, the first gate terminal 1331 of one first gate 133 is connected to one first gate contact 151, and the second gate terminal 1332 of the other first gate 133 is connected to the other first gate contact 151. In two adjacent second gates 135, the third gate terminal 1351 of one second gate 135 is connected to one second gate contact 152, and the fourth gate terminal 1352 of the other second gate 135 is connected to the other second gate contact 152. With this design, the process windows for both the first gate contact 151 and the second gate contact 152 are relatively large, further reducing the manufacturing difficulty of the semiconductor device.

[0197] In other embodiments, reference is made to Figure 4B As shown, at least one first gate contact 151 is connected to the first gate terminal 1331 of at least one first gate 133, and at least one second gate contact 152 is connected to the fourth gate terminal 1352 of at least one second gate 135. The first gate terminals 1331 of two adjacent first gates 133 are respectively connected to the two first gate contacts 151, and the fourth gate terminals 1352 of two adjacent second gates 135 are respectively connected to the two second gate contacts 152. With this design, the process windows for both the first gate contacts 151 and the second gate contacts 152 are relatively large, further reducing the manufacturing difficulty of the semiconductor device.

[0198] In some embodiments, the dimensions of the first gate 133 in the third direction x are different from the dimensions of the second gate 135 in the third direction x, so as to distinguish the first gate 133 and the second gate 135, reduce the difficulty of manufacturing the first gate 133 and the second gate 135, and thus reduce the difficulty of manufacturing semiconductor devices. For example, referring to Figure 4A As shown, the dimension of the first gate 133 in the third direction x is larger than the dimension of the second gate 135 in the third direction x; or, the dimension of the first gate 133 in the third direction x is smaller than the dimension of the second gate 135 in the third direction x. In other embodiments, refer to Figure 4B As shown, the size of the first gate 133 in the third direction x can also be equal to the size of the second gate 135 in the third direction x.

[0199] In some embodiments, the dimensions of the first gate 133 and the second gate 135 in the second direction y are the same, which facilitates the first groove 10c and the second groove 10d having the same dimensions along the second direction y, simplifying the manufacturing process of the semiconductor device. In other embodiments, the dimensions of the first gate 133 and the second gate 135 in the second direction y may also be different.

[0200] In the first direction z, a first bottom insulating portion 144 and a first top insulating portion 141 are located on opposite sides of the first gate. In the first direction z, the first bottom insulating portion 144 is located on the side of the first gate bottom surface 133b away from the first gate top surface 133a and contacts the first gate bottom surface 133b. In the first direction z, the first top insulating portion 141 is located on the side of the first gate top surface 133a away from the first gate bottom surface 133b and contacts the first gate top surface 133a. In some embodiments, the dimension of the first bottom insulating portion 144 along the first direction z is smaller than the dimension of the first top insulating portion 141 along the first direction z.

[0201] In some embodiments, the interior of the first top insulating portion 141 includes a first air gap 1411 to improve the coupling effect between two channel structures 1035 adjacent to the first top insulating portion 141 in the second direction y.

[0202] In the first direction z, the second bottom insulating portion 142 and the second top insulating portion 143 are located on opposite sides of the second gate. In the first direction z, the second bottom insulating portion 142 is located on the side of the second gate bottom surface 135b away from the second gate top surface 135a and contacts the second gate bottom surface 135b. In the first direction z, the second top insulating portion 143 is located on the side of the second gate top surface 135a away from the second gate bottom surface 135b and contacts the second gate top surface 135a. In some embodiments, the dimension of the second bottom insulating portion 142 along the first direction z is larger than the dimension of the second top insulating portion 143 along the first direction z.

[0203] In some embodiments, the second bottom insulating portion 142 includes a second air gap 1423 inside the second bottom insulating portion 142 to improve the coupling effect between two channel structures 1035 adjacent to the second bottom insulating portion 142 in the second direction.

[0204] In some embodiments, the second bottom insulating portion 142 has a larger dimension in the first direction z than the first bottom insulating portion 144 has a smaller dimension in the first direction z than the first top insulating portion 141 has a smaller dimension in the first direction z, so as to accommodate at least a portion of the first gate being offset from the second gate in the first direction.

[0205] The second bottom insulating portion 142 includes an insulating core portion 1421 and a protective layer 1422. The protective layer 1422 covers the sidewall of the insulating core portion 1421 and the bottom wall of the insulating core portion 1421 away from the second gate 135. The material of the insulating core portion 1421 is different from the material of the protective layer 1422.

[0206] In some embodiments of this application, in the second direction, the first gate and the second gate are located on opposite sides of the channel structure. In the first direction, the top surface of the second gate is located on the side of the top surface of the first gate near the end of the first channel, and the bottom surface of the first gate is located on the side of the bottom surface of the second gate near the end of the second channel. With this design, at least a portion of the first gate is offset from the second gate in the first direction, and each of the first and second gates can be shared by two adjacent channel structures in the second direction. That is, each of the first and second gates can control portions of two adjacent channel structures in the second direction to be in a conducting or cut-off state. Moreover, since each of the first and second gates can be shared by two adjacent channel structures in the second direction, the dimensions of the first and second gates in the second direction can be smaller, which is beneficial for miniaturizing the dimensions of the first and second gates in the second direction, increasing the number of first gates, second gates, and channel structures, thereby increasing the storage density of the semiconductor device and improving the performance of the semiconductor device.

[0207] In addition, see Figure 5 and Figure 6 As shown, based on the same inventive concept, this application also provides a storage system 400, which includes a memory 200 and a controller 300. The controller 300 is connected to the memory 200 and is used to control the memory 200. The memory 200 includes the semiconductor device 100 of any of the embodiments described above.

[0208] The storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein.

[0209] In some embodiments, refer to Figure 5 As shown, the storage system 400 includes a memory 200 and a controller 300. The storage system 400 can be integrated into a 3D memory card.

[0210] Among them, 3D memory cards include any one of the following: PC card (PCMCIA, the International Association for Personal Computer 3D Memory Cards), Compact Flash (CF) card, Smart Media (SM) card, 3D memory, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0211] In other embodiments, reference is made to Figure 6 As shown, the storage system 400 includes multiple memory units 200 and a controller 300. The storage system 400 is integrated into a solid-state drive (SSD).

[0212] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0213] In other embodiments, in storage system 400, controller 300 is configured to operate in high duty cycle environments in SSDs or eMMCs used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0214] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and to communicate with external devices (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions relating to data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes relating to data read from or written to the memory 200.

[0215] Of course, controller 300 can also perform any other suitable functions, such as formatting memory 200; for example, controller 300 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0216] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0217] Please refer to Figure 7 Some embodiments of this application also provide an electronic device 500. The electronic device 500 can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0218] Electronic device 500 may include the aforementioned storage system 400 and host 600, wherein host 600 includes at least one of a central processing unit (CPU) and a cache.

[0219] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized by, include: A plurality of channel structures extending along a first direction, the channel structures including a first channel end and a second channel end opposite to each other in the first direction; A first gate extending along the first direction is located between adjacent channel structures, and the first gate includes a first gate top surface and a first gate bottom surface opposite each other in the first direction, the first gate top surface being close to the first channel end; as well as The second gate extends along the first direction and is located on the side of the channel structure opposite to the first gate in the second direction. The second gate includes a second gate top surface and a second gate bottom surface opposite to each other in the first direction. The second gate bottom surface is close to the second channel end. In the first direction, the second gate top surface is located on the side of the first gate top surface close to the first channel end, and the first gate bottom surface is located on the side of the second gate bottom surface close to the second channel end. The first direction intersects the second direction.

2. The semiconductor device according to claim 1, wherein In the first direction, the second gate bottom surface is located on the side of the first gate top surface close to the first gate bottom surface.

3. The semiconductor device of claim 1, wherein In the second direction, the top surface of the first gate is aligned with the bottom surface of the second gate.

4. The semiconductor device of claim 1, wherein In the first direction, the second gate bottom surface is located on the side of the first gate top surface away from the first gate bottom surface.

5. The semiconductor device of claim 1, wherein Also includes: A first bottom insulating portion, in the first direction, is located on the side of the bottom surface of the first gate away from the top surface of the first gate and is in contact with the bottom surface of the first gate; and The second bottom insulating portion, in the first direction, is located on the side of the bottom surface of the second gate away from the top surface of the second gate and is in contact with the bottom surface of the second gate, and the size of the second bottom insulating portion in the first direction is larger than the size of the first bottom insulating portion in the first direction.

6. The semiconductor device of claim 5, wherein, The second bottom insulating portion includes an insulating core and a protective layer. The protective layer covers the sidewalls of the insulating core and the bottom wall of the insulating core away from the second gate. The material of the insulating core is different from the material of the protective layer.

7. The semiconductor device of claim 1, wherein Also includes: A first top insulating portion, in the first direction, is located on the side of the first gate top surface away from the first gate bottom surface and is in contact with the first gate top surface; and The second top insulating portion, in the first direction, is located on the side of the second gate top surface away from the second gate bottom surface and is in contact with the second gate top surface, and the size of the second top insulating portion in the first direction is smaller than the size of the first top insulating portion in the first direction.

8. The semiconductor device of claim 1, wherein A plurality of first gates and a plurality of second gates are arranged alternately and at intervals along the second direction, and the first gates and the second gates also extend along a third direction, which intersects the first direction and the second direction; The first gate is offset from the second gate at its opposite ends in the third direction.

9. The semiconductor device of claim 8, wherein, The dimensions of the first gate in the third direction are different from the dimensions of the second gate in the third direction.

10. The semiconductor device of claim 8, wherein, The first gate includes a first gate terminal and a second gate terminal that are opposite to each other on the third side; The second gate includes a third gate end and a fourth gate end that are opposite to the third gate end, the third gate end being close to the first gate end; The semiconductor device further includes: At least one first gate contact is connected to at least one first gate terminal; as well as At least one second gate contact is connected to the third gate terminal of at least one second gate.

11. The semiconductor device according to claim 10, characterized in that, In two adjacent first gates, the first gate terminal of one first gate is connected to one first gate contact, and the second gate terminal of the other first gate is connected to the other first gate contact. In two adjacent second gates, the third gate terminal of one second gate is connected to a second gate contact, and the fourth gate terminal of the other second gate is connected to the other second gate contact.

12. The semiconductor device according to claim 8, characterized in that, The first gate includes a first gate terminal and a second gate terminal that are opposite to each other on the third side; The second gate includes a third gate end and a fourth gate end that are opposite to the third gate end, the third gate end being close to the first gate end; The semiconductor device further includes: At least one first gate contact is connected to at least one first gate terminal; as well as At least one second gate contact is connected to the fourth gate terminal of at least one second gate.

13. The semiconductor device according to claim 12, characterized in that, The first gate terminals of two adjacent first gates are respectively connected to two first gate contacts, and the fourth gate terminals of two adjacent second gates are respectively connected to two second gate contacts.

14. A method for manufacturing a semiconductor device, characterized in that, The method includes: Multiple active pillars are formed extending along a first direction, the active pillars including a first end and a second end opposite to each other in the first direction; A first gate extending along the first direction is formed between adjacent active pillars, the first gate including a first gate top surface and a first gate bottom surface opposite each other in the first direction, the first gate top surface being close to the first end; and A second gate is formed extending along the first direction. The second gate is located on the side of the active post opposite to the first gate in the second direction. The second gate includes a second gate top surface and a second gate bottom surface opposite to each other in the first direction. The second gate bottom surface is close to the second end. In the first direction, the second gate top surface is located on the side of the first gate top surface close to the first end, and the first gate bottom surface is located on the side of the second gate bottom surface close to the second end. The first direction intersects the second direction.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The formation of a plurality of active pillars extending along the first direction includes: Multiple recesses are formed in a semiconductor layer, and the remaining semiconductor layer includes multiple active lines extending along a first direction. The recesses are recessed from a first surface to a second surface of the semiconductor layer, and the first surface and the second surface are disposed opposite to each other in the first direction. A first groove and a second groove are formed, which are arranged along the second direction and extend along the third direction. The first groove and the second groove intersect with the plurality of active lines. The first groove and the second groove are staggered at their opposite ends in the third direction. The third direction intersects with the first direction and the second direction. The formation of a first gate extending along the first direction between adjacent active pillars includes: The first conductive layer is filled into the first groove; A portion of the first conductive layer near the first end is removed, and the remaining first conductive layer forms the first initial gate. A portion of the first initial gate near the second end is removed, and the remaining portion of the first initial gate forms the first gate.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The method further includes filling the plurality of said recesses with a dielectric layer; The removal of a portion of the first initial gate near the second end includes: The second surface of the semiconductor layer is thinned to expose the dielectric layer, and a thinned third surface is formed. An opening is formed in the dielectric layer to expose the first initial gate, the opening being recessed from the third surface toward the first surface; The portion of the first initial gate near the second end is removed through the opening.

17. The method for manufacturing a semiconductor device according to claim 16, characterized in that, The method further includes forming a first bottom insulating portion on the first gate near the second end through the opening.

18. The method for manufacturing a semiconductor device according to claim 15, characterized in that, Before filling the first conductive layer into the first groove, the method further includes: A sacrificial layer is formed in the first groove and the second groove; A protective layer is formed covering the sacrificial layer in the second groove; and Remove the sacrificial layer from the first groove.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The formation of the second gate extending along the first direction includes: Remove the protective layer and the sacrificial layer in the second groove; A second bottom insulating portion is formed in the second groove, the dimension of the second bottom insulating portion in the first direction being smaller than the depth of the second groove; and The second gate is formed on the second bottom insulating portion.

20. A storage system, characterized in that, include: The memory includes the semiconductor device as described in any one of claims 1-13; as well as A controller, connected to the memory, is used to control the memory.

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