Storage device, method for manufacturing storage device, and semiconductor device

Abstract

The application provides a storage device and a manufacturing method thereof and a semiconductor device. The storage device comprises: a substrate comprising an insulating surface; a storage unit array comprising a plurality of storage units arranged on the insulating surface, the plurality of storage units being repeatedly arranged along a first horizontal direction, a second horizontal direction and a vertical direction, the first horizontal direction intersecting the second horizontal direction; each storage unit comprising a transistor, the transistor comprising a gate insulating layer, a gate structure and an active layer parallel to the insulating surface, the gate structure comprising a gate main body part, the gate main body part comprising a first gate, the first gate extending along a sidewall of the active layer, the gate insulating layer being located between the first gate and the active layer; a common source structure and a bit line structure, the bit line structure comprising a plurality of bit lines extending along the first horizontal direction, and the active layer comprising a source terminal connected to the common source structure and a drain terminal connected to one bit line. The storage device of the application has high storage density and simple manufacturing process.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor technology, and particularly relates to a storage device, a manufacturing method of the storage device, and a semiconductor device. BACKGROUND

[0002] With the miniaturization of technology nodes, the storage unit of a DRAM (Dynamic Random Access Memory) gradually changes from a 1T1C (1 Transistor 1 Capacitor) structure to a 1T0C (1 Transistor 0 Capacitor) structure. Since the capacitor-free structure is adopted, the volume of the storage unit is reduced, and the storage density is improved.

[0003] In the prior art, the DRAM storage unit is usually repeatedly arranged in space to form a three-dimensional stacked structure with high storage density. However, with the increase in the number of stacked layers of the three-dimensional stacked structure and the miniaturization of the process nodes, the preparation process gradually becomes more difficult. SUMMARY

[0004] Embodiments of the present application provide a storage device, which aims to at least solve the technical problem of a large preparation process difficulty of a semiconductor device with a three-dimensional stacked structure.

[0005] Embodiments of the present application are implemented in the following manner. A storage device comprises:

[0006] a substrate comprising an insulating surface;

[0007] a storage unit array comprising a plurality of storage units arranged on the insulating surface, the plurality of storage units being repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction, the first horizontal direction intersecting the second horizontal direction;

[0008] each of the storage units comprises a transistor comprising an active layer, a gate insulating layer, and a gate structure, the gate structure comprising a gate main body portion, the gate main body portion comprising a first gate, the active layer being parallel to the insulating surface, the first gate extending along a sidewall of the active layer, the gate insulating layer being located between the first gate and the active layer;

[0009] the storage device further comprises a common source structure and a bit line structure, the bit line structure comprising a plurality of bit lines, each of the bit lines extending along the first horizontal direction, the active layer comprising a source end and a drain end, the source end being connected to the common source structure, and the drain end being connected to one of the bit lines.

[0010] The application further provides a manufacturing method of a storage device, comprising the steps of:

[0011] providing a substrate;

[0012] preparing a plurality of film layer pairs stacked along a vertical direction on the substrate, the film layer pairs comprising semiconductor material layers and first insulating medium layers arranged sequentially along the vertical direction;

[0013] etching the plurality of film layer pairs to form a plurality of first gaps arranged repeatedly along a first horizontal direction and a second horizontal direction, the first horizontal direction intersecting the second horizontal direction, the first gaps penetrating the plurality of film layer pairs along the vertical direction, forming second insulating medium layers filling the first gaps, in the second horizontal direction, the semiconductor material layers on one side of the first gaps being formed into bit line structures, the bit line structures comprising a plurality of bit lines, each of the bit lines extending along the first horizontal direction, and a common source structure being formed on a side of the first gaps away from the bit lines;

[0014] etching the second insulating medium layers in the first gaps to form a plurality of first trenches arranged repeatedly along the first horizontal direction and the second horizontal direction, the first trenches penetrating the second insulating medium layers along the vertical direction, the first trenches corresponding to the first gaps one by one, both of the sidewalls of the first trenches opposite in the first horizontal direction exposing the semiconductor material layers, and on the orthographic projection of the substrate, the two sidewalls of the first trenches opposite in the second horizontal direction falling into the first trenches;

[0015] forming a gate material layer on the entire sidewall of the first trench, and a gate insulating material layer between the gate material layer and the surface of the semiconductor material layer exposed by the first trench, and filling a third insulating medium layer in the space surrounded by the gate material layer;

[0016] etching the gate material layer to form a plurality of second trenches arranged repeatedly along the first horizontal direction and the second horizontal direction, the second trenches penetrating the gate material layer, so that the gate material layer is formed into first gate structures and second gate structures spaced apart in the first horizontal direction;

[0017] filling a fourth insulating medium layer in the second trenches.

[0018] The application further provides a semiconductor device, comprising:

[0019] a substrate;

[0020] a transistor stack comprising a plurality of transistors stacked vertically on the substrate;

[0021] The transistor comprises an active layer and a gate electrode, the active layer extends in a horizontal direction, the gate electrode is located on the sidewall of the active layer, and all the gate electrodes in a transistor stack overlap in the orthographic projection of the substrate;

[0022] The gate electrode comprises an integral gate body part and a conductor part, the gate body part is arranged along the length direction of the active layer, the conductor part is located on the side of the gate body part away from the active layer, and the conductor part is located at both ends of the gate body part in the horizontal direction.

[0023] In the storage device of the embodiment of the application, a plurality of 1T0C structure DRAM storage units are repeatedly arranged along the first horizontal direction, the second horizontal direction and the vertical direction, the storage unit structure is simple, the storage density is high, the preparation process is simple, and the storage capacity can be improved by continuously increasing the number of stacked layers as needed. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a perspective view of the storage device of the embodiment of the application;

[0025] Figure 2 is Figure 1 is a cross-sectional view of the storage device shown in C1 section;

[0026] Figure 3 is a cross-sectional view of the transistor of the embodiment of the application in the first horizontal direction and the second horizontal direction;

[0027] Figure 4 is a cross-sectional view of the transistor of another embodiment of the application in the first horizontal direction and the second horizontal direction;

[0028] Figure 5 is Figure 1 is a cross-sectional view of the storage device shown in C2 section;

[0029] Figure 6 is Figure 1 is a cross-sectional view of the storage device shown in C3 section;

[0030] Figure 7 is Figure 1 is a cross-sectional view of the storage device shown in C4 section;

[0031] Figure 8 is a structural schematic view of the storage device of the embodiment of the application;

[0032] Figure 9 is a cross-sectional view of the storage device of another embodiment of the application in the first horizontal direction and the second horizontal direction;

[0033] Figure 10is a flowchart of a manufacturing method of a storage device according to an embodiment of the present application;

[0034] Figures 11 to 19 is a flowchart of a manufacturing method of a storage device according to an embodiment of the present application;

[0035] Figure 20 is a circuit connection diagram of a storage unit according to an embodiment of the present application.

[0036] Main element symbol explanation:

[0037] Storage device - 1000; Substrate - 200; Insulating surface - 210; Storage unit - 100; Active layer - 1111; Source terminal - 11111; Drain terminal - 11112; Channel region - 11113; Gate insulating layer - 1112; Gate structure - 1113; Gate main body - 1113A; First gate - 11131; Second gate - 11132; Conductor part - 1113B; First conductor part - 11133; Second conductor part - 11134; Storage unit stack group - 11A; First storage unit stack - 111A; Second storage unit stack - 112A; Common source - 110; Bit line structure - 120; First insulating layer - 130; Second insulating layer - 140; Third insulating layer - 150; Insulating spacer layer - 160;

[0038] Substrate - 1A; Film layer pair - 1; Semiconductor material layer - 2; First insulating dielectric layer - 3; First gap - 4; Second insulating dielectric layer - 5; First trench - 6; Gate material layer - 7; Gate insulating material layer - 8; Third insulating dielectric layer - 9; Second insulating layer - 9a; Third insulating layer - 9b; Second trench - 10; Pre-trench - 10A; First gate structure - 11; Second gate structure - 12; Fourth insulating dielectric layer / first insulating layer - 13; Third trench - 14; Conductive layer - 15. DETAILED DESCRIPTION

[0039] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. The examples of the embodiments are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and should not be understood as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0040] In the description of the application, it should be understood that the indicated positional or directional relationships described in terms of directions and positions are based on the positional or directional relationships shown in the drawings, which are for the purpose of illustrating and describing the application and simplifying the description, and do not indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0041] In addition, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0042] The following disclosure provides many different embodiments or examples for implementing different structures of the application. In order to simplify the disclosure of the application, the components and arrangements of specific examples are described below. Of course, they are only examples and the purpose is not to limit the application. In addition, the application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the application provides examples of various specific processes and materials, but those of ordinary skill in the art can realize the application of other processes and / or the use of other materials.

[0043] In embodiments of the application, the technical concept "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entire underlying structure or overlying structure, or can have a smaller extent than the underlying structure or overlying structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure.

[0044] For example, a layer can be located between any pair of horizontal planes between a top surface and a bottom surface of a continuous structure or at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines, and / or via contacts are formed) and one or more dielectric layers.

[0045] In embodiments of the application, the technical concept "vertically / vertically" should be understood as perpendicular to the lateral surface of the substrate, and the technical concept "parallel / parallelly" should be understood as parallel to the lateral surface of the substrate.

[0046] Specifically, "perpendicular" means approximately perpendicular, such as a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less. In addition, "parallel" means approximately parallel or almost parallel, such as a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less.

[0047] The technical concept "A and B are disposed in the same layer" of the embodiments of the present application means that A and B are formed at the same time by one patterning process. The technical concept "the orthographic projection of B is within the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0048] The technical concept "A and B are of an integrated structure" of the embodiments of the present application can mean that there is no obvious fault or gap or other obvious boundary interface in the microstructure. Generally, the connected film layers are integrated when the film layers are patterned on one film layer. For example, A and B use the same material to form a film layer and are formed at the same time by one patterning process to have a connected structure.

[0049] Please refer to Figures 1 to 7 The storage device 1000 of the embodiments of the present application includes:

[0050] The substrate 200 includes an insulating surface 210.

[0051] The storage unit array includes a plurality of storage units 100 disposed on the insulating surface 210, and the plurality of storage units 100 are repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction, and the first horizontal direction intersects the second horizontal direction.

[0052] Each storage unit 100 includes a transistor including an active layer 1111, a gate insulating layer 1112, and a gate structure 1113, and the gate structure 1113 includes a gate main body portion 1113A including a first gate 11131, and the active layer 1111 is parallel to the insulating surface 210, the first gate 11131 extends along the sidewall of the active layer 1111, and the gate insulating layer 1112 is located between the gate structure 1113 and the active layer 1111.

[0053] The storage device 1000 further includes a common source 110 and a bit line structure 120, and the bit line structure 120 includes a plurality of bit lines, each of which extends along the first horizontal direction, and the active layer 1111 includes a source end 11111 and a drain end 11112, the source end 11111 is connected to the common source 110, and the drain end 11112 is connected to a bit line.

[0054] Specifically, the substrate 200 can include a semiconductor substrate 200 and an insulating layer located on a side of the semiconductor substrate 200 close to the array of memory cells, the insulating layer far from the surface of the semiconductor substrate 200 forming an insulating surface 210 of the substrate 200, the memory cells 100 being insulated from the semiconductor substrate 200 by the insulating layer.

[0055] The substrate 200 can include a semiconductor material, for example, at least one of silicon (e.g., monocrystalline silicon Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), and the like. For example, the semiconductor substrate 200 can be a monocrystalline silicon substrate 200, and optionally, the semiconductor substrate 200 can include logic circuits.

[0056] In one embodiment, the insulating layer can include an insulating material commonly used in the art, such as silicon dioxide (SiO2), silicon nitride (SiNx), and the like.

[0057] In one embodiment, the substrate 200 can be a single-layer structure, for example, a single-layer structure made of at least one of silicon, germanium, gallium arsenide, and the like.

[0058] In another embodiment, the substrate 200 can also be a multi-layer structure, for example, a composite substrate 200 including a stack of silicon and silicon germanium, a stack of silicon and silicon carbide, a silicon-on-insulator, a germanium-on-insulator, or a silicon germanium-on-insulator, and the like.

[0059] In other embodiments, the substrate 200 is an insulating substrate, and its upper surface is the insulating surface 210. The insulating substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer, or the like. Alternatively, the substrate 200 can also be an insulating dielectric material such as silicon dioxide (SiO2), silicon nitride (SiN x ), and the like.

[0060] It can be understood that the first horizontal direction and the second horizontal direction are both parallel to the substrate, and the vertical direction is perpendicular to the substrate. As shown in the embodiment, Figure 1 the first horizontal direction is the Y-axis direction, the second horizontal direction is the X-axis direction, and the vertical direction is the Z-axis direction. It can be understood that the first horizontal direction, the second horizontal direction, and the vertical direction intersect each other. Preferably, the first horizontal direction is perpendicular to the second horizontal direction. Preferably, as shown in the embodiment, Figure 1 the X-axis direction is perpendicular to the Y-axis direction, and both the X-axis direction and the Y-axis direction are perpendicular to the Z-axis direction.

[0061] In the storage device 1000, a plurality of storage units 100 are repeatedly arranged along the first horizontal direction, the second horizontal direction and the vertical direction to form a storage unit array. The storage unit 100 has a simple structure, high storage density, and a simple manufacturing process. The number of stacked layers can be increased to improve the storage capacity as needed.

[0062] In the embodiment, the storage device 1000 can be considered as a plurality of memory device layers stacked in the vertical direction, wherein in each memory device layer, a plurality of storage units 100 are repeatedly arranged along the first horizontal direction and the second horizontal direction to form an array arrangement, as shown in Figure 2 It can be understood that the array arrangement in the memory device layer is the same.

[0063] It is worth noting that "repeatedly arranged" indicates that the storage unit array is a 3D stacked structure, and the plurality of storage units 100 therein can not be completely the same structure, i.e., the plurality of storage units 100 can be the same or different in structure.

[0064] For example, as shown in Figure 1 , the functional structure of two adjacent storage units 100 in the X direction is symmetric about the common source 110, i.e., not completely repeated in space; for example, the size, material, component structure, etc. of any two storage units 100 can be the same or different; for example, the extension direction of the active layer 1111 of any two storage units 100 can be the same or different. However, this is not limited, and is determined according to the specific situation.

[0065] Figure 1 In the embodiment, only a plurality of storage units 100 are shown to form a storage device 1000 by 3D stacking, and it can be understood that the storage device 1000 can include any number of memory device layers, the memory device layer can include any number of storage units 100, and the storage unit 100 can be distributed and extended along the first horizontal direction, the second horizontal direction and the vertical direction to meet different storage requirements.

[0066] In the embodiment, the storage device 1000 can be a DRAM storage device, and the basic storage unit 100 is a 1T0C structure DRAM storage unit, i.e., each storage unit 100 includes one transistor, i.e., a single transistor can be the smallest storage unit 100 in the storage device 1000, as shown in Figure 3 and Figure 4 .

[0067] In the memory cell 100, the active layer 1111 is parallel to the insulating surface 210. For example, the active layer 1111 extends along the second horizontal direction, but is not limited thereto. For example, in other embodiments, the active layer 1111 can extend along a third horizontal direction that intersects both the first horizontal direction and the second horizontal direction. Alternatively, in yet another embodiment, the active layer 1111 can be curved, as the specific circumstances dictate.

[0068] In the memory cell 100, the gate structure 1113 includes a gate body portion 1113A, and the gate body portion 1113A includes a first gate 11131 that extends along a sidewall of the active layer 1111. It can be understood that the gate body portion 1113A, i.e., the portion of the gate structure 1113 that can control the active layer 1111, is the portion of the gate structure 1113 that extends along the active layer 1111. The active layer 1111 includes a top surface, a bottom surface, and two sidewalls between the top surface and the bottom surface. The first gate 11131 extends along a sidewall of the active layer 1111 that is parallel to the substrate 200, and the first gate 11131 is substantially perpendicular to the substrate 200. In the orthographic projection of the substrate 200, the first gate 11131 is located on one side of the active layer 1111.

[0069] In the embodiments of the present application, the source terminal 11111 of the memory cell 100 is connected to a common source structure. The common source structure can be connected to a fixed potential, for example, ground. Thus, a fixed potential can be provided for the source terminal 11111 of the DRAM memory cell 100 of the 1T0C structure.

[0070] In one embodiment, the material of the common source structure can be the same as or different from the material of the active layer 1111. For example, the material of the common source structure can be a conductive material such as polysilicon, doped polysilicon, or metal (for example, tungsten or titanium nitride).

[0071] As shown in FIGS. Figure 1 , 2 , 5, and Figure 6 , the common source structure includes at least one common source 110.

[0072] The common source structure includes at least one common source 110 that is vertically disposed on the substrate 200, and the common source 110 also extends along the first horizontal direction. The common source 110 is connected to a plurality of source terminals 11111 that are adjacent in the vertical direction, and the source terminals 11111 that are adjacent in the first horizontal direction are connected to the same common source 110.

[0073] As shown in FIGS. Figure 5As shown, the common source 110 can vertically pass through all the memory device layers, for example, vertically pass through each of the memory device layers from top to bottom. The transistors in the memory device layers vertically adjacent to each other can be connected to the same common source 110.

[0074] As shown, in the same memory device layer, the memory cells 100 are arranged in a column along the first horizontal direction. Since the common source 110 extends along the first horizontal direction, each memory cell 100 in the same column of transistors can be connected to the same common source 110. Figure 2

[0075] Further, the two columns of memory cells 100 adjacent to the common source 110 in the second horizontal direction are symmetrically arranged with respect to the common source 110 in terms of function structure, and are connected to the same common source 110, that is, the two columns of memory cells 100 adjacent in the second horizontal direction can share the common source 110.

[0076] Therefore, the common source 110 can be formed as a plate-shaped structure extending in the plane formed by the vertical direction and the first horizontal direction. Thus, the common source 110 can be formed by etching a larger trench and then filling the trench with a conductive material, which can reduce the difficulty of the preparation process and has a lower impedance.

[0077] As shown, the common source structure can include a plurality of common sources 110 arranged along the second horizontal direction. Figure 8

[0078] However, the present application is not limited thereto. In other embodiments not shown, the common source structure includes a plurality of common sources 110 vertically arranged on the substrate 200, and the common source 110 is connected to a plurality of source terminals 11111 adjacent in the vertical direction, and the source terminals 11111 adjacent in the first horizontal direction are connected to different common sources 110, that is, the common source 110 is formed as a columnar vertical conductor passing through at least two adjacent memory device layers. At this time, the common source 110 is regarded as a vertical contact, and a plurality of vertical contacts are vertically stacked to form a common source structure.

[0079] Alternatively, the common source structure can include a plurality of common sources 110 extending along the first horizontal direction, each common source 110 corresponding to a memory device layer, and the source terminals 11111 adjacent in the first horizontal direction being connected to the same common source 110, and the source terminals 11111 adjacent in the vertical direction being connected to different common sources 110, that is, the common source 110 can be formed as a linear horizontal conductor extending along the first horizontal direction, and a plurality of common sources 110 can be stacked in the vertical direction to reduce the horizontal area of the common source structure.

[0080] ​​The common source structure is not specifically limited herein, and can be specifically set according to specific requirements.

[0081] As shown in Figure 1 , 2 and Figure 8 , the storage device 1000 includes a bit line structure, the bit line structure includes a plurality of bit lines, the bit lines extend along a first horizontal direction, and the drain terminals 11112 of the storage units 100 are connected to the bit lines. In the embodiment of the present application, a specified storage unit 100 in the storage unit array can be selected by the cross positioning of the gate structure 1113 and the bit line.

[0082] The number of bit lines included in each layer of the storage device layer can be a plurality. The plurality of bit lines included in each layer of the storage device layer can be arranged at intervals along a second horizontal direction. In the same layer of the storage device layer, the storage units 100 are arranged in a column along the first horizontal direction, the bit lines extend along the first horizontal direction, and each storage unit 100 in the same column of transistors can be connected to the same bit line.

[0083] Further, as shown in Figure 2 , Figure 8 , in the storage device layer, two columns of storage units 100 adjacent to the bit lines in the second horizontal direction are symmetrically arranged in function with respect to the bit lines, and are connected to the same bit line, that is, the two columns of storage units 100 adjacent in the second horizontal direction can share the bit line.

[0084] In one embodiment, the material of the bit line can be the same as or different from the material of the common source 110 and the active layer 1111.

[0085] Exemplarily, the material of the bit line can be polysilicon, doped polysilicon or metal (for example, tungsten, titanium nitride, etc.), as long as it can conduct electricity to realize electrical connection between the source of the transistor.

[0086] Exemplarily, the bit line and the active layer 1111 in the above-mentioned transistor can be made of the same material, and the two can be connected as one.

[0087] In one embodiment, the material of the bit line can be the same as the material of the active layer 1111, and the bit line and the active layer 1111 in the same layer of the storage device layer can be provided by the same semiconductor material layer 2, that is, the two can be respectively a part of the same semiconductor material layer 2 and formed as one. Wherein, the semiconductor material layer 2 can be made of N-type polysilicon or P-type polysilicon, for example, can be made of N-type polysilicon.

[0088] Optionally, the doping concentration of the bit line can be higher than that of the active layer 1111.

[0089] In the embodiment of the present application, as shown in Figure 1 ,Figures 5 to 7 As shown, the storage device 1000 can further include an insulating spacer layer 160 for electrically isolating the active layers 1111 of the transistors of adjacent layers stacked in the vertical direction.

[0090] In one embodiment, the material of the insulating spacer layer 160 can be the same as or different from the material of the gate insulating layer 1112 described above. Exemplarily, the material of the insulating spacer layer 160 can be SiO2, SiN x or TEOS (Tetraethoxysilane) or an insulating material such as a low dielectric constant material.

[0091] In the embodiments of the present application, the gate main part 1113A further includes a second gate 11132 extending along the sidewall of the active layer 1111. In the orthographic projection of the substrate 200, the first gate 11131 and the second gate 11132 are located on two sides of the active layer 1111 and extend along the sidewall of the active layer 1111.

[0092] As shown, the transistors in the storage unit 110 are double-gate transistors, and the two gates are the first gate 11131 and the second gate 11132. Figures 2 to 7

[0093] The first gate 11131 and the second gate 11132 of the gate structure 1113 in the transistor are oppositely arranged on the horizontal two sides of the active layer 1111, which can improve the control ability of the gate on the channel in the transistor, and in particular, for the storage unit of the 1T0C structure, it is more conducive to realize the full depletion of the channel region.

[0094] In the embodiments of the present application, the material of the gate structure 1113 can include a conductive material such as metal (for example, tungsten or titanium nitride), wherein the materials of the first gate 11131 and the second gate 11132 can be the same or different. Preferably, the materials of the first gate 11131 and the second gate 11132 are the same.

[0095] Further, the shapes and widths of the first gate 11131 and the second gate 11132 can be the same or different, and can be completely opposite or only partially opposite. Preferably, the first gate 11131, the second gate 11132 and the active layer 1111 all extend along the second horizontal direction.

[0096] As shown, Figure 1 , Figure 2 and Figure 7 ​As shown in FIG. 1, the plurality of memory cells 100 adjacent in the vertical direction form a memory cell stack, and in the plurality of memory cells 100 in the memory cell stack, the active layer 1111, the gate insulating layer 1112, and the gate structure 1113 each respectively overlap in the orthographic projection of the substrate 200, and the portions of the gate structure 1113 that overlap in the orthographic projection of the substrate 200 correspond to being connected.

[0097] As an embodiment of the present application, the structures of two adjacent memory cells 100 stacked in the vertical direction are the same and are simultaneously fabricated or synchronously patterned, so that the structures in the upper and lower memory cells 100 each respectively overlap in the orthographic projection of the substrate 200.

[0098] It can be understood that, due to the process error in the fabrication process of the memory cells 100 adjacent in the vertical direction and located at different depths, the overlap includes complete overlap and approximate overlap.

[0099] It can be understood that the portions of the gate structure 1113 that overlap in the orthographic projection of the substrate 200 correspond to being connected, that is, the gate structure 1113 includes gate main body portions 1113A and other portions, the gate main body portions 1113A overlap in the orthographic projection of the substrate 200, and the gate main body portions 1113A are connected, the other portions overlap in the orthographic projection of the substrate 200, and the other portions are connected, the gate main body portions 1113A include a first gate 11131 and a second gate 11132, and the first gate 11131 and the second gate 11132 respectively overlap in the orthographic projection of the substrate 200, and the first gate 11131 and the second gate 11132 are respectively connected.

[0100] As shown in FIG. 1, the plurality of memory cells 100 adjacent in the vertical direction form a memory cell stack, and in the plurality of memory cells 100 in the memory cell stack, the active layer 1111, the gate insulating layer 1112, and the gate structure 1113 each respectively overlap in the orthographic projection of the substrate 200, and the portions of the gate structure 1113 that overlap in the orthographic projection of the substrate 200 correspond to being connected. Figure 2 Figure 7 As shown in FIG. 1, the plurality of memory cells 100 adjacent in the vertical direction form a memory cell stack, and in the plurality of memory cells 100 in the memory cell stack, the active layer 1111, the gate insulating layer 1112, and the gate structure 1113 each respectively overlap in the orthographic projection of the substrate 200, and the portions of the gate structure 1113 that overlap in the orthographic projection of the substrate 200 correspond to being connected.

[0101] ​In a memory cell stack group 11A, the first gate 11131 of the first memory cell stack 111A and the first gate 11131 of the second memory cell stack 112A are disposed opposite to each other. The gate structure 1113 also includes a conductor portion 1113B. The conductor portion 1113B includes a first conductor portion 11133 formed integrally with the first gate 11131. On the orthographic projection of the substrate 200, the first conductor portion 11133 is located on the side of the first gate 11131 away from the active layer 1111, and the first conductor portion 11133 is located at both horizontal ends of the first gate 11131.

[0102] It should be noted that this embodiment does not specifically limit whether the orthographic projections of the active layer 1111 and the gate insulating layer 1112 on the substrate 200 overlap.

[0103] like Figure 2 , Figure 7 As shown, the storage device 1000 includes a plurality of storage cell stacks horizontally distributed on a substrate 200, wherein at least two storage cell stacks are adjacent in a first horizontal direction, namely a first storage cell stack 111A and a second storage cell stack 112A.

[0104] The first storage cell stack 111A and the second storage cell stack 112A are adjacent to each other in the first horizontal direction to form a storage cell stack group 11A, that is, there are no other storage cell stacks between the first storage cell stack 111A and the second storage cell stack 112A.

[0105] The first gate 11131 of the first memory cell stack 111A is disposed opposite to the first gate 11131 of the second memory cell stack 112A, that is, the first gate 11131 of the first memory cell stack 111A and the second memory cell stack 112A are located between the active layers 1111 of the first memory cell stack 111A and the second memory cell stack 112A.

[0106] Please see Figure 2 Furthermore, in the memory cell 100, the gate structure 1113 further includes a conductor portion 1113B, which includes a first conductor portion 11133 integrally formed with the first gate 11131. In the orthographic projection of the substrate 200, the first conductor portion 11133 is located on the side of the first gate 11131 away from the active layer 1111, and the first conductor portion 11133 is located at both horizontal ends of the first gate 11131. However, this is not a limitation; in some embodiments not shown, the first conductor portion 11133 is located at one end of the first gate 11131.

[0107] Specifically, in the embodiments of this application, the first gate 11131 is generally C-shaped, such as... Figure 2It is shown that the first gate 11131 extends along the active layer 1111, and the first conductor part 11133 extends away from the active layer 1111 along the first horizontal direction by two ends of the first gate 11131.

[0108] It should be noted that the present application does not limit the angle between the first gate 11131 and the first conductor part 11133, which can be an acute angle, an obtuse angle, a right angle, etc. The angles between different first gates 11131 and first conductor parts 11133 can be the same or different. In some embodiments, the first gate 11131 and the first conductor part 11133 can also be connected in a circular arc transition. Moreover, the present application does not specifically limit whether the gate structure 1113 includes the second gate 11132.

[0109] In some embodiments, as shown in Figure 1 , Figure 2 It is shown that the first gate 11131 extends along the active layer 1111, and the first conductor part 11133 extends away from the active layer 1111 along the first horizontal direction by two ends of the first gate 11131.

[0110] Please continue to refer to Figure 2 In some embodiments, the gate body part further includes a second gate 11132, which is the same as the foregoing, and will not be repeated. The conductor part 1113B further includes a second conductor part 11134 formed integrally with the second gate 11132. On the orthographic projection of the substrate 200, the second conductor part 11134 is located on the side of the second gate 11132 away from the active layer 1111, and the second conductor part 11134 is located at the horizontal two ends of the second gate 11132. However, it is not limited to this, and in some embodiments not shown in the figure, the second conductor part 11134 is located at one end of the second gate 11132.

[0111] Specifically, the second gate 11132 in the present application is approximately in the shape of "C", as shown in Figure 2 In the embodiment, the second gate 11132 extends along the active layer 1111, and the second conductor part 11134 extends away from the active layer 1111 along the first horizontal direction by two ends of the second gate 11132.

[0112] It should be noted that the present application does not limit the angle between the first gate 11131 and the first conductor part 11133, which can be an acute angle, an obtuse angle, a right angle, etc. The angles between different first gates 11131 and first conductor parts 11133 can be the same or different. In some embodiments, the first gate 11131 and the first conductor part 11133 can also be connected in a circular arc transition. Moreover, the present application does not specifically limit whether the gate structure 1113 includes the second gate 11132.

[0113] The storage unit stack groups 11A are repeatedly arranged in the first horizontal direction, and the gate structure 1113 includes the second gate 11132 and the second conductor part 11134 of the second gate 11132, and between every two storage unit stacks arranged adjacently in the first horizontal direction, a gate electrode is formed in opposite arrangement and in a "C" shape, which can be understood as the whole formed by the first gate 11131 and the first conductor part 11133, or the whole formed by the second conductor part 11134 and the second gate 11132; for the second gate 11132, it is opposite arranged between every two storage unit stack groups 11A arranged adjacently in the first horizontal direction.

[0114] Please continue to refer to Figure 2 With Figure 9 Further, between the gate structures 1113 of at least one group of adjacent first storage unit stacks 111A and second storage unit stacks 112A, in the direction from the gate structure 1113 of the first storage unit stack 111A to the gate structure 1113 of the second storage unit stack 112A, a first insulating layer 130, a second insulating layer 140 and a third insulating layer 150 are sequentially formed.

[0115] Among them, the first insulating layer 130 and the third insulating layer 150 are made of the same material, and the first insulating layer 130 and the third insulating layer 150 respectively contact the gate main part 1113A of the first storage unit stack 111A and the second storage unit stack 112A, the second insulating layer 140 is arranged between the conductor parts 1113B of the adjacent first storage unit stack 111A and the second storage unit stack 112A, and contacts the conductor parts 1113B of the first storage unit stack 111A and the second storage unit stack 112A.

[0116] The active layer 1111 between the group of adjacent first storage unit stacks 111A and second storage unit stacks 112A includes a spacing area, and for the first storage unit stack 111A and the second storage unit stack 112A, at least part of the gate structure 1113 is located in the spacing area, the at least part of the gate structure 1113 includes at least part of the gate main part 1113A and at least part of the conductor part 1113B, and the parts of the gate structure 1113 located in the spacing area are oppositely arranged.

[0117] For example, as Figure 2As shown, the memory cell 100 includes a first gate 11131, a spacing region between the active layer 1111 of a set of adjacent first memory cell stack 111A and second memory cell stack 112A, and the first gate 11131 is disposed in the spacing region, and the gate structure 1113 includes a first conductor portion 11133 in the spacing region:

[0118] The first insulating layer 130 and the third insulating layer 150 can be prepared in the same layer and have the same material, and the first insulating layer 130 and the third insulating layer 150 contact the gate body portion 1113A, i.e., the first insulating layer 130 and the third insulating layer 150 respectively contact the first gate 11131 of the first memory cell stack 111A and the second memory cell stack 112A; the second insulating layer 140 is disposed between and contacts the adjacent first conductor portion 11133, i.e., the second insulating layer 140 isolates the first conductor portion 11133 in the spacing region.

[0119] However, the present application is not limited thereto, and in some embodiments, the memory cell 100 further includes a second gate 11132, and the second gate 11132 and the second conductor portion 11134 are located in the spacing region, and in the spacing region:

[0120] The first insulating layer 130 and the third insulating layer 150 can be prepared in the same layer and have the same material, and the first insulating layer 130 and the third insulating layer 150 contact the gate body portion 1113A, i.e., the first insulating layer 130 and the third insulating layer 150 respectively contact the second gate 11132 of the first memory cell stack 111A and the second memory cell stack 112A; the second insulating layer 140 is disposed between and contacts the adjacent second conductor portion 11134, i.e., the second insulating layer 140 isolates the second conductor portion 11134 in the spacing region.

[0121] As Figure 2 In the pair of memory cell stacks adjacent in the first horizontal direction, i.e., the first memory cell stack 111A and the second memory cell stack 112A, the portion of the gate structure 1113 located in the spacing region can be prepared from the same material layer, for example, after forming a conductive film layer in the form of a cylinder extending in the vertical direction in the spacing region, a vertical gap is formed to separate the conductive film layer.

[0122] The cutting and separating can be performed by etching. Before etching, the hollow part of the cylindrical conductive film layer is filled with an insulating material, and then etching is performed to form a vertical gap, which separates the conductive film layer into two parts spaced apart from each other, and forms the first gate 11131 and the first conductor part 11133, or the second gate 11132 and the second conductor part 11134, in the group of adjacent first memory cell stack 111A and second memory cell stack 112A, respectively. The remaining insulating material contacts the gate main part 1113A of the first memory cell stack 111A and the second memory cell stack 112A, respectively, to form the first insulating layer 130 and the second insulating layer 140. The conductor parts 1113B of the first memory cell stack 111A and the second memory cell stack 112A are opposite to each other with the vertical gap in between. The vertical gap exposes the opposite conductor parts 1113B. The first insulating layer 130 and the third insulating layer 150 can be completely separated or partially separated by the vertical gap (as shown in Figure 9 ). The second insulating layer 140 is filled in the vertical gap and contacts the conductor parts 1113B.

[0123] The first insulating layer 130 and the third insulating layer 150 isolate the gate main parts 1113A of two adjacent memory cells 100 in the first horizontal direction. The second insulating layer 140 isolates the conductor parts 1113B of two adjacent memory cells 100 in the first horizontal direction.

[0124] The first insulating layer 130 and the third insulating layer 150 can be formed in one process, and therefore, the same insulating material, such as SiO2, SiN x , TEOS, or the like, can be used for both. The materials of the first insulating layer 130 and the third insulating layer 150 can be the same as or different from those of the gate insulating layer 1112 and the insulating spacer layer 160, which are not limited in the present application. The material of the second insulating layer 140 can be the same as or different from those of the first insulating layer 130 and the third insulating layer 150.

[0125] In some embodiments, the first insulating layer 130 and the third insulating layer 150 can be single-layer or multi-layer structures, and the second insulating layer 140 can be single-layer or multi-layer structures, which are not limited in the present application.

[0126] Furthermore, the first insulating layer 130 and the third insulating layer 150 can be completely separated or partially separated by the vertical gap. Specifically, in the orthographic projection of the substrate 200: the first insulating layer 130 and the third insulating layer 150 are separately arranged on both sides of the second insulating layer 140 (as shown in Figure 2 ); or the first insulating layer 130 and the third insulating layer 150 are partially connected (as shown in Figure 9 ).

[0127] For example, the first insulating layer 130 and the third insulating layer 150 can be completely separated by the vertical gap, and the second insulating layer 140 is filled in the vertical gap and contacts the conductor parts 1113B (as shown in Figure 9As shown, the above-mentioned slit can also be formed only between the two opposite conductor portions 1113B (two first conductor portions 11133 or two second conductor portions 11134) of the two adjacent memory cells 100 in the second horizontal direction, i.e. the slit only cuts off the originally connected gate structure 1113 in the two adjacent memory cells 100 in the first horizontal direction and partially extends into the insulating material, i.e. the first insulating layer 130 and the third insulating layer 150 are partially connected.

[0128] It can be understood that even if the first insulating layer 130 and the third insulating layer 150 are partially connected, in the direction from the gate structure 1113 of the first memory cell stack 111A to the gate structure 1113 of the second memory cell stack 112A, the first insulating layer 130, the second insulating layer 140 and the third insulating layer 150 are also arranged in sequence between the gate structures 1113 of the set of adjacent first memory cell stacks 111A and second memory cell stacks 112A.

[0129] Further, between the gate structures 1113 of the set (i.e. at least one set) of adjacent first memory cell stacks 111A and second memory cell stacks 112A, in the orthographic projection of the substrate 200, the first insulating layer 130 is formed in the region surrounded by the gate body portion 1113A, the conductor portion 1113B of the first memory cell stack 111A and the second insulating layer 140, the edge of the first insulating layer 130 extending along the conductor portion 1113B of the first memory cell stack 111A is also adjacent to the second insulating layer 140, and the third insulating layer 150 is formed in the region surrounded by the gate body portion 1113A, the conductor portion 1113B of the second memory cell stack 112A and the second insulating layer 140, the edge of the third insulating layer 150 extending along the conductor portion 1113B of the second memory cell stack 112A is also adjacent to the second insulating layer 150.

[0130] Please refer to Figure 16 , etching to form a vertical slit to cut off the separated conductive film, the etching can include a first step of anisotropic etching, and a second step of wet etching.

[0131] The first step of anisotropic etching forms a pre-groove 10A, the pre-groove 10A penetrates the conductive film and the insulating material filled in the hollow part of the cylindrical conductive film layer, the pre-groove 10A has basically cut off the conductive film and separated it, at the same time, the insulating material filled in the hollow part of the cylindrical conductive film layer is patterned into the first insulating layer 130 and the third insulating layer 150.

[0132] The first insulating layer 130 is formed in the space surrounded by the conductive film along the active layer 1111 of the first memory cell stack 111A, which is formed as the gate body portion 1113A of the first memory cell stack 111A, and the end surface of the first insulating layer 130 away from the gate body portion 1113A of the first memory cell stack 111A and the end surface of the conductive film away from the gate body portion 1113A of the first memory cell stack 111A is formed as a continuous surface, and the continuous surface is exposed to the pre-groove 10A.

[0133] Similarly, the third insulating layer 150 is formed in the space surrounded by the conductive film along the active layer 1111 of the second memory cell stack 112A, which is formed as the gate body portion 1113A of the second memory cell stack 112A, and the end surface of the third insulating layer 150 away from the gate body portion 1113A of the second memory cell stack 112A and the end surface of the conductive film away from the gate body portion 1113A of the second memory cell stack 112A is formed as a continuous surface, and the continuous surface is exposed to the pre-groove 10A.

[0134] In order to completely cut off the separated conductive film and avoid short circuit between the conductor portions 1113B of the adjacent first memory cell stack 111A and the second memory cell stack 112A, the second step wet etching is performed to selectively etch the conductor film exposed to the pre-groove 10A, and the gate structure 1113 of the first memory cell stack 111A and the second memory cell stack 112A is formed.

[0135] With respect to the previous continuous surface, the end surface of the conductive film exposed to the pre-groove 10A is "retreated" due to the wet etching, so that the surface of the first insulating layer 130 and the third insulating layer 150 originally in contact with the conductor film is exposed, the pre-groove 10A is expanded to form a gap for filling the second insulating layer 140, and the exposed surface is formed in contact with the second insulating layer 140, as shown in Figure 16

[0136] Therefore, on the orthographic projection of the substrate 200, the edge of the first insulating layer 130 extending along the conductor portion 1113B of the first memory cell stack 111A is also adjacent to the second insulating layer 140, and the edge of the third insulating layer 150 extending along the conductor portion 1113B of the second memory cell stack 112B is also adjacent to the second insulating layer 140.

[0137] It should be noted that the second insulating layer 140 can be an insulating material layer or an air gap with insulating function, and the composition of the second insulating layer 140 is not specifically limited in the present application. In a preferred embodiment, as shown in Figure 2 ​As shown, the second insulating layer 140 separates the first insulating layer 130 and the third insulating layer 150 as a whole, so that the gap size where the second insulating layer 140 is located is large, and the process difficulty can be reduced.

[0138] Further, the second insulating layer 140 comprises a low dielectric constant (Low K) material, that is, the second insulating layer 140 can be made of a material with a dielectric constant less than 3.9, thereby facilitating the reduction of parasitic capacitance between transistors, including the reduction of coupling between the gate structures 1113 of the two adjacent storage units 100 in the first horizontal direction.

[0139] In particular, in the embodiment, the gate structures 1113 of the two adjacent storage units 100 in the first horizontal direction comprise conductor portions 1113B, and the distance between the closest conductor portions 1113B of the two adjacent storage units 100 in the first horizontal direction is smaller than that between the closest gate main body portions 1113A, so that the material selected for the second insulating layer 140 comprises a low dielectric constant material, and the effect of reducing the coupling between the gate structures 1113 of the two adjacent storage units 100 in the first horizontal direction is more obvious.

[0140] Further, based on the above technical solution, the transistor in the embodiment can be a junctionless field effect transistor, so that the source and the drain of the transistor do not need to be patterned and doped, and the process flow can be simplified and the production cost can be saved.

[0141] In the embodiment, the active layer 1111 is parallel to the insulating surface 210, that is, the active layer 1111 is perpendicular to the vertical direction, and the material thereof comprises polysilicon, and preferably, the material thereof comprises N-type doped polysilicon. However, the material of the active layer 1111 is not limited thereto, and can be set according to actual needs.

[0142] Further, in the embodiment, the transistor is a junctionless transistor, that is, the active layer 1111 further comprises a channel region 11113 between the source end 11111 and the drain end 11112, and the source end 11111, the drain end 11112 and the channel region 11113 have the same conductivity type. In the storage unit 100, the channel region 11113 is arranged correspondingly to the first gate 11131 and the second gate 11132, that is, the channel region 11113 is located between the first gate 11131 and the second gate 11132, and the width of the channel region 11113 in the direction from the first gate 11131 to the second gate 11132 is less than 40 nm.

[0143] It should be noted that, for the active layer 1111 with the material of polysilicon or N-type doped polysilicon, the width of the channel region is less than 40 nm, and for the active layer 1111 with the material other than polysilicon, the width of the channel region 11113 can have different ranges.

[0144] The width of the channel region 11113 in the direction from the first gate 11131 to the second gate 11132 refers to the distance between the two side surfaces of the channel region 11113 in the first horizontal direction. By making the width of the channel region 11113 in the direction from the first gate 11131 to the second gate 11132 less than 40 nm, the transistor can be a 1T0C structure storage unit 100, and read and write operations can be performed on the storage unit 100.

[0145] For example, for the storage unit 100 including one junctionless transistor and the active layer 1111 material including N-type doped polysilicon proposed in the embodiments of the present application, a read and write operation method is proposed, as shown in Figure 20 The method includes:

[0146] A negative voltage is applied to the gate structure 1113, and a positive voltage is applied to the drain end through the bit line BL, and holes are accumulated in the channel region, the threshold voltage of the transistor is reduced, and the "write 1" operation is completed; a positive voltage is applied to the gate structure 1113, and a negative voltage is applied to the drain end through the bit line BL, and carrier recombination occurs in the channel region, the threshold voltage of the transistor is restored, and the "write 0" operation is completed; when a read voltage is applied to the gate structure 1113, due to the difference in threshold voltage caused by the write operation, a drain current of different sizes is generated, so that the "0" and "1" states can be distinguished in the read operation.

[0147] For example, the width of the channel region 11113 can be 30 nm, 20 nm, or 10 nm, etc. In addition, the cross-sectional shape of the channel region 11113 perpendicular to the second horizontal direction can be a circular, square, rectangular, hexagonal, or octagonal geometric shape, and the present application is not limited in this regard.

[0148] The gate insulating layer 1112 is arranged between the gate structure 1113 of the transistor and the active layer 1111 (channel region 11113), and the material thereof can include SiO2 or high dielectric constant material, etc., and the present application is not limited in this regard. For example, the material of the active layer 1111 contains silicon, such as polysilicon, N-type or P-type doped polysilicon, etc. The gate insulating layer 1112 can be formed by oxidizing the surface containing the above-mentioned silicon-containing material, and the unoxidized silicon-containing material layer forms the active layer 1111, so that the gate insulating layer 1112 is formed only at the sidewall of the active layer 1111, and the width of the channel region 11113 can be made less than at least one of the source end 11111 and the drain end 11112, but is not limited thereto.

[0149] As shown in Figure 7 In some embodiments, an insulating material layer can also be deposited on the surface of the active layer 1111 to form the gate insulating layer 1112, so that the gate insulating layers 1112 of a plurality of storage units 100 are formed as an integral structure.

[0150] Further, as an embodiment of the present application, in the gate structure 1113:

[0151] The first gate 11131 and the second gate 11132 are electrically connected, realizing synchronous control of the first gate 11131 and the second gate 11132 in the gate structure 1113; and / or

[0152] The first gate 11131 and the second gate 11132 are independently controlled, that is, the first gate 11131 and the second gate 11132 are respectively electrically connected with an external circuit, realizing different control of the gate structure 1113, which can improve the charge holding capacity of the DRAM storage unit 100 of the 1T0C structure; and / or

[0153] The first gate 11131 and the second gate 11132 are independently controlled, and the first gate 11131 and the second gate 11132 do not completely overlap on the opposite surfaces, that is, the projections of the first gate 11131 and the second gate 11132 on the active layer 1111 do not completely overlap in the storage unit 100, which can improve the charge holding capacity of the DRAM storage unit 100 of the 1T0C structure.

[0154] The first gate 11131 and the second gate 11132 are electrically connected, and a conductive connection structure can be provided on the top and / or bottom of the first gate 11131 and the second gate 11132 to realize electrical connection between the two, but it is not limited thereto, and can be determined as appropriate as long as electrical connection between the two is realized.

[0155] The first gate 11131 and the second gate 11132 do not completely overlap on the opposite surfaces, for example, the length of the first gate 11131 is greater than or the length of the second gate 11132, or the projections of the first gate 11131 and the second gate 11132 on the active layer 1111 are staggered in the horizontal direction, which is not specifically limited in the present application.

[0156] In the storage device 1000 of the embodiment of the present application, a plurality of 1T0C structure DRAM storage units 100 are repeatedly arranged along the first horizontal direction, the second horizontal direction and the vertical direction, the storage unit 100 has simple structure and high storage density, and the storage capacity can be improved by continuing to increase the number of stacked layers as needed; the transistor can be a junctionless field effect transistor, and the active layer 1111 does not need to be patterned by ion implantation, which reduces the process difficulty and saves production cost; in the transistor of the storage unit 100, the first gate 11131 and the second gate 11132 of the gate structure 1113 are horizontally arranged on both sides of the active layer 1111, which can improve the control of the gate on the channel in the transistor.

[0157] The application further provides a manufacturing method of the storage device 1000, which is used for manufacturing the storage device 1000 in the foregoing embodiments. Please refer to Figure 10 The manufacturing method of the storage device 1000 comprises the following steps.

[0158] Please refer to the foregoing embodiments of the storage device 1000 Figure 11 Step S100: providing a substrate 1A.

[0159] In some embodiments, the substrate 1A can be the substrate 200. For the substrate 1A, please refer to the description of the substrate 200 in the foregoing embodiments of the storage device 1000, which will not be repeated here. However, the substrate can also be a temporary substrate in other embodiments.

[0160] Please refer to the foregoing embodiments of the storage device 1000 Figure 11 Step S200: preparing a plurality of film layer pairs 1 stacked along the vertical direction on the substrate 1A, wherein the film layer pairs 1 comprise semiconductor material layers 2 and first insulating medium layers 3 arranged in sequence along the vertical direction.

[0161] The plurality of film layer pairs 1 are stacked along the vertical direction to form a stacked structure, i.e., the stacked structure comprises the first insulating medium layers 3 and the semiconductor material layers 2 stacked alternately along the vertical direction.

[0162] The forming manner of the semiconductor material layers 2 and the first insulating medium layers 3 can comprise thin film deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0163] It can be understood that any suitable material and deposition process can be used to form the first insulating medium layers 3 and the semiconductor material layers 2.

[0164] The material of the semiconductor material layers 2 can be a material containing silicon, such as a semiconductor material like N-type polysilicon, but is not limited thereto. Oxide semiconductor materials and the like can also be used for the semiconductor material layers 2, as the specific case may require.

[0165] For example, the semiconductor material layers 2 can be indium gallium zinc oxide (IGZO) layers. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiO x , InSnO x , Zn x Oy N z Mg x Zn y O z In x Zn y O z In x Ga y Zn z O a Zr x In y Zn z O a Hf x In y Zn z O a Sn x In y Zn z O a Al x Sn y In z Zn a O d Si x In y Zn z O a Zn x Sn y O z Al x Zn y Sn z O a Ga x Zn y Sn z O a Zr x Zn y Sn z O a Materials such as InGaSiO can be selected based on the specific circumstances.

[0166] In one example, the material of the first insulating dielectric layer 3 can be an insulating material, such as, but not limited to, SiO2, and can also be SiN. x .

[0167] In one embodiment, the stacked structure described above may be a stacked structure of SiO2 layer (first insulating dielectric layer 3) / N-type polycrystalline silicon layer (semiconductor material layer 2).

[0168] Please refer to the specific details. Figure 12 and Figure 13, step S300: etching the plurality of film layer pairs 1 to form a plurality of first slits 4 arranged repeatedly along a first horizontal direction and a second horizontal direction, the first horizontal direction and the second horizontal direction intersecting, the first slits 4 penetrating the plurality of film layer pairs 1 along a vertical direction, forming a second insulating medium layer 5 to fill the first slits 4, in the second horizontal direction, the semiconductor material layer 2 on one side of the first slits 4 is formed into a bit line structure 120, the bit line structure 120 comprising a plurality of bit lines, each bit line extending along the first horizontal direction, a common source structure is formed on the side of the first slits 4 away from the bit line structure 120.

[0169] wherein the first horizontal direction and the second horizontal direction are the same as described above.

[0170] In the embodiments of the present application, the stack structure formed by the plurality of film layer pairs 1 can be subjected to a patterning process to form the first slits 4 penetrating the stack structure along the vertical direction, i.e., the first slits 4 vertically penetrating each semiconductor material layer 2 and the first insulating medium layer 3, for example, an anisotropic etching process (such as an ion etching process, a reactive ion etching process, or a dry etching process, or a wet etching process or a combination of dry etching and wet etching) can be used to etch from the topmost semiconductor material layer 2 downwards in a direction perpendicular to the substrate 1A to form the first slits 4, and the first slits 4 are a plurality of first slits 4 arranged repeatedly along the first horizontal direction and the second horizontal direction, i.e., the plurality of first slits 4 are arranged in an array in the stack structure. As shown in Figure 12 , the plurality of first slits 4 are arranged in columns along the first horizontal direction, and the two columns of first slits 4 adjacent in the second horizontal direction are symmetrically distributed.

[0171] As shown in Figure 12 , the semiconductor material layer 2 between the first slits 4 adjacent in the first horizontal direction is used to prepare an active layer 1111, and in the second horizontal direction, the semiconductor material layer 2 on one side of the first slits 4 is formed into a bit line structure.

[0172] It can be understood that the part of the semiconductor material layer 2 used to prepare the active layer 1111 and connected to one end of the bit line structure is used to form a drain terminal, and the part of the semiconductor material layer 2 used to prepare the active layer 1111 and away from the bit line structure is used to form a source terminal, and the source terminal is used to connect to the common source structure.

[0173] The manufacturing method of the storage device 1000 further comprises a step of preparing a common source structure, which is optionally formed on the side of the first slits 4 away from the bit line structure, and it can be understood that the common source structure is electrically connected to the source terminal.

[0174] After that, referring to Figure 13The second insulating medium layer 5 is filled in the first gap 4, and the material of the second insulating medium layer 5 can be the same as or different from that of the first insulating medium layer 3. For example, the material of the second insulating medium layer 5 can also be SiO2.

[0175] Please specifically combine Figure 14 In step S400, the second insulating medium layer 5 in the first gap 4 is etched to form a plurality of first grooves 6 arranged repeatedly along the first horizontal direction and the second horizontal direction, the first grooves 6 penetrate the second insulating medium layer 5 along the vertical direction, the first grooves 6 correspond to the first gap 4 one by one, the opposite two side walls of the first grooves 6 in the first horizontal direction both expose the semiconductor material layer 2, and on the orthographic projection of the substrate 1A, the opposite two side walls of the first grooves 6 in the second horizontal direction fall into the first gap 4.

[0176] Specifically, the first grooves 6 penetrate the second insulating medium layer 5 along the vertical direction and are located in each first gap 4, the first grooves 6 expose the semiconductor material layer 2 and the first insulating medium layer 3 between the two first grooves 6 adjacent in the first horizontal direction, and in the orthographic projection of the substrate 1A, the opposite two side walls of the first grooves 6 overlap with the side walls of the first gap 4. It can be understood that the semiconductor material layer 2 between the two first grooves 6 adjacent in the first horizontal direction is used to form the channel region 11113.

[0177] On the orthographic projection of the substrate 1A, the opposite two side walls of the first grooves 6 in the second horizontal direction fall into the first gap 4. It can be understood that there is the second insulating medium layer 5 between the first grooves 6 and the bit line structure, and the second insulating medium layer 5 is also formed between the first grooves 6 and the common source structure to be formed. The second insulating medium layer 5 can expose the channel region of the active layer 1111 and cover the source terminal and the drain terminal.

[0178] In subsequent steps, the first grooves 6 are used to prepare the gate structure 1113, so that the size of the first grooves 6 can be controlled to control the length of the gate structure 1113 formed in the first grooves 6 subsequently, that is, the length of the gate main body part extending horizontally along the active layer 1111.

[0179] In the embodiments of the present application, the etching process can be dry etching, wet etching or a combination of dry etching and wet etching.

[0180] Please specifically combine Figure 15 And Figure 16 In step S500, a gate material layer 7 is formed on the entire side wall of the first groove 6, a gate insulating material layer 8 is formed between the gate material layer 7 and the surface of the semiconductor material layer 2 exposed by the first groove 6, and a third insulating medium layer 9 is filled in the first groove 6.

[0181] It can be understood that filling the third insulating medium layer 9 in the first trench 6 means filling the third insulating medium layer 9 in the space surrounded by the gate material layer 7.

[0182] The gate material layer 7 is used to form a gate structure 1113, and the gate insulating material layer 8 is used to form a gate insulating layer 1112.

[0183] The gate insulating material layer 8 is formed at least on the surface of the semiconductor material layer 2 exposed by the first trench 6, as shown in FIG. 1C. Figure 15 In one embodiment, the semiconductor material layer 2 contains silicon, for example, N-doped polysilicon, and the gate insulating material layer 8 is obtained by oxidizing the semiconductor material layer 2, and the remaining semiconductor material layer 2 forms a channel region 11113, so that the gate insulating material layer 8 is formed only on the surface of the active layer exposed by the first trench 6, as shown in FIG. 1C. Figure 4 Figure 15 Further, since the semiconductor material layer 2 is consumed by a certain thickness, the width of the channel region 11113 formed later is smaller than the source terminal 11111 and the drain terminal 11112 (not shown); in another embodiment, the gate insulating layer material 8 is deposited on the entire sidewall of the first trench 6, and the formed memory cell 100 can be as shown in FIG. 1D. Figure 3

[0184] Optionally, the gate material layer 7 is arranged on the entire sidewall of the first trench 6, which can be a vertical cylinder, but is not limited thereto, and in some embodiments, the gate material layer 7 can be a plurality of annular shapes stacked vertically and spaced from each other, as the case can be. The preparation process thereof can be a deposition process commonly used in the art.

[0185] Further, the preparation method of the gate material layer 7 can include: depositing a conductor layer on the entire inner wall of the first trench 6, and removing the part of the conductor layer located at the bottom of the first trench 6. The part of the conductor layer located at the bottom of the first trench 6 can be removed by anisotropic etching.

[0186] The formation of the third insulating medium layer 9 can be deposition, that is, after the gate material layer 7 is formed on the entire sidewall of the first trench 6, the insulating material is deposited in the remaining first trench 6 surrounded by the gate material layer 7 to form the third insulating medium layer 9.

[0187] The material of the third insulating medium layer 9 can be the same as or different from the material of the first insulating medium layer 3 and the material of the second insulating medium layer 5, preferably, the material of the third insulating medium layer 9 is the same as the material of the first insulating medium layer 3 and the material of the second insulating medium layer 5, that is, the material of the third insulating medium layer 9 can also be SiO2 or SiN x .

[0188] ​​In addition, the material of the conductor layer can be the same as or different from the material of the semiconductor material layer 2. As an embodiment of the present application, the material of the conductor layer is different from the material of the semiconductor material layer 2, and the conductor layer can be tungsten (W), titanium nitride (TiN), or the like.

[0189] Please specify Figure 16 Step S600: etching the gate material layer 7 to form a plurality of second grooves 10 arranged repeatedly along the first horizontal direction and the second horizontal direction, the second grooves 10 penetrating through the gate material layer 7, so that the gate material layer 7 is formed into the first gate structure 11 and the second gate structure 12 spaced apart in the first horizontal direction.

[0190] The etching method at least includes anisotropic etching. In order to reduce the difficulty of the etching process, preferably, in the process of etching the gate material layer 7 to form the second grooves 10, part of the third insulating medium layer 9 is also etched, that is, the second grooves 10 also penetrate through the third insulating medium layer 9, that is, the second grooves cut the third insulating medium layer 9 into the second insulating layer and the third insulating layer connected in part.

[0191] Preferably, the second grooves 10 cut the third insulating medium layer 9 to form the second insulating layer and the third insulating layer spaced apart.

[0192] Preferably, in the process of etching the gate material layer 7 to form the second grooves 10, part of the second insulating medium layer 5 is also etched, that is, the second grooves 10 also penetrate through the second insulating medium layer 5, which can further reduce the difficulty of the etching process.

[0193] In the embodiment of the present application, the second grooves 10 extend along the second horizontal direction and penetrate through the gate material layer 7 in the vertical direction, which can be understood as that the second grooves 10 cut the gate material layer 7 to form two parts opposite in the first horizontal direction, so that the gate material layer 7 is formed into the first gate structure 11 and the second gate structure 12 spaced apart in the first horizontal direction.

[0194] It can be understood that the first gate structure 11 and the second gate structure 12 respectively belong to two adjacent storage units in the first horizontal direction.

[0195] After etching, the remaining third insulating medium layer 9 is located in the space surrounded by the second grooves 10 and the first gate structure 11 and the second gate structure 12, forming the second insulating layer and the third insulating layer. That is, in the process of etching to prepare the second grooves, the third insulating medium layer 9 covers and protects the part of the first gate structure 11 and the second gate structure 12 extending along the surface of the semiconductor material layer 2 exposed by the first grooves 6.

[0196] It can be understood that the etching to form the hole or trench through the stack structure usually adopts anisotropic etching, for example, dry etching. As the number of stack layers in the stack structure increases, the aspect ratio of the hole or trench to be formed increases, and the etching process becomes more difficult. As shown in the embodiments of the present application, when the aspect ratio of the second trench 10 is high, there is a risk that the anisotropic dry etching cannot completely cut off the gate material layer 7, and the first gate structure 11 and the second gate structure 12 can be short-circuited, resulting in a decrease in yield.

[0197] To this end, the etching of the gate material layer 7 in step S600 can be achieved by step S610.

[0198] Step S610: Anisotropically etching the gate material layer 7 on the portions of the gate material layer 7 located on the two opposite side walls of the first trench 6 in the second horizontal direction to form a pre-trench 10A, the pre-trench 10A penetrating the gate material layer 7, and the pre-trench 10A not exposing the portions of the gate material layer 7 located on the two opposite side walls of the first trench in the first horizontal direction. Wet etching the gate material layer 7 exposed by the pre-trench 10A to form the first gate structure 11 and the second gate structure 12.

[0199] The pre-trench 10A has basically cut off the gate material layer 7 to form two portions opposite in the first horizontal direction, and then a step of wet etching is performed to ensure that the gate material layer 7 is formed into the first gate structure 11 and the second gate structure 12 spaced apart in the first horizontal direction, thereby reducing the risk of short circuit and the difficulty of the etching process. However, it is not limited thereto, and the process for etching the gate material layer 7 exposed by the pre-trench 10A to form the first gate structure 11 and the second gate structure 12 can be other isotropic etching processes commonly used in the art, depending on the specific circumstances.

[0200] Anisotropically etching the gate material layer 7 on the portions of the gate material layer 7 located on the two opposite side walls of the first trench 6 in the second horizontal direction to form a pre-trench 10A, and the pre-trench 10A not exposing the portions of the gate material layer 7 located on the two opposite side walls of the first trench in the first horizontal direction, i.e., the pre-trench 10A overlaps both opposite sides of the gate material layer 7 in the second horizontal direction in the orthographic projection of the substrate 1A, and there is a gap between the two opposite sides of the gate material layer 7 in the first horizontal direction. Thus, when wet etching is performed, the etchant can only contact the end of the gate material layer 7 exposed by the pre-trench 10A.

[0201] Preferably, the pre-trench 10A also penetrates the third insulating medium layer 9, and the wet etching selectively etches the gate material layer 7 without etching the third insulating medium layer 9.

[0202] Specifically, the anisotropic etching forms the pre-trench 10A, which penetrates the gate material layer 7 and the third insulating medium layer 9, and substantially cuts off the gate material layer 7, while the third insulating medium layer 9 filled in the hollow part of the cylinder-shaped gate material layer 7 is patterned into the second insulating layer and the third insulating layer.

[0203] The second insulating layer and the third insulating layer are formed in the space surrounded by the pre-trench 10A and the gate material layer 7 substantially cut off into two parts, wherein the part of the gate material layer 7 extending along the first slit 4 in the first horizontal direction forms the gate body part, the second insulating layer and the third insulating layer are away from the end surface of the gate body part in contact with them, and the end surface of the gate material layer 7 away from the gate body part forms a continuous surface, and the continuous surface is exposed to the pre-trench 10A, as shown in Figure 16 .

[0204] In order to completely cut off the gate material layer 7 and avoid short circuit between the first gate structure 11 and the second gate structure 12, the second step wet etching is performed to selectively etch the gate material layer 7 exposed by the pre-trench 10A, thereby forming the first gate structure 11 and the second gate structure 12.

[0205] The end surface of the gate material layer 7 exposed by the pre-trench 10A “retreats” due to the wet etching relative to the previous continuous surface, so that the surface of the second insulating layer and the third insulating layer originally in contact with the gate material layer 7 is exposed, and the pre-trench 10A is expanded to form the second slit 10, as shown in Figure 16 .

[0206] Preferably, the wet etching does not etch the part of the first gate structure 11 and the second gate structure 12 extending along the surface of the semiconductor material layer 2 exposed by the first trench 6. Specifically, the degree of wet etching of the gate material layer 7 can be achieved by controlling the time of wet etching. Thus, the risk of short circuit is reduced while the gate length is not affected.

[0207] Thus, please refer to Figure 2 , Figure 14 and Figure 19 , the first gate structure 11 and the second gate structure 12 both include the part extending along the surface of the semiconductor material layer 2 exposed by the first trench 6, i.e. both include the gate body part 1113A, and the part located on the side of the gate body part 1113A away from the active layer 1111, i.e. the conductor part 1113B, which is located at the horizontal two ends of the gate body part 1113A.

[0208] Thus, the semiconductor material layer 2 between two first trenches 6 adjacent in the first horizontal direction is formed as an active layer 1111, the part of the gate insulating material layer 8 between the gate structure 1113 and the active layer 1111 is formed as a gate insulating layer 1112, and the active layer 1111, the gate insulating layer 1112 and the gate structure 1113 are formed as a memory cell 100 of the memory device 1000. One end of the active layer 1111 is connected to a bit line, and the other end of the active layer 1111 is connected to a common source structure 120. It can be understood that the gate structure 1113 is one of the first gate structure 11 and the second gate structure 12 described above, and the first gate structure 11 and the second gate structure 12 belong to two memory cells 100 respectively.

[0209] Please specifically combine Figure 17 Step S700: filling the fourth insulating medium layer 13 in the second trench 10.

[0210] The fourth insulating medium layer 13 is formed as the first insulating layer.

[0211] It should be noted that the first insulating layer described above is the second insulating layer 140 in the embodiment of the memory device 1000 described above (for example, Figure 2 ). The fourth insulating medium layer 13 insulates and isolates the gate structures 1113 of the transistors adjacent in the first horizontal direction.

[0212] It should be noted that the fourth insulating medium layer 13 used to form the first insulating layer can be an insulating material layer or an air gap, and the composition of the fourth insulating medium layer 13 and the first insulating layer is not limited in the present application.

[0213] Further, the material of the fourth insulating medium layer 13 includes a low dielectric constant material.

[0214] Exemplarily, the fourth insulating medium layer 13 can be made of a material with a dielectric constant lower than 3.9, thereby facilitating reduction of parasitic capacitance between transistors.

[0215] The material of the fourth insulating medium layer 13 can be the same as or different from the materials of the first insulating medium layer 3 to the third insulating medium layer 9. Further, the material of the fourth insulating medium layer 13 is different from the materials of the first insulating medium layer 3 to the third insulating medium layer 9.

[0216] In the embodiment of the present application, the material of the third insulating medium layer 9 can be SiO2 or SiN x , and the material of the fourth insulating medium layer 13 is a low dielectric constant material.

[0217] Thus, the second insulating layer, the first insulating layer and the third insulating layer are arranged between two gate main body parts adjacent in the first horizontal direction.

[0218] It should be noted that the second insulating layer is the first insulating layer 130 in the above embodiment of the storage device 1000, and the third insulating layer is the third insulating layer 150 in the above embodiment of the storage device 1000. It can be understood that the second insulating layer and the third insulating layer are formed after the third insulating medium layer 9 is patterned.

[0219] Further, as an embodiment of the present application, the two first trenches 6 adjacent in the first horizontal direction do not completely overlap on the two opposite surfaces in the first horizontal direction.

[0220] It can be understood that the two first trenches 6 adjacent in the first horizontal direction can be used to form the gate structure 1113 in the same transistor, the gate structure 1113 including the first gate 11131 and the second gate 11132, so that the two opposite surfaces of the two first trenches 6 adjacent in the first horizontal direction do not completely overlap, and the first gate 11131 and the second gate 11132 which do not completely overlap on the opposite surfaces can be formed. The storage unit 100 includes a transistor including a first gate 11131 and a second gate 11132 which are opposite and do not completely overlap, which is the same as the above-mentioned embodiment, and will not be described again.

[0221] In some embodiments, the method of forming a common source structure includes:

[0222] Step S310: forming a common source 110, the common source 110 including a plurality of vertical contacts.

[0223] Embodiments in which the common source 110 includes vertical contacts are the same as the above-mentioned embodiments of the storage device 1000, and will not be described again.

[0224] In a preferred embodiment of the present application, the common source 110 is a plate-shaped structure extending in the first horizontal direction, i.e. parallel to the bit line structure 120, and the common source 110 extends through the stack structure in the vertical direction and is connected to the semiconductor material layer 2 of each layer.

[0225] Based on the above, the method of forming a common source structure includes: etching a plurality of film layer pairs 1 to form a plurality of third gaps arranged repeatedly in the second horizontal direction, the third gaps extending in the first horizontal direction and extending through the plurality of film layer pairs 1 in the vertical direction, filling the third gaps with a conductive material to form a common source 110, the common source 110 being connected to the semiconductor material layer 2 adjacent in the vertical direction, or in other words, the common source 110 being connected to the semiconductor material layer 2 of each layer.

[0226] Specifically, referring to Figure 18 , Figure 19As shown, the semiconductor material layer 2 and the fourth insulating medium layer 13 are etched to form a third trench 14, the third trench 14 extends along the first horizontal direction, the third trench 14 penetrates the semiconductor material layer 2 and the fourth insulating medium layer 13, and the conductive layer 15 is filled in the third trench 14 to form the common source 110.

[0227] The embodiment in which the common source 110 includes a plate-shaped structure is the same as the foregoing embodiment of the storage device 1000, and will not be described again.

[0228] It is worth mentioning that, although the content of the manufacturing method of the storage device in the embodiment is described in the order of method steps, in specific implementation, the order of some method steps can be changed, for example, the preparation step of the common source structure can be performed after step S200, before any step, according to specific needs.

[0229] In one embodiment, the method of forming the common source structure includes: the semiconductor material layer 2 located on both sides of the first gap 4 in the second horizontal direction respectively forms the bit line structure 120 and the common source 110.

[0230] The embodiment in which the common source 110 includes a horizontal wire extending along the first direction is the same as the foregoing, and will not be described again.

[0231] The manufacturing method of the storage device of the embodiment of the application can reduce the risk of short circuit while not affecting the gate length, and significantly improve the yield of the storage device 1000, in addition to the beneficial effects of the foregoing embodiment of the storage device 1000.

[0232] Although the foregoing embodiment of the application proposes a 3D 1T0C DRAM storage device, the storage device has a C-shaped gate electrode and can reduce the risk of short circuit, but for a repeated unit including a 3D stack of semiconductor devices with a horizontal channel and a vertical gate, a C-shaped gate can be prepared to reduce short circuit. Therefore, the application also proposes the following embodiments of the semiconductor device.

[0233] The semiconductor device of the embodiment of the application includes: a substrate; a transistor stack including a plurality of transistors vertically stacked on the substrate; the transistor includes an active layer and a gate electrode, the active layer extends along the horizontal direction, and the gate electrode is located on the sidewall of the active layer. The projections of all gate electrodes in a transistor stack on the substrate overlap, the gate electrode includes an integral gate body and a conductor, the gate body is arranged along the length direction of the active layer, the conductor is located on the side of the gate body away from the active layer, and the conductor is located at both ends of the gate body in the horizontal direction.

[0234] The gate main body part, the conductor part, the gate electrode, and the transistor stack can be similar to the gate main body part, the conductor part, the gate structure, and the memory cell stack including only one transistor in the foregoing embodiments of the memory device, and thus will not be described again.

[0235] In some embodiments not shown, the conductor part can be located at one end of the gate main body part in the horizontal direction.

[0236] In the semiconductor device according to the embodiments, the transistor included in the repeating unit can be a JFET or a MOSFET, and is not specifically limited. However, it should be noted that when the transistor is a MOSFET, the transistor further includes a gate insulating layer between the gate main body part and the active layer. It can be understood that the repeating unit can further include other structures in addition to the transistor as described in the foregoing embodiments.

[0237] In the embodiments, the plurality of transistor stacks are horizontally distributed on the substrate, and the gate electrodes of the two adjacent transistor stacks are oppositely arranged in the horizontal direction perpendicular to the extending direction of the gate main body part.

[0238] It can be understood that the gate electrodes of the two adjacent transistor stacks are oppositely arranged, that is, the gate electrodes of the two transistor stacks are located between the active layers of the two transistor stacks and are oppositely arranged, including the gate main body part and the conductor part.

[0239] For example, the extending direction of the active layer and the gate main body part is the second horizontal direction, and the horizontal direction perpendicular to the extending direction of the gate main body part is the first horizontal direction, that is, the gate electrodes of the two adjacent transistor stacks are oppositely arranged in the first horizontal direction.

[0240] In the embodiments, the oppositely arranged gate electrodes of the adjacent transistor stacks are in the shape of “C”. The formation of the gate electrodes of the transistor stacks in the shape of “C” can be achieved by the method of step S610 of the manufacturing method of the memory device, that is, etching to form a pre-groove to substantially disconnect the gate material layer integrally prepared for forming the gate electrodes of the adjacent transistor stacks, and then performing wet etching to form the gate electrodes of the adjacent transistor stacks disconnected from each other. Here, the same as the foregoing, and thus will not be described again. In this way, while ensuring the cutting and reducing the risk of short circuit, the length of the gate electrode is not affected.

[0241] Further, in the embodiment of the present application, the semiconductor device comprises a first insulating layer, a second insulating layer and a third insulating layer, the first insulating layer, the second insulating layer and the third insulating layer are sequentially arranged between the gate electrodes of two adjacent transistor stacks in the horizontal direction perpendicular to the extension direction of the gate main body, the first insulating layer and the third insulating layer are made of the same material and respectively contact the gate main body of two adjacent transistor stacks, and the second insulating layer is arranged between the conductor of two adjacent transistor stacks and contacts the conductor of two adjacent transistor stacks.

[0242] Specifically, the first insulating layer and the third insulating layer isolate the gate main body of two adjacent transistor stacks in the first horizontal direction (i.e. the horizontal direction perpendicular to the extension direction of the gate main body), and the second insulating layer isolates the conductor of two adjacent transistor stacks in the first horizontal direction. The first insulating layer and the third insulating layer can be formed in one process, and therefore, the same insulating material, such as SiO2, SiN x or TEOS, etc. can be used.

[0243] Further, since the gate electrode can be prepared by the step S610 in the manufacturing method of the storage device, in the orthographic projection of the substrate, between the gate electrodes of two adjacent transistor stacks: the first insulating layer and the third insulating layer are respectively formed in the area surrounded by the second insulating layer and the gate electrodes of two adjacent transistor stacks, and the first insulating layer is adjacent to the second insulating layer along the edge of the conductor part in contact with the first insulating layer, and the third insulating layer is adjacent to the second insulating layer along the edge of the conductor part in contact with the third insulating layer.

[0244] The material of the second insulating layer can be the same as or different from the material of the first insulating layer and the third insulating layer. Since the second insulating layer is formed in a different process from the first insulating layer and the third insulating layer, preferably, the material of the second insulating layer is different from the material of the first insulating layer and the third insulating layer.

[0245] It should be noted that the structure, material and function, etc. of the first insulating layer, the second insulating layer and the third insulating layer mentioned in the context of the embodiment of the semiconductor device are basically the same as the structure, material and function, etc. of the first insulating layer, the second insulating layer and the third insulating layer mentioned in the above embodiment of the storage device, and other contents of the first insulating layer, the second insulating layer and the third insulating layer not mentioned in the embodiment of the semiconductor device can be referred to the corresponding contents of the first insulating layer, the second insulating layer and the third insulating layer in the above embodiment of the storage device, which will not be described in detail herein.

[0246] Further, in the embodiment of the present application, the first insulating layer and the third insulating layer are separately arranged on both sides of the second insulating layer; or the first insulating layer and the third insulating layer are partially connected.

[0247] The space between the adjacent transistor stacks is filled with a material layer, and the part of the material layer in the space is cut to form a gap in the vertical direction.

[0248] The cutting can be performed by etching, and before the etching, the hollow part of the material layer is filled with an insulating material, and then the etching is performed to form the gap, which separates the material layer into two parts, which are formed as the conductor part and the gate main part of the adjacent transistor stacks, respectively, and the remaining insulating material is formed as the first and second insulating layers, respectively, and the conductor parts of the two transistor stacks are opposite to each other, and the gap exposes the opposite conductor parts, and the first and third insulating layers can be completely separated or partially separated by the gap, and the second insulating layer fills the gap and contacts the conductor parts.

[0249] For example, the gap can be formed only between the opposite conductor parts of the two transistor stacks adjacent in the second horizontal direction, that is, the gap only cuts the gate electrodes originally connected between the two transistor stacks adjacent in the second horizontal direction and partially extends into the insulating material, that is, the first and third insulating layers are partially connected.

[0250] In a preferred embodiment, the second insulating layer separates the first and third insulating layers as a whole, so that the gap has a larger size, which can reduce the process difficulty.

[0251] Further, in the embodiments of the present application, the second insulating layer includes a low dielectric constant (Low K) material.

[0252] That is, the second insulating layer can be made of a material with a dielectric constant less than 3.9, which is beneficial to reduce the parasitic capacitance between the transistors, including reducing the coupling between the gate electrodes of the two transistors adjacent in the horizontal direction.

[0253] In particular, in the embodiments of the present application, the gate electrodes of the two transistors adjacent in the horizontal direction include the conductor parts, and the distance between the closest conductor parts of the two transistors is smaller than the distance between the closest gate main parts, so that the material selected for the second insulating layer includes a low dielectric constant material, which can more obviously reduce the coupling between the gate electrodes of the two transistors adjacent in the horizontal direction, and avoid crosstalk between the conductor parts of the two transistors adjacent in the horizontal direction.

[0254] Further, in the embodiments of the present application, the overlapping part of the gate electrodes in the orthographic projection of the substrate corresponds to the connection.

[0255] That is to say, the gate electrodes in the transistor stack are integrally prepared, that is, the gate electrodes of each transistor in the transistor stack are connected together as an integral structure, and the gate electrodes are prepared and formed in one process, so that all the transistors stacked in the vertical direction can be controlled through the "one" vertically arranged gate electrode, which can simplify the manufacturing process of the semiconductor device and reduce the manufacturing cost.

[0256] In the semiconductor device of the embodiments of the present application, the plurality of transistors are vertically stacked to form a transistor stack, and the transistors have horizontal channels and vertical gates. The gates of adjacent transistor stacks can be prepared synchronously, thereby reducing the manufacturing cost. The vertical gate includes a gate main body portion extending horizontally along the active layer, and a conductor portion located at both horizontal ends of the gate main body portion. The conductor portion is horizontally located at the side of the gate main body portion away from the active layer, which can reduce the risk of short circuit between the vertical gates while not affecting the length of the gate.

[0257] In the description of the present specification, the description referring to the terms "embodiment one", "embodiment two", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. The illustrative description of the above terms does not necessarily refer to the same embodiment or example in the present specification. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0258] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory device, comprising: Comprising: a substrate comprising an insulating surface; an array of memory cells comprising a plurality of memory cells disposed on the insulating surface, the plurality of memory cells being repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction, the first horizontal direction intersecting the second horizontal direction; each of the memory cells comprising a transistor comprising an active layer, a gate insulating layer, and a gate structure, the gate structure comprising a gate main portion, the gate main portion comprising a first gate, the active layer being parallel to the insulating surface, the first gate extending along a sidewall of the active layer, the gate insulating layer being between the first gate and the active layer; the memory device further comprising a common source structure and a bit line structure, the bit line structure comprising a plurality of bit lines, each of the bit lines extending along the first horizontal direction, the active layer comprising a source end and a drain end, the source end being connected to the common source structure, the drain end being connected to one of the bit lines; wherein a plurality of the memory cells adjacent in the vertical direction form a memory cell stack, in the memory cell stack, the gate structure overlaps in a projection onto the substrate; a plurality of the memory cell stacks comprising a first memory cell stack and a second memory cell stack, the first memory cell stack and the second memory cell stack being adjacent in the first horizontal direction to form a memory cell stack group, in the memory cell stack group, the first gate of the first memory cell stack is oppositely disposed from the first gate of the second memory cell stack; the gate structure further comprising a conductor portion, the conductor portion comprising a first conductor portion formed integrally with the first gate, in a projection onto the substrate, the first conductor portion is on a side of the first gate away from the active layer, and the first conductor portion is at horizontal ends of the first gate; between the gate structures of at least one group of adjacent first memory cell stacks and second memory cell stacks, in a direction from the gate structure of the first memory cell stack to the gate structure of the second memory cell stack, a first insulating layer, a second insulating layer, and a third insulating layer are sequentially formed, the first insulating layer and the third insulating layer are of the same material; the first insulating layer and the third insulating layer respectively contact the gate main portion of the first memory cell stack and the second memory cell stack, the second insulating layer is disposed between the conductor portions of the first memory cell stack and the second memory cell stack opposite each other and contacts the conductor portions of the first memory cell stack and the second memory cell stack.

2. The memory device of claim 1, wherein, the gate main portion further comprising a second gate, the second gate extending along a sidewall of the active layer, in a projection onto the substrate, the first gate and the second gate are oppositely disposed on two sides of the active layer.

3. The memory device of claim 1, wherein, A plurality of the memory cells adjacent in the vertical direction form a memory cell stack, in the plurality of the memory cells in the memory cell stack, the active layer, the gate insulating layer, and the gate structure respectively overlap in the orthographic projection of the substrate, and the overlapping part of the gate structure in the orthographic projection of the substrate corresponds to being connected.

4. The memory device of claim 1, wherein, The memory cell stack groups are arranged repeatedly in the first horizontal direction.

5. The memory device of claim 4, wherein, The gate main part comprises a second gate, the second gate extends along the sidewall of the active layer, in the orthographic projection of the substrate, the first gate and the second gate are oppositely arranged on both sides of the active layer; The conductor part further comprises a second conductor part formed integrally with the second gate, in the orthographic projection of the substrate, the second conductor part is located on the side of the second gate away from the active layer, and the second conductor part is located at the horizontal two ends of the second gate; The second gate is oppositely arranged between two memory cell stacks adjacent in the first horizontal direction.

6. The memory device of any one of claims 1 to 5, wherein, In the gate structure between the at least one group of adjacent first memory cell stacks and second memory cell stacks, in the orthographic projection of the substrate: The first insulating layer is formed in the region surrounded by the gate main part, the conductor part of the first memory cell stack, and the second insulating layer, and the edge of the first insulating layer extending along the conductor part of the first memory cell stack is also adjacent to the second insulating layer; The third insulating layer is formed in the region surrounded by the gate main part, the conductor part of the second memory cell stack, and the second insulating layer, and the edge of the third insulating layer extending along the conductor part of the second memory cell stack is also adjacent to the second insulating layer.

7. The memory device of any one of claims 1 to 5, wherein, In the orthographic projection of the substrate: The first insulating layer and the third insulating layer are arranged separately on both sides of the second insulating layer; or the first insulating layer and the third insulating layer are partially connected.

8. The memory device of any one of claims 1 to 5, wherein, The second insulating layer comprises a low dielectric constant material.

9. The memory device of claim 2 or 5, wherein, The transistor is a junctionless transistor, the material of the active layer comprises N-type doped polysilicon, and the active layer further comprises a channel region between the source terminal and the drain terminal, in the memory cell, the channel region is located between the first gate and the second gate, and the width of the channel region in the direction from the first gate to the second gate is less than 40nm.

10. The memory device of claim 2 or 5, wherein, In the gate structure: The first gate and the second gate are electrically connected; and / or The first gate and the second gate are independently controlled; and / or The first gate and the second gate are independently controlled, and the first gate and the second gate do not completely overlap on the opposite faces.

11. The memory device of claim 1, wherein, The common source structure comprises at least one common source vertically arranged on the substrate, the common source further extends along the first horizontal direction, and the common source is connected with the source terminals of a plurality of the active layers adjacent in the vertical direction, the source terminals of the active layers adjacent in the first horizontal direction are connected to the same common source.

12. The memory device of any one of claims 1 to 5, 11, wherein, The transistor is a junctionless transistor.

13. A method for manufacturing a storage device, characterized by comprising: The method comprises the steps of: providing a substrate; forming a plurality of film layer pairs stacked along a vertical direction on the substrate, the film layer pairs comprising semiconductor material layers and first insulating medium layers arranged sequentially along the vertical direction; etching the plurality of film layer pairs to form a plurality of first gaps arranged repeatedly along a first horizontal direction and a second horizontal direction, the first horizontal direction intersecting the second horizontal direction, the first gaps penetrating the plurality of film layer pairs along the vertical direction, forming second insulating medium layers filling the first gaps, in the second horizontal direction, the semiconductor material layers on one side of the first gaps forming bit line structures, the bit line structures comprising a plurality of bit lines, each of the bit lines extending along the first horizontal direction, the common source structures being formed on the side of the first gaps away from the bit lines; etching the second insulating medium layers in the first gaps to form a plurality of first trenches arranged repeatedly along the first horizontal direction and the second horizontal direction, the first trenches penetrating the second insulating medium layers along the vertical direction, the first trenches corresponding to the first gaps one by one, both of the sidewalls of the first trenches opposite in the first horizontal direction exposing the semiconductor material layers, and on the orthographic projection of the substrate, both of the sidewalls of the first trenches opposite in the second horizontal direction falling into the first trenches; forming a gate material layer on the entire sidewalls of the first trenches, and a gate insulating material layer between the gate material layer and the surfaces of the semiconductor material layers exposed by the first trenches, filling a third insulating medium layer in the space surrounded by the gate material layer; etching the gate material layer to form a plurality of second trenches arranged repeatedly along the first horizontal direction and the second horizontal direction, the second trenches penetrating the gate material layer, so that the gate material layer forms first gate structures and second gate structures spaced apart in the first horizontal direction; filling a fourth insulating medium layer in the second trenches.

14. The method for manufacturing a memory device according to claim 13, wherein the etching the gate material layer to form a plurality of second trenches arranged repeatedly along the first horizontal direction and the second horizontal direction, the second trenches penetrating the gate material layer, so that the gate material layer forms first gate structures and second gate structures spaced apart in the first horizontal direction comprises: anisotropically etching the portions of the gate material layer on the sidewalls of the first trenches opposite in the second horizontal direction to form pre-trenches, the pre-trenches penetrating the gate material layer and the pre-trenches not exposing the portions of the gate material layer on the sidewalls of the first trenches opposite in the first horizontal direction; wet etching the gate material layer exposed by the pre-trenches to form the second trenches.

15. The method for manufacturing a storage device according to claim 14, wherein in the step of anisotropically etching the portions of the gate material layer on the sidewalls of the first trenches opposite in the second horizontal direction to form pre-trenches, further comprising etching the third insulating medium layer, the pre-trenches further causing the third insulating medium layer to form second insulating layers and third insulating layers at least partially spaced apart in the first horizontal direction.

16. The method for manufacturing a storage device according to claim 13, wherein The forming of the gate material layer on the whole sidewall of the first trench comprises: depositing a conductor layer on the whole inner wall of the first trench, and removing the part of the conductor layer located at the bottom of the first trench.

17. The method for manufacturing a storage device according to claim 13, wherein The method for preparing the gate insulating material layer comprises deposition; or The material of the semiconductor material layer comprises polysilicon, and the method for preparing the gate insulating material layer comprises thermal oxidation of the semiconductor material layer.

18. The method for manufacturing a storage device according to claim 13, wherein The material of the fourth insulating medium layer comprises low dielectric constant material, and / or The material of the third insulating medium layer is different from that of the fourth insulating medium layer.

19. The method for manufacturing a storage device according to claim 13, wherein In the first horizontal direction, two first trenches adjacent to each other, the two surfaces opposite to each other do not completely overlap.

20. The method for manufacturing a storage device according to claim 13, wherein The method for forming the common source structure comprises the following steps: Etching the semiconductor material layer to form a third trench extending along the first horizontal direction, the third trench penetrating through the whole semiconductor material layer, filling a conductive layer in the third trench to form a common source structure; In the second horizontal direction, the common source structure and the bit line structure are respectively located on both sides of the first gap.

21. A semiconductor device, comprising: Comprise: a substrate; a transistor stack comprising a plurality of transistors vertically stacked on the substrate; The transistor comprises an active layer and a gate electrode, the active layer extends along the horizontal direction, and the gate electrode is located on the sidewall of the active layer, and the projections of all gate electrodes in a transistor stack on the substrate overlap; The gate electrode comprises an integral gate body part and a conductor part, the gate body part is arranged along the length direction of the active layer, the conductor part is located on the side of the gate body part away from the active layer, and the conductor part is located at both ends of the gate body part in the horizontal direction; Wherein, the transistor stack is multiple, and multiple transistor stacks are horizontally distributed on the substrate; in the horizontal direction perpendicular to the extension direction of the gate body part, the gate electrodes of two adjacent transistor stacks are oppositely arranged. The semiconductor device further comprises a first insulating layer, a second insulating layer and a third insulating layer; in the horizontal direction perpendicular to the extension direction of the gate body part, the first insulating layer, the second insulating layer and the third insulating layer are sequentially arranged between the gate electrodes of the two adjacent transistor stacks, the first insulating layer and the third insulating layer are made of the same material and respectively contact the gate body parts of the two transistor stacks, and the second insulating layer is arranged between the conductor parts of the two adjacent transistor stacks and contacts the conductor parts of the two adjacent transistor stacks.

22. The semiconductor device according to claim 21, wherein Between the gate electrodes of the two adjacent transistor stacks, on the projection of the substrate: The first insulating layer and the third insulating layer are respectively formed in the area surrounded by the gate electrodes of the two adjacent transistor stacks and the second insulating layer, the edge of the first insulating layer extending along the conductor part contacting it is also adjacent to the second insulating layer, and the edge of the third insulating layer extending along the conductor part contacting it is also adjacent to the second insulating layer.

23. The semiconductor device according to claim 21, wherein In the orthographic projection of the substrate: the first insulating layer and the third insulating layer are separately arranged on both sides of the second insulating layer; or the first insulating layer and the third insulating layer are partially connected.

24. The semiconductor device according to claim 21, wherein The second insulating layer comprises a low dielectric constant material.

25. The semiconductor device according to claim 21, wherein The transistor further comprises a gate insulating layer between the gate main body and the active layer; and / or The overlapping part of the gate electrode in the orthographic projection of the substrate corresponds to the connection.

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