Semiconductor structure

Abstract

A semiconductor structure includes a plurality of active regions disposed on a substrate, and a plurality of gate structures extending in a first direction and intersecting the active regions, dividing each active region into an intermediate portion and two end portions. The plurality of bit line structures extend across the active region in the second direction and are electrically connected with the middle part of the active region. The bit line structures include a first bit line structure on the outer side and a second bit line structure on the inner side. The first plug structures and the second plug structures are alternately arranged on the outer side of the first bit line structure at intervals in the second direction, the bottoms of the first plug structures are lower than the bottoms of the second plug structures, the contact area between the bottoms of the first plug structures and the ends of the active region is large, and the electric connection quality can be improved.

Description

Technical Field

[0001] The invention relates to a semiconductor structure, in particular to a semiconductor structure with a plug structure. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory, including an array region consisting of multiple memory cells and a peripheral area consisting of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage or release of the charge of the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array region and are electrically connected to each memory cell.

[0003] In order to obtain a chip with a higher density, the structure of the memory cell has been developed towards three-dimensionality, such as using buried wordline connection and stacked capacitor technology. Stacked capacitor technology refers to setting the capacitor of the memory cell above the substrate and realizing electrical connection with the transistor in the substrate in the vertical direction through a plug structure and a connection pad structure, thereby saving the substrate area occupied by the capacitor and conveniently increasing the height of the electrode plate of the capacitor to obtain a larger capacitance. At present, there are still some technical problems that need to be further improved. Summary of the invention

[0004] The present invention aims to provide a semiconductor structure, wherein the plug structure has different depths, so as to improve the contact quality between the plug structure and the active region of the transistor.

[0005] An embodiment of the present invention provides a semiconductor structure, which includes a substrate, the substrate includes a plurality of active regions. A plurality of gate structures extend along a first direction and intersect with the active regions, and divide each of the active regions into a middle portion and two end portions. A plurality of bit line structures extend along a second direction and are electrically connected to the middle portion of the active regions, wherein the first direction and the second direction are perpendicular to each other, and the bit line structure includes an outer first bit line structure and an inner second bit line structure. A plurality of first plug structures and second plug structures are alternately and spaced apart along the second direction on the outer side of the first bit line structure and are electrically connected to the end portions, wherein the bottom of the first plug structure is lower than the bottom of the second plug structure.

[0006] An embodiment of the present invention provides a semiconductor structure, comprising a substrate, the substrate comprising a plurality of active regions, a plurality of gate structures extending along a first direction and intersecting the active regions, a plurality of spacers disposed on the gate structures, a plurality of first plug structures and second plug structures alternately arranged between the spacers along the second direction and electrically connected to the active regions respectively, wherein the bottom of the first plug structure is lower than the bottom of the second plug structure.

[0007] An embodiment of the present invention provides a semiconductor structure, which includes a substrate, the substrate includes a plurality of active regions. A plurality of gate structures extend along a first direction and intersect with the active regions. A plurality of bit line structures extend along a second direction and are electrically connected to the active regions, wherein the first direction and the second direction are perpendicular to each other, and the bit line structures include a first bit line structure on the outside and a second bit line structure on the inside. At least one first plug structure is arranged on the outside of the first bit line structure. A plurality of third plug structures are arranged on the inside of the first bit line structure and between the second bit line structure and are arranged with the first plug structure along the first direction, wherein in a cross-sectional view, the bottom of the first plug structure is lower than the bottom of the third plug structure, and the width of the first plug structure is greater than the width of the third plug structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 16 FIG. 1 is a schematic diagram of a semiconductor structure during a manufacturing process according to an embodiment of the present invention, wherein Figure 1 , Figure 7 and Fig.12 For the plan view, Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 8 and Fig.13 It is a cross-sectional view of the semiconductor structure taken along the AA cut line in the plan view. Figure 6 , Fig. 9 and Fig.14It is a cross-sectional view of the semiconductor structure taken along the BB cut line in the plan view. Fig.10 and Fig.15 It is a cross-sectional view of the semiconductor structure taken along the CC cut line in the plan view. Fig.11 and Fig.16 It is a cross-sectional view of the semiconductor structure taken along the DD cut line in the plan view.

[0009] The reference numerals are described as follows:

[0010] PR surrounding area

[0011] AR Array Area

[0012] 100 Substrate

[0013] 102 Active Area

[0014] 104 Isolation Structure

[0015] 106 Gate Structure

[0016] 108 Insulation pad

[0017] 122 Semiconductor layer

[0018] 124 Interface layer

[0019] 126 Metal Layer

[0020] 128 Hard mask layer

[0021] 132 gate dielectric layer

[0022] 134 Metal Layer

[0023] 136 Polysilicon layer

[0024] 138 Insulation cover

[0025] 142 first insulation layer

[0026] 144 Second insulation layer

[0027] 152 Third insulation layer

[0028] 154 Dielectric layer

[0029] 156 Spacer

[0030] 162 contact material layer

[0031] 164 Barrier

[0032] 166 Conductive layer

[0033] 172 Insulation Materials

[0034] 174 Etch stop layer

[0035] 176 Support layer

[0036] 108a Silicon oxide layer

[0037] 108b Silicon nitride layer

[0038] 108c Silicon oxide layer

[0039] 144s gap

[0040] AA Tangent

[0041] BB Tangent

[0042] BE bottom electrode

[0043] BL bit line structure

[0044] BL1 First bit line structure

[0045] BL2 Second bit line structure

[0046] CAP capacitor structure

[0047] CC Tangent

[0048] D1 First direction

[0049] D2 Second direction

[0050] D3 third direction

[0051] D4 Fourth direction

[0052] DBL Dummy Bit Line Structure

[0053] DD Tangent

[0054] IL Capacitor dielectric layer

[0055] OP1 First contact hole

[0056] OP2 Second contact hole

[0057] OP3 Third contact hole

[0058] OP4 Fourth contact hole

[0059] R1 First depression

[0060] R2 Second depression

[0061] SC1 first plug structure

[0062] SC2 Second plug structure

[0063] SC3 third plug structure

[0064] SC4 Fourth plug structure

[0065] SNP contact pad

[0066] SP sidewall structure

[0067] TE top electrode

[0068] W1 Width

[0069] W1' Width

[0070] W1" Width

[0071] W2 Width

[0072] Width

[0073] Wb Width

[0074] Wc Width

[0075] Wd Width DETAILED DESCRIPTION

[0076] In order to enable those skilled in the art to further understand the present invention, the following lists the preferred embodiments of the present invention, and with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0077] In order to make it easier for readers to understand and the illustrations are concise, the multiple illustrations in this disclosure only depict a portion of the semiconductor structure, and the specific elements in the illustrations are not drawn according to the actual scale. In addition, the number and size of each element in the figure are only for illustration and are not used to limit the scope of this disclosure. The description of the upper and lower relationships of the relative elements in the figure in the text should be understood by those in the art to refer to the relative positions of the elements, so they can all be flipped to present the same structure, which should all fall within the scope of this specification.

[0078] In order to facilitate the description and help understand the semiconductor structure of the present invention, the figure shows the spatial reference directions such as the first direction D1, the second direction D2, the third direction D3, and the fourth direction D4, wherein the first direction D1, the second direction D2, and the third direction D3 are parallel to the surface of the substrate 100, and the first direction D1 and the second direction D2 are perpendicular to each other and are different from the third direction D3. The angle between the second direction D2 and the third direction D3 can be between 15 degrees and 75 degrees, but is not limited thereto. The fourth direction D4 is perpendicular to the surface of the substrate 100. The first direction D1, the second direction D2, and the third direction D3 can also be referred to as horizontal directions, and the fourth direction D4 can also be referred to as a vertical direction.

[0079] Figures 1 to 16 FIG. 1 is a schematic diagram of a semiconductor structure during a manufacturing process according to an embodiment of the present invention. Fig.13 Fig.15 To simplify the illustration, some components may be omitted from each figure. The semiconductor structure of the present invention may be used to manufacture a dynamic random access memory (DRAM) including stacked capacitors. Without departing from the spirit of the present invention, the present invention may also be used to manufacture other types of semiconductor devices.

[0080] Please refer to Figure 1 and Figure 2 . First, a substrate 100 is provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto. The substrate 100 includes an array region AR and a peripheral region PR. The array region AR may also be referred to as a cell region, which is a region where a memory cell array is arranged, wherein the memory cell is, for example, a dynamic random access memory cell. The peripheral region PR is arranged adjacent to the outer side of the array region AR, separating the array region AR from other circuit regions of the substrate 100. In some embodiments, the peripheral region PR may also include peripheral circuits, such as drivers, buffers, amplifiers, and decoders, but not limited thereto.

[0081] The substrate 100 includes an isolation structure 104 and a plurality of active regions 102 defined by the isolation structure 104. The isolation structure 104 is, for example, a shallow trench isolation (STI) structure and may be composed of a single layer or multiple layers of dielectric material. Applicable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but are not limited thereto. The active regions 102 are separated from each other by the isolation structure 104, and are each in the shape of a long strip with the long axis extending along the third direction D3. The active regions 102 are alternately arranged along the second direction D2 and the first direction D1 to form an active region array.

[0082] A plurality of gate structures 106 are disposed on the substrate 100, extending along the first direction D1 and arranged in parallel along the second direction D2, and cut through the active region 102 to divide each active region 102 into two end portions and a middle portion. The portion of the gate structure 106 cutting through the active region 102 is the gate of the transistor of the memory cell. The portion of the gate structure 106 cutting through the isolation structure 104 is a passing gate.

[0083] According to an embodiment of the present invention, the manufacturing steps of the gate structure 106 may include forming a gate trench in the substrate 100 that cuts through the isolation structure 104 and the active area 102, then forming a gate dielectric layer 132 along the bottom surface and sidewalls of the gate trench, then forming a metal layer 134 to fill the lower part of the word line trench, and then forming an insulating cap layer 138 to fill the upper part of the word line trench. The insulating cap layer 138 and the gate dielectric layer 132 may respectively include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but not limited thereto. In some embodiments, the metal layer 134 may include a low resistance metal, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), or compounds, alloys, and / or composite layers of the above materials, but not limited thereto. In some embodiments, a polysilicon layer 136 may be included between the metal layer 134 and the insulating cap layer 138 to adjust the conductivity of the gate structure 106 .

[0084] After the gate structure 106 is completed, an insulating pad layer 108 is then formed on the substrate 100, and then an etching process is performed to form a first recess R1 and a second recess R2 that pass through the insulating pad layer 108 and respectively expose the middle portion of the active area 102 of the array area AR. A bit line material stack (not shown) is then formed on the substrate 100 to fully cover the substrate 100 and fill the first recess R1 and the second recess R2. An etching process is then performed to remove excess portions of the bit line material stack to obtain a plurality of bit line structures BL and a dummy bit line structure DBL.

[0085] In some embodiments, the insulating pad layer 108 may be a composite layer, such as an ONO composite layer composed of a silicon oxide layer 108 a , a silicon nitride layer 108 b , and a silicon oxide layer 108 c , but is not limited thereto.

[0086] The first recess R1 is located outside the array region AR, and the second recess R2 is located inside the array region AR. The first recess R1 and the second recess R2 have a substantially circular or elliptical profile in a plan view, and along the first direction D1, the width W1 of the first recess R1 is greater than the width W2 of the second recess R2, and the first recess R1 is slightly offset toward the peripheral region PR, so the active region 102 exposed from the first recess R1 is not located at the center of the first recess R1, but closer to the inner side of the first recess R1 (away from the peripheral region PR). In some embodiments, the depths of the first recess R1 and the second recess R2 are substantially equal.

[0087] The bit line structures BL extend along the second direction D2 and are arranged in parallel along the first direction D1 on the array region AR of the substrate 100. The bit line structure BL may include a semiconductor layer 122, an interface layer 124, a metal layer 126, and a hard mask layer 128 from bottom to top. The material of the semiconductor layer 122 may include crystalline silicon, polysilicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials, but not limited thereto. The material of the interface layer 124 may include metal, metal silicide, or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but not limited thereto. The material of the metal layer 126 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but not limited thereto. The hard mask layer 128 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), or a combination of the above materials, but is not limited thereto. According to one embodiment of the present invention, the material of the semiconductor layer 122 includes polysilicon, the material of the interface layer 124 includes tungsten silicide (WSi), the material of the metal layer 126 includes tungsten (W), and the material of the hard mask layer 128 includes silicon nitride (SiN). The bit line structure BL includes a first bit line structure BL1 on the outside (the side adjacent to the peripheral region PR) and a second bit line structure BL2 on the inside (the side away from the peripheral region PR). The first bit line structure BL1 is in direct contact with the middle portion of the active region 102 exposed by the first recess R1. The second bit line structure BL2 is in direct contact with the middle portion of the active region 102 exposed by the second recess R2. As Figure 2 As shown, since the first recess R1 is slightly offset toward the peripheral region PR, the portions of the first recess R1 exposed from both sides of the first bit line structure BL1 have different widths, wherein the outer width W1' is greater than the inner width W1".

[0088] The dummy bit line DBL is disposed on the peripheral region PR of the substrate 100 adjacent to the outer side of the first bit line structure BL1, and extends along the second direction D2, crossing the active region 102 disposed in the peripheral region PR. The dummy bit line DBL and the bit line structure BL have the same stacked structure and material. The active region 102 of the peripheral region PR and the dummy bit line DBL are completely isolated by the insulating pad layer 108 and are not in direct contact.

[0089] Please refer to Figure 3 . Then, a first insulating layer 142 and a second insulating layer 144 are sequentially formed to conformally cover the insulating pad layer 108, the first recess R1, the second recess R2, and the top surface and sidewalls of the bit line structure BL and the dummy bit line structure DBL. The first insulating layer 142 and the second insulating layer 144 include different dielectric materials, for example, they may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a combination of the above materials, but are not limited thereto. According to an embodiment of the present invention, the first insulating layer 142 includes silicon nitride (SiN), and the second insulating layer 144 includes silicon oxide (SiO2). The thickness of the second insulating layer 144 needs to be controlled to completely fill the second recess R2 exposed on both sides of the second bit line structure BL2 and the first recess R1 inside the first bit line structure BL1, and does not fill the first recess R1 outside the first bit line structure BL1, and forms a gap 144s in the second insulating layer 144 at that location.

[0090] Please refer to Figure 4 Then, an etching process is performed to remove part of the second insulating layer 144 , so that the remaining second insulating layer 144 is only filled in the first recess R1 and the second recess R2 , and the first insulating layer 142 covering the top surface and sidewalls of the dummy bit line structure DBL, the first bit line structure BL1 and the second bit line structure BL2 and the insulating pad layer 108 is exposed.

[0091] Please refer to Figure 5 and Figure 6 Next, a third insulating layer 152 is formed on the sidewalls of the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2, and then a dielectric layer 154 is formed to fill the gap between the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2, and then the dielectric layer 154 directly above the gate structure 106 is etched away and then refilled with a spacer 156, so as to form a gap between the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2. Figure 6The dielectric layer 154 and the spacer 156 are alternately arranged. The third insulating layer 152, the dielectric layer 154 and the spacer 156 are made of dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but not limited thereto. According to an embodiment of the present invention, the material of the third insulating layer 152 includes silicon nitride (SiN), the material of the dielectric layer 154 includes silicon oxide (SiO2), and the material of the spacer 156 includes silicon nitride (SiN).

[0092] Please refer to Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 Then, an etching process is performed using the spacer 156 and the hard mask layer 128 as masks to remove a portion of the dielectric layer 154 to form a plurality of openings separated by the spacer 156 between the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2, and then the first insulating layer 142, the insulating pad layer 108, the second insulating layer 144, and the active area 102 are etched downward through the openings to obtain a plurality of contact holes, including a first contact hole OP1 and a second contact hole OP2 alternately arranged along the second direction D2 between the outer side of the first bit line structure BL1 and the dummy bit line structure DBL, and a third contact hole OP3 and a fourth contact hole OP4 alternately arranged along the second direction D2 between the inner side of the first bit line structure BL1 and the second bit line structure BL2 and between adjacent second bit line structures BL2. In some embodiments, the dielectric layer 154 partially covering the sidewalls of the dummy bit line structure DBL, the first bit line structure BL1 and the second bit line structure BL2 may be retained to form a sidewall structure SP together with the first insulating layer 142 and the second insulating layer 144 .

[0093] The first contact hole OP1 and the third contact hole OP3 are aligned along the first direction D1. One side of the first contact hole OP1 overlaps with the end portion of the active area 102 crossed by the dummy bit line structure DBL, and the other side overlaps with the first recess R1. One side of the third contact hole OP3 overlaps with the end portion of the active area 102 crossed by the second bit line structure BL2, and the other side of the third contact hole OP3 arranged next to the first bit line structure BL1 overlaps with the first recess R1, and the other side of the remaining third contact holes OP3 overlaps with the second recess R2. Along the first direction D1, the first contact hole OP1 has a width Wa, and the third contact hole OP3 has a width Wc. In some embodiments, the width Wa is greater than the width Wc.

[0094] The second contact hole OP2 and the fourth contact hole OP4 are aligned along the first direction D1. One side of the second contact hole OP2 partially overlaps with the end portion of the active area 102 crossed by the first bit line structure BL1, and the other side is adjacent to or partially overlaps with the middle portion of the active area 102 crossed by the dummy bit line structure DBL. One side of the fourth contact hole OP4 partially overlaps with the end portion of the active area 102 crossed by the second bit line structure BL2, and the other side partially overlaps with the second recess R2. Along the first direction D1, the second contact hole OP2 has a width Wb, and the fourth contact hole OP4 has a width Wd. In some embodiments, the width Wb is greater than or equal to the width Wd. In some embodiments, the width Wb, the width Wc, and the width Wd are equal. In some embodiments, the width Wa of the first contact hole OP1 is greater than the width Wb of the second contact hole OP2, the width Wc of the third contact hole OP3, and the width Wd of the fourth contact hole OP4.

[0095] It is worth noting that due to the gap 144s (refer to Figure 5 ) makes it easier for the etchant to etch downwards, so under the same etching process conditions, the depth of the first contact hole OP1 is greater than the depths of the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4. In some embodiments, Figure 8 and Fig.10 As shown, the bottom surfaces of the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4 are lower than the bottom surface of the insulating pad layer 108, and are not lower than the bottom surface of the first recess R1 or the second recess R2. The bottom surface of the first contact hole OP1 is lower than the bottom surface of the first recess R1. In some embodiments, Fig. 9 and Fig.11 As shown, the bottom surfaces of the first contact hole OP1, the second contact hole OP2, the third contact hole OP3 and the fourth contact hole OP4 are all higher than the top surface of the metal layer 134 of the gate structure 106. Fig.10 and Fig.11 As shown, the depths of the second contact hole OP2 , the third contact hole OP3 and the fourth contact hole OP4 are substantially equal.

[0096] Please refer to Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16Then, a contact material layer 162 is formed to fill the lower half of the first contact hole OP1, the second contact hole OP2, the third contact hole OP3 and the fourth contact hole OP4, and then a barrier layer 164 is formed to conformally cover the top surface of the contact material layer 162, the sidewalls of the first contact hole OP1, the second contact hole OP2, the third contact hole OP3 and the fourth contact hole OP4, and the sidewall structure SP, the top surface of the dummy bit line structure DBL, the first bit line structure BL1 and the second bit line structure BL2, and then a conductive layer 166 is formed to comprehensively cover the dummy bit line structure DBL, the first bit line structure BL1 and the second bit line structure BL2 and fill the upper half of the first contact hole OP1, the second contact hole OP2, the third contact hole OP3 and the fourth contact hole OP4. Next, an etching process is performed to remove the excess conductive layer 166 and barrier layer 164 and pattern the conductive layer 166 and barrier layer 164 outside the openings of the first contact hole OP1, the second contact hole OP2, the third contact hole OP3 and the fourth contact hole OP4 into a plurality of contact pads SNP separated from each other, and at the same time, a first plug structure SC1, a second plug structure SC2, a third plug structure SC3 and a fourth plug structure SC4 are respectively arranged in the first contact hole OP1, the second contact hole OP2, the third contact hole OP3 and the fourth contact hole OP4. The size of the plug structure is determined by the size of the contact hole, so along the first direction D1, the widths of the first plug structure SC1, the second plug structure SC2, the third plug structure SC3 and the fourth plug structure SC4 are Wa, Wb, Wc and Wd respectively.

[0097] The first plug structure SC1, the second plug structure SC2, the third plug structure SC3 and the fourth plug structure SC4 respectively include a contact material layer 162 located in the lower half and directly contacting the active area 102, a conductive layer 166 located on the contact material layer 162, and a barrier layer 164 along the bottom surface and sidewall of the conductive layer 166. The contact material layer 162 may include a semiconductor material, such as single crystal silicon (crystalline silicon), polycrystalline silicon (poly silicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), but not limited thereto. The materials of the barrier layer 164 and the conductive layer 166 may include tungsten (W), titanium (Ti), nitrides, silicides, alloys, and / or composite layers of the above materials, but not limited thereto. According to an embodiment of the present invention, the material of the contact material layer 162 includes phosphorus (P) doped silicon, the material of the barrier layer 164 includes titanium nitride (TiN), and the material of the conductive layer 166 includes tungsten (W). The contact pad SNP is formed integrally with the conductive layer 166 of the first plug structure SC1, the second plug structure SC2, the third plug structure SC3 or the fourth plug structure SC4, and includes the same material. Fig.12As shown, the contact pads SNP are aligned along the first direction D1, staggered along the second direction D2, and partially overlap with the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2. In some embodiments, the contact pads SNP may partially overlap with the spacer 156 directly above the gate structure 106. With this design, the arrangement density of the contact pads SNP can be increased, and a larger process margin (process window) can be provided for the subsequent manufacture of the bottom electrode BE of the capacitor structure CAP, thereby improving the electrical connection quality with the bottom electrode (not shown).

[0098] At this point, the semiconductor structure of this embodiment is obtained. Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 As shown, the semiconductor structure includes a substrate 100, which includes an array region AR and a peripheral region PR. A plurality of active regions 102 are arranged on the array region AR and the peripheral region PR of the substrate 100. A plurality of gate structures 106 extend through the array region AR and the peripheral region PR along a first direction D1, and intersect with the active region 102 to divide each active region 102 into a middle portion and two end portions. A plurality of bit line structures BL are arranged on the array region AR, extend along a second direction D2 across the active region 102, and directly contact and electrically connect with the middle portion of the active region 102, wherein the first direction D1 and the second direction D2 are perpendicular to each other. The bit line structure BL includes a first bit line structure BL1 on the outside (adjacent to the peripheral region PR), and a second bit line structure BL2 on the inside (away from the peripheral region PR). A dummy bit line junction DBL is arranged on the peripheral region, and extends along a second direction D2 across the active region 102. The dummy bit line junction DBL is completely separated and electrically isolated from the active region 102 by an insulating pad layer 108. A plurality of first plug structures SC1 and second plug structures SC2 are alternately and spacedly arranged along the second direction D2 between the outer side of the first bit line structure B1 and the dummy bit line junction DBL, and are electrically connected to the ends of the active region 102, respectively. A plurality of third plug structures SC3 and fourth plug structures SC4 are alternately arranged along the second direction D2 between the inner side of the first bit line structure BL1 and the adjacent second bit line structure BL2, and are electrically connected to the ends of the active region 102, respectively. The third plug structure SC3 is aligned with the first plug structure SC1 along the first direction D1, and the fourth plug structure SC4 is aligned with the second plug structure SC2 along the first direction D1. As described above, due to the presence of a gap 144s (refer to FIG. 1 ) in the second insulating layer 144 at the expected position of the first contact hole OP1, the gap 144s is formed. Figure 5), so that the etchant can etch downward more easily, so the depth of the obtained first contact hole OP1 will be greater than the depths of the second contact hole OP2, the third contact hole OP3 and the fourth contact hole OP4, and therefore the bottom of the first plug structure SC1 disposed in the first contact hole OP1 will be lower than the second plug structure S2, the third plug structure S3 and the fourth plug structure S4 disposed in the second contact hole OP2, the third contact hole OP3 and the fourth contact hole OP4 respectively. The first plug structure SC1 extends further downward to the deeper part of the substrate 100, increasing the contact area between the first plug structure SC1 and the end of the active area 102, thereby reducing the contact resistance and improving the quality of the electrical connection.

[0099] In some embodiments, Fig.13 and Fig.15 As shown, the bottom of the first plug structure SC1 is lower than the bottom surface of the first recess R1, and the bottoms of the second plug structure SC2, the third plug structure SC3 and the fourth plug structure SC4 are not lower than the bottom surface of the second recess R2. In other words, the bottom of the first plug structure SC1 is lower than the top surface of the middle portion of the recessed active region 102, and the bottoms of the second plug structure SC2, the third plug structure SC3 and the fourth plug structure SC4 are not lower than the top surface of the middle portion of the recessed active region 102. The bottom of the semiconductor layer 122 of the first bit line structure BL1 located in the first recess R1 is higher than the bottom of the first plug structure SC1, and the bottom of the semiconductor layer 122 of the second bit line structure BL2 located in the second recess R2 is lower than the bottom of the second plug structure SC2, the third plug structure SC3 and the fourth plug structure SC4.

[0100] In some embodiments, Fig.14 As shown, the first plug structure SC1 and the second plug structure SC2 are alternately arranged between the spacers 156. The bottoms of the first plug structure SC1 and the second plug structure SC2 extend to a level lower than the top surface of the insulating cap layer 138 of the gate structure 106, and are higher than the top surface of the metal layer 134 of the gate structure 106, and are arranged alternately in high and low positions. In some embodiments, when the gate structure 106 further includes a polysilicon layer 136 disposed between the metal layer 134 and the insulating cap layer 138, the bottoms of the first plug structure SC1 and the second plug structure SC2 are higher than the top surface of the polysilicon layer 136.

[0101] In some embodiments, Fig.15 and Fig.16 As shown, the bottoms of the second plug structure SC2 , the third plug structure SC3 , and the fourth plug structure SC4 are substantially located at the same depth in the substrate 100 and are aligned with each other.

[0102] The widths of the first plug structure SC1, the second plug structure SC2, the third plug structure SC3, and the fourth plug structure SC4 are determined by the first contact hole OP1, the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4, respectively. In some embodiments, along the first direction D1, the width of the first plug structure SC1 is greater than the width of the third plug structure SC3. In some embodiments, along the first direction D1, the widths of the second plug structure SC2, the third plug structure SC3, and the fourth plug structure SC3 are substantially equal. In some embodiments, the width of the first plug structure SC1 is greater than the width of the second plug structure SC2, the third plug structure SC3, and the fourth plug structure SC4.

[0103] Please continue to refer to Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 . In some embodiments, the semiconductor structure of the present invention can be used to manufacture dynamic random access memory (DRAM) including stacked capacitors. For example, after forming the contact pads SNP, an insulating material 172 is then formed to cover the substrate 100 and fill the gaps between the contact pads SNP to flatten the surface and ensure electrical isolation between the contact pads SNP, and then the semiconductor manufacturing process is continued to make a capacitor structure CAP on the contact pads SNP. The capacitor structure CAP includes a bottom electrode BE vertically erected on the contact pad SNP, a capacitor dielectric layer IL covering the side walls and top surface of the bottom electrode BE, and a top electrode TE disposed on the capacitor dielectric layer IL and capacitively coupled to the bottom electrode BE. According to design requirements, the bottom electrode BE can be as follows Fig.13 , Fig.14 , Fig.15 and Fig.16 The bottom of the bottom electrode BE is shown as a solid columnar structure. In other embodiments, the bottom electrode BE may be a solid columnar structure so that the top electrode TE can be filled into the inner cavity of the bottom electrode BE to increase the capacitive coupling area between the bottom electrode BE. In some embodiments, the capacitor structure CAP may include a support layer 176, which extends horizontally between the bottom electrodes BE and directly contacts the sidewalls of the bottom electrode BE to support each bottom electrode BE. In some embodiments, an etch stop layer 174 may be provided on the insulating material 172, and the bottom of the bottom electrode BE penetrates the etch stop layer 174 to directly contact the contact pad SNP.

[0104] The insulating material 172, the etching stop layer 174, the supporting layer 176 and the capacitor dielectric layer IL respectively include dielectric materials. The bottom electrode BE and the top electrode TE may respectively include conductive materials. The bottom electrode BE of the capacitor structure CAP is electrically connected to the active area 102 through the contact pad SNP and the first plug structure SC1, the second plug structure SC2, the third plug structure SC3 or the fourth plug structure SC4, and the gate structure 106 and the bit line structure BL control the storage or release of the charge of the capacitor structure CAP to achieve the purpose of storing data.

[0105] In summary, the semiconductor structure and its manufacturing method provided by the present invention can obtain contact holes of different depths at the desired position through the same etching step, thereby obtaining plug structures of different depths, and improving the electrical connection quality between the plug structure and the active area. The semiconductor structure of the present invention is used to manufacture dynamic random access memory (DRAM), and can obtain improved device performance.

[0106] The above description is only the preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a substrate including a plurality of active regions; a plurality of gate structures extending along a first direction and intersecting the active regions, dividing each of the active regions into a middle portion and two end portions; a plurality of bit line structures extending along a second direction and electrically connected to the middle portion of the active regions, wherein the first direction and the second direction are perpendicular to each other, and the bit line structures include a first bit line structure on an outer side and a second bit line structure on an inner side; and A plurality of first plug structures and second plug structures are alternately and spaced apart along the second direction outside the first bit line structure and electrically connected to the end, wherein the bottom of the first plug structure is lower than the bottom of the second plug structure.

2. The semiconductor structure according to claim 1, characterized in that: The second plug structure is not lower than a top surface of the middle portion of the active region, and the first plug structure is lower than a top surface of the middle portion of the active region.

3. The semiconductor structure according to claim 1, characterized in that: It also includes a dummy bit line structure located outside the first bit line structure, wherein the first plug structure and the second plug structure are alternately sandwiched between the first bit line structure and the dummy bit line structure along the second direction.

4. The semiconductor structure according to claim 1, characterized in that: The dummy bit line structure is electrically isolated from each of the active regions.

5. The semiconductor structure according to claim 1, characterized in that: The gate structure comprises: a gate dielectric layer; a metal layer, located on the gate dielectric layer; and An insulating capping layer is located on the conductive layer, wherein the bottom of the first plug structure is higher than the top surface of the metal layer.

6. The semiconductor structure according to claim 5, characterized in that: The gate structure further includes a polysilicon layer disposed between the conductive layer and the insulating cap layer, wherein the bottom of the first plug structure is higher than a top surface of the polysilicon layer.

7. The semiconductor structure according to claim 5, characterized in that: The bottom of the second plug structure is lower than the top surface of the insulating cover layer.

8. The semiconductor structure according to claim 1, characterized in that: It also includes a plurality of third plug structures and a fourth plug structure, which are alternately arranged along the second direction between the inner side of the first bit line structure and the second bit line structure, wherein the third plug structure and the first plug structure are arranged along the first direction, and the fourth plug structure and the second plug structure are arranged along the first direction, and the bottom of the third plug structure and the bottom of the fourth plug structure are both higher than the bottom of the first plug structure.

9. The semiconductor structure according to claim 8, characterized in that: The bottoms of the second plug structure, the third plug structure, and the fourth plug structure extend to the same depth in the substrate.

10. The semiconductor structure according to claim 1, wherein: It also includes a plurality of capacitor structures, which are respectively located on the first plug structure and the second plug structure.

11. A semiconductor structure, characterized in that: include: a substrate including a plurality of active regions; A plurality of gate structures extending along a first direction and intersecting the active area; a plurality of spacers disposed on the gate structure; A plurality of first plug structures and second plug structures are alternately arranged between the spacers along the second direction and are electrically connected to the active regions respectively, wherein the bottom of the first plug structure is lower than the bottom of the second plug structure.

12. The semiconductor structure according to claim 11, characterized in that: The gate structure comprises: Metal layer; a gate dielectric layer, disposed between the substrate and the metal layer; and The insulating capping layer is located on the metal layer, wherein the bottom of the first plug structure is higher than the top surface of the metal layer. 13 . The semiconductor structure according to claim 12 , wherein the gate structure further comprises a polysilicon layer between the metal layer and the insulating cap layer, wherein the bottom of the first plug structure is higher than a top surface of the polysilicon layer.

14. The semiconductor structure according to claim 12, characterized in that: The bottom of the second plug structure is lower than the top surface of the insulating cover layer.

15. A semiconductor structure, characterized in that: include: a substrate including a plurality of active regions; A plurality of gate structures extending along a first direction and intersecting the active area; A plurality of bit line structures extending along a second direction and electrically connected to the active area, wherein the first direction and the second direction are perpendicular to each other, and the bit line structure includes an outer first bit line structure and an inner second bit line structure; at least one first plug structure disposed outside the first bit line structure; as well as A plurality of third plug structures are arranged on the inner side of the first bit line structure and between the second bit line structure and are arranged along the first direction with the first plug structure, wherein in the cross-sectional view, the bottom of the first plug structure is lower than the bottom of the third plug structure, and the width of the first plug structure is greater than the width of the third plug structure.

16. The semiconductor structure according to claim 15, characterized in that Also includes: at least one second plug structure disposed outside the first bit line structure; as well as A plurality of fourth plug structures are disposed inside the first bit line structure and between the second bit line structure and are arranged along the first direction with the second plug structure, wherein in the cross-sectional view, the bottom of the second plug structure is at the same height as the bottom of the fourth plug structure.

17. The semiconductor structure according to claim 15, characterized in that The invention also includes a dummy bit line structure located outside the first bit line structure, wherein the first plug structure is sandwiched between the first bit line structure and the dummy bit line structure.

18. The semiconductor structure according to claim 15, characterized in that The gate structure comprises: a gate dielectric layer; a metal layer, located on the gate dielectric layer; and The insulating capping layer is located on the metal layer, wherein the bottom of the first plug structure is higher than the top surface of the metal layer.

19. The semiconductor structure according to claim 18, characterized in that The gate structure further includes a polysilicon layer disposed between the metal layer and the insulating cap layer, wherein the bottom of the first plug structure is higher than a top surface of the polysilicon layer.

20. The semiconductor structure according to claim 18, characterized in that The bottom of the third plug structure is lower than the top surface of the insulating cover layer.

21. A semiconductor structure, characterized in that: include: a substrate including a plurality of active regions; A plurality of gate structures extending along a first direction and intersecting the active area; a plurality of bit line structures extending along a second direction; At least one first plug structure is disposed adjacent to the bit line structure, and a bottom of the first plug structure is lower than a bottom of the bit line structure.

22. The semiconductor structure according to claim 21, characterized in that The bit line structure includes a semiconductor layer, the semiconductor layer is in direct contact with the active region, and the bottom of the first plug structure is lower than the bottom of the semiconductor layer.

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