Method of forming a semiconductor structure, semiconductor structure, device and apparatus

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor structure forming method, a semiconductor structure, a device and an apparatus. The method comprises the following steps: providing an initial semiconductor structure; forming a side wall structure located at the side wall of a control gate structure, at least one layer of a tunneling oxide layer located at an erasing gate region, and a gate oxide layer located at a logic region; the gate oxide layer comprises a first type of gate oxide layer and a second type of gate oxide layer, and the gate oxide layer is synchronously formed with the side wall structure and the tunneling oxide layer; based on the side wall structure, a target gap oxide layer is formed, based on the first type of gate oxide layer, a target first type of gate oxide layer is formed, based on the tunneling oxide layer, a target tunneling oxide layer is formed, and based on the second type of gate oxide layer, a target second type of gate oxide layer is formed, so as to obtain a target semiconductor structure. Based on the stacked side wall, the gap oxide layer is prepared, the thickness of the gap oxide layer can be accurately controlled, and the uniformity of the gap oxide layer is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure, a semiconductor structure, a device, and an apparatus. Background Art

[0002] With the rapid development and widespread adoption of embedded devices, a wide variety of embedded components have been designed and developed. Flash memory, with its high performance, low power consumption, and non-volatility, has become a crucial data storage medium for these devices. Flash memory typically comprises a word line (WL) and a floating gate (FG). The gap oxide structure between the word line and the floating gate is crucial for achieving efficient flash memory performance.

[0003] Currently, the manufacturing process for flash memory is complex, typically involving both logic and flash processes. The gap oxide layer between the word line and floating gate is affected not only by the flash process but also by the logic process. Due to the different requirements of the two processes, a balance must be struck during the manufacturing process, making it difficult to control the consistency of the gap oxide layer in flash memory. This can lead to decreased device performance and poor yield. Summary of the Invention

[0004] In order to solve the above technical problems, the present application provides a method for forming a semiconductor structure, a semiconductor structure, a device and an apparatus.

[0005] In a first aspect, an embodiment of the present application discloses a method for forming a semiconductor structure, the method comprising:

[0006] Providing an initial semiconductor structure; the initial semiconductor structure includes a flash memory area and a logic area; the flash memory area includes a control gate area and an erase gate area, and a control gate structure is formed on the surface of the control gate area; the logic area includes a first type of logic gate area and a second type of logic gate area;

[0007] forming a sidewall structure located on the sidewall of the control gate structure, at least one tunneling oxide layer located in the erase gate region, and a gate oxide layer located in the logic region; the gate oxide layer includes at least one first-type gate oxide layer located in the first-type logic gate region and at least one second-type gate oxide layer located in the second-type logic gate region, and the gate oxide layer is formed synchronously with the sidewall structure and the tunneling oxide layer;

[0008] A target gap oxide layer is formed based on the sidewall structure, a target first-type gate oxide layer is formed based on the first-type gate oxide layer, a target tunneling oxide layer is formed based on the tunneling oxide layer, and a target second-type gate oxide layer is formed based on the second-type gate oxide layer to obtain a target semiconductor structure.

[0009] In a second aspect, an embodiment of the present application discloses a semiconductor structure, comprising: a logic region and a flash memory region;

[0010] Logic area and flash memory area; the logic area includes a first type of logic gate area and a second type of logic gate area; the flash memory area includes a control gate area and an erase gate area;

[0011] A target first-type gate oxide layer located on the surface of the first-type logic gate region; the target first-type gate oxide layer is obtained based on at least one first-type gate oxide layer;

[0012] a target second type gate oxide layer located on the surface of the second type logic gate region; the target second type gate oxide layer is obtained based on at least one layer of the second type gate oxide layer;

[0013] A control gate structure is located on the surface of the control gate region, and a target gap oxide layer is formed on the sidewall of the control gate structure; the target gap oxide layer is obtained based on the sidewall structure sequentially formed on the sidewall of the control gate structure;

[0014] A target tunneling oxide layer is formed on the surface of the erase gate region; the target tunneling oxide layer is obtained based on at least one tunneling oxide layer.

[0015] In a third aspect, an embodiment of the present application discloses a memory device, which includes the semiconductor structure described above.

[0016] In a fourth aspect, an embodiment of the present application discloses an electronic device, which includes the storage device described above.

[0017] The technical solution has the following technical effects:

[0018] The method for forming a semiconductor structure, the semiconductor structure, the device and the apparatus provided by the embodiments of the present application form a side wall structure located at the side wall of the control gate structure, at least one tunneling oxide layer located at the erase gate region and a gate oxide layer located at the logic region. The gate oxide layer includes at least one first type of gate oxide layer located at the first type of logic gate region and at least one second type of gate oxide layer located at the second type of logic gate region. The gate oxide layer is formed synchronously with the side wall structure and the tunneling oxide layer, and the target gap oxide layer is formed based on the side wall structure, the target first type of gate oxide layer is formed based on the first type of gate oxide layer, the target tunneling oxide layer is formed based on the tunneling oxide layer, and the target second type of gate oxide layer is formed based on the second type of gate oxide layer, so as to obtain the target semiconductor structure. The scheme can combine the flash memory process and the logic process, and can simultaneously realize the preparation of the gap oxide layer, the first type of gate oxide layer, the tunneling oxide layer and the second type of gate oxide layer, thereby improving the preparation efficiency of the flash memory device. Meanwhile, when the oxide layers in the erase gate region, the first type of logic gate region and the second type of logic gate region are prepared, a plurality of stacked side walls can be obtained on the side wall of the control gate structure, and the gap oxide layer is prepared based on the side walls, so as to realize the accurate control of the thickness of the gap oxide layer, thereby improving the uniformity of the gap oxide layer, and further improving the performance of the flash device and the preparation yield of the flash memory device. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, and the advantages thereof, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0020] Figure 1 FIG. 1 is a structure schematic diagram of a flash memory device;

[0021] Figure 2 FIG. 2 is a microstructure scanning schematic diagram of different gap oxide layers in a flash memory device;

[0022] Figure 3 FIG. 3 is a test result schematic diagram of a flash memory device;

[0023] Figure 4 FIG. 4 is a flow schematic diagram of a method for forming a semiconductor structure provided by an embodiment of the present application;

[0024] Figures 5 to 15 FIG. 5 is a structure schematic diagram of a semiconductor structure forming process provided by an embodiment of the present application;

[0025] Figure 16 FIG. 6 is another test result schematic diagram of a flash memory device provided by an embodiment of the present application;

[0026] Figure 17 It is a structural schematic diagram of a semiconductor structure provided in an embodiment of the present application.

[0027] The following is a supplementary description of the accompanying drawings:

[0028] 11-Floating gate; 12-Word line; 13-Control gate; 14-Gap oxide layer; 15-Erase gate; 16-High voltage logic gate region; 17-Medium voltage logic gate region; 18-Low voltage logic gate region; 1-Substrate; 100-Flash memory region; 101-First oxide layer; 102-Second oxide layer; 103-Third oxide layer; 104-Fourth oxide layer; 105-Fifth oxide layer; 110-Erase gate region; 111-Target tunneling oxide layer; 112-Erase gate; 120-Control gate region; 121-Floating gate oxide layer; 122-Floating gate; 123-Dielectric layer; 124-Control gate; 1200-Target gap oxide layer; 1201-Third oxide layer One side wall; 1202-second side wall; 1203-third side wall; 1204-fourth side wall; 1205-fifth side wall; 131-first sacrificial layer; 132-second sacrificial layer; 133-third sacrificial layer; 134-fourth sacrificial layer; 140-word line area; 141-word line; 200-logic area; 210-logic gate area; 211-target first gate oxide layer; 212-target second gate oxide layer; 213-target third gate oxide layer 213; 221-first logic gate; 222-second logic gate; 223-third logic gate; 231-first logic gate area; 232-second logic gate area; 233-third logic gate area. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] It should be noted that the "one embodiment" or "embodiment" referred to in the description of the embodiments of the present application refers to specific features, structures, or characteristics that may be included in at least one implementation of the present application. It should be understood that in the description and claims of the embodiments of the present application, as well as in the above-mentioned figures, the terms "upper," "lower," "top," "bottom," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the figures and are intended solely for the purpose of facilitating the description of the present application and simplifying the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. The terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Furthermore, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, in the description of this embodiment, unless otherwise specified, "a plurality of" means two or more. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system or product that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products or devices.

[0031] In order to make the purpose, technical solutions and advantages disclosed in the embodiments of the present application more clearly understood, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present application and are not intended to limit the embodiments of the present application.

[0032] See also Figure 1 , Figure 1 It is a structural diagram of a flash memory device, such as Figure 1 As shown in FIG, a flash memory device includes a flash memory area and a logic area. The flash memory area is formed with a word line 12, a floating gate 11, a control gate (CG) 13, and an erase gate (EG) 15. A tunneling oxide layer is formed under the erase gate. A gap oxide layer 14 ( Figure 1The oxide layer structure can affect the erase current (IR1) of the flash memory device, thereby affecting the performance of the flash memory device. The logic area includes a high voltage (HV) logic gate area 16, a medium voltage (MV) logic gate area 17, and a low voltage (LV) logic gate area 18. Different voltage logic areas have gate oxide layers of different thicknesses. Therefore, the thickness of the gap oxide layer between the word line 12 and the floating gate 11 is affected not only by the flash memory area preparation process, but also by the gate oxide layer preparation process of the high, medium, and low regions in the logic area, making it difficult to control the uniformity of the gap oxide layer thickness between the word line 12 and the floating gate 11.

[0033] The non-uniformity of the gap oxide layer thickness is not only reflected between different gap oxide layers in the same flash memory device, but also between different flash memory devices fabricated on the same wafer. Figure 2 This is a schematic diagram of the microstructure scanning of different gap oxide layers in a flash memory device, such as Figure 2 As shown, the average thickness of the gap oxide layer on the left is 378 angstroms, and the thickness of the gap oxide layer on the right is 346 angstroms. The erase current corresponding to the gap oxide layer on the left is 18 μA, and the erase current corresponding to the gap oxide layer on the right is 13 μA. Figure 3 This is a schematic diagram of the test results of a flash memory device, such as Figure 3 As shown, by performing current testing on the storage cells of the flash memory devices in a certain test group (Group: 1), it can be found that the interfaces (I / O) of the storage cells of some flash memory devices in the test group have a low erase current (IR1), that is, the erase current consistency is poor. The poor consistency of the erase current will directly affect the yield of the flash memory device. According to statistics, the yield of the above flash memory devices is around 60%. Therefore, how to form an excellent gap oxide layer and balance the process contradictions caused by the structural differences between the flash memory area and the logic area is an urgent problem to be solved.

[0034] In view of this, an embodiment of the present application provides a method for forming a semiconductor structure. Figure 4 is a flow chart of a method for forming a semiconductor structure provided in an embodiment of the present application, such as Figure 4 As shown, the method includes:

[0035] S101: providing an initial semiconductor structure; the initial semiconductor structure includes a flash memory area and a logic area; the flash memory area includes a control gate area and an erase gate area, and a control gate structure is formed on the surface of the control gate area; the logic area includes a first type of logic gate area and a second type of logic gate area.

[0036] In the embodiment of the present application, the initial semiconductor structure refers to a semiconductor structure obtained by completing the preparation of a partial device structure during the preparation process of the flash memory device. Figure 5 is a schematic structural diagram of an initial semiconductor structure provided in an embodiment of the present application, such as Figure 5 As shown, the initial semiconductor structure includes a substrate 1. Optionally, the substrate 1 can be one of semiconductor substrates such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, and a silicon germanium substrate. As an example, the substrate 1 in the initial semiconductor structure can be a single crystal silicon substrate. When preparing a flash memory device, the substrate 1 can be divided into a flash memory area 100 and a logic area 200, wherein a flash memory cell structure can be prepared on the flash memory area 100, and a logic gate structure can be prepared on the logic area 200. Optionally, a shallow trench can be formed on the surface of the substrate 1 by a shallow trench process, thereby dividing the substrate 1 into the flash memory area 100 and the logic area 200.

[0037] like Figure 5 As shown, at least one control gate region 120 is formed on the surface of the flash memory region 100 in the substrate 1, and a control gate structure (not labeled) is formed on each control gate region 120. In the flash memory region 100, the number of control gate structures can be one, or two or more. Generally speaking, a flash memory device can have two control gate structures. For any control gate structure, it can include a floating gate oxide layer 121 formed on the surface of the substrate 1, a floating gate 122 formed on the surface of the floating gate oxide layer 121, a dielectric layer 123 formed on the floating gate 122, and a control gate 124 formed on the dielectric layer 123. In some embodiments, an oxide layer and a silicon nitride layer located on the oxide layer can also be formed on the control gate 124. The area adjacent to the control gate structure in the flash memory region 100 is an erase gate region 110. Optionally, the erase gate region 110 is formed between two adjacent control gate structures.

[0038] like Figure 5 As shown, at least one logic gate region 210 is formed in the logic area 200 in the substrate 1. These logic gate regions 210 can be divided into a first type of logic gate region and a second type of logic gate region according to the thickness of the gate oxide layer required to be formed thereon. The first type of logic gate region refers to a region on which a gate oxide layer with a thickness greater than the thickness of the tunnel oxide layer is required to be formed, and the second type of logic gate region refers to a region on which a gate oxide layer with a thickness less than the thickness of the tunnel oxide layer is required to be formed. Optionally, the first type of logic gate region includes at least one logic gate region 210, and the second type of logic gate region includes at least one logic gate region 210. As an example, Figure 5As shown, three logic gate regions 210 are formed in the logic region 200, wherein the first logic gate region 231 is a first type logic gate region, and the second logic gate region 232 and the third logic gate region 233 are second type logic gate regions. In some embodiments, the first logic gate region 231 can be a high voltage logic gate region, the second logic gate region 232 can be a medium voltage logic gate region, and the third logic gate region 233 can be a low voltage logic gate region. The terms high voltage, medium voltage, and low voltage refer to the turn-on voltages of the logic gates. For example, the turn-on voltage of the logic gate formed on the high voltage logic gate region can be 5V, the turn-on voltage of the logic gate formed on the medium voltage logic gate region can be 3.3V, and the turn-on voltage of the logic gate formed on the low voltage logic gate region can be 1.5V. It should be noted that, generally speaking, the higher the turn-on voltage of the logic gate, the thicker the gate oxide layer that needs to be formed in the corresponding logic gate region 210.

[0039] S103: forming a sidewall structure located on the sidewall of the control gate structure, at least one tunneling oxide layer located in the erase gate region, and a gate oxide layer located in the logic region; the gate oxide layer includes at least one first-type gate oxide layer located in the first-type logic gate region and at least one second-type gate oxide layer located in the second-type logic gate region, and the gate oxide layer is formed synchronously with the sidewall structure and the tunneling oxide layer.

[0040] In an embodiment of the present application, after obtaining the initial semiconductor structure, a target semiconductor structure can be prepared based on the initial semiconductor structure. Optionally, the target semiconductor structure refers to a semiconductor structure after the target gap oxide layer 1200, tunnel oxide layer, first type gate oxide layer and second type gate oxide layer are prepared during the preparation process of the flash memory device. The target semiconductor structure can also be the semiconductor structure obtained after the flash memory device is prepared. When preparing the target semiconductor structure, the target gap oxide layer 1200, tunnel oxide layer, first type gate oxide layer and second type gate oxide layer can be prepared simultaneously by combining the flash memory process and the logic process. Specifically, according to the structural size design of the flash memory device, the preparation scheme of the target gap oxide layer 1200, tunnel oxide layer, first type gate oxide layer and second type gate oxide layer can be designed to achieve the corresponding thickness through several oxide layer depositions. Optionally, the target gap oxide layer 1200, tunnel oxide layer, first type gate oxide layer and second type gate oxide layer are all made of silicon oxide.

[0041] In the embodiment of the present application, when simultaneously preparing the target gap oxide layer 1200, the tunnel oxide layer, the first type gate oxide layer, and the second type gate oxide layer, since the thickness of the target gap oxide layer 1200 is generally thicker, the first oxide layer 101 can be first deposited on the sidewall of the control gate structure to form a first spacer 1201 on the sidewall of the control gate structure. The first spacer 1201 is used to make the target gap oxide layer structure (not marked). Optionally, the thickness of the first oxide layer 101 is 250 angstroms to 280 angstroms. For example, 250 angstroms, 255 angstroms, 260 angstroms, 265 angstroms, 270 angstroms, 275 angstroms, 280 angstroms, etc.

[0042] In the embodiment of the present application, when depositing the first oxide layer 101 on the sidewalls of the control gate structure, an optional implementation method is to shield the erase gate region 110, the first type logic gate region, and the second type logic gate region by making a mask, exposing only the control gate region 120, and then depositing the first oxide layer 101 on the surface of the control gate region 120. Due to the shielding of the mask, the first oxide layer 101 can only be deposited in the control gate region 120, so that the first spacer 1201 composed of the first oxide layer 101 can be formed only on the sidewalls of the control gate structure.

[0043] In an embodiment of the present application, in order to reduce process complexity, improve manufacturing efficiency, and enhance process control accuracy, when forming the first spacer 1201 on the sidewall of the control gate structure, another optional implementation is to deposit the first oxide layer 101 on the entire surface of the initial semiconductor structure. Specifically, the first oxide layer 101 is deposited on the surfaces of the control gate region 120, the erase gate region 110, the first type logic gate region, and the second type logic gate region, thereby forming the first spacer 1201 on the sidewall of the control gate structure. Optionally, the process for depositing the first oxide layer 101 can be a high temperature oxidation deposition (HTO) process, a chemical vapor deposition tetraethoxysilane (TEOS) process, an in-situ steam generation (ISSG) process, or the like. In some embodiments, the process for depositing the first oxide layer 101 can also be a chemical vapor deposition process or a physical vapor deposition process, or the like.

[0044] In the embodiment of the present application, after the first oxide layer 101 is deposited on the surface of the initial semiconductor structure, a first semiconductor structure can be obtained. Figure 6 is a schematic structural diagram of a first semiconductor structure provided in an embodiment of the present application, such as Figure 6As shown, the surface of the first semiconductor is covered by the first oxide layer 101, and the sidewalls of the control gate structure form first sidewalls 1201. After the deposition of the first oxide layer 101 is completed, the surface of the initial semiconductor structure other than the control gate region 120 can also be etched by an etching process to remove the first oxide layer 101 deposited in other areas. Optionally, the etching process can be dry etching. Since the principle of dry etching is to use plasma to bombard the surface of the etched object, dry etching is used to remove the first oxide layer 101, and will not cause damage to the first sidewalls 1201 formed on the sidewalls of the control gate structure. In some embodiments, in order to avoid damaging the substrate 1 in the initial semiconductor structure, when dry etching is used to remove the first oxide layer 101, part of the first oxide layer 101 can be left to protect the substrate 1.

[0045] It should be noted that it is not necessary to etch the first oxide layer 101 deposited in other areas. This is because when the tunneling oxide layer, the first type gate oxide layer, and the second type gate oxide layer are subsequently prepared, the oxide layer previously deposited in each area will be removed in order to control the thickness of the oxide layer in different areas. However, using dry etching to remove the first oxide layer 101 in other areas can improve the efficiency of subsequent removal of the oxide layer in each area. Therefore, whether to use dry etching to remove the first oxide layer 101 in other areas can be independently selected according to actual process requirements, and this process does not require creative work.

[0046] In an embodiment of the present application, after forming a first spacer 1201 on the sidewall of the control gate structure, a first gate oxide layer of a first preset thickness can be formed in the first logic gate region, and a second spacer 1202 can be formed on the sidewall of the first spacer 1201. Specifically, a second oxide layer 102 is deposited on the surface of the first semiconductor structure to form the second spacer 1202 on the sidewall of the first spacer 1201, and a first gate oxide layer of a first preset thickness is simultaneously formed in the first logic gate region. The first preset thickness is the same as the thickness of the second oxide layer 102, and the first spacer 1201 and the second spacer 1202 are used to form the target gap oxide layer 1200. Optionally, the thickness of the second oxide layer 102 is 40 angstroms to 70 angstroms. For example, 40 angstroms, 45 angstroms, 50 angstroms, 55 angstroms, 60 angstroms, 65 angstroms, 70 angstroms, etc.

[0047] In the embodiment of the present application, when forming the first-type gate oxide layer, if the first oxide layer 101 is not deposited in the first-type logic gate region, the second oxide layer 102 can be directly deposited on the control gate region 120, the erase gate region 110, the first-type logic gate region, and the second-type logic gate region, so as to form the second spacer 1202 on the sidewall of the first spacer 1201 and simultaneously form a first-type gate oxide layer of partial thickness in the first-type logic gate region. If the first oxide layer 101 is deposited in the first-type logic gate region, in order to achieve precise control of the thickness of the first-type gate oxide layer, the first oxide layer 101 on the surface of the first-type logic gate region can be first removed, and then the second oxide layer 102 can be deposited on the control gate region 120, the erase gate region 110, the first-type logic gate region, and the second-type logic gate region, so as to form the second spacer 1202 on the sidewall of the first spacer 1201 and form a first-type gate oxide layer of partial thickness in the first-type logic gate region. In another embodiment, if a first oxide layer 101 is deposited in the first type of logic gate region, after depositing the second oxide layer 102, part of the thickness of the second oxide layer 102 in the first type of logic gate region can be removed, or the second oxide layer 102 and part of the thickness of the first oxide layer 101 in the first type of logic gate region can be removed, so that the thickness of the first type of gate oxide layer in the first type of logic gate region is the same as the thickness of the second oxide layer 102.

[0048] Specifically, taking the first type of logic gate region including the first logic gate region 231 as an example, if a first oxide layer 101 is deposited in the first logic gate region 231, the first sacrificial layer 131 can be covered on the surface of the first semiconductor structure and the first logic gate region 231 can be exposed, thereby removing the first oxide layer 101 in the first logic gate region 231. Figure 7 This is a schematic diagram of a structure after a first sacrificial layer is covered on the surface of a first semiconductor structure according to an embodiment of the present application. Figure 7 As shown, the first sacrificial layer 131 covers the control gate region 120, the erase gate region 110, and the second type logic gate region, exposing only the first logic gate region 231. Then, the first oxide layer 101 in the first logic gate region 231 is removed by an etching process. Optionally, the first sacrificial layer 131 can be made of photoresist (PR). When etching the first oxide layer 101 in the first logic gate region 231, a combination of dry etching and wet etching can be used to completely remove the first oxide layer 101 in the first logic gate region 231. In some embodiments, the first oxide layer 101 in the first logic gate region 231 can also be completely removed by wet etching alone.

[0049] Figure 8 This is a schematic diagram of a structure after a second oxide layer is deposited on the surface of a first semiconductor structure provided by an embodiment of the present application, such as Figure 8As shown, after the first oxide layer 101 in the first logic gate region 231 is completely removed, the first sacrificial layer 131 can be removed. Then, a second oxide layer 102 is deposited on the surface of the first semiconductor structure, thereby forming the second spacer 1202 outside the first spacer 1201 and simultaneously forming a partial thickness of the first gate oxide layer in the first logic gate region 231. Optionally, the process for depositing the second oxide layer 102 includes, but is not limited to, a high-temperature oxidation deposition process, an in-situ water vapor generation process, a chemical vapor deposition process, a physical vapor deposition process, and the like.

[0050] It should be noted that when the first type of logic gate region includes multiple logic gate regions 210, the above process of depositing the second oxide layer 102 can be divided into multiple repeated preparation processes. For example, the first type of logic gate region includes a first sub-logic gate region and a second sub-logic gate region, and the thickness of the corresponding first sub-gate oxide layer in the first sub-logic gate region is greater than the thickness of the corresponding second sub-gate oxide layer in the second sub-logic gate region. In this case, the first oxide layer 101 in the first sub-logic gate region can be removed first, and then a second oxide layer 102 can be deposited on the surface of the first semiconductor structure. Then, the first oxide layer 101 and the second oxide layer 102 in the second sub-logic gate region can be removed, and then a second oxide layer 102 can be deposited on the surface of the first semiconductor structure.

[0051] In an embodiment of the present application, after depositing a second oxide layer 102 on the surface of the first semiconductor structure, a second semiconductor structure can be obtained. In the second semiconductor structure, a first sidewall spacer 1201 and a second sidewall spacer 1202 are formed on the sidewalls of the control gate structure, and a first type gate oxide layer with a first preset thickness is formed in the first type logic gate region. Then, a third oxide layer 103 can be deposited on the surface of the second semiconductor structure to form a third sidewall spacer 1203 outside the second sidewall spacer 1202, and to form a first type gate oxide layer with a second preset thickness. At the same time, a tunneling oxide layer with a third preset thickness can also be formed in the erase gate region 110. The first sidewall spacer 1201, the second sidewall spacer 1202 and the third sidewall spacer 1203 are used to make the target gap oxide layer 1200. The second preset thickness and the third preset thickness are both the same as the thickness of the third oxide layer 103. Optionally, the thickness of the third oxide layer 103 is 100 angstroms to 140 angstroms. For example, 100 angstroms, 105 angstroms, 110 angstroms, 115 angstroms, 120 angstroms, 125 angstroms, 130 angstroms, 135 angstroms, 140 angstroms, etc.

[0052] In the embodiment of the present application, when a tunneling oxide layer of partial thickness is formed in the erase gate region 110, if the first oxide layer 101 is not deposited in the erase gate region 110, only the second oxide layer 102 deposited in the erase gate region 110 is removed. If the first oxide layer 101 is deposited in the erase gate region 110, it is necessary to remove the first oxide layer 101 and the second oxide layer 102 deposited in the erase gate region 110. Specifically, taking the removal of the first oxide layer 101 and the second oxide layer 102 deposited in the erase gate region 110 as an example, a second sacrificial layer 132 can be covered on the surface of the second semiconductor structure, and the erase gate region 110 can be exposed, thereby removing the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110. Figure 9 is a schematic diagram of a structure after a second sacrificial layer is covered on the surface of a second semiconductor structure provided by an embodiment of the present application, such as Figure 9 As shown, the second sacrificial layer 132 covers the control gate region 120, the first type logic gate region, and the second type logic gate region, exposing only the erase gate region 110. Then, the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110 are removed by an etching process. Optionally, the second sacrificial layer 132 can be made of photoresist. When etching the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110, a combination of dry etching and wet etching can be used to completely remove the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110. In some embodiments, only wet etching can be used to completely remove the first oxide layer 101 and the second oxide layer 102 in the erase gate region 110.

[0053] In the embodiment of this application, Figure 10 This is a schematic diagram of a structure after a third oxide layer is deposited on the surface of a second semiconductor structure provided by an embodiment of the present application. Figure 10 As shown, after the oxide layer in the erase gate region 110 is completely removed, the second sacrificial layer 132 can be removed. Then, a third oxide layer 103 is deposited on the surface of the second semiconductor structure, so that the third spacer 1203 can be formed outside the second spacer 1202. At the same time, a first-type gate oxide layer of partial thickness is formed in the first-type logic gate region, and a tunnel oxide layer of partial thickness is formed in the erase gate region 110. Optionally, the process for depositing the third oxide layer 103 includes, but is not limited to, a high-temperature oxidation deposition process, an in-situ water vapor generation process, a chemical vapor deposition process, a physical vapor deposition process, etc.

[0054] In an embodiment of the present application, after depositing a third oxide layer 103 on the surface of the second semiconductor structure, a third semiconductor structure can be obtained. In the third semiconductor structure, a stacked first spacer 1201, a second spacer 1202, and a third spacer 1203 are formed on the sidewalls of the control gate structure, a first gate oxide layer of partial thickness is formed in the first-type logic gate region, and a tunnel oxide layer of partial thickness is formed in the erase gate region 110. Subsequently, a fourth oxide layer 104 can be deposited on the surface of the third semiconductor structure to form a fourth spacer 1204 outside the third spacer 1203, as well as a first gate oxide layer of partial thickness and a tunnel oxide layer. At the same time, a second gate oxide layer of partial thickness can also be formed in the second-type logic gate region.

[0055] In the embodiment of the present application, when forming a partial-thick second-type gate oxide layer in the second-type logic gate region, if the first oxide layer 101 is not deposited in the second-type logic gate region, the second oxide layer 102 and the third oxide layer 103 deposited in the second-type logic gate region are removed. If the first oxide layer 101 is deposited in the second-type logic gate region, the first oxide layer 101, the second oxide layer 102, and the third oxide layer 103 deposited in the second-type logic gate region need to be removed. The second-type logic gate region may include one or more logic gate regions 210. When multiple logic gate regions 210 are included, the oxide layer in the logic gate region 210 corresponding to the thicker gate oxide layer may be removed first.

[0056] In an embodiment of the present application, after the oxide layer deposited in the second-type logic gate region is removed, a fourth oxide layer 104 is deposited on the surface of the third semiconductor to form a fourth sidewall 1204 outside the third sidewall 1203, and at the same time, a first-type gate oxide layer of partial thickness is formed in the first-type logic gate region, a tunneling oxide layer of partial thickness is formed in the erase gate region 110, and a second-type gate oxide layer of partial thickness is formed in the second-type logic gate region.

[0057] In the embodiment of the present application, when the second-type logic gate region includes multiple logic gate regions 210, for example, the second-type logic gate region includes a second logic gate region 232 and a third logic gate region 233. When depositing the fourth oxide layer 104 on the surface of the third semiconductor structure, the first oxide layer 101, the second oxide layer 102, and the third oxide layer 103 on the surface of the second logic gate region 232 can be removed first. The fourth oxide layer 104 is then deposited on the control gate region 120, the erase gate region 110, the first-type logic gate region, and the second-type logic gate region, forming a first-type gate oxide layer of a fourth predetermined thickness in the first-type logic gate region, a tunneling oxide layer of a fifth predetermined thickness in the erase gate region 110, a second gate oxide layer of a sixth predetermined thickness in the second logic gate region 232, and a fourth spacer 1204 on the sidewalls of the third spacer 1203. The first oxide layer 101, the second oxide layer 102, the third oxide layer 103, and the fourth oxide layer 104 on the surface of the third logic gate region 233 are then removed. Finally, a fifth oxide layer 105 is deposited in the control gate region 120, the erase gate region 110, the first type logic gate region and the second type logic gate region to form a first type gate oxide layer with a seventh preset thickness in the first type logic gate region, a tunneling oxide layer with an eighth preset thickness in the erase gate region 110, a second gate oxide layer with a ninth preset thickness in the second logic gate region 232, a third type gate oxide layer with a tenth preset thickness in the third logic gate region 233, and a fifth sidewall 1205 on the sidewall of the fourth sidewall 1204 to obtain a target semiconductor structure.

[0058] As an optional embodiment, the thickness of the second gate oxide layer corresponding to the second logic gate region 232 is greater than the thickness of the third gate oxide layer corresponding to the third logic gate region 233. When removing the oxide layer in the second type of logic gate region, the oxide layer in the second logic gate region 232 can be removed first. Specifically, a third sacrificial layer 133 is covered on the surface of the third semiconductor structure, and the second logic gate region 232 is exposed, thereby removing the oxide layer in the second logic gate region 232. Figure 11 is a schematic diagram of a structure after a third sacrificial layer is covered on the surface of a third semiconductor structure provided by an embodiment of the present application, such as Figure 11As shown, the third sacrificial layer 133 covers the control gate region 120, the erase gate region 110, the first type logic gate region, and the third logic gate region 233, leaving only the second logic gate region 232 exposed. The oxide layer in the second logic gate region 232 is then removed through an etching process. Optionally, the third sacrificial layer 133 can be made of photoresist. When etching the oxide layer in the second logic gate region 232, a combination of dry etching and wet etching can be used to completely remove the oxide layer in the second logic gate region 232. In some embodiments, only wet etching can be used to completely remove the oxide layer in the second logic gate region 232. A fourth oxide layer 104 is then deposited on the control gate region 120, the erase gate region 110, the first type logic gate region, and the second type logic gate region to form a fourth sidewall spacer 1204 on the sidewall of the third sidewall spacer 1203.

[0059] Figure 12 is a schematic diagram of a structure after a fourth oxide layer is deposited on the surface of a third semiconductor structure provided in an embodiment of the present application, such as Figure 12 As shown, after the oxide layer in the second logic gate region 232 is completely removed, the third sacrificial layer 133 can be removed, and then the fourth oxide layer 104 can be deposited on the surface of the third semiconductor structure, thereby forming the fourth spacer 1204 outside the third spacer 1203. Simultaneously, a first type gate oxide layer of a fourth preset thickness is formed in the first type logic gate region, a tunneling oxide layer of a fifth preset thickness is formed in the erase gate region 110, and a second gate oxide layer of a sixth preset thickness is formed in the second logic gate region 232. The first spacer 1201, the second spacer 1202, the third spacer 1203, and the fourth spacer 1204 are used to form the target gap oxide layer 1200. Optionally, the process for depositing the fourth oxide layer 104 includes, but is not limited to, a high-temperature oxidation deposition process, an in-situ water vapor generation process, a chemical vapor deposition process, a physical vapor deposition process, and the like. Optionally, the fourth and fifth preset thicknesses can be zero or the same as the thickness of the fourth oxide layer 104. The sixth preset thickness is the same as the thickness of the fourth oxide layer 104. Optionally, the thickness of the fourth oxide layer 104 is 40 angstroms to 80 angstroms, specifically 55 angstroms to 60 angstroms, for example, 55 angstroms, 55.5 angstroms, 56 angstroms, 56.5 angstroms, 57 angstroms, 57.5 angstroms, 58 angstroms, 58.5 angstroms, 59 angstroms, 59.5 angstroms, 60 angstroms, etc.

[0060] In a flash memory device, the second logic gate region 232 is typically formed between the first logic gate region 231 and the third logic gate region 233. The gate oxide integrity (GOI) of the second gate oxide layer ultimately formed thereon may be affected by the first logic region and the second logic region. Therefore, to ensure the gate oxide integrity of the second gate oxide layer, a high-quality oxide deposition process can be used to form the second gate oxide layer. For example, an in-situ water vapor generation process can be used to deposit the fourth oxide layer 104, thereby forming a high-quality second gate oxide layer in the second logic gate region 232. Specifically, when depositing the fourth oxide layer 104 on the control gate region 120, the erase gate region 110, the first type logic gate region, and the second type logic gate region, the fourth oxide layer 104 can be deposited on the control gate region 120, the erase gate region 110, the first type logic gate region, and the second type logic gate region based on the in-situ water vapor generation process to form the fourth spacer 1204 on the sidewall of the third spacer 1203. Since the in-situ water vapor generation process is based on the reaction between silicon and oxygen to generate an oxide layer, and the control gate region 120, the erase gate region 110, the first type logic gate region and the third logic gate region 233 are all covered with an oxide layer, only the surface of the silicon substrate 1 in the second logic gate region 232 is exposed. Therefore, when the fourth oxide layer 104 is deposited using the in-situ water vapor generation process, the fourth oxide layer 104 will only be formed in the second logic gate region 232.

[0061] Next, after depositing a fourth oxide layer 104 on the surface of the third semiconductor structure, a fourth semiconductor structure can be obtained. In the fourth semiconductor structure, a first spacer 1201, a second spacer 1202, a third spacer 1203, and a fourth spacer 1204 are formed on the sidewalls of the control gate structure, a first gate oxide layer of partial thickness is formed in the first logic gate region, a tunnel oxide layer of partial thickness is formed in the erase gate region 110, and a second gate oxide layer of partial thickness is formed in the second logic gate region 232. Then, a fifth oxide layer 105 can be deposited on the surface of the fourth semiconductor structure to form a fifth spacer 1205 outside the fourth spacer 1204, as well as a first gate oxide layer of a seventh preset thickness, a tunnel oxide layer of an eighth preset thickness, and a second gate oxide layer of a ninth preset thickness. At the same time, a third gate oxide layer of a tenth preset thickness can also be formed in the third logic gate region 233. The first spacer 1201, the second spacer 1202, the third spacer 1203, the fourth spacer 1204, and the fifth spacer 1205 are used to form the target gap oxide layer 1200. The seventh preset thickness, the eighth preset thickness, the ninth preset thickness, and the tenth preset thickness are all the same as the thickness of the fifth oxide layer 105. Optionally, the thickness of the fifth oxide layer 105 is 5 angstroms to 40 angstroms. For example, 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, 30 angstroms, 35 angstroms, 40 angstroms, etc.

[0062] Before forming the third gate oxide layer in the third logic gate region 233, the oxide layer in the third logic gate region 233 needs to be removed. Furthermore, since the third logic gate region 233 is the last region where an oxide layer needs to be formed, when removing the oxide layer in the third logic gate region 233, the oxide layer in the dual gate (DG) region of the fourth semiconductor structure can also be removed simultaneously. Specifically, the flash memory region 100 also includes a word line region 140, which is adjacent to the control gate region 120. The control gate region 120 is formed between the word line region 140 and the erase gate region 110. The dual gate region refers to the word line region 140 and the portion of the control gate region 120 adjacent to the word line region 140. A fourth sacrificial layer 134 is covered on the surface of the fourth semiconductor structure, exposing the dual gate region and the third logic gate region 233, thereby removing the oxide layers in the dual gate region and the third logic gate region 233. Figure 13 is a schematic diagram of a structure after a fourth sacrificial layer is covered on the surface of a fourth semiconductor structure provided by an embodiment of the present application, such as Figure 13 As shown, a fourth sacrificial layer 134 is covered over the erase gate region 110, the portion of the control gate region 120 adjacent to the erase gate region 110, the first type logic gate region, and the second logic gate region 232 in the fourth semiconductor structure. The word line region 140, the portion of the control gate region 120 adjacent to the word line region 140, and the third logic gate region 233 are exposed, and then the oxide layer in the word line region 140, the portion of the control gate region 120 adjacent to the word line region 140, and the third logic gate region 233 is removed through an etching process. Optionally, the fourth sacrificial layer 134 can be formed using a photoresist. When etching the oxide layer in the word line region 140, the portion of the control gate region 120 adjacent to the word line region 140, and the third logic gate region 233, a combination of dry etching and wet etching can be used to remove the oxide layer in the word line region 140, the portion of the control gate region 120 adjacent to the word line region 140, and the third logic gate region 233. In some embodiments, a combination of dry etching and wet etching may be used to remove the oxide layer in the word line region 140, a portion of the control gate region 120 adjacent to the word line region 140, and the third logic gate region 233. In other embodiments, only wet etching may be used to remove the oxide layer in the word line region 140, a portion of the control gate region 120 adjacent to the word line region 140, and the third logic gate region 233.

[0063] It should be noted that when wet etching is used to remove the oxide layer in the dual-gate region, since the wet etching will laterally etch the first spacer 1201, the second spacer 1202, the third spacer 1203, and the fourth spacer 1204 formed on the sidewalls of the control gate structure, it is necessary to control the wet etching time to ensure that the subsequent formation of the target gap oxide layer 1200 can reach the target thickness. In some embodiments, in order not to affect the subsequent formation of the target gap oxide layer 1200, the fourth sacrificial layer 134 may also cover the word line region 140 and the control gate region 120.

[0064] Figure 14 is a schematic diagram of a structure after a fifth oxide layer is deposited on the surface of a fourth semiconductor structure provided in an embodiment of the present application, such as Figure 14 As shown, after removing the oxide layers in the dual-gate region and the third logic gate region 233, the fourth sacrificial layer 134 can be removed, and then a fifth oxide layer 105 can be deposited on the surface of the fourth semiconductor structure, thereby forming the fifth spacer 1205 outside the fourth spacer 1204. At the same time, a first-type gate oxide layer of a remaining thickness is formed in the first-type logic gate region, a tunneling oxide layer of an eighth preset thickness is formed in the erase gate region 110, a second gate oxide layer of a ninth preset thickness is formed in the second logic gate region 232, and a third gate oxide layer of a tenth preset thickness is formed in the third logic gate region 233. Optionally, the process for depositing the fifth oxide layer 105 includes, but is not limited to, a high-temperature oxidation deposition process, a chemical vapor deposition process, a physical vapor deposition process, and the like.

[0065] S105: forming a target gap oxide layer based on the sidewall structure, forming a target first-type gate oxide layer based on the first-type gate oxide layer, forming a target tunneling oxide layer based on the tunneling oxide layer, and forming a target second-type gate oxide layer based on the second-type gate oxide layer to obtain a target semiconductor structure.

[0066] In an embodiment of the present application, after depositing the first oxide layer 101, the second oxide layer 102, the third oxide layer 103, the fourth oxide layer 104, and the fifth oxide layer 105 in the initial semiconductor structure, a first spacer 1201, a second spacer 1202, a third spacer 1203, a fourth spacer 1204, and a fifth spacer 1205 are sequentially formed on the sidewalls of the control gate structure. The spacer structure formed by these five spacers constitutes an initial gap oxide layer. By removing the initial gap oxide layer of the target thickness to obtain a target gap oxide layer 1200 of a preset thickness, a target semiconductor structure is obtained. Optionally, the target thickness can be 200 angstroms to 240 angstroms, such as 200 angstroms, 205 angstroms, 210 angstroms, 215 angstroms, 220 angstroms, 225 angstroms, 230 angstroms, 235 angstroms, 240 angstroms, etc.

[0067] It should be noted that after the first spacer 1201, the second spacer 1202, the third spacer 1203, the fourth spacer 1204, and the fifth spacer 1205 are prepared, it is not necessary to remove the initial gap oxide layer of the target thickness. Removal of the initial gap oxide layer of the target thickness can also be achieved before forming the fifth spacer 1205. When the oxide layer in the dual-gate region and the third logic gate region 233 is previously removed, the wet etching will laterally etch the spacer structure formed by the first spacer 1201, the second spacer 1202, the third spacer 1203, and the fourth spacer 1204. At this time, by controlling the wet etching time, the spacer structure of the target thickness can be removed. Therefore, after the fifth spacer 1205 is formed, there is no need to remove the initial gap oxide layer of the target thickness, thereby simplifying the process flow and improving the efficiency of semiconductor structure preparation.

[0068] In the embodiment of the present application, for the oxide layer deposited in the first-type logic gate region, the first-type gate oxide layer of the first preset thickness, the first-type gate oxide layer of the second preset thickness, the first-type gate oxide layer of the fourth preset thickness, and the first-type gate oxide layer of the seventh preset thickness are combined to form a target first-type gate oxide layer. Taking the first-type logic gate region including the first logic gate region 231 as an example, a first gate oxide layer of the first preset thickness, a first gate oxide layer of the second preset thickness, a first gate oxide layer of the fourth preset thickness, and a first gate oxide layer of the seventh preset thickness are formed in the first logic gate region 231. These first gate oxide layers are stacked together to form a target first gate oxide layer 211 that meets the required thickness.

[0069] Similarly, for the oxide layer deposited in the erase gate area 110, the tunnel oxide layer of the third preset thickness, the tunnel oxide layer of the fifth preset thickness and the tunnel oxide layer of the eighth preset thickness are stacked together, and combined with the subsequently formed tunnel oxide layer of the eighth preset thickness, a target tunnel oxide layer 111 that meets the thickness requirements is formed.

[0070] Furthermore, for the oxide layer deposited in the second-type logic gate region, the second-type gate oxide layer of the sixth preset thickness forms the target second-type gate oxide layer. Where the second-type logic gate region includes multiple logic gate regions, taking the example of the second-type logic gate region including the second logic gate region 232 and the third logic gate region 233, a second gate oxide layer of the sixth preset thickness and a second gate oxide layer of the ninth preset thickness are formed in the second logic gate region 232. These second gate oxide layers are stacked together to form the target second gate oxide layer 212 that meets the required thickness. A third-type gate oxide layer of the tenth preset thickness is formed in the third logic gate region 233, and this third gate oxide layer forms the target third gate oxide layer 213 that meets the required thickness.

[0071] In an embodiment of the present application, after removing the initial gap oxide layer of the target thickness to obtain the target gap oxide layer 1200, electrode materials can also be deposited in the word line area 140, the erase gate area 110, the first type of logic gate area and the second type of logic gate area to obtain the target semiconductor structure. Depositing electrode material in the word line area 140 can form a word line 141. Depositing electrode material in the erase gate area 110 can form an erase gate 112, and depositing electrode material in the first type of logic gate area can form a first type of logic gate. Depositing electrode material in the second type of logic gate area can form a second type of logic gate. Optionally, the electrode material is polysilicon. As an optional embodiment, Figure 15 is a schematic structural diagram of a target semiconductor structure provided in an embodiment of the present application, such as Figure 15 As shown, the first type of logic gate region includes a first logic gate region 231, in which an electrode material is deposited to form a first logic gate 221. The second type of logic gate region includes a second logic gate region 232 and a third logic gate region 233, in which an electrode material is deposited to form a second logic gate 222, and in which an electrode material is deposited to form a third logic gate 223.

[0072] Through the above method, the flash memory process and the logic process can be combined, and the preparation of the gap oxide layer, the first type gate oxide layer, the tunnel oxide layer and the second type gate oxide layer can be achieved simultaneously, thereby unifying the oxide layer preparation process of each region, simplifying the oxide layer preparation process, and improving the efficiency of semiconductor structure preparation. Moreover, since the gap oxide layer finally prepared is obtained by compounding the oxide layers prepared multiple times, and since the oxide layers in other regions have been prepared at the same time, the thickness of the gap oxide layer is no longer affected by the logic area process and the flash memory area process, and precise control of the gap oxide layer thickness is achieved, thereby improving the uniformity of the gap oxide layer and further improving the performance of the flash device. In addition, in practical applications, this method can realize the simultaneous preparation of the gap oxide layers in different flash memory devices in a whole wafer, thereby maintaining the uniformity of the gap oxide layers in different flash memory devices in the whole wafer, and thus improving the preparation yield of the flash memory device.

[0073] Figure 16 FIG. 1 is a schematic diagram of test results of another flash memory device provided in an embodiment of the present application. Figure 16As shown, a group of flash memory devices containing a target semiconductor structure prepared based on the above-described semiconductor structure formation method is arbitrarily selected as a test group. By performing current testing on the interfaces (I / O) of the memory cells of this group of flash memory devices, it is found that the erase and write currents (IR1) corresponding to the memory cells of these flash memory devices are highly consistent. According to statistics, the yield rate of the flash memory devices obtained based on the above-described semiconductor structure formation method is above 97%. This method significantly improves the yield rate of flash memory devices.

[0074] The embodiment of the present application provides a semiconductor structure, Figure 17 is a schematic diagram of a semiconductor structure provided in an embodiment of the present application, such as Figure 17 As shown, the semiconductor structure may include a flash memory region 100 and a logic region 200 .

[0075] In an embodiment of the present application, the flash memory region 100 includes a control gate region 120 and an erase gate region 110. A control gate structure is formed on the surface of the control gate region 120, and a target gap oxide layer structure is formed on the sidewalls of the control gate structure. The target gap oxide layer structure is obtained based on a first spacer 1201, a second spacer 1202, a third spacer 1203, and a fourth spacer 1204, which are sequentially formed on the sidewalls of the control gate structure. The first spacer 1201 is obtained based on the first oxide layer 101. Optionally, the thickness of the first spacer 1201 is 250 angstroms to 280 angstroms. For example, 250 angstroms, 255 angstroms, 260 angstroms, 265 angstroms, 270 angstroms, 275 angstroms, 280 angstroms, etc. The second spacer 1202 is obtained based on the second oxide layer 102. Optionally, the thickness of the second spacer 1202 is 40 angstroms to 70 angstroms. For example, 40 angstroms, 45 angstroms, 50 angstroms, 55 angstroms, 60 angstroms, 65 angstroms, 70 angstroms, etc. The third spacer 1203 is obtained based on the third oxide layer 103. Optionally, the thickness of the third spacer 1203 is 100 angstroms to 140 angstroms. For example, 100 angstroms, 105 angstroms, 110 angstroms, 115 angstroms, 120 angstroms, 125 angstroms, 130 angstroms, 135 angstroms, 140 angstroms, etc. The fourth spacer 1204 is obtained based on the fourth oxide layer 104. Optionally, the thickness of the fourth spacer 1204 is 0 angstroms to 80 angstroms. For example, 0 angstroms or 40 angstroms to 80 angstroms. Optionally, the thickness of the target gap oxide layer 1200 is 220 angstroms to 260 angstroms, such as 220 angstroms, 225 angstroms, 230 angstroms, 235 angstroms, 240 angstroms, 245 angstroms, 250 angstroms, 255 angstroms, 260 angstroms, etc.

[0076] In an embodiment of the present application, a target tunneling oxide layer 111 is formed on the surface of the erase gate region 110. The target tunneling oxide layer 111 is obtained based on a tunneling oxide layer of a third preset thickness and a tunneling oxide layer of a fifth preset thickness. The tunneling oxide layer of the third preset thickness is obtained based on the third oxide layer 103 formed in the erase gate region 110, and the tunneling oxide layer of the fifth preset thickness is obtained based on the fourth oxide layer 104 formed in the erase gate region 110. Optionally, the thickness of the tunneling oxide layer is 120 angstroms to 160 angstroms. For example, 120 angstroms, 125 angstroms, 130 angstroms, 135 angstroms, 140 angstroms, 145 angstroms, 150 angstroms, 155 angstroms, 160 angstroms, etc.

[0077] In an embodiment of the present application, the logic region 200 includes a first-class logic gate region and a second-class logic gate region. A target first-class gate oxide layer is formed on the surface of the first-class logic gate region, and the target first-class gate oxide layer is obtained based on a first-preset thickness of a first-class gate oxide layer, a second-preset thickness of a first-class gate oxide layer, and a fourth-preset thickness of a first-class gate oxide layer. The first-class gate oxide layer of the first-preset thickness is obtained based on the second oxide layer 102 formed in the first-class logic gate region, the first-class gate oxide layer of the second-preset thickness is based on the third oxide layer 103 formed in the first-class logic gate region, and the first-class gate oxide layer of the fourth-preset thickness is obtained based on the fourth oxide layer 104 formed in the first-class logic gate region. In an optional embodiment, the target first-class gate oxide layer includes a target first gate oxide layer 211. Optionally, the thickness of the target first gate oxide layer 211 is 170 angstroms to 220 angstroms. For example, 170 angstroms, 175 angstroms, 180 angstroms, 185 angstroms, 190 angstroms, 195 angstroms, 200 angstroms, 205 angstroms, 210 angstroms, 215 angstroms, 220 angstroms, etc. A target second-class gate oxide layer is formed on the surface of the second-class logic gate region, and the target second-class gate oxide layer is obtained based on the second-class gate oxide layer of the sixth preset thickness. The target second-class gate oxide layer includes a target second gate oxide layer 212 and a target third gate oxide layer 213. Optionally, the thickness of the second gate oxide layer is 60 angstroms to 100 angstroms. Specifically, it can be 75 angstroms to 80 angstroms, for example, 75.5 angstroms, 76 angstroms, 76.5 angstroms, 77 angstroms, 77.5 angstroms, 78 angstroms, 78.5 angstroms, 79 angstroms, 79.5 angstroms, 80 angstroms, etc. Optionally, the thickness of the third gate oxide layer is 5 angstroms to 35 angstroms. For example, 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, 30 angstroms, 35 angstroms, etc.

[0078] The semiconductor structure described in the embodiments of the present application can be formed based on the above-described method for forming a semiconductor structure. In this semiconductor junction, the gap oxide layer between the word line 141 and the floating gate 122 has high consistency, thereby achieving excellent storage performance. Furthermore, this semiconductor structure has high fabrication efficiency and low fabrication cost, and therefore can be widely promoted and applied.

[0079] An embodiment of the present application further provides a memory device, which includes the semiconductor structure described above.

[0080] The memory device described in the embodiments of the present application can be a flash memory device, which can be used in embedded devices. Because this memory device includes the aforementioned semiconductor structure, the gap oxide layer between the word line and the floating gate has a high consistency, resulting in excellent storage performance, higher manufacturing efficiency, and lower manufacturing costs. Therefore, this memory device also has similar advantages.

[0081] An embodiment of the present application provides an electronic device, which includes the memory device described above.

[0082] The electronic device described in the embodiments of the present application can be any electronic product or device such as a smartphone, a desktop computer, a tablet computer, a laptop computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, an intelligent voice interaction device, a smart home appliance, a smart wearable device, an in-vehicle terminal device, or any intermediate product that includes the above-mentioned storage device.

[0083] The electronic device described in the embodiments of the present application includes the aforementioned access device, and the memory device includes the aforementioned semiconductor structure. In this semiconductor structure, the gap oxide layer between the word line and the floating gate has a high consistency, thereby having excellent storage performance, higher manufacturing efficiency, and lower manufacturing costs. Therefore, this electronic device also has similar advantages.

[0084] It should be noted that the order of the embodiments of the present application described above is for descriptive purposes only and does not represent the superiority or inferiority of the embodiments. The above description is of specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0085] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0086] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0087] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: The method comprises: Providing an initial semiconductor structure; the initial semiconductor structure includes a flash memory area and a logic area; the flash memory area includes a control gate area and an erase gate area, and a control gate structure is formed on the surface of the control gate area; the logic area includes a first type of logic gate area and a second type of logic gate area; forming a sidewall structure located on a sidewall of the control gate structure, at least one tunneling oxide layer located in the erase gate region, and a gate oxide layer located in the logic region; the gate oxide layer includes at least one first-type gate oxide layer located in the first-type logic gate region and at least one second-type gate oxide layer located in the second-type logic gate region, and the gate oxide layer is formed synchronously with the sidewall structure and the tunneling oxide layer; A target gap oxide layer is formed based on the sidewall structure, a target first-type gate oxide layer is formed based on the first-type gate oxide layer, a target tunneling oxide layer is formed based on the tunneling oxide layer, and a target second-type gate oxide layer is formed based on the second-type gate oxide layer to obtain a target semiconductor structure.

2. The method according to claim 1, characterized in that The spacer structure includes: a first spacer, a second spacer, a third spacer, and a fourth spacer; the spacer structure forming the sidewall of the control gate structure, at least one tunneling oxide layer located in the erase gate region, and the gate oxide layer located in the logic region includes: forming a first spacer on a sidewall of the control gate structure; forming a first type gate oxide layer with a first preset thickness in the first type logic gate region, and forming a second spacer on the sidewall of the first spacer; forming a first type gate oxide layer of a second preset thickness in the first type logic gate region, forming a tunnel oxide layer of a third preset thickness in the erase gate region, and forming a third sidewall spacer on the sidewall of the second sidewall spacer; A first type gate oxide layer of a fourth preset thickness is formed in the first type logic gate region, a tunnel oxide layer of a fifth preset thickness is formed in the erase gate region, a second type gate oxide layer of a sixth preset thickness is formed in the second type logic gate region, and a fourth sidewall is formed on the sidewall of the third sidewall.

3. The method according to claim 2, characterized in that The forming of a first spacer on the sidewall of the control gate structure comprises: A first oxide layer is deposited to form a first sidewall spacer covering the sidewall of the control gate structure.

4. The method according to claim 2, characterized in that The first type of logic gate region includes a first logic gate region; forming a first type of gate oxide layer with a first preset thickness in the first type of logic gate region, and forming a second spacer on the sidewall of the first spacer, comprises: A second oxide layer is deposited to form a first type gate oxide layer with a first preset thickness in the first type logic gate region, and a second spacer is formed on the sidewall of the first spacer.

5. The method according to claim 2, characterized in that Forming a first type gate oxide layer with a second preset thickness in the first type logic gate region, forming a tunnel oxide layer with a third preset thickness in the erase gate region, and forming a third sidewall spacer on the sidewall of the second sidewall spacer, comprising: A third oxide layer is deposited to form a first gate oxide layer of a second preset thickness in the first logic gate region, a tunnel oxide layer of a third preset thickness is formed in the erase gate region, and a third sidewall spacer is formed on the sidewall of the second sidewall spacer.

6. The method according to claim 2, characterized in that The second-type logic gate region includes a second logic gate region; forming a first-type gate oxide layer with a fourth preset thickness in the first-type logic gate region, forming a tunnel oxide layer with a fifth preset thickness in the erase gate region, forming a second-type gate oxide layer with a sixth preset thickness in the second-type logic gate region, and forming a fourth spacer on the sidewall of the third spacer, including: A fourth oxide layer is deposited to form a first gate oxide layer of a fourth preset thickness in the first logic gate region, a tunnel oxide layer of a fifth preset thickness is formed in the erase gate region, a second gate oxide layer of a sixth preset thickness is formed in the second logic gate region, and a fourth sidewall is formed on the sidewall of the third sidewall.

7. The method according to claim 6, characterized in that The depositing of the fourth oxide layer, forming a first type gate oxide layer with a fourth preset thickness in the first type logic gate region, forming a tunneling oxide layer with a fifth preset thickness in the erase gate region, forming a second gate oxide layer with a sixth preset thickness in the second logic gate region, and forming a fourth spacer on the sidewall of the third spacer, includes: A fourth oxide layer is deposited based on an in-situ water vapor generation process, a first gate oxide layer of a fourth preset thickness is formed in the first logic gate area, a tunnel oxide layer of a fifth preset thickness is formed in the erase gate area, a second gate oxide layer of a sixth preset thickness is formed in the second logic gate area, and a fourth sidewall is formed on the sidewall of the third sidewall.

8. The method according to claim 6, characterized in that The second type of logic gate region further includes a third logic gate region; the spacer structure further includes a fifth spacer; and the method for forming the semiconductor structure further includes: A fifth oxide layer is deposited to form a first type gate oxide layer with a seventh preset thickness in the first type logic gate region, a tunnel oxide layer with an eighth preset thickness is formed in the erase gate region, a second gate oxide layer with a ninth preset thickness is formed in the second logic gate region, a third type gate oxide layer with a tenth preset thickness is formed in the third logic gate region, and a fifth sidewall is formed on the sidewall of the fourth sidewall.

9. The method according to claim 8, characterized in that The target second-type gate oxide layer includes a target second gate oxide layer and a target third gate oxide layer; the target gap oxide layer is formed based on the sidewall structure, the target first-type gate oxide layer is formed based on the first-type gate oxide layer, the target tunneling oxide layer is formed based on the tunneling oxide layer, and the target second-type gate oxide layer is formed based on the second-type gate oxide layer, to obtain a target semiconductor structure, including: forming an initial gap oxide layer based on the first spacer, the second spacer, the third spacer, the fourth spacer and the fifth spacer; Removing the target thickness of the initial gap oxide layer to obtain the target gap oxide layer; forming a target first type gate oxide layer based on the first type gate oxide layer of the first preset thickness, the first type gate oxide layer of the second preset thickness, the first type gate oxide layer of the fourth preset thickness, and the first type gate oxide layer of the seventh preset thickness; forming a target tunneling oxide layer based on the tunneling oxide layer having the third preset thickness, the tunneling oxide layer having the fifth preset thickness, and the tunneling oxide layer having the eighth preset thickness; forming a target second gate oxide layer based on the second gate oxide layer of the sixth preset thickness and the second gate oxide layer of the ninth preset thickness; A target third gate oxide layer is formed based on the third type gate oxide layer with the tenth preset thickness to obtain a target semiconductor structure.

10. The method according to claim 1, characterized in that The flash memory area further includes a word line region, and the control gate region is formed between the word line region and the erase gate region; The target gap oxide layer is formed based on the spacer structure, the target first-type gate oxide layer is formed based on the first-type gate oxide layer, the target tunneling oxide layer is formed based on the tunneling oxide layer, and the target second-type gate oxide layer is formed based on the second-type gate oxide layer to obtain a target semiconductor structure, including: Based on the sidewall structure, a target gap oxide layer is formed; Based on the first type of gate oxide layer, forming a target first type gate oxide layer; Based on the tunneling oxide layer, forming a target tunneling oxide layer; forming a target second-type gate oxide layer based on the second-type gate oxide layer; Electrode materials are deposited on the word line region, the erase gate region, the first type logic gate region, and the second type logic gate region to obtain the target semiconductor structure.

11. A semiconductor structure, characterized in that include: A logic area and a flash memory area; the logic area includes a first type of logic gate area and a second type of logic gate area; the flash memory area includes a control gate area and an erase gate area; a target first-type gate oxide layer located on the surface of the first-type logic gate region; the target first-type gate oxide layer is obtained based on at least one first-type gate oxide layer; a target second type gate oxide layer located on a surface of the second type logic gate region; The target second type gate oxide layer is obtained based on at least one second type gate oxide layer; A control gate structure located on the surface of the control gate region, wherein a target gap oxide layer is formed on the sidewall of the control gate structure; the target gap oxide layer is obtained based on a spacer structure sequentially formed on the sidewall of the control gate structure; A target tunneling oxide layer is formed on the surface of the erase gate region; The target tunneling oxide layer is obtained based on at least one tunneling oxide layer; the gate oxide layer is formed synchronously with the sidewall structure and the tunneling oxide layer.

12. The semiconductor structure according to claim 11, wherein: The sidewall structure includes: a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; the thickness of the first sidewall is 250 angstroms to 280 angstroms; the thickness of the second sidewall is 40 angstroms to 70 angstroms; the thickness of the third sidewall is 100 angstroms to 140 angstroms; the thickness of the fourth sidewall is 0-80 angstroms.

13. The semiconductor structure according to claim 11 or 12, characterized in that: The target gap oxide layer has a thickness of 220 angstroms to 260 angstroms; the tunnel oxide layer has a thickness of 120 angstroms to 160 angstroms.

14. The semiconductor structure according to claim 11 or 12, characterized in that: The target first type gate oxide layer includes a target first gate oxide layer; the target first gate oxide layer has a thickness of 170 angstroms to 220 angstroms.

15. The semiconductor structure according to claim 14, wherein: The target second type gate oxide layer includes a target second gate oxide layer and a target third gate oxide layer: the target second gate oxide layer has a thickness of 60 angstroms to 100 angstroms; the target third gate oxide layer has a thickness of 5 angstroms to 35 angstroms.

16. A memory device, characterized in that: The memory device comprises the semiconductor structure according to any one of claims 11 to 15.

17. An electronic device, characterized in that: The electronic device includes the memory device according to claim 16.

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