Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include: a first support including a first inclined surface; a first gate structure including first insulating layers and first conductive layers alternately stacked along the first inclined surface; a second support located above or on the first support and including a second inclined surface; a second gate structure including a second insulating layer and a second conductive layer alternately stacked along the second inclined surface; a first contact plug extending through the second gate structure and connected to at least one of the first conductive layers; and a second contact plug disposed over or on the second gate structure and connected to at least one second conductive layer among the second conductive layers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-1023-0105301, filed on August 11, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to an electronic device and a method of manufacturing the electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0004] The degree of integration of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the degree of integration of a semiconductor device in which a memory cell is formed as a single layer on a substrate has reached a limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate has been proposed. In addition, various structures and manufacturing methods are being developed to improve the operational reliability of the three-dimensional semiconductor device. Summary of the invention

[0005] According to one embodiment of the present disclosure, a semiconductor device may include: a first support member, which includes a first inclined surface; a first gate structure, which includes a first insulating layer and a first conductive layer alternately stacked along the first inclined surface; a second support member, which is located above or on the first support member and includes a second inclined surface; a second gate structure, which includes a second insulating layer and a second conductive layer alternately stacked along the second inclined surface; a first contact plug, which extends through the second gate structure and is connected to at least one first conductive layer among the first conductive layers; and a second contact plug, which is arranged above or on the second gate structure and is connected to at least one second conductive layer among the second conductive layers.

[0006] According to one embodiment of the present disclosure, a semiconductor device may include: a first support member, which includes a first inclined surface; a first gate structure, which includes a first insulating layer and a first conductive layer alternately stacked along the first inclined surface; a second support member, which is located above or on the first support member and includes a second inclined surface; a second gate structure, which includes a second insulating layer and a second conductive layer alternately stacked along the second inclined surface; a channel structure, which extends through the second gate structure and the first gate structure; a first contact plug, which is on the first gate structure and includes a top surface located at substantially the same level as a top surface of the channel structure; and a second contact plug, which is on the second gate structure and connected to at least one second conductive layer among the second conductive layers.

[0007] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a first support member including a first inclined surface; forming a first stack, the first stack including a first material layer and a second material layer alternately stacked along the first inclined surface; forming a second support member including a second inclined surface on the first support member; forming a second stack, the second stack including a third material layer and a fourth material layer alternately stacked along the second inclined surface; forming a first contact opening, the first contact opening extending through the second stack and exposing at least one of the second material layers; and forming a first contact plug in the first contact opening.

[0008] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a first support member including a first inclined surface; forming a first stack, the first stack including a first material layer and a second material layer alternately stacked along the first inclined surface; forming a first channel sacrificial layer in the first stack; forming a second support member including a second inclined surface on the first support member; forming a second stack, the second stack including a third material layer and a fourth material layer alternately stacked along the second inclined surface; forming a channel opening in the second stack to expose the first channel sacrificial layer; when forming the channel opening, forming a first contact opening exposing at least one second material layer among the second material layers; forming a second contact opening exposing at least one fourth material layer among the fourth material layers; forming a first contact plug in the first contact opening; and forming a second contact plug in the second contact opening.

[0009] These and other features and advantages of the embodiments of the present disclosure will become apparent to those of ordinary skill in the art from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 1D is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0011] FIG. 2A to FIG. 2D is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] FIG. 3A to FIG. 10B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] FIG. 11A to FIG. 17B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] FIG. 18A to FIG. 22B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0015] FIG. 23A to FIG. 28Bis a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] FIG. 29A to FIG. 33B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0017] FIG. 34A to FIG. 36B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] According to one aspect of the present disclosure, a semiconductor device having a stable structure and improved characteristics is provided. According to another aspect of the present disclosure, a method of manufacturing the semiconductor device is also provided.

[0019] Hereinafter, various embodiments according to the technical concept of the present disclosure are described with reference to the accompanying drawings.

[0020] Figures 1A to 1D is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1A is a plan view, and Figure 1B , Figure 1C and Figure 1D It is along Figure 1A Cross-sectional view along line AA′.

[0021] Reference now Figures 1A to 1D , the semiconductor device may include a first support 110, a first gate structure 120, a second support 130, a second gate structure 140, a first contact plug 160, a second contact plug 170, a third contact plug 180, and a slit structure 190. The semiconductor device may further include an insulating spacer 150, a channel contact plug CHCT, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, or a channel structure CH, or may further include a combination thereof.

[0022] The first support member 110 may include a first inclined surface 110A. The first inclined surface 110A may have an acute angle of inclination. An acute angle means an angle exceeding 0 degrees to less than 90 degrees, or in other words, between 0 degrees and 90 degrees. For example, the acute angle may be about 60 degrees. The first support member 110 may include an insulating material such as an oxide.

[0023] The second support 130 may be located above or on the first support 110. The second support 130 may include a second inclined surface 130A. For example, the second inclined surface 130A may have an acute inclination. The second inclined surface 130A may have an inclination substantially equal to or equal to or different from the inclination of the first inclined surface 110A.

[0024] The first gate structure 120 may be located above or on the first support 110, and may include first insulating layers 120A and first conductive layers 120B that are alternately stacked. For example, the first gate structure 120 may include first insulating layers 120A and first conductive layers 120B that are alternately stacked along the first inclined surface 110A. The first gate structure 120 may include a first cell region CR1 and a first contact region CTR1 extending along the first inclined surface 110A, in which the first conductive layer 120B extends in the first direction I. In the first contact region CTR1, the top surface of each of the first conductive layers 120B may be located at substantially the same level.

[0025] The second gate structure 140 may be located above or on the second support 130, and may include a second insulating layer 140A and a second conductive layer 140B alternately stacked. For example, the second gate structure 140 may include a second insulating layer 140A and a second conductive layer 140B alternately stacked along the second inclined surface 130A. The second gate structure 140 may include a second cell region CR2 and a second contact region CTR2 extending along the second inclined surface 130A, in which the second conductive layer 140B extends in the first direction I. In the second contact region CTR2, the top surface of each of the second conductive layers 140B in the second conductive layers 140B may be located at substantially the same level.

[0026] The first gate structure 120 and the second gate structure 140 may overlap each other. For example, in a third direction III intersecting the first direction I, the first cell region CR1 and the second cell region CR2 may overlap each other. In addition, in the third direction III, the first contact region CTR1 and the second contact region CTR2 may overlap each other. For example, the first direction I may be a horizontal direction in which the first conductive layer 120B extends, and the third direction III may be a vertical direction in which the first conductive layer 120B is stacked. However, the present disclosure is not limited thereto, and the first cell region CR1 and the second contact region CTR2 may partially overlap, and the second cell region CR2 and the first contact region CTR1 may not overlap each other. By overlapping the first cell region CR1 and the second cell region CR2 and overlapping the first contact region CTR1 and the second contact region CTR2, the area occupied by the first gate structure 120 and the second gate structure 140 in the semiconductor device is reduced. Therefore, the degree of integration of the semiconductor device can be significantly improved. The degree of integration (as the term is used herein) refers to how tightly the various elements of a semiconductor device are packaged or integrated into a semiconductor wafer or chip, and may also be referred to as semiconductor device density or compactness. This is an important improvement because increasing semiconductor device integration can result in more powerful and efficient electronic devices.

[0027] The channel structure CH may extend through the second gate structure 140 and the first gate structure 120. The channel structure CH may be located in the second cell region CR2 of the second gate structure 140 and the first cell region CR1 of the first gate structure 120. The channel structure CH may include a channel layer CHA. The channel structure CH may further include a memory layer CHB surrounding the channel layer CHA and an insulating core CHC formed inside the channel layer CHA. The channel structure CH may include a channel layer CHA. The channel layer CHA and the memory layer CHB may extend from the bottom of the channel structure CH to the top along the III direction. The insulating core CHC may extend from the bottom of the channel structure CH to a level lower than the top of the channel structure CH along the III direction. The top surface of the insulating core CHC may be covered by the channel layer CHA.

[0028] The slit structure 190 may extend through the second gate structure 140 and the first gate structure 120. The slit structure 190 may extend in the first direction I. The slit structure 190 may be an insulating layer formed in a slit (not shown) that serves as a path for replacing a sacrificial layer (not shown) with the first conductive layer 120B and the second conductive layer 140B during a manufacturing process. Alternatively, the slit structure 190 may include a source contact structure connected to a source structure.

[0029] The first contact plugs 160 may extend through the second gate structure 140 and may be connected to at least one first conductive layer 120B among the first conductive layers 120B. Each of the first contact plugs 160 may be connected to at least one first conductive layer 120B among the first conductive layers 120B. The heights of the first contact plugs 160 may be substantially the same. The top surfaces of the first contact plugs 160 may be located at substantially the same level as the top surface of the channel structure CH.

[0030] The first contact plug 160 may be located in the first contact region CTR1 and the second contact region CTR2. The first contact plug 160 may extend through the first interlayer insulating layer IL1 and may be connected to at least one of the first conductive layers 120B. The first interlayer insulating layer IL1 may be located between the first gate structure 120 and the second gate structure 140. The first contact plug 160 may include a conductive material such as tungsten. The first interlayer insulating layer IL1 may include an insulating material such as oxide.

[0031] In some embodiments, the first contact plug 160 may be connected to at least one of the first conductive layers 120B and may form a single layer. However, the present disclosure is not limited thereto, and the first contact plug 160 and the first conductive layer 120B may be layers formed by separate processes. Now referring to Figure 1B , the first contact plug 160 and the first conductive layer 120B may be layers formed by separate processes. An interface may exist between the first contact plug 160 and the first conductive layer 120B. However, depending on various parameters of the deposition method(s) used to form the first contact plug 160 and the first conductive layer 120B, the material(s) used, the interface therebetween may not be easily identified or may not be identified at all. Now referring to Figure 1C and Figure 1D , the first contact plug 160 and the first conductive layer 120B may be connected and may form a single layer.

[0032] The insulating spacer 150 may cover the sidewall of the first contact plug 160. The insulating spacer 150 may electrically isolate the first contact plug 160 from the second gate structure 140. Since the first contact plug 160 extends through the second gate structure 140 and is connected to at least one of the first conductive layers 120B of the first gate structure 120, it is necessary to electrically isolate the first contact plug 160 from the second conductive layer 140B. Therefore, the insulating spacer 150 may be located between the first contact plug 160 and the second gate structure 140 to electrically isolate (or insulate) the first contact plug 160 from the second gate structure 140. The insulating spacer 150 may include an insulating material such as an oxide.

[0033] The second contact plugs 170 may be located above or on the second gate structure 140 and may be connected to at least one second conductive layer 140B among the second conductive layers 140B. Each of the second contact plugs 170 may be connected to at least one second conductive layer 140B among the second conductive layers 140B. The heights of the second contact plugs 170 may be substantially the same.

[0034] The second contact plug 170 may be located in the first contact region CTR1 and the second contact region CTR2. The second contact plug 170 may be adjacent to the first contact plug 160 in a second direction II intersecting the first direction I and the third direction III. This is because the first contact plug 160 and the second contact plug 170 are located in an overlapping region of the first gate structure 120 and the second gate structure 140. For example, the second direction II may mean a horizontal direction intersecting the first direction I on the same plane as the first direction I. The second contact plug 170 may extend through the second interlayer insulating layer IL2 and may be connected to at least one of the second conductive layers 140B. For example, the second interlayer insulating layer IL2 may be located above the second gate structure 140 or on the second gate structure 140. The second contact plug 170 may include a conductive material such as tungsten. The second interlayer insulating layer IL2 may include an insulating material such as an oxide.

[0035] The second contact plug 170 may be connected to at least one of the second conductive layers 140B and may form a single layer. However, the present disclosure is not limited thereto, and the second contact plug 170 and the second conductive layer 140B may be layers formed by separate processes. Now referring to Figure 1B and Figure 1C , the second contact plug 170 and the second conductive layer 140B may be layers formed by separate processes. An interface may exist between the second contact plug 170 and the second conductive layer 140B. However, depending on the (one or more) materials and (one or more) deposition methods used to form the second contact plug 170 and the second conductive layer 140B, their interface may not be easily identified or may not be identified at all. Now referring to Figure 1D , the second contact plug 170 and the second conductive layer 140B may be connected and may form a single layer.

[0036] The third contact plug 180 may be located above or on the first contact plug 160 and may be connected to the first contact plug 160. Each of the third contact plugs 180 may be connected to at least one first contact plug 160 among the first contact plugs 160. The heights of the third contact plugs 180 may be substantially the same. The top surface of the third contact plug 180 may be located at substantially the same level as the top surface of the second contact plug 170. The third contact plug 180 may be located in the first contact region CTR1 and the second contact region CTR2. The third contact plug 180 may be adjacent to the second contact plug 170 in the second direction II. The third contact plug 180 may extend through the second interlayer insulating layer IL2 and may be connected to the first contact plug 160.

[0037] The third contact plug 180 may be connected to at least one of the first conductive layers 120B and the first contact plug 160, and may form a single layer. However, the present disclosure is not limited thereto, and the third contact plug 180, the first conductive layer 120B, and the first contact plug 160 may be layers formed by separate processes. Now, referring to Figure 1B and Figure 1C , the third contact plug 180, the first conductive layer 120B, and the first contact plug 160 may be layers formed by separate processes. However, depending on the (one or more) materials and (one or more) deposition methods used to make the third contact plug 180, the first conductive layer 120B, and the first contact plug 160, the interface may not be easily identified or not be identified at all. Now referring to Figure 1D , the third contact plug 180 , the first conductive layer 120B, and the first contact plug 160 may be connected and may form a single layer.

[0038] The channel contact plug CHCT may be located above or on the channel structure CH. The channel contact plug CHCT may extend through the second interlayer insulating layer IL2 and may be connected to the channel structure CH. A top surface of the channel contact plug CHCT may be located at substantially the same level as a top surface of the second contact plug 170 and a top surface of the third contact plug 180. The channel contact plug CHCT may include a conductive material such as tungsten.

[0039] According to the structure as described above, the first gate structure 120 and the second gate structure 140 may overlap each other. Therefore, the area occupied by the first gate structure 120 and the second gate structure 140 in the semiconductor device may be reduced, and the integration degree of the semiconductor device may be improved.

[0040] The first contact plug 160 connected to at least one of the first conductive layers 120B of the first gate structure 120 may extend through the second gate structure 140. For example, in order to prevent electrical connection between the second conductive layer 140B of the second gate structure 140 and the first contact plug 160, an insulating spacer 150 may be formed to surround a sidewall of the first contact plug 160.

[0041] The first contact plug 160 and the first conductive layer 120B may be connected and may form a single layer. Alternatively, the first contact plug 160, the first conductive layer 120B, and the third contact plug 180 may be connected and may form a single layer. Alternatively, the second contact plug 170 and the second conductive layer 140B may be connected and may form a single layer. By forming the first contact plug 160, the second contact plug 170, the third contact plug 180, the first conductive layer 120B, or the second conductive layer 140B in a single operation, process time, cost, and complexity may be significantly reduced.

[0042] FIG. 2A to FIG. 2D is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2A is a plan view, and FIG. 2B to FIG. 2D yes Figure 2A Hereinafter, any contents repeated with those previously described may be omitted.

[0043] Reference now FIG. 2A to FIG. 2D The semiconductor device may include a first support 210, a first gate structure 220, a second support 230, a second gate structure 240, a first contact plug 260, a second contact plug 270, a third contact plug 280, or a slit structure 290, or may include a combination thereof. The semiconductor device may further include a channel contact plug CHCT, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, or a channel structure CH, or may further include a combination thereof.

[0044] The first support 210 may include a first inclined surface 210A, and the second support 230 may include a second inclined surface 230A. For example, the second support 230 may be located above the first support 210 or on the first support 210. The first inclined surface 210A and the second inclined surface 230A may have an acute inclination angle. An acute angle means an angle between 0 and 90 degrees. For example, the acute angle may be about 60 degrees. The first support 210 and the second support 230 may include an insulating material such as an oxide.

[0045] The first gate structure 220 may be located above or on the first support 210, and may include first insulating layers 220A and first conductive layers 220B alternately stacked along the first inclined surface 210A. The first gate structure 220 may include a first cell region CR1 and a first contact region CTR1 extending along the first inclined surface 210A, in which the first conductive layer 220B extends in the first direction I. In the first contact region CTR1, top surfaces of the first conductive layers 220B may be located at substantially the same level.

[0046] The second gate structure 240 may be located above or on the second support 230, and may include a second insulating layer 240A and a second conductive layer 240B alternately stacked along the second inclined surface 230A. The second gate structure 240 may include a second cell region CR2 and a second contact region CTR2 extending along the second inclined surface 230A, in which the second conductive layer 240B extends in the first direction I. In the second contact region CTR2, top surfaces of the second conductive layers 240B may be located at substantially the same level.

[0047] The first gate structure 220 and the second gate structure 240 may overlap each other. For example, in a third direction III intersecting the first direction I, the first cell region CR1 may overlap with the second cell region CR2 and the second contact region CTR2. The first contact region CTR1 may not overlap with the second cell region CR2 and the second contact region CTR2. For example, the first direction I may be a horizontal direction in which the first conductive layer 220B extends, and the third direction III may be a vertical direction in which the first conductive layer 220B is stacked. However, the present disclosure is not limited thereto, and the first contact region CTR1 and the second contact region CTR2 may not overlap with each other.

[0048] The first contact plug 260 may extend through the second support 230 and may be connected to at least one of the first conductive layers 220B. The heights of the first contact plugs 260 may be substantially the same. The top surfaces of the first contact plugs 260 may be located at substantially the same level as the top surfaces of the channel structures CH. The first contact plugs 260 may be located in the first contact region CTR1. Since the first contact plugs 260 extend through the second support 230, a separate insulating spacer is not required. The first contact plugs 260 may include a conductive material such as tungsten.

[0049] The second contact plug 270 may be connected to at least one of the second conductive layers 240B. The heights of the second contact plugs 270 may be substantially the same. The second contact plug 270 may be located in the second contact region CTR2. The second contact plug 270 may be spaced apart from the first contact plug 260 in the first direction I. For example, the second contact plug 270 may be located in the second contact region CTR2, and the first contact plug 260 may be located in the first contact region CTR1 spaced apart from the second contact region CTR2. The second contact plug 270 may include a conductive material such as tungsten.

[0050] The third contact plug 280 may be located above or on the first contact plug 260 and may be connected to the first contact plug 260. The heights of the third contact plugs 280 may be substantially the same. The top surface of the third contact plug 280 may be located at substantially the same level as the top surface of the second contact plug 270. The third contact plug 280 may be spaced apart from the second contact plug 270 in the first direction I. The third contact plug 280 may include a conductive material such as tungsten.

[0051] The first conductive layer 220B, the first contact plug 260, and the third contact plug 280 may be connected and may form a single layer, or may not be connected as a single layer. In addition, the second conductive layer 240B and the second contact plug 270 may be connected and may form a single layer, or may not be connected as a single layer. Now, referring to Figure 2B , the first conductive layer 220B, the first contact plug 260, and the third contact plug 280 may be layers formed by separate processes. The second conductive layer 240B and the second contact plug 270 may be formed by separate processes. Figure 2C , the first conductive layer 220B and the first contact plug 260 may be connected and may form a single layer. The third contact plug 280 may be a layer formed by a process separate from the process of the first conductive layer 220B and the first contact plug 260. The second conductive layer 240B and the second contact plug 270 may be layers formed by separate processes. Figure 2D , the first conductive layer 220B, the first contact plug 260, and the third contact plug 280 may be connected and may form a single layer. The second conductive layer 240B and the second contact plug 270 may be connected and may form a single layer. However, in FIG. 2B to FIG. 2D In such cases, depending on the material(s) and deposition method(s) used to make the first conductive layer 220B, the second conductive layer 240B, the first contact plug 260, the second contact plug 270, and the third contact plug 280, the interface may not be easily identifiable or may not be identifiable at all.

[0052] According to the above structure, the first contact region CTR1 of the first gate structure 220 and the second contact region CTR2 of the second gate structure 240 may not overlap each other. Therefore, the first contact plug 260 and the third contact plug 280 may be located in the first contact region CTR1, and the second contact plug 270 may be located in the second contact region CTR2 spaced apart from the first contact region CTR1 in the first direction I.

[0053] The first contact plug 260, the first conductive layer 220B, and the third contact plug 280 may be connected and may form a single layer. Alternatively, the second contact plug 270 and the second conductive layer 240B may be connected and may form a single layer. By forming the first conductive layer 220B, the first contact plug 260, or the third contact plug 280, or forming the second conductive layer 240B or the second contact plug 270 in a single operation, the process time, cost, and complexity may be significantly reduced.

[0054] FIG. 3A to FIG. 10B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A and Fig. 10A is a plan view, and Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B is an AA' cross-sectional view of each A view. Hereinafter, any contents repeated with the previously described contents may be omitted.

[0055] Reference now Figure 3A and Figure 3B , a first support member 310 including a first inclined surface 310A may be formed. The first inclined surface 310A may have an acute angle of inclination. An acute angle means an angle between 0 degrees and 90 degrees. For example, the acute angle may be about 60 degrees. The first support member 310 may include an insulating material such as an oxide.

[0056] The first stack 320 may be formed by alternately stacking a first material layer 320A and a second material layer 320B on the first support 310. The first stack 320 may include a first cell region CR1, in which the second material layer 320B extends in the first direction I, and a first contact region CTR1, in which the second material layer 320B extends along the first inclined surface 310A. For example, the first material layer 320A may include an insulating material such as an oxide, and the second material layer 320B may include a sacrificial material such as a nitride. Subsequently, the first stack 320 may be etched to be located at substantially the same level as the top surface of the first support 310. Therefore, the top surface of the second material layer 320B of the first contact region CTR1 may be exposed at substantially the same level. Subsequently, a first interlayer insulating layer IL11 may be formed on the first stack 320. The first interlayer insulating layer IL11 may include an insulating material such as an oxide.

[0057] A channel sacrificial layer CHS may be formed in the first stack 320. The channel sacrificial layer CHS may extend through the first interlayer insulating layer IL11 and may be formed in the first stack 320. The channel sacrificial layer CHS may be formed in the first cell region CR1. The channel sacrificial layer CHS may include a material having an etching selectivity with respect to the first material layer 320A and the second material layer 320B. For example, the channel sacrificial layer CHS may include tungsten, titanium nitride, SiCN, etc.

[0058] Subsequently, a second support member 330 including a second inclined surface 330A may be formed on the first support member 310. The second inclined surface 330A may have substantially the same inclination angle as the first inclined surface 310A. For example, the second inclined surface 330A may have an acute inclination angle. The second support member 330 may include an insulating material such as oxide.

[0059] The second stack 340 may be formed by alternately stacking the third material layer 340A and the fourth material layer 340B on the second support 330. The second stack 340 may include a second cell region CR2 and a second contact region CTR2, in which the fourth material layer 340B extends in the first direction I, and in which the fourth material layer 340B extends along the second inclined surface 330A. For example, the third material layer 340A may include an insulating material such as an oxide, and the fourth material layer 340B may include a sacrificial material such as a nitride. Subsequently, the second stack 340 may be etched to be located at substantially the same level as the top surface of the second support 330. Therefore, the top surface of the fourth material layer 340B of the second contact region CTR2 may be exposed at substantially the same level. Subsequently, a second interlayer insulating layer IL21 may be formed on the second stack 340. The second interlayer insulating layer IL21 may include an insulating material such as an oxide.

[0060] The first stack 320 and the second stack 340 may overlap each other. For example, in a third direction III intersecting the first direction I, the first unit region CR1 and the second unit region CR2 may overlap each other. In addition, in the third direction III, the first contact region CTR1 and the second contact region CTR2 may overlap each other. For example, the first direction I may be a horizontal direction in which the second material layer 320B extends, and the third direction III may be a vertical direction in which the second material layer 320B is stacked. However, the present disclosure is not limited thereto, and the first unit region CR1 and the second contact region CTR2 may partially overlap, and the second unit region CR2 and the first contact region CTR1 may not overlap each other. By overlapping the first unit region CR1 and the second unit region CR2 and overlapping the first contact region CTR1 and the second contact region CTR2, the area occupied by the first gate structure 120 and the second gate structure 140 in the semiconductor device can be reduced. Therefore, the degree of integration of the semiconductor device can be improved.

[0061] For reference, before forming the second stack 340, an additional first interlayer insulating layer IL12 may be formed on the first interlayer insulating layer IL11. The additional first interlayer insulating layer IL12 may include an insulating material such as oxide.

[0062] Reference now Figure 4A and Figure 4B , a channel opening CHH exposing the channel sacrificial layer CHS may be formed in the second stack 340. For example, the channel opening CHH may be formed in the second stack 340 through the second interlayer insulating layer IL21.

[0063] A first contact opening CTH1 exposing at least one second material layer 320B among the second material layers 320B may be formed in the second stack 340. The first contact opening CTH1 may also be formed in the first contact region CTR1 and the second contact region CTR2. When the channel opening CHH is formed, the first contact opening CTH1 may also be formed. Therefore, by unifying the process to simultaneously form the channel opening CHH and the first contact opening CTH1, the process time, cost, and complexity may be significantly reduced.

[0064] Reference now Figure 5A and Figure 5B , a first mask pattern M1 may be formed on the second stack 340. For example, a first mask pattern M1 covering the channel opening CHH and exposing the first contact opening CTH1 may also be formed. For example, the first mask pattern M1 may at least partially fill the channel opening CHH.

[0065] Subsequently, a preliminary insulating spacer 350A may be formed in the first contact opening CTH1. For example, the preliminary insulating spacer 350A may be formed in a state of exposing the channel opening CHH. The preliminary insulating spacer 350A may be conformally formed in the first contact opening CTH1. The preliminary insulating spacer 350A may include an insulating material such as oxide.

[0066] Subsequently, a contact sacrificial layer CTS may be formed in the first contact opening CTH1. The contact sacrificial layer CTS may be formed to fill the first contact opening CTH1. The contact sacrificial layer CTS may include a material having an etching selectivity with respect to the second material layer 320B. For example, the contact sacrificial layer CTS may include SiCN or the like.

[0067] Reference now Fig. 6A and Figure 6B , a second mask pattern M2 may be formed on the second stack 340. Before forming the second mask pattern M2, the first mask pattern M1 may be removed. The second mask pattern M2 may cover the contact sacrificial layer CTS and expose the channel opening CHH. Subsequently, the channel sacrificial layer CHS may be removed through the channel opening CHH to extend the channel opening CHH.

[0068] Reference now Fig. 7A and Figure 7B , a channel structure CH may be formed in the channel opening CHH. The channel structure CH may include a channel layer CHA. The channel structure CH may include a memory layer CHB surrounding the channel layer CHA and an insulating core CHC in the channel layer CHA. Subsequently, the second mask pattern M2 may be removed.

[0069] Subsequently, slits SL extending through the second stack 340 and the first stack 320 may be formed. The slits SL may extend in the first direction I. Subsequently, a recess R may be formed by removing the second material layer 320B and the fourth material layer 340B through the slits SL.

[0070] For reference, before forming the slits SL, an additional second interlayer insulating layer IL22 may be formed. The additional second interlayer insulating layer IL22 may cover the channel structure CH and the contact sacrificial layer CTS. The additional second interlayer insulating layer IL22 may include an insulating material such as oxide.

[0071] Reference now Fig. 8A and Figure 8B , fifth material layers 320C and 340C may be formed in the recess R. Thus, a first gate structure 320G including alternately stacked first material layers 320A and fifth material layers 320C may be formed. A second gate structure 340G including alternately stacked third material layers 340A and fifth material layers 340C may be formed. For example, the fifth material layers 320C and 340C may be used as gate lines of the gate structures 320G and 340G, and may include a conductive material such as tungsten.

[0072] A slit structure 390 may be formed in the slit SL. The slit structure 390 may be an insulating layer including an insulating material such as an oxide. Alternatively, the slit structure 390 may include a source contact structure connected to the source structure. For reference, the first interlayer insulating layer IL11 and the additional first interlayer insulating layer IL12 may be used as the first interlayer insulating layer IL1, and the second interlayer insulating layer IL21 and the additional second interlayer insulating layer IL22 may be used as the second interlayer insulating layer IL2.

[0073] Reference now Fig. 9A and Fig. 9B , a third contact opening CTH3 exposing the contact sacrificial layer CTS may be formed. For example, the third contact opening CTH3 extending through the second interlayer insulating layer IL2 and exposing the contact sacrificial layer CTS may be formed.

[0074] The second contact opening CTH2 exposing at least one fifth material layer 340C among the fifth material layers 340C of the second gate structure 340G may be exposed. When the second contact opening CTH2 is formed, the third contact opening CTH3 may also be formed.

[0075] A channel contact opening CHCTH exposing the channel structure CH may be formed. For example, a channel contact opening CHCTH exposing the channel layer CHA may be formed. The channel contact opening CHCTH may be formed when the third contact opening CTH3 or the second contact opening CTH2 is formed. Therefore, by forming the second contact opening CTH2, the third contact opening CTH3, or the channel contact opening CHCTH in a single operation, process time and process cost may be reduced.

[0076] Subsequently, the contact sacrificial layer CTS may be removed through the third contact opening CTH3. The first contact opening CTH1 may be reopened by removing the contact sacrificial layer CTS. Subsequently, at least one fifth material layer 320C among the fifth material layers 320C of the first gate structure 320G may be exposed by removing the preliminary insulating spacer 350A formed on the lower surface of the first contact opening CTH1. Thus, an insulating spacer 350 may be formed.

[0077] Reference now Fig. 10A and Fig. 10B , a first contact plug 360 may be formed in the first contact opening CTH1. A third contact plug 380 may be formed in the third contact opening CTH3. When the first contact plug 360 is formed, the third contact plug 380 may also be formed. For example, the first contact plug 360 or the third contact plug 380 may include a conductive material such as tungsten.

[0078] The second contact plug 370 may be formed in the second contact opening CTH2. The channel contact plug CHCT may be formed in the channel contact opening CHCTH. When the first contact plug 360 is formed, the second contact plug 370 or the channel contact plug CHCT may also be formed. Therefore, by forming the first contact plug 360, the second contact plug 370, the third contact plug 380, or the channel contact plug CHCT in a single operation, the process time and the process cost may be reduced.

[0079] According to the manufacturing method as described above, the first contact region CTR1 of the first gate structure 320G and the second contact region CTR2 of the second gate structure 340G may overlap each other. In addition, a first contact plug 360 extending through the second contact region CTR2 of the second gate structure 340G may be formed. Therefore, the area occupied by the first gate structure 320G and the second gate structure 340G in the semiconductor device may be reduced, and the degree of integration of the semiconductor device may be improved.

[0080] When forming the channel opening CHH, the first contact opening CTH1 may also be formed. Furthermore, when forming the second contact opening CTH2, the third contact opening CTH3 may also be formed. Furthermore, when forming the first contact plug 360, the second contact plug 370 and the third contact plug 380 may also be formed. Therefore, by unifying the above process operations, the process time, cost and complexity may be significantly reduced.

[0081] FIG. 11A to FIG. 17B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17A is a plan view, and Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B and Fig. 17B is an AA' cross-sectional view of each A view. Hereinafter, any contents repeated with the previously described contents may be omitted.

[0082] Reference now Fig.11A and Fig. 11B , a first support member 410 including a first inclined surface 410A may be formed. The first inclined surface 410A may have an acute inclination angle. The first support member 410 may include an insulating material such as oxide.

[0083] The first stack 420 may be formed by alternately stacking first material layers 420A and second material layers 420B on the first support 410. For example, the first material layers 420A may include an insulating material such as an oxide, and the second material layers 420B may include a sacrificial material such as a nitride. Subsequently, a first interlayer insulating layer IL11 may be formed on the first stack 420. The first interlayer insulating layer IL11 may include an insulating material such as an oxide.

[0084] A channel sacrificial layer CHS may be formed in the first stack 420. The channel sacrificial layer CHS may extend through the first interlayer insulating layer IL11 and may be formed in the first stack 420. The channel sacrificial layer CHS may include a material having an etching selectivity with respect to the first material layer 420A and the second material layer 420B. For example, the channel sacrificial layer CHS may include tungsten, titanium nitride, SiCN, etc.

[0085] Subsequently, the second support member 430 including the second inclined surface 430A may be formed on the first support member 410. The second inclined surface 430A may have an acute inclination angle. The second support member 410 may include an insulating material such as oxide.

[0086] The second stack 440 may be formed by alternately stacking a third material layer 440A and a fourth material layer 440B on the second support member 430. Before forming the second stack 440, an additional first interlayer insulating layer IL12 may be formed on the first interlayer insulating layer IL11. The third material layer 440A may include an insulating material such as an oxide, and the fourth material layer 440B may include a sacrificial material such as a nitride. Subsequently, a second interlayer insulating layer IL21 may be formed on the second stack 440. The second interlayer insulating layer IL21 may include an insulating material such as an oxide.

[0087] Subsequently, a channel opening CHH exposing the channel sacrificial layer CHS may be formed in the second stack 440. A first contact opening CTH1 exposing at least one second material layer 420B among the second material layers 420B may be formed in the second stack 440. When forming the channel opening CHH, the first contact opening CTH1 may also be formed.

[0088] refer to Fig. 12A and Fig. 12B , a first mask pattern M1 may be formed on the second stack 440. For example, a first mask pattern M1 covering the channel opening CHH and exposing the first contact opening CTH1 may also be formed. Subsequently, a preliminary insulating spacer (not shown) may be formed in the first contact opening CTH1. The preliminary insulating spacer may be conformally formed in the first contact opening CTH1. Subsequently, at least one of the second material layers 420B may be exposed by removing the preliminary insulating spacer formed on the lower surface of the first contact opening CTH1. Thus, an insulating spacer 450 may be formed on the sidewall of the first contact opening CTH1.

[0089] Reference now Fig.13A and Fig. 13B, a contact sacrificial layer CTS may be formed in the first contact opening CTH1. The contact sacrificial layer CTS may be formed to fill the first contact opening CTH1. The contact sacrificial layer CTS may include a material having an etching selectivity relative to the first material layer 420A. The contact sacrificial layer CTS may include a material having an etching rate substantially equal to or similar to that of the second material layer 420B. For example, the contact sacrificial layer CTS may include a material substantially the same as the second material layer 420B. The contact sacrificial layer CTS may be connected to at least one second material layer 420B among the second material layers 420B. This is because the contact sacrificial layer CTS is formed in a state where the lower surface of the first contact opening CTH1 is opened.

[0090] Subsequently, a second mask pattern M2 may be formed on the second stack 440. Before forming the second mask pattern M2, the first mask pattern M1 may be removed. The second mask pattern M2 may cover the contact sacrificial layer CTS and expose the channel opening CHH. Subsequently, the channel sacrificial layer CHS may be removed through the channel opening CHH to extend the channel opening CHH.

[0091] Reference now Fig.14A and Fig. 14B , a channel structure CH may be formed in the channel opening CHH. The channel structure CH may include a channel layer CHA. The channel structure CH may include a memory layer CHB surrounding the channel layer CHA and an insulating core CHC in the channel layer CHA. Subsequently, the second mask pattern M2 may be removed.

[0092] Subsequently, an additional second interlayer insulating layer IL22 may be formed. The additional second interlayer insulating layer IL22 may be used to cover the channel structure CH and the contact sacrificial layer CTS. The additional second interlayer insulating layer IL22 may include an insulating material such as oxide.

[0093] Subsequently, a slit SL extending through the second stack 440 and the first stack 420 may be formed. The slit SL may extend in the first direction I. Subsequently, a recess R may be formed by removing the second material layer 420B and the fourth material layer 440B through the slit SL. The first contact opening CTH1 may be reopened by removing the contact sacrificial layer CTS through the slit SL. Because the second material layer 420B, the fourth material layer 440B, and the contact sacrificial layer CTS include substantially the same material, the second material layer 420B, the fourth material layer 440B, and the contact sacrificial layer CTS may be removed at the same time. That is, the second material layer 420B, the fourth material layer 440B, and the contact sacrificial layer CTS may be removed through the slit SL. For example, at least one recess R among the recesses R and the first contact opening CTH1 may be connected. Because the process of additionally removing the contact sacrificial layer CTS may be omitted, the process time and the process cost may be reduced.

[0094] Reference now Fig.15A and Fig. 15B , the first contact plug 460 may be formed by forming a fifth material layer 420C in the first contact opening CTH1. For example, the fifth material layer 420C may be formed in the first contact opening CTH1 through the slit SL. For example, the fifth material layer 420C may include a conductive material such as tungsten.

[0095] The fifth material layers 420C and 440C may be formed in the recess R. For example, the fifth material layer 420C may be formed in the recess R through the slit SL. Thus, a first gate structure 420G including the first material layers 420A and the fifth material layers 420C alternately stacked may be formed. A second gate structure 440G including the third material layers 440A and the fifth material layers 440C alternately stacked may be formed.

[0096] The recess R and the first contact opening CTH1 connected to the recess R may be filled with the fifth material layers 420C and 440C at the same time. For example, among the fifth material layers 420C and 440C, the fifth material layers 420C and 440C formed in the gate structures 420G and 440G may be used as gate lines, and the fifth material layer 420C formed in the first contact opening CTH1 may be used as the first contact plug 460. Therefore, by forming the first contact plug 460 using a process of replacing the second material layer 420B and the fourth material layer 440B with the fifth material layers 420C and 440C, process time and process cost may be reduced.

[0097] A slit structure 490 may be formed in the slit SL. The slit structure 490 may be an insulating layer including an insulating material such as an oxide. Alternatively, the slit structure 490 may include a source contact structure connected to the source structure. For reference, the first interlayer insulating layer IL11 and the additional first interlayer insulating layer IL12 may be defined as a first interlayer insulating layer IL1, and the second interlayer insulating layer IL21 and the additional second interlayer insulating layer IL22 may be defined as a second interlayer insulating layer IL2.

[0098] Reference now Fig.16A and Fig. 16B , a third contact opening CTH3 exposing the first contact plug 460 may be formed. A second contact opening CTH2 exposing at least one fifth material layer 440C among the fifth material layers 440C of the second gate structure 440G may be exposed. A channel contact opening CHCTH exposing the channel structure CH may be formed. When the third contact opening CTH3 or the second contact opening CTH2 is formed, a channel contact opening CHCTH may also be formed.

[0099] Reference now Fig.17A and Fig. 17B , a third contact plug 480 may be formed in the third contact opening CTH3. A second contact plug 470 may be formed in the second contact opening CTH2. A channel contact plug CHCT may be formed in the channel contact opening CHCTH. When forming the third contact plug 480, the second contact plug 470 or the channel contact plug CHCT may also be formed. For example, the second contact plug 470, the third contact plug 480, or the channel contact plug CHCT may include a conductive material such as tungsten.

[0100] According to the manufacturing method as described above, when the gate structures 420G and 440G are formed by forming the fifth material layer 420C in the recess R, the first contact plug 460 may be formed by forming the fifth material layer 420C in the first contact opening CTH1. In addition, when the third contact opening CTH3 is formed, the second contact opening CTH2 may also be formed. Therefore, the process time and process cost may be reduced by unifying the above process operations.

[0101] FIG. 18A to FIG. 22B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig.18A , Fig.19A , Fig. 20A , Fig.21A and Fig.22A is a plan view, and Fig.18B , Fig.19B , Fig. 20B , Fig. 21B and Fig. 22B is an AA' cross-sectional view of each A view. Hereinafter, any contents repeated with the previously described contents may be omitted.

[0102] See now Fig.18A and Fig.18B , a first support member 510 including a first inclined surface 510A may be formed. The first inclined surface 510A may have an acute inclination angle. The first support member 510 may include an insulating material such as oxide.

[0103] The first stack 520 may be formed by alternately stacking first material layers 520A and second material layers 520B on the first support 510. For example, the first material layer 520A may include an insulating material such as an oxide, and the second material layer 520B may include a sacrificial material such as a nitride. Subsequently, a first interlayer insulating layer IL11 may be formed on the first stack 520. The first interlayer insulating layer IL11 may include an insulating material such as an oxide.

[0104] A channel sacrificial layer (not shown) may be formed in the first stack 520. Subsequently, a second support member 530 including a second inclined surface 530A may be formed on the first support member 510. The second inclined surface 530A may have an acute inclination angle. The second support member 530 may include an insulating material such as oxide.

[0105] The second stack 540 may be formed by alternately stacking a third material layer 540A and a fourth material layer 540B on the second support member 530. Before forming the second stack 540, an additional first interlayer insulating layer IL12 may be formed on the first interlayer insulating layer IL11. The third material layer 540A may include an insulating material such as an oxide, and the fourth material layer 540B may include a sacrificial material such as a nitride. Subsequently, a second interlayer insulating layer IL21 may be formed on the second stack 540. The second interlayer insulating layer IL21 may include an insulating material such as an oxide.

[0106] Thereafter, a channel opening CHH exposing the channel sacrificial layer may be formed in the second stack 540. A first contact opening CTH1 exposing at least one second material layer 520B among the second material layers 520B may be formed in the second stack 540. When forming the channel opening CHH, the first contact opening CTH1 may also be formed.

[0107] A first mask pattern (not shown) covering the channel opening CHH and exposing the first contact opening CTH1 may also be formed. Subsequently, a preliminary insulating spacer (not shown) may be formed in the first contact opening CTH1. Subsequently, at least one of the second material layers 520B may be exposed by removing the preliminary insulating spacer formed on the lower surface of the first contact opening CTH1. Thus, the insulating spacer 550 may be formed on the sidewall of the first contact opening CTH1.

[0108] Subsequently, a contact sacrificial layer CTS may be formed in the first contact opening CTH1. The contact sacrificial layer CTS may be formed to fill the first contact opening CTH1. The contact sacrificial layer CTS may include a material substantially the same as the second material layer 520B. Therefore, the contact sacrificial layer CTS may be connected to at least one second material layer 520B among the second material layers 520B.

[0109] Subsequently, a second mask pattern M2 may be formed on the second stack 540. Before forming the second mask pattern M2, the first mask pattern may be removed. The second mask pattern M2 may cover the contact sacrificial layer CTS and expose the channel opening CHH. Subsequently, the channel opening CHH may be extended by removing the channel sacrificial layer through the channel opening CHH.

[0110] Reference now Fig.19A and Fig.19B , a channel structure CH may be formed in the channel opening CHH. The channel structure CH may include a channel layer CHA. The channel structure CH may include a memory layer CHB surrounding the channel layer CHA and an insulating core CHC in the channel layer CHA. Subsequently, the second mask pattern M2 may be removed.

[0111] Subsequently, an additional second interlayer insulating layer IL22 may be formed. The additional second interlayer insulating layer IL22 may cover the channel structure CH and the contact sacrificial layer CTS. The additional second interlayer insulating layer IL22 may include an insulating material such as oxide.

[0112] Reference now Fig. 20A and Fig. 20B , slits SL extending through the second stack 540 and the first stack 520 may be formed. The slits SL may extend in the first direction I.

[0113] A third contact opening CTH3 exposing the contact sacrificial layer CTS may be formed. A second contact opening CTH2 exposing at least one fourth material layer 540B among the fourth material layers 540B may be formed. A channel contact opening CHCTH exposing the channel structure CH may be formed. When the third contact opening CTH3 is formed, the second contact opening CTH2 or the channel contact opening CHCTH may also be formed.

[0114] Reference now Fig.21A and Fig. 21B, the recess R may be formed by removing the second material layer 520B and the fourth material layer 540B through the slit SL. The first contact opening CTH1 may be reopened by removing the contact sacrificial layer CTS through the slit SL. For example, at least one second material layer 520B among the contact sacrificial layer CTS or the second material layer 520B may be removed through the third contact opening CTH3. At least one fourth material layer 540B among the fourth material layer 540B may be removed through the second contact opening CTH2. That is, the second material layer 520B and the contact sacrificial layer CTS may be removed through the slit SL and the third contact opening CTH3. The fourth material layer 540B may be removed through the slit SL and the second contact opening CTH2. At least one recess R among the recesses R, the first contact opening CTH1, and the third contact opening CTH3 may be connected to each other, and at least one recess R among the recesses R and the second contact opening CTH2 may be connected to each other. Therefore, because the second material layer 520B and the contact sacrificial layer CTS can be removed from one end to the other end through the slit SL, and the second material layer 520B and the contact sacrificial layer CTS can be removed from the other end to one end through the third contact opening CTH3, the process time and process cost can be reduced by removing the second material layer 520B and the contact sacrificial layer CTS at a higher speed than the case where the second material layer 520B and the contact sacrificial layer CTS are removed in one direction.

[0115] Reference now Fig.22A and Fig. 22B , the first contact plug 560 may be formed by forming the fifth material layer 520C in the first contact opening CTH1. The third contact plug 580 may be formed by forming the fifth material layer 520C in the third contact opening CTH3. For example, the first contact plug 560 and the third contact plug 580 may be formed by forming the fifth material layer 520C in the first contact opening CTH1 and the third contact opening CTH3 through the slit SL. For example, the fifth material layer 520C may include a conductive material such as tungsten.

[0116] The fifth material layers 520C and 540C may be formed in the recess R. For example, the fifth material layer 520C may be formed in the recess R through the slit SL, the second contact opening CTH2, and the third contact opening CTH3. Thus, a first gate structure 520G including the first material layers 520A and the fifth material layers 520C alternately stacked may be formed. A second gate structure 540G including the third material layers 540A and the fifth material layers 540C alternately stacked may be formed.

[0117] The second contact plug 570 may be formed in the second contact opening CTH2. The channel contact plug CHCT may be formed in the channel contact opening CHCTH. When the first contact plug 560 or the third contact plug 580 is formed, the second contact plug 570 or the channel contact plug CHCT may also be formed.

[0118] The recess R, the first contact opening CTH1 connected to the recess R, the third contact opening CTH3 connected to the first contact opening CTH1, and the second contact opening CTH2 connected to the recess R may be simultaneously filled with fifth material layers 520C and 540C. Among the fifth material layers 520C and 540C, the fifth material layers 520C and 540C formed in the gate structures 520G and 540G may be used as gate lines, the fifth material layer 520C formed in the first contact opening CTH1 may be used as a first contact plug 560, and the fifth material layer 520C formed in the third contact opening CTH3 may be used as a third contact plug 580. The fifth material layer 540C formed in the second contact opening CTH2 may be used as a second contact plug 570.

[0119] A slit structure 590 may be formed in the slit SL. The slit structure 590 may be an insulating layer including an insulating material such as an oxide. Alternatively, the slit structure 590 may include a source contact structure connected to the source structure. For reference, the first interlayer insulating layer IL11 and the additional first interlayer insulating layer IL12 may be defined as a first interlayer insulating layer IL1, and the second interlayer insulating layer IL21 and the additional second interlayer insulating layer IL22 may be defined as a second interlayer insulating layer IL2.

[0120] According to the manufacturing method as described above, the second material layer 520B and the contact sacrificial layer CTS can be removed through the slit SL and the third contact opening CTH3. In addition, the first contact plug 560 can be formed through the slit SL and the third contact opening CTH3. Therefore, since the process can be performed at a higher speed than the case where the process is performed through the slit SL or the third contact opening CTH3, the process time and process cost can be reduced.

[0121] FIG. 23A to FIG. 28B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A and Fig.28A is a plan view, and Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B and Fig.28BIt may be a BB' cross-sectional view of each A view. Hereinafter, any contents repeated with the previously described contents may be omitted.

[0122] Reference now Fig.23A and Fig. 23B , a first support member 610 including a first inclined surface 610A may be formed. The first inclined surface 610A may have an acute inclination angle.

[0123] The first stack 620 may be formed by alternately stacking a first material layer 620A and a second material layer 620B on the first support 610. The first stack 620 may include a first cell region CR1, in which the second material layer 620B extends in the first direction I, and a first contact region CTR1, in which the second material layer 620B extends along the first inclined surface 610A. Subsequently, the first stack 620 may be etched to be located at substantially the same level as the top surface of the first support 610. Therefore, the top surface of the second material layer 620B of the first contact region CTR1 may be exposed at substantially the same level. Subsequently, a first interlayer insulating layer IL11 may be formed on the first stack 620.

[0124] A first channel sacrificial layer CHS1 may be formed in the first stack 620. The first channel sacrificial layer CHS1 may be formed in the first cell region CR1. The first channel sacrificial layer CHS1 may include a material having an etch selectivity with respect to the first material layer 620A and the second material layer 620B.

[0125] Subsequently, the second support member 630 including the second inclined surface 630A may be formed on the first support member 610. The second inclined surface 630A may have substantially the same inclination angle as the first inclined surface 610A.

[0126] The second stack 640 may be formed by alternately stacking the third material layer 640A and the fourth material layer 640B on the second support 630. The second stack 640 may include a second cell region CR2, in which the fourth material layer 640B extends in the first direction I, and a second contact region CTR2, in which the fourth material layer 640B extends along the second inclined surface 630A. Subsequently, the second stack 640 may be etched to be located at substantially the same level as the top surface of the second support 630. Therefore, the top surface of the fourth material layer 640B of the second contact region CTR2 may be exposed at substantially the same level. Subsequently, a second interlayer insulating layer IL21 may be formed on the second stack 640.

[0127] The first stack 620 and the second stack 640 may overlap each other. For example, in a third direction III intersecting the first direction I, the first cell region CR1 may overlap with the second cell region CR2 and the second contact region CTR2. The first contact region CTR1 may not overlap with the second cell region CR2 and the second contact region CTR2. For example, the first direction I may be a horizontal direction in which the second material layer 620B extends, and the third direction III may be a vertical direction in which the second material layer 620B is stacked. However, the present disclosure is not limited thereto, and the first contact region CTR1 and the second contact region CTR2 may not overlap with each other. For reference, before forming the second stack 640, an additional first interlayer insulating layer IL12 may be formed on the first interlayer insulating layer IL11. Subsequently, a second interlayer insulating layer IL21 may be formed on the second stack 640.

[0128] Reference now Fig.24A and Fig. 24B , a channel opening CHH exposing the first channel sacrificial layer CHS1 may be formed in the second stack 640. A first contact opening CTH1 exposing at least one second material layer 620B among the second material layers 620B may be formed in the second support member 630. The first contact opening CTH1 may also be formed in the first contact region CTR1. When the channel opening CHH is formed, the first contact opening CTH1 may also be formed. Therefore, by unifying the process to simultaneously form the channel opening CHH and the first contact opening CTH1, the process time, cost, and complexity may be significantly reduced.

[0129] Reference now Fig.25A and Fig.25B , a second channel sacrificial layer CHS2 may be formed in the channel opening CHH. For example, the second channel sacrificial layer CHS2 may include a material having an etching selectivity relative to the third material layer 640A and the fourth material layer 640B. For example, the second channel sacrificial layer CHS2 may include a material substantially the same as the first channel sacrificial layer CHS1. The second channel sacrificial layer CHS2 may include a sacrificial material such as tungsten.

[0130] A first contact plug 660 may be formed in the first contact opening CTH1. When the second channel sacrificial layer CHS2 is formed, the first contact plug 660 may also be formed. By forming the second channel sacrificial layer CHS2 and the process of forming the first contact plug 660 in a single operation, process time, cost, and complexity may be significantly reduced. Because the first contact plug 660 extends through the second support member 630, a separate insulating spacer is not required. The first contact plug 660 may include a material having an etching selectivity relative to the second material layer 620B. For example, the first contact plug 660 may include a conductive material such as tungsten.

[0131] Reference now Fig.26A and Fig.26B , a second mask pattern M2 may be formed on the second stack 640. The second mask pattern M2 may cover the first contact plug 660 and expose the second channel sacrificial layer CHS2. Subsequently, the channel opening CHH may be reopened by removing the second channel sacrificial layer CHS2 and the first channel sacrificial layer CHS1.

[0132] Reference now Fig.27A and Fig.27B , a channel structure CH may be formed in the channel opening CHH. The channel structure CH may include a channel layer CHA. The channel structure CH may include a memory layer CHB surrounding the channel layer CHA and an insulating core CHC in the channel layer CHA. Subsequently, the second mask pattern M2 may be removed.

[0133] Subsequently, slits SL extending through the second stack 640 and the first stack 620 may be formed. The slits SL may extend in the first direction I. Subsequently, recesses R may be formed by removing the second material layer 620B and the fourth material layer 640B through the slits SL. For reference, before forming the slits SL, an additional second interlayer insulating layer IL22 may be formed.

[0134] The fifth material layers 620C and 640C may be formed in the recess R. Thus, a first gate structure 620G including the first material layers 620A and the fifth material layers 620C alternately stacked may be formed. A second gate structure 640G including the third material layers 640A and the fifth material layers 640C alternately stacked may be formed. For example, at least one fifth material layer 620C among the fifth material layers 620C of the first gate structure 620G may be connected to the first contact plug 660. The fifth material layers 620C and 640C may be used as gate lines of the gate structures 620G and 640G, and may include a conductive material such as tungsten.

[0135] A slit structure 690 may be formed in the slit SL. The slit structure 690 may be an insulating layer including an insulating material such as an oxide. Alternatively, the slit structure 690 may include a source contact structure connected to the source structure. For reference, the first interlayer insulating layer IL11 and the additional first interlayer insulating layer IL12 may be used as the first interlayer insulating layer IL1, and the second interlayer insulating layer IL21 and the additional second interlayer insulating layer IL22 may be used as the second interlayer insulating layer IL2.

[0136] Reference now Fig.28A and Fig.28B, a third contact opening CTH3 exposing the first contact plug 660 may be formed. A second contact opening CTH2 exposing at least one of the fifth material layers 640C of the second gate structure 640G may be exposed. When the second contact opening CTH2 is formed, the third contact opening CTH3 may also be formed. A channel contact opening CHCTH exposing the channel structure CH may be formed. When the third contact opening CTH3 or the second contact opening CTH2 is formed, the channel contact opening CHCTH may also be formed. Therefore, by forming the second contact opening CTH2, the third contact opening CTH3, or the channel contact opening CHCTH in a single operation, process time and process cost may be reduced.

[0137] Subsequently, a third contact plug 680 may be formed in the third contact opening CTH3. The third contact plug 680 may be connected to the first contact plug 660 and may include a conductive material such as tungsten. A second contact plug 670 may be formed in the second contact opening CTH2. The second contact plug 670 may be connected to the fifth material layer 640C and may include a conductive material such as tungsten. A channel contact plug CHCT may be formed in the channel contact opening CHCTH. The channel contact plug CHCT may include a conductive material such as tungsten. When the third contact plug 680 is formed, the second contact plug 670 or the channel contact plug CHCT may also be formed. Therefore, by forming the second contact plug 670, the third contact plug 680, or the channel contact plug CHCT in a single operation, the process time and process cost may be reduced.

[0138] According to the manufacturing method as described above, the first contact region CTR1 of the first gate structure 620G and the second contact region CTR2 of the second gate structure 640G may not overlap each other. Therefore, the first contact plug 660 and the third contact plug 680 may be located in the first contact region CTR1, and the second contact plug 670 may be located in the second contact region CTR2 spaced apart from the first contact region CTR1 in the first direction I.

[0139] When the channel opening CHH is formed, the first contact opening CTH1 may also be formed. In addition, when the second channel sacrificial layer CHS2 is formed, the first contact plug 660 may be formed. When the second contact opening CTH2 is formed, the third contact opening CTH3 may also be formed. In addition, when the second contact plug 670 is formed, the third contact plug 680 may also be formed. Therefore, by unifying the above process operations, the process time and process cost may be reduced.

[0140] FIG. 29A to FIG. 33B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig.29A , Fig. 30A , Fig.31A , Fig.32A and Fig.33A is a plan view, and Fig.29B , Fig. 30B , Fig.31B , Fig.32B and Fig.33B It may be a BB' cross-sectional view of each view A. Hereinafter, any contents repeated with the previously described contents may be omitted.

[0141] See now Fig.29A and Fig.29B , a first support member 710 including a first inclined surface 710A may be formed. The first inclined surface 710A may have an acute inclination angle. A first stack 720 may be formed by alternately stacking first material layers 720A and second material layers 720B on the first support member 710. A channel sacrificial layer CHS may be formed in the first stack 720.

[0142] Subsequently, a second support 730 including a second inclined surface 730A may be formed on the first support 710. The second inclined surface 730A may have an acute inclination angle. The second stack 740 may be formed by alternately stacking third material layers 740A and fourth material layers 740B on the second support 730.

[0143] Channel openings CHH exposing the channel sacrificial layers CHS may be formed in the second stack 740. First contact openings CTH1 exposing at least one second material layer 720B among the second material layers 720B may be formed in the second support 730. When forming the channel openings CHH, the first contact openings CTH1 may also be formed.

[0144] Reference now Fig. 30A and Fig. 30B , a first mask pattern M1 may be formed on the second stack 740. The first mask pattern M1 may cover the channel opening CHH and expose the first contact opening CTH1. Subsequently, a contact sacrificial layer CTS may be formed in the first contact opening CTH1. The contact sacrificial layer CTS may be formed to fill the first contact opening CTH1. The contact sacrificial layer CTS may include a material substantially the same as the second material layer 720B.

[0145] Reference now Fig.31A and Fig.31B , a second mask pattern M2 may be formed on the second stack 740. Before forming the second mask pattern M2, the first mask pattern M1 may be removed. The second mask pattern M2 may cover the contact sacrificial layer CTS and expose the channel opening CHH. Subsequently, the channel sacrificial layer CHS may be removed through the channel opening CHH to extend the channel opening CHH.

[0146] Reference now Fig.32A and Fig.32B , a channel structure CH may be formed in the channel opening CHH. The channel structure CH may include a channel layer CHA. The channel structure CH may include a memory layer CHB surrounding the channel layer CHA and an insulating core CHC in the channel layer CHA. Subsequently, the second mask pattern M2 may be removed.

[0147] Subsequently, a slit SL extending through the second stack 740 and the first stack 720 may be formed. Subsequently, a recess R may be formed by removing the second material layer 720B and the fourth material layer 740B through the slit SL. The first contact opening CTH1 may be reopened by removing the contact sacrificial layer CTS through the slit SL. Because the second material layer 720B, the fourth material layer 740B, and the contact sacrificial layer CTS include substantially the same material, the second material layer 720B, the fourth material layer 740B, and the contact sacrificial layer CTS may be removed at the same time. That is, the second material layer 720B, the fourth material layer 740B, and the contact sacrificial layer CTS may be removed through the slit SL.

[0148] Subsequently, the first contact plug 760 may be formed by forming a fifth material layer 720C in the first contact opening CTH1. For example, the fifth material layer 720C may be formed in the first contact opening CTH1 through the slit SL. For example, the fifth material layer 720C may include a conductive material such as tungsten.

[0149] The fifth material layers 720C and 740C may be formed in the recess R. For example, the fifth material layer 720C may be formed in the recess R through the slit SL. Thus, a first gate structure 720G including the first material layers 720A and the fifth material layers 720C alternately stacked may be formed. A second gate structure 740G including the third material layers 740A and the fifth material layers 740C alternately stacked may be formed.

[0150] The recess R and the first contact opening CTH1 connected to the recess R may be simultaneously filled with the fifth material layers 720C and 740C. For example, among the fifth material layers 720C and 740C, the fifth material layers 720C and 740C formed in the gate structures 720G and 740G may be used as gate lines, and the fifth material layer 720C formed in the first contact opening CTH1 may be used as the first contact plug 760. Therefore, by forming the first contact plug 760 using a process of replacing the second material layer 720B and the fourth material layer 740B with the fifth material layers 720C and 740C, process time and process cost may be reduced.

[0151] A slit structure 790 may be formed in the slit SL. The slit structure 790 may be an insulating layer including an insulating material such as oxide. Alternatively, the slit structure 490 may include a source contact structure connected to a source structure.

[0152] Reference now Fig.33A and Fig.33B , a third contact plug 780 connected to the first contact plug 760 may be formed. A second contact plug 770 connected to at least one fifth material layer 740C among the fifth material layers 740C of the second gate structure 740G may be formed. A channel contact plug CHCT connected to the channel structure CH may be formed. When the third contact plug 780 is formed, the second contact plug 770 or the channel contact plug CHCT may also be formed.

[0153] According to the manufacturing method as described above, when the gate structures 720G and 740G are formed by forming the fifth material layers 720C and 740C in the recess R, the first contact plug 760 may be formed by forming the fifth material layer 720C in the first contact opening CTH1. Therefore, by unifying the above process operations, the process time and process cost may be reduced.

[0154] FIG. 34A to FIG. 36B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig.34A , Fig.35A and Fig.36A is a plan view, and Fig.34B , Fig.35B and Fig.36B It may be a BB' cross-sectional view of each A view. Hereinafter, any contents repeated with the previously described contents may be omitted.

[0155] Reference now Fig.34A and Fig.34B , a first support member 810 including a first inclined surface 810A may be formed. The first inclined surface 810A may have an acute angle of inclination. The first stack 820 may be formed by alternately stacking a first material layer 820A and a second material layer 820B on the first support member 810. A channel sacrificial layer (not shown) may be formed in the first stack 820. Subsequently, a second support member 830 including a second inclined surface 830A may be formed on the first support member 810. The second inclined surface 830A may have an acute angle of inclination. The second stack 840 may be formed by alternately stacking a third material layer 840A and a fourth material layer 840B on the second support member 830.

[0156] Thereafter, a channel opening CHH exposing the channel sacrificial layer CHS may be formed in the second stack 840. A first contact opening (not shown) exposing at least one second material layer 820B among the second material layers 820B may be formed in the second support member 830. When the channel opening CHH is formed, a first contact opening may be formed.

[0157] Subsequently, a first mask pattern (not shown) may be formed on the second stack 840. The first mask pattern M1 may cover the channel opening CHH and expose the first contact opening. Subsequently, a contact sacrificial layer CTS may be formed in the first contact opening. The contact sacrificial layer CTS may include a material substantially the same as the second material layer 820B.

[0158] Subsequently, a second mask pattern M2 may be formed on the second stack 840. Before forming the second mask pattern M2, the first mask pattern may be removed. The second mask pattern M2 may cover the contact sacrificial layer CTS and expose the channel opening CHH. Subsequently, the channel sacrificial layer CHS may be removed through the channel opening CHH to extend the channel opening CHH.

[0159] Reference now Fig.35A and Fig.35B , a channel structure CH may be formed in the channel opening CHH. Subsequently, the second mask pattern M2 may be removed. Subsequently, a slit SL extending through the second stack 840 and the first stack 820 may be formed.

[0160] A third contact opening CTH3 exposing the contact sacrificial layer CTS may be formed. A second contact opening CTH2 exposing at least one fourth material layer 840B among the fourth material layers 840B may be formed. A channel contact opening CHCTH exposing the channel structure CH may be formed. When the third contact opening CTH3 is formed, the second contact opening CTH2 or the channel contact opening CTH3 may also be formed.

[0161] Thereafter, the recess R may be formed by removing the second material layer 820B and the fourth material layer 840B through the slit SL. The first contact opening CTH1 may be reopened by removing the contact sacrificial layer CTS through the slit SL. For example, at least one second material layer 820B among the contact sacrificial layer CTS or the second material layer 820B may be removed through the third contact opening CTH3. At least one fourth material layer 840B among the fourth material layer 840B may be removed through the second contact opening CTH2. The second material layer 820B and the contact sacrificial layer CTS may be removed through the slit SL and the third contact opening CTH3. The fourth material layer 840B may be removed through the slit SL and the second contact opening CTH2. Therefore, because the second material layer 820B and the contact sacrificial layer CTS can be removed from one end to the other end through the slit SL, and the second material layer 820B and the contact sacrificial layer CTS can be removed from the other end to one end through the third contact opening CTH3, the process time and process cost can be reduced by removing the second material layer 820B and the contact sacrificial layer CTS at a higher speed than the case where the second material layer 820B and the contact sacrificial layer CTS are removed in one direction.

[0162] Reference now Fig.36A and Fig.36B , the first contact plug 860 may be formed by forming the fifth material layer 820C in the first contact opening CTH1. The third contact plug 880 may be formed by forming the fifth material layer 820C in the third contact opening CTH3. For example, the first contact plug 860 and the third contact plug 880 may be formed by forming the fifth material layer 820C in the first contact opening CTH1 and the third contact opening CTH3 through the slit SL.

[0163] The fifth material layers 820C and 840C may be formed in the recess R. For example, the fifth material layer 820C may be formed in the recess R through the slit SL, the second contact opening CTH2, and the third contact opening CTH3. Thus, a first gate structure 820G including the first material layers 820A and the fifth material layers 820C alternately stacked may be formed. A second gate structure 840G including the third material layers 840A and the fifth material layers 840C alternately stacked may be formed.

[0164] The second contact plug 870 may be formed in the second contact opening CTH2. The channel contact plug CHCT may be formed in the channel contact opening CHCTH. When the first contact plug 860 or the third contact plug 880 is formed, the second contact plug 870 or the channel contact plug CHCT may also be formed.

[0165] The recess R, the first contact opening CTH1 connected to the recess R, the third contact opening CTH3 connected to the first contact opening CTH1, and the second contact opening CTH2 connected to the recess R may be simultaneously filled with the fifth material layers 820C and 840C. For example, among the fifth material layers 820C and 840C, the fifth material layers 820C and 840C formed in the gate structures 820G and 840G may be used as gate lines, the fifth material layer 820C formed in the first contact opening CTH1 may be used as a first contact plug 860, the fifth material layer 820C formed in the third contact opening CTH3 may be used as a third contact plug 880, and the fifth material layer 840C formed in the second contact opening CTH2 may be used as a second contact plug 870.

[0166] A slit structure 890 may be formed in the slit SL. The slit structure 890 may be an insulating layer including an insulating material such as oxide. Alternatively, the slit structure 890 may include a source contact structure connected to a source structure.

[0167] According to the manufacturing method as described above, the second material layer 820B and the contact sacrificial layer CTS can be removed through the slit SL and the third contact opening CTH3. In addition, the first contact plug 860 can be formed through the slit SL and the third contact opening CTH3. Therefore, since the process can be performed at a higher speed than the speed of the case where the process is performed through the slit SL or the third contact opening CTH3, the process time and process cost can be reduced.

[0168] Although the embodiments according to the technical spirit of the present disclosure have been described with reference to the accompanying drawings, this is only used to describe the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above-mentioned embodiments. Within the scope of the technical spirit of the present disclosure described in the claims, technicians in the field to which the present disclosure belongs will be able to make various forms of replacement, modification and change to the embodiments, and these also belong to the scope of the present disclosure. In addition, the embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: a first support member including a first inclined surface; A first gate structure comprising a first insulating layer and a first conductive layer alternately stacked along the first inclined surface; a second support member located above or on the first support member and comprising a second inclined surface; a second gate structure comprising a second insulating layer and a second conductive layer alternately stacked along the second inclined surface; a first contact plug extending through the second gate structure and connected to at least one first conductive layer among the first conductive layers; as well as A second contact plug is disposed above or on the second gate structure and connected to at least one second conductive layer among the second conductive layers.

2. The semiconductor device according to claim 1, further comprising: An insulating spacer surrounds a sidewall of the first contact plug. 3 . The semiconductor device according to claim 1 , wherein the first conductive layer extends in a first direction, and the first contact plug and the second contact plug are adjacent to each other in a second direction crossing the first direction.

4. The semiconductor device according to claim 1 , wherein the first gate structure comprises a first cell region and a first contact region extending along the first inclined surface, in which the first conductive layer extends in a first direction, wherein the second gate structure comprises a second unit region and a second contact region extending along the second inclined surface, in which the second conductive layer extends in the first direction, and The first contact area and the second contact area overlap in a third direction intersecting the first direction. 5 . The semiconductor device according to claim 4 , wherein in the first contact regions, top surfaces of the first conductive layers are located at substantially the same level. 6 . The semiconductor device according to claim 4 , wherein in the second contact region, top surfaces of the second conductive layers are located at substantially the same level.

7. The semiconductor device according to claim 1, further comprising: a channel structure extending through the second gate structure and the first gate structure; as well as A slit structure extends through the second gate structure and the first gate structure. 8 . The semiconductor device of claim 7 , wherein a top surface of the channel structure is located at substantially the same level as a top surface of the first contact plug. 9 . The semiconductor device according to claim 1 , wherein the first inclined surface and the second inclined surface have an acute inclination angle. 10 . The semiconductor device according to claim 1 , wherein at least one first conductive layer among the first conductive layers and the first contact plug are connected and form a single layer.

11. The semiconductor device according to claim 1, further comprising: A third contact plug is located above or on the first contact plug and is connected to the first contact plug. 12 . The semiconductor device according to claim 11 , wherein at least one first conductive layer among the first conductive layers, the first contact plug, and the third contact plug are connected and form a single layer.

13. A semiconductor device comprising: a first support member including a first inclined surface; A first gate structure comprising a first insulating layer and a first conductive layer alternately stacked along the first inclined surface; a second support member located above or on the first support member and comprising a second inclined surface; a second gate structure comprising a second insulating layer and a second conductive layer alternately stacked along the second inclined surface; a channel structure extending through the second gate structure and the first gate structure; a first contact plug on the first gate structure including a top surface located at substantially the same level as a top surface of the channel structure; as well as A second contact plug is on the second gate structure and connected to at least one second conductive layer among the second conductive layers. 14 . The semiconductor device according to claim 13 , wherein the first contact plug extends through the second gate structure and is connected to at least one first conductive layer among the first conductive layers. 15 . The semiconductor device according to claim 14 , wherein the first contact plug is connected to at least one first conductive layer among the first conductive layers and forms a single layer.

16. The semiconductor device according to claim 14, further comprising: A third contact plug is located above or on the first contact plug and is connected to the first contact plug. 17 . The semiconductor device according to claim 16 , wherein the third contact plug is connected to at least one first conductive layer among the first contact plug and the first conductive layer and forms a single layer. 18 . The semiconductor device according to claim 13 , wherein the first contact plug extends through the second supporter and is connected to at least one first conductive layer among the first conductive layers. 19 . The semiconductor device according to claim 18 , wherein the first contact plug is connected to at least one first conductive layer among the first conductive layers and forms a single layer.

20. The semiconductor device according to claim 18, further comprising: A third contact plug is located above or on the first contact plug and is connected to the first contact plug. 21 . The semiconductor device according to claim 20 , wherein the third contact plug is connected to at least one first conductive layer among the first contact plug and the first conductive layer and forms a single layer.

22. The semiconductor device according to claim 13, wherein the first gate structure comprises a first cell region and a first contact region extending along the first inclined surface, in which the first conductive layer extends in a first direction, The second gate structure includes a second unit region and a second contact region extending along the second inclined surface, and the second conductive layer extends in the first direction in the second unit region. The first contact area and the second contact area overlap in a third direction intersecting the first direction. 23 . The semiconductor device according to claim 22 , wherein in the first contact regions, top surfaces of the first conductive layers are located at substantially the same level. 24 . The semiconductor device according to claim 22 , wherein in the second contact region, top surfaces of the second conductive layers are located at substantially the same level. 25 . The semiconductor device according to claim 13 , wherein the first inclined surface and the second inclined surface have an acute inclination angle.

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