An IGBT device

Abstract

The present invention discloses an IGBT device, comprising at least one IGBT cell and at least one MOSFET cell; the semiconductor substrate comprises a second conductive type collector region and a first conductive type collector region; the MOSFET cell and the IGBT cell share a first conductive type buffer region, a first conductive type drift region and a second conductive type well region; the MOSFET cell also comprises an active region and a second gate structure; the vertical projection of the first conductive type collector region on the semiconductor substrate is located within or at least partially overlaps the vertical projection of the second gate structure on the semiconductor substrate; the source is located on one side of the second conductive type well region of the active region; the size of at least one MOSFET cell in the first direction is smaller than the size of at least one IGBT cell in the first direction, and the first direction is perpendicular to the direction from the first surface to the second surface. The technical solution provided by the embodiment of the present invention effectively reduces the switching loss of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an IGBT device. Background Art

[0002] Insulated gate bipolar transistor (IGBT) devices combine the high input impedance of metal-oxide semiconductor field-effect transistors (MOSFETs) with the low on-resistance characteristics of bipolar transistors.

[0003] IGBT has lower on-resistance at high voltage, but its switching speed is slower than MOSFET. This is because when IGBT is turned off, there is a tail current due to the carrier storage effect, resulting in higher switching losses. Summary of the invention

[0004] The present invention provides an IGBT device to effectively reduce the switching loss of the device.

[0005] An IGBT device provided according to the present invention includes at least one IGBT unit cell and at least one MOSFET unit cell;

[0006] The IGBT unit cell comprises a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface arranged opposite to each other; the semiconductor substrate comprises a collector region of a second conductivity type; the first surface of the semiconductor substrate is provided with a first conductivity type buffer region, a first conductivity type drift region, and a second conductivity type well region in sequence; an emitter region is located on a side of the second conductivity type well region away from the first conductivity type drift region; a first gate structure is located on a side of the emitter region away from the second conductivity type well region or is located and extends from a surface of the emitter region away from the second conductivity type well region to the emitter region; an emitter is located on a side of the emitter region away from the second conductivity type well region; and a collector is located on the second surface of the semiconductor substrate;

[0007] The MOSFET unit cell includes the semiconductor substrate, which includes a first conductive type collector region; the MOSFET unit cell also includes the first conductive type buffer region, the first conductive type drift region and the second conductive type well region; an active region, located on a side of the second conductive type well region away from the first conductive type drift region; a second gate structure, located on a side of the active region away from the second conductive type well region or extending from a surface of the active region away from the second conductive type well region to the active region; a vertical projection of the first conductive type collector region on the semiconductor substrate is located within or at least partially overlaps with the vertical projection of the second gate structure on the semiconductor substrate; a source electrode, located on a side of the second conductive type well region of the active region; the source electrode and the emitter electrode are located on the same layer and are connected; a drain electrode is located on the second surface of the semiconductor substrate; the drain electrode and the collector electrode are located on the same layer and are connected;

[0008] The size of at least one of the MOSFET cells in a first direction is smaller than the size of at least one of the IGBT cells in the first direction, and the first direction is perpendicular to the direction from the first surface to the second surface.

[0009] Optionally, the MOSFET unit cell is located on one side of the IGBT unit cell.

[0010] Optionally, the IGBT unit cell and the MOSFET unit cell are arranged at intervals in the first direction.

[0011] Optionally, at least two of the IGBT cells are arranged continuously in the first direction; and / or at least two of the MOSFET cells are arranged continuously in the first direction.

[0012] Optionally, the MOSFET unit cell is located inside the IGBT unit cell;

[0013] The first gate structure is reused as the second gate structure;

[0014] The first conductive type collector region is located within the second conductive type collector region;

[0015] The emission area is reused as the active area.

[0016] Optionally, the first conductive type collector region includes a plurality of sub-collector regions spaced apart in the first direction, and the second conductive type collector region is located between the sub-collector regions.

[0017] Optionally, a size of each of the MOSFET units in the first direction is smaller than a size of each of the IGBT units in the first direction.

[0018] Optionally, the first gate structure includes a gate oxide layer and a polysilicon layer;

[0019] The second gate structure includes a gate oxide layer and a polysilicon layer.

[0020] Optionally, the second conductive type collector region and the first conductive type collector region are ion implantation regions;

[0021] And / or, at least one of the first conductive type buffer region, the first conductive type drift region, the second conductive type well region, the emitter region, and the active region is an ion implantation region.

[0022] Optionally, the emitter region includes a first sub-region and a second sub-region, the first sub-region is set to a first conductivity type; the second sub-region is set to a second conductivity type;

[0023] And / or, the active region includes a third sub-region and a fourth sub-region, the third sub-region is set to the first conductivity type; the fourth sub-region is set to the second conductivity type.

[0024] The IGBT device provided in the embodiment of the present invention, the MOSFET unit cell adopts a vertical current flow structure, has a lower on-resistance and a higher switching speed, because the structural MOSFET unit cell design of the vertical double-diffused Metal Oxide Semiconductor (VDMOS) device determines that the charge stored inside the device is less, so the switching loss is usually low; combining the characteristics of IGBT and VDMOS, the technical solution provided in the embodiment of the present invention designs an IGBT structure that can effectively reduce switching losses, which not only ensures the unique advantages of IGBT in high voltage and high current applications, but also can significantly reduce switching losses.

[0025] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 It is a structural schematic diagram of an IGBT device provided by an embodiment of the present invention;

[0028] Figure 2 is a schematic structural diagram of another IGBT device provided by an embodiment of the present invention;

[0029] Figure 3 is a structural schematic diagram of another IGBT device provided by an embodiment of the present invention;

[0030] Figure 4 It is a structural schematic diagram of another IGBT device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] In order to effectively reduce the switching loss of the device, the embodiment of the present invention provides the following technical solution:

[0034] like Figure 1 As shown, Figure 11 is a schematic structural diagram of an IGBT device provided by an embodiment of the present invention, the IGBT device comprising: at least one IGBT unit cell 01 and at least one MOSFET unit cell 02; the IGBT unit cell 01 comprises a semiconductor substrate 100, the semiconductor substrate 100 comprises a first surface and a second surface arranged opposite to each other; the semiconductor substrate 100 comprises a second conductive type collector region 101; a first conductive type buffer region 102, a first conductive type drift region 103 and a second conductive type well region 104 are sequentially arranged on the first surface of the semiconductor substrate 100; an emitter region 105 is located on a side of the second conductive type well region 104 away from the first conductive type drift region 103; a first gate structure 106 is located on a side of the emitter region 105 away from the second conductive type well region 104 or is located extending from a surface of the emitter region 105 away from the second conductive type well region 104 to the emitter region 105; an emitter 107 is located on a side of the emitter region 105 away from the second conductive type well region 104; and a collector 108 is located on the second surface of the semiconductor substrate 100.

[0035] The MOSFET unit cell 02 includes a semiconductor substrate 100, the semiconductor substrate 100 includes a first conductive type collector region 201; the MOSFET unit cell 02 also includes a first conductive type buffer region 102, a first conductive type drift region 103 and a second conductive type well region 104; an active region 202 is located on a side of the second conductive type well region 104 away from the first conductive type drift region 103; a second gate structure 203 is located on a side of the active region 202 away from the second conductive type well region 104 or located from the active region 202 The surface away from the second conductive type well region 104 extends into the active area 202; the vertical projection of the first conductive type collector region 201 on the semiconductor substrate 100 is located within or at least partially overlaps with the vertical projection of the second gate structure 203 on the semiconductor substrate 100; the source 204 is located on one side of the second conductive type well region 104 in the active area 202; the source 204 and the emitter 107 are located in the same layer and are connected; the drain 205 is located on the second surface of the semiconductor substrate 100; the drain 205 and the collector 108 are located in the same layer and are connected.

[0036] The size of at least one MOSFET unit cell 02 in the first direction is smaller than the size of at least one IGBT unit cell 01 in the first direction, and the first direction is perpendicular to the direction from the first surface to the second surface.

[0037] The first direction is Figure 1 The X direction in .

[0038] Optionally, Figure 1In the IGBT cell 01, the first gate structure 106 includes a first gate oxide layer 1061 and a first polysilicon layer 1062. In the MOSFET cell 02, the second gate structure 203 includes a second gate oxide layer 2031 and a second polysilicon layer 2032.

[0039] Figure 1 In the embodiment, the first gate structure 106 and the second gate structure 203 are both trench gate structures. In other optional embodiments, the first gate structure 106 may also be a planar gate structure, and the second gate structure 203 may also be a planar gate structure.

[0040] The technical solution provided by the embodiment of the present invention is that the MOSFET unit cell 02 adopts a vertical current flow structure, has a lower on-resistance and a higher switching speed, because the design of the structure of the vertical double-diffused Metal Oxide Semiconductor (Vertical Double-diffused Metal Oxide Semiconductor, VDMOS) unit cell 02 determines that the charge stored inside the device is less, so the switching loss is usually low; combining the characteristics of IGBT and VDMOS, the technical solution provided by the embodiment of the present invention designs an IGBT structure that can effectively reduce switching losses, which not only ensures the unique advantages of IGBT in high voltage and high current applications, but also can significantly reduce switching losses.

[0041] Optionally, based on the above technical solution, Figure 1 and Figure 2 As shown, Figure 2 01 is a schematic diagram of the structure of another IGBT device provided by an embodiment of the present invention, in which a MOSFET unit cell 02 is located on one side of an IGBT unit cell 01.

[0042] Optionally, based on the above technical solution, Figure 2 As shown, at least two IGBT cells 01 are arranged continuously in the first direction; and / or, at least two MOSFET cells 02 are arranged continuously in the first direction.

[0043] For example, Figure 2 2 shows two IGBT cells 01 and one MOSFET cell 02. The two IGBT cells 01 are arranged continuously in a first direction.

[0044] Optionally, based on the above technical solution, Figure 1 As shown, the IGBT unit cell 01 and the MOSFET unit cell 02 are arranged at intervals in the first direction.

[0045] Optionally, based on the above technical solution, Figure 3 As shown, Figure 3It is a structural schematic diagram of another IGBT device provided by an embodiment of the present invention, wherein the MOSFET cell 02 is located inside the IGBT cell 01; the first gate structure 106 is reused as the second gate structure 203; the first conductive type collector region 201 is located inside the second conductive type collector region 101; and the emitter region 105 is reused as the active region 202.

[0046] Specifically, Figure 3 An IGBT device structure is shown in which a MOSFET unit cell 02 is located inside an IGBT unit cell 01, thereby reducing the size of the entire IGBT device structure in a first direction.

[0047] Optionally, based on the above technical solution, Figure 4 As shown, Figure 4 It is a schematic structural diagram of another IGBT device provided by an embodiment of the present invention. The first conductive type collector region 201 includes a plurality of sub-collector regions spaced apart in a first direction, and the second conductive type collector region 101 is located between the sub-collector regions.

[0048] The arrangement of a plurality of sub-collector regions spaced apart in the first direction enables the IGBT device to include a plurality of MOSFET cells 02.

[0049] Optionally, based on the above technical solution, the size of each MOSFET unit cell 02 in the first direction is smaller than the size of each IGBT unit cell 01 in the first direction.

[0050] Specifically, the size of each MOSFET unit cell 02 in the first direction is smaller than the size of each IGBT unit cell 01 in the first direction, which further reduces the size of the IGBT device in the first direction.

[0051] Optionally, based on the above technical solution, Figure 1-Figure 4 As shown, the second conductivity type collector region 101 and the first conductivity type collector region 201 are ion implantation regions; and / or, at least one of the first conductivity type buffer region 102, the first conductivity type drift region 103, the second conductivity type well region 104, the emitter region 105 and the active region 202 is an ion implantation region.

[0052] Specifically, the second conductive type collector region 101 and the first conductive type collector region 201, and at least one of the first conductive type buffer region 102, the first conductive type drift region 103, the second conductive type well region 104, the emitter region 105 and the active region 202 are completed by an ion implantation process, wherein the second conductive type collector region 101 and the first conductive type collector region 201 are completed by performing an ion implantation process on the second surface of the semiconductor substrate 100.

[0053] Optionally, based on the above technical solution, the emission region 105 includes a first sub-region 1051 and a second sub-region 1052, the first sub-region 1051 is set to the first conductivity type; the second sub-region 1052 is set to the second conductivity type; and / or, the active region 202 includes a third sub-region 2021 and a fourth sub-region 2022, the third sub-region 2021 is set to the first conductivity type; the fourth sub-region 2022 is set to the second conductivity type.

[0054] It should be noted that, in the embodiment of the present invention, the second conductivity type is P type, and the first conductivity type is N type. Alternatively, the second conductivity type is N type, and the first conductivity type is P type.

[0055] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0056] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An IGBT device, characterized in that: comprising at least one IGBT unit cell and at least one MOSFET unit cell; The IGBT unit cell comprises a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface arranged opposite to each other; the semiconductor substrate comprises a second conductive type collector region; the first surface of the semiconductor substrate is provided with a first conductive type buffer region, a first conductive type drift region, and a second conductive type well region in sequence; an emitter region is located on a side of the second conductive type well region away from the first conductive type drift region; a first gate structure is located on a side of the emitter region away from the second conductive type well region or is located and extends from a surface of the emitter region away from the second conductive type well region to the emitter region; an emitter electrode, located at a side of the emitter region away from the second conductivity type well region; and a collector electrode, located at a second surface of the semiconductor substrate; The MOSFET unit cell includes the semiconductor substrate, the semiconductor substrate includes a first conductive type collector region; the MOSFET unit cell also includes the first conductive type buffer region, the first conductive type drift region and the second conductive type well region; an active region is located on a side of the second conductive type well region away from the first conductive type drift region; a second gate structure is located on a side of the active region away from the second conductive type well region or is located extending from a surface of the active region away from the second conductive type well region to the active region; a vertical projection of the first conductive type collector region on the semiconductor substrate is located within a vertical projection of the second gate structure on the semiconductor substrate; A source electrode, located at one side of the second conductivity type well region of the active region; The source electrode and the emitter electrode are located in the same layer and connected; The drain is located on the second surface of the semiconductor substrate; the drain and the collector are located in the same layer and connected; The size of at least one of the MOSFET cells in the first direction is smaller than the size of at least one of the IGBT cells in the first direction, and the first direction is perpendicular to the direction from the first surface to the second surface; The MOSFET unit cell is located inside the IGBT unit cell; The first gate structure is reused as the second gate structure; The first conductive type collector region is located within the second conductive type collector region; The emission area is reused as the active area.

2. The IGBT device according to claim 1, characterized in that: The first conductive type collector region includes a plurality of sub-collector regions spaced apart in the first direction, and the second conductive type collector region is located between the sub-collector regions.

3. The IGBT device according to claim 1, characterized in that: The size of each of the MOSFET units in the first direction is smaller than the size of each of the IGBT units in the first direction.

4. The IGBT device according to claim 1, characterized in that: The first gate structure includes a gate oxide layer and a polysilicon layer; The second gate structure includes a gate oxide layer and a polysilicon layer.

5. The IGBT device according to claim 1, characterized in that: The second conductive type collector region and the first conductive type collector region are ion implanted regions; And / or, at least one of the first conductive type buffer region, the first conductive type drift region, the second conductive type well region, the emitter region, and the active region is an ion implantation region.

6. The IGBT device according to claim 1, characterized in that: The emitter region includes a first sub-region and a second sub-region, the first sub-region is set to a first conductivity type; the second sub-region is set to a second conductivity type; And / or, the active region includes a third sub-region and a fourth sub-region, the third sub-region is set to the first conductivity type; the fourth sub-region is set to the second conductivity type.

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