A vertical compact trench gate silicon carbide VDMOS and a preparation method thereof

Abstract

The invention provides a vertical compact trench gate silicon carbide VDMOS and a preparation method thereof, which comprises the following steps: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; ion implanting the drift layer to form a low resistance region, a P-type source region, a P-type well region and an N-type source region; reforming a barrier layer, etching the barrier layer to form a through hole, etching the drift layer and the P-type well region to form a groove, and oxidizing to form an insulating dielectric layer, wherein a groove is provided in the insulating dielectric layer; reforming the barrier layer, etching the barrier layer to form a through hole, depositing metal to form a gate metal layer; reforming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side of the P-type well region, depositing a metal layer to form a source metal layer, removing the barrier layer, and completing the preparation, thereby realizing a compact design of a device gate structure, reducing the device gate thickness, and improving the device power density.

Description

Technical Field

[0001] The invention relates to a vertical compact trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, different fields have different requirements for device performance, and the existing technology has higher and higher requirements for the thickness of silicon carbide VDMOS, which makes the thickness of silicon carbide VDMOS smaller while ensuring higher voltage resistance, lower on-resistance, faster switching speed, higher reliability and lower body diode conduction loss. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a vertical compact trench gate silicon carbide VDMOS and a preparation method thereof, so as to realize a compact design of the device gate structure, reduce the device gate thickness, and improve the power density of the device.

[0004] In a first aspect, the present invention provides a method for preparing a vertical compact trench gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a low resistance region by ion implantation into the drift layer;

[0007] Step 3, forming a barrier layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a P-type source region;

[0008] Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region;

[0009] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer and the P-type well region to form a groove, and oxidize to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a groove;

[0011] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0012] Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the P-type well region, deposit a metal layer to form a source metal layer, remove the barrier layer, and complete the preparation.

[0013] In a second aspect, the present invention provides a vertical compact trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a vertical compact trench gate silicon carbide VDMOS described in the first aspect.

[0014] The advantages of the present invention are:

[0015] 1. The present invention separates the N-type source region and the P-type source region, and allows the P-type source region to be distributed outside the P-type well region of the device, thereby reducing the contact resistance between the source metal and the P-type material of the device body diode and reducing the body diode conduction loss;

[0016] Second, the P-type well region wraps the N-type source region, and at the same time constructs an area directly below the insulating dielectric layer, thereby realizing the electric field protection of the P-type well region at the corner of the insulating dielectric layer and improving the gate reliability of the device;

[0017] 3. The gate structure, P-type well region structure, and N-type low-resistance region structure of the device are designed to be compact in the vertical structure, which can reduce the device thickness from the gate structure;

[0018] Fourth, an N-type low-resistance region is constructed under the device gate structure. It has two main functions: the first is to redistribute the current from the N-type source region laterally, reduce the on-resistance and avoid heat concentration problems; the second is to construct a transition region from the P-type source region to the N-type drift layer. Since the doping concentration of the N-type low-resistance region is higher than that of the drift layer, the voltage in this area increases and the space charge region diffuses more slowly, reducing device damage caused by electric field mutations. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0020] Figure 1 The schematic diagram of a vertical compact trench gate silicon carbide VDMOS of the present invention.

[0021] Figure 2 A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 1 .

[0022] Figure 3 A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 2 .

[0023] Figure 4A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 3 .

[0024] Figure 5 A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 4 .

[0025] Figure 6 A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 5 .

[0026] Figure 7 A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 6 .

[0027] Figure 8 A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 7 .

[0028] Fig. 9 A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 8 .

[0029] Fig.10 A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 9 .

[0030] Fig.11 A cross-sectional view of the process of a vertical compact trench gate silicon carbide VDMOS of the present invention Figure 10 . DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] like Figures 1 to 11 As shown, the embodiment of the present application provides a method for preparing a vertical compact trench gate silicon carbide VDMOS, comprising the following steps:

[0037] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; epitaxially growing a drift layer 2 on the side of the silicon carbide substrate 1;

[0038] Step 2, forming a low resistance region 3 by performing ion implantation on the drift layer 2;

[0039] Step 3, forming a barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a P-type source region 4;

[0040] Step 4, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a P-type well region 5;

[0041] Step 5, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the P-type well region 5 to form an N-type source region 51;

[0042] Step 6, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, etching the drift layer 2 and the P-type well region a to form a groove 52, and oxidizing to form an insulating dielectric layer 6, wherein the insulating dielectric layer 6 is provided with a groove 61;

[0043] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 7;

[0044] Step 8, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the drift layer 2 to the upper side of the P-type well region 5, deposit metal to form a source metal layer 8, remove the barrier layer a, and complete the preparation.

[0045] In this embodiment, preferably, the thickness of the low resistance region 3 is 300-500 nm.

[0046] In this embodiment, preferably, the distance between the lower side of the insulating dielectric layer 6 and the upper side of the low resistance region 3 is 100-200 nm.

[0047] In this embodiment, preferably, the doping concentration of the low resistance region 3 is greater than the doping concentration of the drift layer 2 , and the doping concentration of the P-type source region 4 is greater than the doping concentration of the low resistance region 3 .

[0048] In this embodiment, preferably, the silicon carbide substrate 1 , the drift layer 2 and the low resistance region 3 are all of N type.

[0049] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0050] Silicon carbide substrate 1,

[0051] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1;

[0052] A low resistance region 3, wherein the lower side of the low resistance region 3 is connected to the upper side of the drift layer 2;

[0053] A P-type source region 4, wherein the lower side of the P-type source region 4 is connected to the upper side of the low resistance region 3;

[0054] A P-type well region 5, wherein the lower side of the P-type well region 5 is connected to the upper side of the low resistance region 3, the outer side of the P-type well region 5 is connected to the inner side of the P-type source region 4, an N-type source region 51 is provided in the P-type well region 5, and a groove 52 is provided in the P-type well region 5;

[0055] An insulating dielectric layer 6, wherein the lower portion of the insulating dielectric layer 6 is disposed in the groove 52, the outer side surface of the insulating dielectric layer 6 is respectively connected to the inner side surface of the P-type well region 5 and the inner side surface of the N-type source region 51, and a groove 61 is disposed in the insulating dielectric layer 6;

[0056] A gate metal layer 7, wherein the gate metal layer 7 is disposed in the groove 61;

[0057] A source metal layer 8, wherein the source metal layer 8 is respectively connected to the P-type source region 4, the P-type well region 5 and the N-type source region 51;

[0058] and a drain metal layer 9 , wherein the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1 .

[0059] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e16cm -3 , the doping concentration of the N-type low resistance region 3 is 1-5e17cm -3 , the doping concentration of the P-type well region 5 is 1-5e17cm -3 , the insulating dielectric layer 6 is silicon dioxide, and the doping concentration of the P-type source region 4 is 1-2e19cm -3 , the doping concentration of the N-type source region 51 is 2-8e18cm -3 ; The concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 9 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the N-type low-resistance region 3 is designed with two considerations. One is to achieve current equalization in the device and reduce the on-resistance of the device, which requires ensuring that its doping concentration is high. The second is to construct a transition zone from the P-type source region 4 to the N-type drift layer 2. Since the doping concentration of the N-type low-resistance region 3 is higher, the voltage in this region increases and the space charge region diffuses more slowly, reducing device damage caused by electric field mutations.

[0060] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, and the thickness of the N-type drift layer 2 is 30-100 μm, which can be adjusted within the above range according to different requirements for the withstand voltage characteristics of the device; the present invention designs a longitudinal compact gate structure, the thickness of the P-type well region 5 below the insulating dielectric layer 6 structure is 100-200nm, the thickness of the N-type low resistance region 3 is 300-500nm, the thickness of the N-type source region 51 is 200nm, the thickness of the P-type well region 5 below the N-type source region 51 is 200-400nm, the thickness of the source metal layer 8 is 200nm, and the thickness of the overall device gate structure is 600-800nm, thereby reducing the device thickness from the gate structure; the designed longitudinal compact gate structure has a compact structure, the P-type well region 5 is tightly surrounded by the insulating dielectric layer 6, and the gate control capability of the device can be guaranteed, and the N-type low resistance region 3 realizes partial shielding of the gate to device drain capacitance, which can reduce the device gate capacitance, thereby improving the switching speed of the device;

[0061] The present invention separates the N-type source region 51 and the P-type source region 4 so that the P-type source region 4 is distributed outside the P-type well region 5 of the device. Due to the separation of the N-type source region 51 and the P-type source region 4, the body diode freewheeling path of the device and the normal conduction freewheeling path of the device are separated. The body diode freewheeling path is source metal layer 8-P-type source region 4-N-type low resistance region 3 redistribution-N-type drift layer 2-N-type silicon carbide substrate 1-drain metal layer 9, and the normal conduction freewheeling path of the device is source metal layer 8-N-type source region 51-N-type low resistance region 3 redistribution-N-type drift layer 2-N-type silicon carbide substrate 1-drain metal layer 9. This separation can avoid current concentration in the gate structure of the device and damage such as electromigration caused by current concentration, thereby improving device reliability. Since the doping concentration of the P-type source region 4 is high, the contact resistance between the source metal layer 8 of the device and the P-type source region 4 is lower, which can effectively reduce the body diode loss of the device.

[0062] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a vertical compact trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a low resistance region by ion implantation into the drift layer; Step 3, forming a barrier layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a P-type source region; Step 4, removing the barrier layer of step 3, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a P-type well region; Step 5, removing the barrier layer of step 4, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 6, removing the barrier layer of step 5, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer and the P-type well region to form a groove, and oxidizing to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a groove; Step 7, removing the barrier layer of step 6, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 8, removing the barrier layer of step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side of the P-type well region, depositing a metal layer to form a source metal layer, removing the barrier layer, and completing the preparation; The lower side of the low resistance region is connected to the upper side of the drift layer; The lower side of the P-type source region is connected to the upper side of the low resistance region; the lower side of the P-type well region is connected to the upper side of the low resistance region, and the outer side of the P-type well region is connected to the inner side of the P-type source region; the source metal layer is respectively connected to the P-type source region, the P-type well region and the N-type source region.

2. The method for preparing a vertical compact trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the low resistance region is 300-500 nm.

3. The method for preparing a vertical compact trench gate silicon carbide VDMOS according to claim 1, characterized in that: The distance between the lower side of the insulating dielectric layer and the upper side of the low resistance region is 100-200 nm.

4. The method for preparing a vertical compact trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the low resistance region is greater than the doping concentration of the drift layer, and the doping concentration of the P-type source region is greater than the doping concentration of the low resistance region.

5. The method for preparing a vertical compact trench gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, drift layer and low resistance region are all N-type.

6. A vertical compact trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods described in claim 1 to claim 5.

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