Semiconductor device having gate electrical contact forming junctions having different energy barrier

Abstract

The present application discloses a semiconductor device having a gate electrical contact forming junctions with a gate layer having different energy barrier heights, and generally relates to a semiconductor device that includes a gate electrical contact forming junctions with a gate layer having different energy barrier heights. In one example, a semiconductor device includes a semiconductor substrate (302), a drain electrical contact (344), a source electrical contact (342), a barrier layer (308), a gate layer (310), and a gate electrical contact (322, 422, 522, 112, 122, 132, 162, 182). A drain electrical contact (344) and a source electrical contact (342) are on the semiconductor substrate (302). A barrier layer (308) is over a channel region of the semiconductor substrate (302) between the drain electrical contact (344) and the source electrical contact (342). The gate layer (310) is over the barrier layer (308). The gate layer (310) includes a first semiconductor portion and a second semiconductor portion. A gate electrical contact (322, 422, 522, 112, 122, 132, 162, 182) contacts the gate layer (310). The gate electrical contact (322, 422, 522, 112, 122, 132, 162, 182) includes a first metal portion and a second metal portion. The first and second metal portions form a first junction (334) and a second junction (336) with the first and second semiconductor portions, respectively. The first junction (334) and the second junction (336) have different energy barrier heights.

Description

Background Art

[0001] One type of semiconductor device is a high electron mobility transistor (HEMT). HEMTs typically use different semiconductor materials to form a heterojunction, where a channel can be formed near the heterojunction and between a source region and a drain region. HEMTs can operate at high speeds, making them attractive for high-frequency applications, among other applications. Summary of the Invention

[0002] This summary is provided to introduce a brief selection of the disclosed concepts in a simplified form, which are further described in the detailed description below (including the accompanying figures). Various disclosed devices and methods can be beneficially applied to semiconductor devices including gate electrical contacts that form junctions with gate layers having different energy barrier heights. While these embodiments can be expected to achieve low gate leakage, stable gate overdrive voltage (V GT ) and increased drain current (I d ), but no specific result is required unless explicitly recited in a specific claim.

[0003] The example described herein is a semiconductor device. The semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. The drain electrical contact is on the semiconductor substrate, and the source electrical contact is on the semiconductor substrate. The barrier layer is above a channel region of the semiconductor substrate between the drain electrical contact and the source electrical contact. The gate layer is above the barrier layer. The gate layer includes a first semiconductor portion and a second semiconductor portion. The gate electrical contact contacts the gate layer. The gate electrical contact includes a first metal portion and a second metal portion. The first metal portion forms a first junction with the first semiconductor portion, and the second metal portion forms a second junction with the second semiconductor portion. The first junction and the second junction have different energy barrier heights.

[0004] Another example is a method. A patterned gate layer is formed above a barrier layer. The barrier layer is above a channel layer above a semiconductor substrate. The patterned gate layer includes a first semiconductor portion and a second semiconductor portion. A gate electrical contact is formed in contact with the patterned gate layer. The gate electrical contact includes a first metal portion and a second metal portion. A first energy barrier height is an energy barrier height of a junction between the first metal portion and the first semiconductor portion, and a second energy barrier height is an energy barrier height of a junction between the second metal portion and the second semiconductor portion. The first energy barrier height is greater than the second energy barrier height.

[0005] The foregoing summary has generally outlined various features of the examples of the present disclosure in order to better understand the following detailed description. Additional features and advantages of these examples will be described below. The described examples can be readily used as a basis for modifying or designing other examples within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A cross-sectional view of an enhancement mode high electron mobility transistor (HEMT) with an overlaid circuit model of the HEMT is illustrated.

[0007] Figure 2 Illustrated is a cross-sectional view of an enhancement-mode HEMT with an overlaid circuit model of the HEMT, according to some examples.

[0008] Figure 3 、 Figure 4 and Figure 5 is a cross-sectional view of a corresponding semiconductor device according to some examples.

[0009] Figure 6 、 Figure 7 、 Figure 8 and Figure 9 are perspective views of corresponding semiconductor devices according to some examples.

[0010] Figure 10 are layout diagrams of semiconductor devices according to some examples.

[0011] Figure 11 、 Figure 12 and Figure 13 is a cross-sectional view of a corresponding semiconductor device according to some examples.

[0012] Figure 14 and Figure 15 are perspective views of corresponding semiconductor devices according to some examples.

[0013] Figure 16 is a cross-sectional view of a semiconductor device according to some examples.

[0014] Figure 17 is a perspective view of a semiconductor device according to some examples.

[0015] Figure 18 and Figure 19 is a cross-sectional view of a corresponding semiconductor device according to some examples.

[0016] Figure 20 Made based on some examples Figure 3 A flow chart of a method for a semiconductor device.

[0017] Figure 21 、 Figure 22、 Figure 23 、 Figure 24 、 Figure 25 and Figure 26 Based on some examples Figure 3 Cross-sectional views of a semiconductor device at various stages of fabrication.

[0018] Figure 27 Made based on some examples Figure 4 A flow chart of a method for a semiconductor device.

[0019] Figure 28 、 Figure 29 、 Figure 30 、 Figure 31 and Figure 32 Based on some examples Figure 4 Cross-sectional views of a semiconductor device at various stages of fabrication.

[0020] Figure 33 Made based on some examples Figure 5 A flow chart of a method for a semiconductor device.

[0021] Figure 34 、 Figure 35 、 Figure 36 、 Figure 37 and Figure 38 Based on some examples Figure 5 Cross-sectional views of a semiconductor device at various stages of fabrication.

[0022] Figure 39 Made based on some examples Figure 11 A flow chart of a method for a semiconductor device.

[0023] Figure 40 、 Figure 41 and Figure 42 Based on some examples Figure 11 Cross-sectional views of a semiconductor device at various stages of fabrication.

[0024] Figure 43 Made based on some examples Figure 12 A flow chart of a method for a semiconductor device.

[0025] Figure 44 、 Figure 45 、 Figure 46 、 Figure 47 and Figure 48 Based on some examples Figure 12 Cross-sectional views of a semiconductor device at various stages of fabrication.

[0026] Figure 49 Made based on some examples Figure 13 A flow chart of a method for a semiconductor device.

[0027] Figure 50 、 Figure 51 、 Figure 52 and Figure 53 Based on some examples Figure 13 Cross-sectional views of a semiconductor device at various stages of fabrication.

[0028] Figure 54 Made based on some examples Figure 16 A flow chart of a method for a semiconductor device.

[0029] Figure 55 、 Figure 56 and Figure 57 Based on some examples Figure 16 Cross-sectional views of a semiconductor device at various stages of fabrication.

[0030] Figure 58 Made based on some examples Figure 18 A flow chart of a method for a semiconductor device.

[0031] Figure 59 、 Figure 60 and Figure 61 Based on some examples Figure 18 Cross-sectional views of a semiconductor device at various stages of fabrication.

[0032] The drawings and the accompanying detailed description are provided for understanding the features of the various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description can be easily used as a basis for modifying or designing other examples within the scope of the appended claims. Wherever possible, the same reference numerals can be used to represent the same elements that are common to the figures. The figures are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0033] Various features are described below with reference to the accompanying drawings. The illustrated examples may not have all aspects or advantages shown. An aspect or advantage described in conjunction with a particular example is not necessarily limited to that example and may be practiced in any other example, even if not illustrated or explicitly described as such. In addition, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented in various other orders with more or fewer operations (e.g., including different serial or parallel executions of the various operations).

[0034] The present disclosure relates to a semiconductor device including a gate electrical contact that forms a junction with a gate layer having different energy barrier heights. In some examples described herein, the semiconductor device is a high electron mobility transistor (HEMT), such as an enhancement mode HEMT. The junction with different energy barrier heights can allow the semiconductor device to achieve low gate leakage, stable gate overdrive voltage (V GT ) and increased drain current (I d ). Other benefits and advantages may be realized.

[0035] Various examples are described herein. Although specific examples may illustrate various aspects of the features generally described above, the examples may combine any combination of the features generally described above (described in more detail in the examples below). For ease of reference, three-dimensional xyz axes are illustrated in some of the figures. Some cross-sectional views of various semiconductor devices herein may be general descriptions that convey various aspects or concepts about such semiconductor devices. More specifically, except to the extent described herein, some gate electrical contacts illustrated in the cross-sectional views may not necessarily accurately depict the structure of such gate electrical contacts. The illustrations of those gate electrical contacts are intended to convey various aspects or concepts about those gate electrical contacts.

[0036] Various examples are described in the context of HEMTs. Some examples may be implemented in enhancement-mode lateral HEMTs for high voltage (e.g., 650V to 1200V) applications or low to medium voltage (e.g., 10V to 100V or 10V to 200V) applications. In other examples, the semiconductor device may be or include a bidirectional field effect transistor (FET), a gate-controlled Schottky barrier diode (e.g., a gate-to-drain shorted structure or a gate-to-source shorted structure), or the like. Although various methods of forming semiconductor devices are described herein, some examples may be implemented in gate-first or replacement gate processes and may be implemented in self-aligned or non-self-aligned processes. Some examples may be implemented with any epitaxial structure, any field plate and / or ohmic contact process, planar or three-dimensional structures (e.g., fin structures), and / or various other modifications.

[0037] Figure 1A cross-sectional view of an enhancement-mode HEMT 100 is illustrated with an overlaid circuit model of the HEMT 100. The HEMT 100 includes a channel layer 102, a barrier layer 104 above the channel layer 102, and a gate layer 106 above the barrier layer 104. The configuration of the barrier layer 104 above the channel layer 102 forms a two-dimensional electron gas (2DEG) in the channel layer 102 near the interface between the channel layer 102 and the barrier layer 104. A gate electrical contact 112 is on and above the gate layer 106. In this illustration, the gate electrical contact 112 and the gate layer 106 form a Schottky junction, which may be caused by the metal of the gate electrical contact 112 and / or the doping of the gate layer 106. A source electrical contact 114 and a drain electrical contact 116 are electrically coupled to the channel layer 102 on opposite sides of the gate layer 106. Dielectric layer 118 is on and over barrier layer 104 , gate layer 106 , and electrical contacts 112 , 114 , 116 .

[0038] Referring to the circuit model, gate contact node 120 is in gate electrical contact 112, and gate layer node 122 is in gate layer 106. Channel source side node 124 and channel drain side node 126 are at the interface between channel layer 102 and barrier layer 104. Source contact node 128 is in source electrical contact 114, and drain contact node 130 is in drain electrical contact 116.

[0039] Schottky diode (D SH )140 and Schottky capacitor (C SH ) 142 is electrically coupled between gate contact node 120 and gate layer node 122. A cathode terminal of Schottky diode 140 is electrically coupled to gate contact node 120, and an anode terminal of Schottky diode 140 is electrically coupled to gate layer node 122. Similarly, a first terminal of Schottky capacitor 142 is electrically coupled to gate contact node 120, and a second terminal (opposite the first terminal) of Schottky capacitor 142 is electrically coupled to gate layer node 122.

[0040] p-type intrinsic n-type (pin) source-side diode (D s )144 and the gate-to-source capacitor (C gs ) 146 is electrically coupled between the gate layer node 122 and the channel source side node 124. An anode terminal of the source side diode 144 is electrically coupled to the gate layer node 122, and a cathode terminal of the source side diode 144 is electrically coupled to the channel source side node 124. In addition, a first terminal of a gate-to-source capacitor 146 is electrically coupled to the gate layer node 122, and a second terminal (opposite to the first terminal) of the gate-to-source capacitor 146 is electrically coupled to the channel source side node 124.

[0041] The pin drain side diode (D d)148 and the gate-to-drain capacitor (C gd ) 150 is electrically coupled between gate layer node 122 and channel drain side node 126. An anode terminal of drain side diode 148 is electrically coupled to gate layer node 122, and a cathode terminal of drain side diode 148 is electrically coupled to channel drain side node 126. Similarly, a first terminal of gate-to-drain capacitor 150 is electrically coupled to gate layer node 122, and a second terminal (opposite the first terminal) of gate-to-drain capacitor 150 is electrically coupled to channel drain side node 126.

[0042] Field effect transistor (FET) 152 has a gate terminal electrically coupled to gate layer node 122. FET 152 has a source terminal electrically coupled to channel source side node 124 and has a drain terminal electrically coupled to channel drain side node 126. The channel of FET 154 and the channel-to-source resistor (R cs ) 156 is electrically coupled in series between the channel source side node 124 and the source contact node 128. The channel of the FET 158 and the channel-to-drain resistor (R cd ) 160 are electrically coupled in series between the channel drain side node 126 and the drain contact node 130 .

[0043] Having a Schottky junction between gate electrical contact 112 and gate layer 106 (illustrated by Schottky diode 140 and Schottky capacitor 142 coupled between gate contact node 120 and gate layer node 122) can result in low gate leakage current during operation of HEMT 100. A positive voltage applied to gate electrical contact 112 (e.g., gate contact node 120) reverse biases the Schottky junction, which can result in low gate leakage current. However, the Schottky junction between gate electrical contact 112 and gate layer 106 results in a back-to-back diode configuration at gate layer node 122 (e.g., the anode terminals of Schottky diode 140 and source-side diode 144 are electrically coupled to gate layer node 122). In some cases, this back-to-back diode configuration results in a floating quasi-neutral node (e.g., gate layer node 122) in gate layer 106. Under direct current (DC) conditions, the node in the gate layer 106 is in a voltage divider formed by diodes 140, 144, which reduces the effective gate overdrive voltage (V GT ), which reduces the drain current (I d ), and increases the drain-to-source on-resistance (R DSON). During a switching event, the nodes in the gate layer 106 may be biased based on past switching events due to their floating nature. This biasing may cause non-deterministic behavior of the HEMT 100 and may adversely affect the drain current of the HEMT 100. Furthermore, when turned on, the Schottky capacitor 142 may initially form a low impedance path, which may quickly pull the voltage of the gate layer node 122 up to the voltage applied on the gate contact node 120. However, after the initial turn-on, due to the voltage divider, the voltage of the gate layer node 122 stabilizes to a certain voltage that is proportional to the voltage applied on the gate electrical contact 112. The voltage change at the gate layer node 122 may cause an initial peak in the drain current, which may then decrease and stabilize. As a result, the HEMT 100 may experience a dynamic gate overdrive voltage (V GT ).

[0044] To address these adverse effects, the examples described herein provide a gate electrical contact comprising a first metal portion and a second metal portion. The first metal portion forms a first junction with a first semiconductor portion of the gate layer, and the second metal portion forms a second junction with a second semiconductor portion of the gate layer. The energy barrier height of the first junction is greater than the energy barrier height of the second junction. For example, the first junction may be a high energy barrier height Schottky junction, and the second junction may be a low energy barrier height Schottky junction or an ohmic junction.

[0045] Figure 2 A cross-sectional view of the enhancement-mode HEMT 200 with an overlaid circuit model of the HEMT 200 is illustrated. Figure 2 HEMT 200 includes at least some of the components of HEMT 100 and a gate electrical contact 212. Gate electrical contact 212 includes a first metal portion 214 and a second metal portion 216. First metal portion 214 forms a first junction, such as the Schottky junction described above, with a portion of gate layer 106. Second metal portion 216 forms a second junction with another portion of gate layer 106. As shown, this second junction is an ohmic junction, although a low-energy barrier height junction may be formed. The ohmic junction formed between first metal portion 214 and second metal portion 216 can maintain the same electrical potential.

[0046] exist Figure 2 In the circuit model, the ohmic resistor (R OH) 218 ​​is electrically coupled between the gate contact node 120 and the gate layer node 122. The ohmic resistor 218 is formed by the junction between the second metal portion 216 and the second semiconductor portion of the gate layer 106. The ohmic junction or low energy barrier height junction can provide a path through which the gate layer node 122 (e.g., gate layer 106) is biased by the voltage applied to the gate electrical contact 212 and can reduce the voltage drop between the gate electrical contact and the gate layer node 122. The voltage drop can be the same under DC conditions and during switching events. Therefore, the gate overdrive voltage (V GT ) can increase (under DC conditions) and stabilize (during switching events), and the drain current (I d ) can also be increased. Thus, the gate layer 106 can be driven to a voltage that more accurately and precisely tracks the voltage at the gate electrical contact 112, which can avoid peak current response in the switch. The surface area of ​​the first junction and the second junction can be scaled to obtain a target gate leakage while obtaining a stable gate overdrive voltage (V GT ) and increased drain current (I d For example, by making the surface area of ​​the second junction relatively small compared to the surface area of ​​the first junction, gate leakage can be kept low while still providing a path to bias the gate layer 106 to achieve a stable gate overdrive voltage (V GT ) and increased drain current (I d ).

[0047] Figure 3 A cross-sectional view of a semiconductor device 300 according to some examples is shown. In this example, the semiconductor device 300 is or includes a HEMT. Additionally, the semiconductor device 300 may be or include an enhancement-mode HEMT. Other examples may be or include other types of devices. Figure 3 Also included are circuit symbols overlaid on the cross-sectional view to represent the properties / functions of the elements of semiconductor device 300 .

[0048] Figure 3 Shown are a semiconductor substrate 302 and one or more transition layers 304 on and above semiconductor substrate 302. A channel layer 306 is on and above the uppermost transition layer 304. A barrier layer 308 is on and above channel layer 306.

[0049] The semiconductor substrate 302 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. For example, the semiconductor substrate 302 may be or include a bulk silicon wafer. The transition layer(s) 304 may include any number of layers of any material configured to accommodate the lattice mismatch between the semiconductor substrate 302 and the channel layer 306 (e.g., to reduce or minimize the generation and / or propagation of lattice defects in the channel layer 306). For example, the transition layer(s) 304 may have a gradient concentration of one or more elements in a direction perpendicular to the upper surface of the semiconductor substrate 302.

[0050] Channel layer 306 is configured, possibly in combination with barrier layer 308, to conduct and confine charge carriers (such as electrons) in two dimensions. In some examples, in various examples, channel layer 306 is configured to include a 2DEG. The 2DEG can be formed by band bending caused by barrier layer 308 on and above channel layer 306. In some examples, channel layer 306 can be part of a semiconductor substrate (e.g., without transition layer(s), and / or semiconductor substrate 302 with transition layer(s) 304 and channel layer 306 can be considered a semiconductor substrate). In some examples, channel layer 306 includes a gallium nitride (GaN) layer, and in such examples, can be referred to as a GaN channel layer. In some examples, the material of channel layer 306 is or includes an unintentionally doped material, such as a material doped by diffusion of dopants from another layer, or is or includes an intrinsic material. In some examples, barrier layer 308 can be or include an aluminum gallium nitride (AlGaN) layer, and in such examples, can be referred to as an AlGaN barrier layer. More generally, in some examples, channel layer 306 can be or include an aluminum gallium nitride (InGaN) layer. i Al j Ga 1-i-j N) (where 0≤i≤1, 0≤j≤1, and 0≤i+j≤1), and the barrier layer 308 may be or include indium aluminum gallium nitride (InGaN). k Al l Ga 1-k-l N) (where 0≤k≤1, 0≤l≤1, and 0≤k+l≤1). Other materials may be implemented for the channel layer 306 and / or the barrier layer 308 .

[0051] Gate layer 310 is on and above the upper surface of barrier layer 308. In some examples, gate layer 310 is or includes a semiconductor layer of a semiconductor material. Furthermore, in some examples, gate layer 310 is doped with a dopant. In some examples, gate layer 310 is doped with a p-type dopant. In some examples, gate layer 310 can be or include a gallium nitride (GaN) layer, or more generally, an indium aluminum gallium nitride (InGaN) layer.m Al n Ga 1-m-n N) (where 0≤m<1, 0≤n<1, and 0≤m+n≤1), and the dopant doped with the gate layer 310 is a p-type dopant, which can be or include magnesium (Mg), carbon (C), zinc (Zn), etc., or a combination thereof. In the example where the gate layer 310 is gallium nitride (GaN) doped with a p-type dopant, the gate layer 310 can be referred to as a p-doped GaN (pGaN) layer. In addition, in the example where the gate layer 310 is gallium nitride (GaN) doped with magnesium, the gate layer 310 can be referred to as a magnesium-doped gallium nitride (GaN:Mg) layer. In some examples, the concentration of the dopant in the electrically activated gate layer 310 is equal to or greater than 1×10 17 cm -3 In some examples, the concentration is equal to or greater than 1×10 18 cm -3 In other examples, other materials, dopants, and / or concentrations may be implemented.

[0052] The semiconductor device 300 includes a source region S, a channel region C, a drain region D, and a gate structure G. The gate structure G includes a gate layer 310. The channel region C is in a channel layer 306 below the gate structure G. The channel region C is laterally between the drain region D and the source region S, which are also in the channel layer 306.

[0053] First dielectric layer 320 is on and above barrier layer 308 and gate layer 310. First dielectric layer 320 is on and above the respective upper surfaces of barrier layer 308 and gate layer 310, and along the sidewall surfaces of gate layer 310. First dielectric layer 320 may include multiple dielectric layers of the same dielectric material or different dielectric materials. For example, first dielectric layer 320 may include a silicon oxide-based material such as phosphosilicate glass (PSG), and may further include one or more etch stop layers such as silicon nitride (SiN).

[0054] Gate electrical contact 322 extends through first dielectric layer 320 and contacts gate layer 310. A lateral portion of gate electrical contact 322 may be on and above the upper surface of first dielectric layer 320. Gate electrical contact 322 includes a first metal portion and a second metal portion. In the illustrated example, the first metal portion includes a first metal layer 324, and the second metal portion includes a second metal layer 326. First metal layer 324 is substantially conformal to the upper surface of gate layer 310, the sidewall surfaces of the opening through first dielectric layer 320, and the upper surface of first dielectric layer 320. First metal layer 324 contacts a first surface area of ​​gate layer 310. Second metal layer 326 is substantially conformal to first metal layer 324 and extends through the opening through first metal layer 324 (which further extends through the opening through first dielectric layer 320) to contact gate layer 310. Second metal layer 326 contacts a second surface area of ​​gate layer 310. In some examples, the first surface area (e.g., where first metal layer 324 contacts gate layer 310) is larger than the second surface area (e.g., where second metal layer 326 contacts gate layer 310). In some examples, the first surface area can be at least 10 times larger than the second surface area, such as in the range of 10 to 100 times larger.

[0055] A first metal portion of gate electrical contact 322 (e.g., first metal layer 324) forms a high-energy barrier height junction 334 with the first semiconductor portion of gate layer 310, for example, as illustrated by a Schottky diode symbol, wherein the first metal portion contacts the first semiconductor portion of gate layer 310. A second metal portion of gate electrical contact 322 (e.g., second metal layer 326) forms a low-energy barrier height junction 336 with the second semiconductor portion of gate layer 310, for example, as illustrated by a resistor (e.g., an ohmic junction), wherein the second metal portion contacts the second semiconductor portion of gate layer 310. In some examples, the first metal portion of gate electrical contact 322 (e.g., first metal layer 324) has a work function greater than a work function of the second metal portion of gate electrical contact 322 (e.g., second metal layer 326). In some examples, the work function of the first metal portion of gate electrical contact 322 is equal to or greater than 4.6 electron volts (eV), and the work function of the second metal portion of gate electrical contact 322 is less than 4.6 eV. In some examples, the high-energy barrier height junction 334 has an energy barrier height that is greater than the energy barrier height of the low-energy barrier height junction 336. In some examples, the energy barrier height of the high-energy barrier height junction 334 is equal to or greater than 1.7 eV, and the energy barrier height of the low-energy barrier height junction 336 is less than 1.7 eV. In some examples, the high-energy barrier height junction 334 can be a high-energy barrier height Schottky junction, and the low-energy barrier height junction 336 can be an ohmic junction (e.g., having an energy barrier height of approximately 0 eV) or can be a low-energy barrier height Schottky junction. Within the gate electrical contact 322, the first metal portion (e.g., the first metal layer 324) forms an ohmic junction with the second metal portion (e.g., the second metal layer 326).

[0056] The first metal portion (e.g., first metal layer 324) and the second metal portion (e.g., second metal layer 326) can be or include different metals. The energy barrier height of the junction between a given metal and a semiconductor material can be a function of the materials of the metal and semiconductor material and any doping of the semiconductor material. In order to obtain unequal energy barrier heights for the junctions 334, 336 as described above, in the example shown, the first metal layer 324 is or includes a different metal than the second metal layer 326. In the example shown, the first semiconductor portion of the gate layer 310 is the same semiconductor material as the second semiconductor portion of the gate layer 310 and is doped (e.g., with a p-type dopant) as the second semiconductor portion of the gate layer 310. As an example, the gate layer 310 can be a magnesium-doped gallium nitride (GaN:Mg) layer, where the magnesium (Mg) is present at 2×10 18 cm -3The first metal layer 324 may be titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), or an alloy thereof; and the second metal layer 326 may be gold (Au), aluminum (Al), or an alloy thereof, which may include titanium tungsten aluminum (TiWAl) and titanium aluminum nitride (TiAlN), each with an increasing percentage of aluminum. In some examples, the first metal portion and the second metal portion have different metal materials, wherein the metal material may include any of the above-mentioned metal materials, such as titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), titanium tungsten aluminum (TiWAl), and titanium aluminum nitride (TiAlN).

[0057] In some examples, the first metal portion and the second metal portion may also have the same metal, the same metal material, or the same metal alloy composition. The same metal / metal material / metal alloy may include, for example, titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), titanium tungsten aluminum (TiWAl), and titanium aluminum nitride (TiAlN). The first metal portion and the second metal portion may be processed with different process conditions (e.g., different annealing conditions, different deposition / etching conditions, etc.) to create junctions with different energy barrier heights.

[0058] Figure 3 Also shown is a reference plane 340 in the xy plane. Reference plane 340 intersects gate electrical contact 322. The pattern of the first and second metal portions of gate electrical contact 322 is illustrated by the following three-dimensional (3D) figures, which show the pattern at reference plane 340.

[0059] A source electrical contact 342 extends through the first dielectric layer 320 and contacts the channel layer 306 at the source region S, and a drain electrical contact 344 extends through the first dielectric layer 320 and contacts the channel layer 306 at the drain region D. The source electrical contact 342 and the drain electrical contact 344 are electrically coupled to the source region S and the drain region D, respectively, in the channel layer 306. A gate structure G (including the gate layer 310) is laterally disposed between the source electrical contact 342 and the drain electrical contact 344. Metal lines 352 and 354 in the first metal layer are disposed on and above the electrical contacts 342 and 344 and the upper surface of the first dielectric layer 320, respectively. Electrical contacts 342, 344 may each conformally include one or more metal-barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) in respective openings through first dielectric layer 320, and a filler metal (e.g., aluminum (Al), copper (Cu), tungsten (W), etc., or combinations thereof) on and / or over the metal-barrier and / or adhesion layers. Metal lines 352, 354 may each include one or more metal-barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) and a bulk metal (e.g., aluminum (Al), copper (Cu), etc., or combinations thereof) on and / or over the metal-barrier and / or adhesion layers.

[0060] Second dielectric layer 360 is disposed on and above first dielectric layer 320, gate electrical contact 322, and metal lines 352 and 354. Second dielectric layer 360 may be a single dielectric layer, or may include multiple dielectric layers of the same dielectric material or different dielectric materials. For example, second dielectric layer 360 may include a silicon oxide-based material, such as PSG, and may further include one or more etch stop layers, such as silicon nitride (SiN).

[0061] Metal vias 362, 364 extend through second dielectric layer 360 and respectively contact metal lines 352, 354. Metal lines 372, 374 in the second metal layer are respectively on and above metal vias 362, 364 and the upper surface of second dielectric layer 360. Metal vias 362, 364 may each conformally include one or more metal-barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) in their respective openings through second dielectric layer 360, and a fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or a combination thereof) on and / or over the metal-barrier and / or adhesion layer(s). Metal lines 372, 374 may include one or more metal-barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) and bulk metal (e.g., aluminum (Al), copper (Cu), etc., or combinations thereof) on and / or over the (one or more) metal-barrier and / or adhesion layers.

[0062] Additional dielectric layers and metal layers may be formed on and over second dielectric layer 360. First dielectric layer 320, second dielectric layer 360, additional dielectric layers, first metal layer, second metal layer, and additional metal layers may form an interconnect structure. Metal lines in adjacent metal layers may be electrically coupled through metal vias.

[0063] Figure 4 A cross-sectional view of a semiconductor device 400 according to some examples is illustrated. In this example, the semiconductor device 400 is or includes a HEMT. Additionally, the semiconductor device 400 may be or include an enhancement-mode HEMT. Other examples may be or include other types of devices.

[0064] Figure 4 The semiconductor device 400 includes Figure 3At least some components of the semiconductor device 300 and a gate electrical contact 422 are provided. The gate electrical contact 422 extends through the first dielectric layer 320 and contacts the gate layer 310. A lateral portion of the gate electrical contact 422 may be on and above the upper surface of the first dielectric layer 320. The gate electrical contact 422 includes a first metal portion and a second metal portion. In the illustrated example, the first metal portion includes a first metal layer 424, and the second metal portion includes a second metal layer 426. The first metal layer 424 may be conformal on the upper surface of the gate layer 310, the sidewall surfaces of the first opening through the first dielectric layer 320, and the upper surface of the first dielectric layer 320. The first metal layer 424 contacts a first surface region of the upper surface of the gate layer 310 through the first opening. The second metal layer 426 is on the upper surface of the gate layer 310, the sidewall surfaces of the second opening through the first dielectric layer 320, the upper surface of the first dielectric layer 320, and the first metal layer 424. The first opening through the first dielectric layer 320 is separated from the second opening through the first dielectric layer 320. The second metal layer 426 contacts the second surface area of ​​the upper surface of the gate layer 310 through the second opening. As shown in the manufacturing method described later, etching through the opening through the first metal layer 424 (e.g., in which the second metal layer 426 is deposited) can be avoided when forming the gate electrical contact 422, which can reduce the impact at the interface between the second metal layer 426 and the gate layer 310.

[0065] Other aspects of the first metal layer 424 and the second metal layer 426 are respectively Figure 1 The first metal layer 324 and the second metal layer 326 are similar. Specifically, the description of the surface area of ​​the gate layer 310 contacted by the metal layers 324 and 326, the junctions 334 and 336 formed by the metal layers 324 and 326 and the gate layer 310 and the energy barrier height and the materials of the metal layers 324 and 326 also applies to Figure 4 The first metal layer 424 and the second metal layer 426 are formed.

[0066] Figure 5 A cross-sectional view of a semiconductor device 500 according to some examples is illustrated. In this example, the semiconductor device 500 is or includes a HEMT. Additionally, the semiconductor device 500 may be or include an enhancement-mode HEMT. Other examples may be or include other types of devices.

[0067] Figure 5 The semiconductor device 500 includes Figure 3At least some of the components of the semiconductor device 300 and a gate electrical contact 522 are provided. The gate electrical contact 522 extends through the first dielectric layer 320 and contacts the gate layer 310. The gate electrical contact 522 includes a first metal portion and a second metal portion. In the illustrated example, the first metal portion includes a first metal layer 524, and the second metal portion includes a second metal layer 526. The first metal layer 524 may be on the upper surface of the gate layer 310 within an opening through the first dielectric layer 320. The first metal layer 524 contacts a first surface region of the upper surface of the gate layer 310. The second metal layer 526 may be on the first metal layer 524 and may be on the upper surface of the gate layer 310 within an opening through the first dielectric layer 320. The second metal layer 526 contacts a second surface region of the upper surface of the gate layer 310. As shown in the manufacturing method described later, the gate electrical contact 522 can be formed using a self-aligned process for forming the gate electrical contact 522 and the gate layer 310. The self-aligned process may help prevent misalignment of the gate electrical contact with the gate layer 310 .

[0068] Other aspects of the first metal layer 524 and the second metal layer 526 are respectively Figure 1 The first metal layer 324 and the second metal layer 326 are similar. Specifically, the description of the surface area of ​​the gate layer 310 contacted by the metal layers 324 and 326, the junctions 334 and 336 formed by the metal layers 324 and 326 and the gate layer 310 and the energy barrier height and the materials of the metal layers 324 and 326 also applies to Figure 5 The first metal layer 524 and the second metal layer 526 are formed.

[0069] Figure 6 、 Figure 7 、 Figure 8 and Figure 9 is a perspective view of respective semiconductor devices 600, 700, 800, 900 according to some examples. The semiconductor devices 600, 700, 800, 900 may be Figure 3 、 Figure 4 and Figure 5 As shown, each of the semiconductor devices 600, 700, 800, 900 includes a channel layer 306, a barrier layer 308, a gate layer 310, and a drain electrical contact 344. The semiconductor devices 600, 700, 800, 900 include a corresponding gate electrical contact (which may correspond to Figure 3 、 Figure 4 and Figure 5 ), which has the upper surface shown corresponding to the above-mentioned reference plane 340. The gate electrical contacts may actually have different upper surfaces. Figure 6 、 Figure 7 、 Figure 8 and Figure 9 The gate electrical contact in includes a first metal layer corresponding to the first metal layer 324, 424, 524, and includes a second metal layer corresponding to the second metal layer 326, 426, 526, respectively. As described above, Figure 6 、 Figure 7 、 Figure 8 and Figure 9 The gate electrical contact in forms a junction with the gate layer 310. In addition, Figure 6 、 Figure 7 and Figure 9 The semiconductor devices 600 , 700 , 900 further include a source electrical contact 342 .

[0070] refer to Figure 6 , the gate electrical contact includes a first metal layer 624 and a second metal layer 626 . Figure 6 The illustration shows that the gate layer 310 extends from a lateral boundary of the active area (e.g., along the x-direction) to another lateral boundary of the active area (e.g., along another x-direction) in the channel width direction (e.g., the y-direction). The portion of the second metal layer 626 that contacts the upper surface of the gate layer 310 is at the sidewalls of the gate layer 310, where the sidewalls intersect with the corresponding lateral boundaries of the active area. These intersections are illustrated as corners of the gate layer 310, although it is noted that the gate layer 310 can extend beyond the lateral boundaries of the active area. Another portion of the second metal layer 626 that contacts the upper surface of the gate layer 310 is located at the center of the gate layer 310 relative to the lateral boundaries of the active area with which the gate layer 310 intersects. A similar pattern of portions of the second metal layer 626 that contact the gate layer 310 can be repeated on the gate layer 310.

[0071] refer to Figure 7 , the gate electrical contact includes a first metal layer 724 and a second metal layer 726 . Figure 7 The illustration shows that the gate layer 310 extends from a lateral boundary of the active area (e.g., along the x-direction) to another lateral boundary of the active area (e.g., along another x-direction) in the channel width direction (e.g., the y-direction). The portion of the second metal layer 726 that contacts the upper surface of the gate layer 310 extends longitudinally along and across the upper surface of the gate layer 310 in the channel length direction (e.g., the x-direction). Two portions of the second metal layer 726 are shown. Other examples may include more portions of the second metal layer 726 that contact the upper surface of the gate layer 310. Figure 6 and Figure 7 The second metal layers 626 , 726 dispersed throughout the gate layer 310 may help bias the gate layer 310 to the same potential throughout the gate layer 310 . Figure 6 and Figure 7Different layouts of portions of the second metal layer 626, 726 are shown, which can compromise gate current, ohmic delay, and other considerations. DSAT ) and gate overdrive voltage (V GT ) increases with the gate-to-channel resistance (R GC ) delay and gate current (I G ) to balance layout-related tradeoffs.

[0072] refer to Figure 8 , the gate electrical contact includes a first metal layer 824 and a second metal layer 826 . Figure 8 The illustration of shows that the gate layer 310 extends from a lateral boundary of the active area (e.g., along the x-direction) to another lateral boundary of the active area (e.g., along another x-direction) in the channel width direction (e.g., the y-direction). The portion of the second metal layer 826 that contacts the upper surface of the gate layer 310 is at the sidewalls of the gate layer 310, adjacent to the source electrical contact 842, where the sidewalls intersect with the corresponding lateral boundaries of the active area. These intersections are illustrated as corners of the gate layer 310, although it is noted that the gate layer can extend beyond the lateral boundaries of the active area. The portion of the second metal layer 826 that contacts the gate layer 310 can be repeated on the gate layer 310 in a similar manner.

[0073] A side of the source electrical contact 842 adjacent to the gate layer 310 is notched 846 in the channel length direction (e.g., in the x-direction) corresponding to the location where the second metal layer 826 contacts the upper surface of the gate layer 310. At the midpoint between the portions of the second metal layer 826 that contact the upper surface of the gate layer 310, there is a first dimension 852 (e.g., in the x-direction) between the sidewall surface of the source electrical contact 842 (outside of any notches 846) and the sidewall surface of the gate layer 310. There is a second dimension 854 (e.g., in the x-direction) between the sidewall surface of the source electrical contact 842 at the corresponding notch 846 and the sidewall surface of the gate layer 310 at the location where the corresponding portion of the second metal layer 826 contacts the upper surface of the gate layer 310. The second dimension 854 is greater than the first dimension 852. Thus, the side of source electrical contact 842 is associated with the placement of second metal layer 826 that contacts gate layer 310 such that source electrical contact 842 is maintained at a greater distance from a portion of second metal layer 826 than from first metal layer 824. This type of association can result in lower gate-to-source current in regions adjacent to portions of second metal layer 826. Additionally, the gate electrical contact can result in less debiasing. By increasing the gate-to-source length (L GS ), the voltage drop in the gate-to-source length (e.g., current multiplied by the resistor voltage drop) increases, and the effective gate overdrive voltage (V GT ) decreases, which reduces the gate current (IG ). Debiasing can be an effective reduction in the internal gate-to-source voltage due to an increase in the voltage drop in the source electrical contact and / or access region (e.g., a region of the barrier layer 308 and / or channel layer 306 laterally located between the source electrical contact and the gate layer 310). The source electrical contact can dominate (e.g., relative to the drain electrical contact) the gate overdrive voltage (V GT ) and the gate-to-source current (I GS ). The gate-to-drain current (IGD) can be low because the drain electrical contact can be relatively far away from the gate layer 310. In addition, the gate electrical contact and the source electrical contact 842 can cause a small active area penalty.

[0074] refer to Figure 9 , the gate electrical contact includes a first metal layer 924 and a second metal layer 926 . Figure 9 The illustration shows that the gate layer 310 extends beyond the lateral boundary 902 of the active area (e.g., along the x-direction) in the channel width direction (e.g., the y-direction). The first metal layer 924 contacts the upper surface of the gate layer 310 within the boundary of the active area, and the second metal layer 926 contacts the upper surface of the gate layer 310 outside the lateral boundary 902 of the active area. Having the second metal layer 926 contact the upper surface of the gate layer 310 outside the active area can increase the distance between (i) the second metal layer 926 and (ii) the source electrical contact 342 and / or the drain electrical contact 344, which can reduce gate-to-source and gate-to-drain leakage.

[0075] Figure 10 is a layout diagram of a semiconductor device 1000 according to some examples. Figure 10 The semiconductor device 1000 further illustrates Figure 9 The semiconductor device 1000 may be referred to as a multi-finger device, where various components are electrically coupled together to form the semiconductor device 1000 . Figure 10 Active regions 1002, 1004 are illustrated. Isolation regions, such as shallow trench isolation (STI) regions, may define one or more boundaries of the active regions 1002, 1004. For example, the isolation region(s) may be outside the active regions 1002, 1004, where the active regions 1002, 1004 include the channel layer 306 and the barrier layer 308 between the isolation region(s).

[0076] Semiconductor device 1000 includes multiple gate layers 310 spanning active regions 1002 and 1004, as well as multiple source electrical contacts 342 and multiple drain electrical contacts 344 contacting active regions 1002 and 1004. Source electrical contacts 342 are electrically coupled together (not shown), and drain electrical contacts 344 are electrically coupled together (not shown). Gate electrical contacts include a first metal layer 1024 and a second metal layer 1026. First metal layer 1024 is on the respective gate layers 310 within the boundaries of the respective active regions 1002 and 1004. Second metal layer 1026 is on the gate layers 310 between and outside the active regions 1002 and 1004. Second metal layer 1026 electrically couples gate layers 310 together.

[0077] Figure 11 A cross-sectional view of a semiconductor device 1100 according to some examples is illustrated. In this example, the semiconductor device 1100 is or includes a HEMT. Additionally, the semiconductor device 1100 may be or include an enhancement-mode HEMT. Other examples may be or include other types of devices.

[0078] Figure 11 The semiconductor device 1100 includes Figure 3 At least some components of the semiconductor device 300 and a gate electrical contact 1122 are shown. The gate electrical contact 1122 extends through the first dielectric layer 320 and contacts the gate layer 310. A lateral portion of the gate electrical contact 1122 can be on and above the upper surface of the first dielectric layer 320. The gate electrical contact 1122 includes a first metal portion and a second metal portion. In the example shown, the first metal portion includes a first metal layer 1124, and the second metal portion includes a second metal layer 1126. The first metal layer 1124 can be conformal on the upper surface of the gate layer 310, on the sidewall surfaces of the first opening through the first dielectric layer 320, and on the upper surface of the first dielectric layer 320. The first metal layer 1124 contacts a first surface region of the upper surface of the gate layer 310. Second metal layer 1126 may be conformal on first metal layer 1124 and extend through an opening through first metal layer 1124 (through a second opening through first dielectric layer 320) to contact sidewall surfaces of gate layer 310. Second metal layer 1126 contacts a second surface region of the sidewall surfaces of gate layer 310.

[0079] Other aspects of the first metal layer 1124 and the second metal layer 1126 are respectively Figure 1The first metal layer 324 and the second metal layer 326 are similar. Specifically, the description of the surface area of ​​the gate layer 310 contacted by the metal layers 324 and 326, the junctions 334 and 336 formed by the metal layers 324 and 326 and the gate layer 310 and the energy barrier height and the materials of the metal layers 324 and 326 also applies to Figure 11 The first metal layer 1124 and the second metal layer 1126 are formed.

[0080] Figure 12 A cross-sectional view of a semiconductor device 1200 according to some examples is illustrated. In this example, the semiconductor device 1200 is or includes a HEMT. Additionally, the semiconductor device 1200 may be or include an enhancement-mode HEMT. Other examples may be or include other types of devices.

[0081] Figure 12 The semiconductor device 1200 includes Figure 3 At least some components of the semiconductor device 300 and a gate electrical contact 1222 are provided. The gate electrical contact 1222 extends through the first dielectric layer 320 and contacts the gate layer 310. A lateral portion of the gate electrical contact 1222 may be on and above the upper surface of the first dielectric layer 320. The gate electrical contact 1222 includes a first metal portion and a second metal portion. In the illustrated example, the first metal portion includes a first metal layer 1224, and the second metal portion includes a second metal layer 1226. The first metal layer 1224 may be conformal on the upper surface of the gate layer 310, the sidewall surfaces of the first opening through the first dielectric layer 320, and the upper surface of the first dielectric layer 320. The first metal layer 1224 contacts a first surface region of the upper surface of the gate layer 310. The second metal layer 1226 is on the sidewall surfaces of the gate layer 310, the sidewall surfaces of the second opening through the first dielectric layer 320, the upper surface of the first dielectric layer 320, and the first metal layer 1224. The first opening through the first dielectric layer 320 is separated from the second opening through the first dielectric layer 320. The second metal layer 1226 contacts a second surface region of the sidewall surface of the gate layer 310.

[0082] Other aspects of the first metal layer 1224 and the second metal layer 1226 are respectively Figure 1 The first metal layer 324 and the second metal layer 326 are similar. Specifically, the description of the surface area of ​​the gate layer 310 contacted by the metal layers 324 and 326, the junctions 334 and 336 formed by the metal layers 324 and 326 and the gate layer 310 and the energy barrier height and the materials of the metal layers 324 and 326 also applies to Figure 12 The first metal layer 1224 and the second metal layer 1226 are formed.

[0083] Figure 13A cross-sectional view of a semiconductor device 1300 according to some examples is illustrated. In this example, the semiconductor device 1300 is or includes a HEMT. Additionally, the semiconductor device 1300 may be or include an enhancement-mode HEMT. Other examples may be or include other types of devices.

[0084] Figure 13 The semiconductor device 1300 includes Figure 3 At least some components of the semiconductor device 300 and a gate electrical contact 1322 are shown. The gate electrical contact 1322 extends through the first dielectric layer 320 and contacts the gate layer 310. The gate electrical contact 1322 includes a first metal portion and a second metal portion. In the illustrated example, the first metal portion includes a first metal layer 1324, and the second metal portion includes a second metal layer 1326. The first metal layer 1324 may be on the upper surface of the gate layer 310 within an opening through the first dielectric layer 320. The first metal layer 1324 contacts a first surface region of the upper surface of the gate layer 310. The second metal layer 1326 may be on the first metal layer 1324 and on a sidewall surface of the gate layer 310 within the opening through the first dielectric layer 320. The second metal layer 1326 contacts a second surface region of the sidewall surface of the gate layer 310.

[0085] Other aspects of the first metal layer 1324 and the second metal layer 1326 are respectively Figure 1 The first metal layer 324 and the second metal layer 326 are similar. Specifically, the description of the surface area of ​​the gate layer 310 contacted by the metal layers 324 and 326, the junctions 334 and 336 formed by the metal layers 324 and 326 and the gate layer 310 and the energy barrier height and the materials of the metal layers 324 and 326 also applies to Figure 13 The first metal layer 1324 and the second metal layer 1326 are formed.

[0086] Figure 14 and Figure 15 is a perspective view of respective semiconductor devices 1400, 1500 according to some examples. The semiconductor devices 1400, 1500 may be Figure 11 、 Figure 12 and Figure 13 1. As shown in the figure, each of the semiconductor devices 1400, 1500 includes a channel layer 306, a barrier layer 308, a gate layer 310 and a drain electrical contact 344. The semiconductor devices 1400, 1500 include a corresponding gate electrical contact (which may correspond to Figure 11 、 Figure 12 and Figure 13), which has the upper surface shown corresponding to the above-mentioned reference plane 340. The gate electrical contacts may actually have different upper surfaces. Figure 14 and Figure 15 The gate electrical contact in includes a first metal layer corresponding to the first metal layers 1124, 1224, 1324, and includes a second metal layer corresponding to the second metal layers 1126, 1226, 1326, respectively. As described above, Figure 14 and Figure 15 The gate electrical contact in forms a junction with the gate layer 310. In addition, Figure 14 The semiconductor device 1400 further includes a source electrical contact 342 .

[0087] refer to Figure 14 , the gate electrical contact includes a first metal layer 1424 and a second metal layer 1426 . Figure 14 The illustration shows that the gate layer 310 extends beyond the lateral boundary 1402 of the active area (e.g., along the x-direction) in the channel width direction (e.g., the y-direction). The first metal layer 1424 contacts the upper surface of the gate layer 310 at least within the boundary of the active area, and the second metal layer 1426 contacts the sidewall surface of the gate layer 310 outside the lateral boundary 1402 of the active area. Having the second metal layer 1426 contact the sidewall surface of the gate layer 310 outside the active area can increase the distance between (i) the second metal layer 1426 and (ii) the source electrical contact 342 and / or the drain electrical contact 344, which can reduce gate-to-source and gate-to-drain leakage.

[0088] refer to Figure 15 , the gate electrical contact includes a first metal layer 1524 and a second metal layer 1526 . Figure 15 The illustration of shows the gate layer 310 extending from a lateral boundary of the active area (e.g., along the x-direction) to another lateral boundary of the active area (e.g., along another x-direction) in the channel width direction (e.g., the y-direction). Portions of the second metal layer 1526 contact sidewall surfaces of the gate layer 310 adjacent to the source electrical contact 1542, and where the sidewalls intersect with corresponding lateral boundaries of the active area. These intersections are illustrated as being at the corners of the gate layer 310, although it is noted that the gate layer can extend beyond the lateral boundaries of the active area. Portions of the second metal layer 1526 contacting the gate layer 310 can be repeated along the sidewall surfaces of the gate layer 310 in a similar manner.

[0089] One side of the source electrical contact 1542 is notched 1546 in the channel length direction (e.g., in the x-direction) corresponding to the location where the sidewall surface of the second metal layer 1526 contacts the gate layer 310. At the midpoint between the portions of the second metal layer 1526 that contact the sidewall surface of the gate layer 310, there is a first dimension 1552 (e.g., in the x-direction) between the sidewall surface of the source electrical contact 1542 (outside of any notches 1546) and the sidewall surface of the gate layer 310. There is a second dimension 1554 (e.g., in the x-direction) between the sidewall surface of the source electrical contact 1542 at the corresponding notch 846 and the adjacent sidewall surface of the corresponding portion of the second metal layer 1526 that contacts the sidewall surface of the gate layer 310. Second dimension 1554 is greater than first dimension 1552. Thus, the side of source electrical contact 1542 that contacts second metal layer 1526 in contact with gate layer 310 is correlated with the placement of source electrical contact 1542 so that source electrical contact 1542 is maintained at a greater distance from a portion of second metal layer 1526 than from first metal layer 1524. This type of correlation can result in lower gate-to-source current in regions adjacent to portions of second metal layer 1526. Additionally, the gate electrical contact can result in a lower gate current (I G ) by increasing the gate-to-source length (L GS ), the voltage drop in the gate-to-source length (e.g., current multiplied by the resistor voltage drop) increases, and the effective gate overdrive voltage (V GT ) decreases, which reduces the gate current (I G Furthermore, by having the second metal layer 1526 along the sidewall surface, any area of ​​the etched opening that may intersect the sidewall surface of the gate layer 310 may permit the second metal layer 1526 to be formed along the sidewall surface, and thus, photolithography alignment issues may be reduced.

[0090] Figure 16 A cross-sectional view of a semiconductor device 1600 according to some examples is illustrated. In this example, the semiconductor device 1600 is or includes a HEMT. Additionally, the semiconductor device 1600 may be or include an enhancement-mode HEMT. Other examples may be or include other types of devices.

[0091] Figure 16 The semiconductor device 1600 includes Figure 3At least some components of the semiconductor device 300 and a gate electrical contact 1622 are provided. The gate electrical contact 1622 extends through the first dielectric layer 320 and contacts the gate layer 310. A lateral portion of the gate electrical contact 1622 may be on and above the upper surface of the first dielectric layer 320. The gate electrical contact 1622 includes a first metal portion and a second metal portion. In the illustrated example, the gate electrical contact 1622 is a metal layer, wherein the first metal portion includes a first portion of the metal layer and the second metal portion includes a second portion of the metal layer. The metal layer of the gate electrical contact 1622 is on the upper surface and sidewall surfaces of the gate layer 310, the sidewall surfaces of the opening through the first dielectric layer 320, and the upper surface of the first dielectric layer 320. The first portion of the metal layer contacts a first surface region of the upper surface of the gate layer 310, and the second portion of the metal layer contacts a second surface region of the sidewall surfaces of the gate layer 310. In some examples, the first surface area (e.g., where the metal layer contacts the upper surface of gate layer 310) is larger than the second surface area (e.g., where the metal layer contacts the sidewall surface of gate layer 310). For example, the first surface area can be at least 10 times larger than the second surface area, such as in the range of 10 to 100 times larger than the second surface area.

[0092] A first metal portion of the gate electrical contact 1622 (e.g., a portion of the metal layer contacting the upper surface of the gate layer 310) forms a high-energy barrier height junction 334 with the first semiconductor portion of the gate layer 310, wherein the first metal portion contacts the first semiconductor portion of the gate layer 310. A second metal portion of the gate electrical contact 1622 (e.g., a portion of the metal layer contacting the sidewall surface of the gate layer 310) forms a low-energy barrier height junction 336 with the second semiconductor portion of the gate layer 310, wherein the second metal portion contacts the second semiconductor portion of the gate layer 310. In some examples, the high-energy barrier height junction 334 and the low-energy barrier height junction 336 can be as described in reference to FIG. Figure 3 As stated.

[0093] The first metal portion (e.g., the portion of the metal layer that contacts the upper surface of the gate layer 310) and the second metal portion (e.g., the portion of the metal layer that contacts the sidewall surface of the gate layer 310) can be the same metal. In some cases, the metal formed on the semiconductor material can react differently to the thermal treatment depending on whether the metal is on the upper surface or the sidewall surface of the semiconductor material. In some examples, the metal of the metal layer of the gate electrical contact 1622 reacts differently with the upper surface of the semiconductor material of the gate layer 310 than with the sidewall surface of the semiconductor material of the gate layer 310. For example, when undergoing a thermal treatment (such as annealing), the metal has more spiking through the sidewall surface than through the upper surface. The different reactions can result in the high energy barrier height junction 334 and the low energy barrier height junction 336 as described above. As an example, the gate layer 310 can be a magnesium-doped gallium nitride (GaN:Mg) layer, where the magnesium (Mg) is present at a concentration of 2×10 18 cm -3 The metal layer of the gate electrical contact 1622 may be titanium aluminum tungsten (TiAlW), titanium aluminum tungsten nitride (TiAlWN), or an alloy thereof. Titanium aluminum tungsten (TiAlW) and titanium aluminum tungsten nitride (TiAlWN) may allow aluminum (Al) spikes to form on the sidewall surface of the semiconductor material of the gate layer 310.

[0094] Figure 17 is a perspective view of a semiconductor device 1700 according to some examples. The semiconductor device 1700 may be Figure 16 16. The semiconductor device 1700 shown includes a channel layer 306, a barrier layer 308, a gate layer 310, a source electrical contact 342, a drain electrical contact 344, and a gate electrical contact 1722. The gate electrical contact 1722 includes a first metal portion on the upper surface of the gate layer 310 and a second metal portion on the sidewall surface of the gate layer 310. Figure 17 The illustration of shows that the gate layer 310 extends beyond the lateral boundary 1702 of the active area (e.g., along the x-direction) in the channel width direction (e.g., the y-direction). The first metal portion contacts the upper surface of the gate layer 310 at least within the boundary of the active area, and the second metal portion contacts the sidewall surface of the gate layer 310 outside the lateral boundary 1702 of the active area. Having the second metal portion contact the sidewall surface of the gate layer 310 outside the active area can increase the distance between (i) the second metal portion and (ii) the source electrical contact 342 and / or the drain electrical contact 344, which can reduce gate-to-source and gate-to-drain leakage. The gate electrical contact 1722 can cause the gate current (I G ) by increasing the gate-to-source length (L GS), the voltage drop in the gate-to-source length (e.g., current multiplied by the resistor voltage drop) increases, and the effective gate overdrive voltage (V GT ) decreases, which reduces the gate current (I G ).

[0095] Figure 18 A cross-sectional view of a semiconductor device 1800 according to some examples is illustrated. In this example, the semiconductor device 1800 is or includes a HEMT. Additionally, the semiconductor device 1800 may be or include an enhancement-mode HEMT. Other examples may be or include other types of devices.

[0096] Figure 18 The semiconductor device 1800 includes Figure 3 At least some components of the semiconductor device 300 of FIG. 1 and including the highly doped region 1802 and the gate electrical contact 1822. As described above, the gate layer 310 may be doped with a dopant (eg, a p-type dopant). Figure 18 In the semiconductor device 1800, the gate layer 310 further includes a highly doped region 1802 having an activated dopant concentration greater than any activated dopant concentration in the remainder of the gate layer 310. The highly doped region 1802 extends from a portion of the upper surface of the gate layer 310 into the gate layer 310. The highly doped region 1802 may be doped with a p-type dopant or an n-type dopant, which may be the same conductivity type dopant as or a different conductivity type dopant than the dopant in the remainder of the gate layer 310.

[0097] Gate electrical contact 1822 extends through first dielectric layer 320 and contacts gate layer 310. A lateral portion of gate electrical contact 1822 may be on and above the upper surface of first dielectric layer 320. Gate electrical contact 1822 includes a first metal portion and a second metal portion. In the illustrated example, gate electrical contact 1822 is a metal layer, wherein the first metal portion comprises a first portion of the metal layer, and the second metal portion comprises a second portion of the metal layer. The metal layer of gate electrical contact 1822 conformally extends over the upper surface of gate layer 310, the sidewall surfaces of the opening through first dielectric layer 320, and the upper surface of first dielectric layer 320. The first portion of the metal layer contacts a first surface region of the upper surface of gate layer 310 that is outside the portion of the upper surface of gate layer 310 from which highly doped region 1802 extends. The second portion of the metal layer contacts a second surface area of ​​the upper surface of gate layer 310, which is the portion of the upper surface of gate layer 310 from which highly doped region 1802 extends. In some examples, the first surface area (e.g., where the metal layer contacts the upper surface of gate layer 310 outside of highly doped region 1802) is larger than the second surface area (e.g., where the metal layer contacts the upper surface of gate layer 310 corresponding to highly doped region 1802). For example, the first surface area can be at least 10 times larger than the second surface area, such as in the range of 10 to 100 times larger than the second surface area.

[0098] A first metal portion of the gate electrical contact 1822 (e.g., a portion of the metal layer contacting the upper surface of the gate layer 310 outside the highly doped region 1802) forms a high-energy barrier height junction 334 with the first semiconductor portion of the gate layer 310, wherein the first metal portion contacts the first semiconductor portion of the gate layer 310. A second metal portion of the gate electrical contact 1822 (e.g., a portion of the metal layer contacting the upper surface of the gate layer 310 corresponding to the highly doped region 1802) forms a low-energy barrier height junction 336 with the second semiconductor portion of the gate layer 310 (e.g., the highly doped region 1802). In some examples, the high-energy barrier height junction 334 and the low-energy barrier height junction 336 may be formed as described with reference to FIG. Figure 3 As stated.

[0099] The first metal portion (e.g., the portion of the metal layer that contacts the upper surface of the gate layer 310 outside the highly doped region 1802) and the second metal portion (e.g., the portion of the metal layer that contacts the upper surface of the gate layer 310 corresponding to the highly doped region 1802) can be the same metal. Different doping of the gate layer 310 (e.g., the activated dopant concentration of the highly doped region 1802 compared to the activated dopant concentration of the remaining portion of the gate layer 310) can result in the high energy barrier height junction 334 and the low energy barrier height junction 336 as described above, such as when the first metal portion and the second metal portion are the same metal. As an example, the gate layer 310 can be a gallium nitride (GaN) layer; the highly doped region 1802 can be a 2×10 19 cm -3 The remaining portion of the gate layer 310 can be doped with magnesium (Mg) at an activation concentration of 2×10 18 cm -3 and the metal layer of the gate electrical contact 1822 may be titanium aluminum tungsten (TiAlW), titanium aluminum tungsten nitride (TiAlWN) or an alloy thereof.

[0100] Figure 19 A cross-sectional view of a semiconductor device 1900 according to some examples is illustrated. In this example, the semiconductor device 1900 is or includes a HEMT. Additionally, the semiconductor device 1900 may be or include an enhancement-mode HEMT. Other examples may be or include other types of devices.

[0101] Figure 19 The semiconductor device 1900 includes Figure 3 The dielectric layer 1902 between the gate layer 310 and the first metal layer 324 and at least some components of the semiconductor device 300 is shown. The dielectric layer 1902 can be any dielectric layer, such as an oxide or a nitride, and more specifically, can be silicon oxide. The dielectric layer 1902 can have a thickness in a range from greater than 0 nanometers (nm) to less than or equal to 3 nm (e.g., in a direction perpendicular to the upper surface of the gate layer 310). For example, the dielectric layer 1902 can be a single layer.

[0102] The dielectric layer 1902 may be between the first metal portion of the gate electrical contact and the first semiconductor portion of the gate layer 310. The dielectric layer 1902 may be included in any of the previously described semiconductor devices 300, 400, 500, 1100, 1200, 1300, 1600, 1800. The dielectric layer 1902 may increase the energy barrier height of the high energy barrier height junction 334. In addition, the dielectric layer 1902 may further reduce the gate current (I G ), which can compensate for the increase in gate current due to the low energy barrier height junction.

[0103] Figure 20 Made based on some examples Figure 3 Flowchart of method 2000 of a semiconductor device 300 . Figure 20 The method 2000 is composed of Figures 21 to 26 The diagram is shown in Figures 21 to 26 is described in the context of Figures 21 to 26 Cross-sectional views of a semiconductor device 300 at various stages of fabrication are illustrated.

[0104] refer to Figure 20 Box 2002 and Figure 21 , one or more transition layers 304 are formed on and above semiconductor substrate 302. At block 2004, a channel layer 306 is formed on and above the transition layer(s) 304. At block 2006, a barrier layer 308 is formed on and above the channel layer 306. In some examples, the transition layer(s) 304, the channel layer 306, and the barrier layer 308 can be formed using any suitable deposition process, which can also be an epitaxial growth process. For example, the transition layer(s) 304, the channel layer 306, and the barrier layer 308 can each be epitaxially grown using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD), or another epitaxial process. The materials of semiconductor substrate 302, the transition layer(s) 304, the channel layer 306, and the barrier layer 308 can be as described above.

[0105] In block 2008, a gate layer 310 is formed on and above the barrier layer 308. In some examples, the gate layer 310 can be epitaxially grown, such as by MOCVD, MBE, LPCVD, plasma enhanced chemical vapor deposition (PECVD), atomic layer epitaxy, or another epitaxial process. The gate layer 310 can be doped in situ during deposition (e.g., epitaxial growth) or doped after deposition by implantation (e.g., ion implantation). After deposition, the gate layer 310 is patterned. The gate layer 310 can be patterned using appropriate photolithography and etching processes. For example, to pattern the gate layer 310, a photoresist is deposited (e.g., by spin coating) on ​​and / or above the semiconductor substrate 302 (e.g., on and / or above the gate layer 310) and patterned using photolithography. The photoresist is patterned to remain in an area corresponding to the area where the gate structure G is to be formed. An etching process, such as anisotropic etching, such as reactive ion etching (RIE), is performed using the patterned photoresist as a mask to pattern the gate layer 310. After the etching process, the photoresist is removed, such as by ashing. The material of the gate layer 310, any dopant, and any concentration of the dopant can be as described above.

[0106] In block 2010, a first dielectric layer 320 is formed on and over gate layer 310 and barrier layer 308. First dielectric layer 320 may be deposited using any suitable deposition process, such as LPCVD, PECVD, or the like. The material(s) of first dielectric layer 320 may be as described above. First dielectric layer 320 may be planarized, such as by chemical mechanical polishing (CMP).

[0107] Reference Box 2012 and Figure 22 , forming a first opening 2202 through the first dielectric layer 320 to the gate layer 310. The first opening 2202 is formed to expose the upper surface of the gate layer 310. The first opening 2202 can be formed using appropriate photolithography and etching processes. For example, to form the first opening 2202, a photoresist 2204 is deposited (e.g., by spin coating) on ​​and / or over the semiconductor substrate 302 (e.g., on and / or over the first dielectric layer 320) and patterned using photolithography. The photoresist 2204 is patterned to expose the area where the first opening 2202 is to be formed. By using the patterned photoresist 2204 as a mask, an etching process, such as anisotropic etching such as RIE, is performed to form the first opening 2202. After the etching process, the photoresist 2204 is removed, such as by ashing.

[0108] Reference Box 2014 and Figure 23 , first metal layer 324 is formed in first opening 2202 and on and above gate layer 310. First metal layer 324 is conformally deposited on and above the upper surface of first dielectric layer 320, along the sidewall surfaces of first dielectric layer 320 defining first opening 2202, and on and above the upper surface of gate layer 310 exposed by first opening 2202. First metal layer 324 can be deposited using any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. First metal layer 324 may include or be the material described above.

[0109] Reference Box 2016 and Figure 24, a second opening 2402 is formed through the first metal layer 324 and the first opening 2202 to the gate layer 310. The second opening 2402 is formed to expose the upper surface of the gate layer 310. The second opening 2402 can be formed using appropriate photolithography and etching processes. For example, to form the second opening 2402, a photoresist 2404 is deposited (e.g., by spin coating) on ​​and / or above the semiconductor substrate 302 (e.g., on and / or above the first metal layer 324) and patterned using photolithography. The photoresist 2404 is patterned to expose the area where the second opening 2402 is to be formed. By using the patterned photoresist 2404 as a mask, an etching process, such as anisotropic etching such as RIE, is performed to form the second opening 2402. After the etching process, the photoresist 2404 is removed, such as by ashing.

[0110] Reference Box 2018 and Figure 25 , second metal layer 326 is formed on and over first metal layer 324 and on and over gate layer 310 in second opening 2402. Second metal layer 326 is conformally deposited on and over first metal layer 324, along sidewall surfaces of first dielectric layer 320 and first metal layer 324 defining second opening 2402, and on and over the upper surface of gate layer 310 exposed by second opening 2402. Second metal layer 326 may be deposited using any suitable deposition process, such as CVD, PVD, etc. Second metal layer 326 may include or be the material described above.

[0111] Reference Box 2020 and Figure 26 , first metal layer 324 and second metal layer 326 are patterned into gate electrical contact 322. First metal layer 324 and second metal layer 326 can be patterned using appropriate photolithography and etching processes. For example, in order to pattern first metal layer 324 and second metal layer 326 into gate electrical contact 322, photoresist 2602 is deposited (e.g., by spin coating) on ​​and / or over semiconductor substrate 302 (e.g., on and / or over second metal layer 326) and patterned using photolithography. Photoresist 2602 is patterned to remain in an area corresponding to the area where gate electrical contact 322 is to be formed. By using patterned photoresist 2602 as a mask, an etching process, such as anisotropic etching such as RIE, is performed to pattern first metal layer 324 and second metal layer 326 into gate electrical contact 322. After the etching process, photoresist 2602 is removed, such as by ashing.

[0112] Reference Box 2022 and Figure 3, source electrical contact 342 and drain electrical contact 344 are formed through first dielectric layer 320, and metal lines 352, 354 are formed on and above first dielectric layer 320. For example, a contact opening can be formed through first dielectric layer 320 to channel layer 306. Appropriate photolithography and etching processes can be used to form the contact opening. One or more metals are deposited into the contact opening and deposited on and above the upper surface of first dielectric layer 320. The one or more metals deposited into the contact opening form source electrical contact 342 and drain electrical contact 344. Appropriate deposition process(es) (such as CVD, PVD, etc.) can be used to deposit the metal(s). The metal(s) above the upper surface of first dielectric layer 320 are patterned into metal lines 352, 354. Metal lines 352, 354 can be patterned using appropriate photolithography and etching processes. At block 2024, a second dielectric layer 360 is formed on and over gate electrical contact 322, metal lines 352, 354, and first dielectric layer 320. Second dielectric layer 360 may be deposited using any suitable deposition process, such as PECVD, etc. Second dielectric layer 360 may be planarized, such as by CMP.

[0113] In block 2026, metal vias 362, 364 are formed through the second dielectric layer 360, and metal lines 372, 374 are formed on and above the second dielectric layer 360. Appropriate photolithography and etching processes can be used to form openings through the second dielectric layer 360 to the metal lines 352, 354. The metal(s) for the metal vias 362, 364 and metal lines 372, 374 are deposited above and in the openings through the second dielectric layer 360. The metal(s) can be deposited using one or more appropriate deposition processes (e.g., CVD, PVD, etc.). The metal(s) can be patterned into the metal lines 372, 374 using appropriate photolithography and etching processes. The metal(s) below the metal lines 372, 374 and in the corresponding openings through the second dielectric layer 360 form the metal vias 362, 364.

[0114] In view of the foregoing description, the photolithography and etching processes are briefly described below, where appropriate.

[0115] Figure 27 Made based on some examples Figure 4 2700 of a method of the semiconductor device 400. Figure 27 Method 2700 by Figures 28 to 32 The diagram is shown in Figures 28 to 32 Describe in the context of Figures 28 to 32 Cross-sectional views of a semiconductor device 400 at various stages of fabrication are illustrated.

[0116] As reference Figure 21 As described, processing is performed at blocks 2002, 2004, 2006, 2008, and 2010. Referring to blocks 2702 and Figure 28 , a first opening 2802 and a second opening 2804 are formed through the first dielectric layer 320 to the gate layer 310. The first opening 2802 and the second opening 2804 are formed to expose the upper surface of the gate layer 310. The first opening 2802 and the second opening 2804 can be formed using appropriate photolithography and etching processes (for example, using a photoresist 2810).

[0117] Reference box 2704 and Figure 29 , first metal layer 424 is formed in first opening 2802 and second opening 2804 and on and over gate layer 310. First metal layer 424 is conformally deposited on and over the upper surface of first dielectric layer 320, along sidewall surfaces of first dielectric layer 320 defining first opening 2802 and second opening 2804, and on and over the upper surface of gate layer 310 exposed by first opening 2802 and second opening 2804. Any suitable deposition process may be used to deposit first metal layer 424. First metal layer 424 may include or be the material described above.

[0118] Reference box 2706 and Figure 30 , patterning the first metal layer 424. The first metal layer 424 is patterned to remove the first metal layer from the second opening 2804 through the first dielectric layer 320. The first metal layer 424 may be patterned using appropriate photolithography and etching processes (eg, using the photoresist 3002).

[0119] Reference box 2708 and Figure 31 , second metal layer 426 is formed on and over first metal layer 424 and on and over gate layer 310 in second opening 2804. Second metal layer 426 is conformally deposited on and over first metal layer 424, along sidewall surfaces of first dielectric layer 320 defining second opening 2804, and on and over the upper surface of gate layer 310 exposed by second opening 2804. Any suitable deposition process may be used to deposit second metal layer 426. Second metal layer 426 may include or be the materials described above.

[0120] Reference box 2710 and Figure 32 , the first metal layer 424 and the second metal layer 426 are patterned into the gate electrical contact 422. The first metal layer 424 and the second metal layer 426 can be patterned using appropriate photolithography and etching processes (eg, using photoresist 3202). Figure 3As described, processing continues at blocks 2022 , 2024 , and 2026 .

[0121] Figure 33 Made based on some examples Figure 5 3300 of a method of semiconductor device 500 . Figure 33 Method 3300 by Figures 34 to 38 The diagram is shown in Figures 34 to 38 Describe in the context of Figures 34 to 38 Cross-sectional views of a semiconductor device 500 at various stages of fabrication are illustrated.

[0122] As reference Figure 21 As described above, processing is performed at blocks 2002, 2004, and 2006. Referring to blocks 3302 and Figure 34 , gate layer 310 is formed on and above barrier layer 308. Gate layer 310 can be deposited using any suitable deposition process. Gate layer 310 can include or be the materials described above. At block 3304, first metal layer 524 is formed on and above gate layer 310. First metal layer 524 can be deposited using any suitable deposition process. First metal layer 524 can include or be the materials described above.

[0123] Reference box 3306 and Figure 35 , the first metal layer 524 is patterned. The first metal layer 524 is patterned to remove the first metal layer 524 from the area above the gate layer 310 that will form part of the gate structure. The first metal layer 524 can be patterned using appropriate photolithography and etching processes (e.g., using photoresist 3502).

[0124] Reference box 3308 and Figure 36 , second metal layer 526 is formed on and over gate layer 310 and first metal layer 524. Any suitable deposition process may be used to deposit second metal layer 526. Second metal layer 526 may include or be the materials described above.

[0125] Reference box 3310 and Figure 37 , the first metal layer 524 and the second metal layer 526 are patterned into a gate electrical contact 522, and the gate layer 310 is patterned. The first metal layer 524, the second metal layer 526, and the gate layer 310 can be patterned using appropriate photolithography and etching processes (e.g., using photoresist 3702). The patterning of the second metal layer 526, the first metal layer 524, and the gate layer 310 can form a gate electrical contact 522 that is self-aligned with the gate layer 310.

[0126] Reference box 3312 and Figure 38, barrier layer 308, and along gate electrical contact 522 to form a first dielectric layer 320. Gate electrical contact 522 can be exposed through the upper surface of first dielectric layer 320. Any suitable deposition process can be used to deposit first dielectric layer 320. The material(s) of first dielectric layer 320 can be as described above. First dielectric layer 320 can be planarized, such as by CMP, which can cause gate electrical contact 522 to be exposed through the upper surface of first dielectric layer 320. As described in reference Figure 3 As described, processing continues at blocks 2022 , 2024 , and 2026 .

[0127] Figure 39 Made based on some examples Figure 11 Flowchart of method 3900 of semiconductor device 1100. Figure 39 Method 3900 by Figures 40 to 42 The diagram is shown in Figures 40 to 42 Describe in the context of Figures 40 to 42 Cross-sectional views of a semiconductor device 1100 at various stages of fabrication are illustrated.

[0128] Processing is performed at blocks 2002, 2004, 2006, 2008, 2010, 2012, and 2014, as described with respect to Figure 21 、 Figure 22 and Figure 23 (the first metal layer 1124 is used as the first metal layer 324). Figure 40 A second opening 4002 is formed through the first metal layer 1124 and the first dielectric layer 320 to the gate layer 310. The second opening 4002 is formed to expose the sidewall surface of the gate layer 310. The second opening 4002 can be formed using appropriate photolithography and etching processes (e.g., using a photoresist 4004).

[0129] Reference box 3904 and Figure 41 , second metal layer 1126 is formed on and over first metal layer 1124 and on the sidewall surfaces of gate layer 310 in second opening 4002. Second metal layer 1126 is conformally deposited on and over first metal layer 1124 and along the sidewall surfaces of first dielectric layer 320, first metal layer 1124, and gate layer 310 defining second opening 4002. Any suitable deposition process may be used to deposit second metal layer 1126. Second metal layer 1126 may include or be the materials described above.

[0130] Reference box 3906 and Figure 42, the first metal layer 1124 and the second metal layer 1126 are patterned into the gate electrical contact 1122. The first metal layer 1124 and the second metal layer 1126 can be patterned using appropriate photolithography and etching processes (e.g., using photoresist 4202). Figure 3 As described, processing continues at blocks 2022 , 2024 , and 2026 .

[0131] Figure 43 Made based on some examples Figure 12 4300 of a method for semiconductor device 1200. Figure 43 Method 4300 by Figures 44 to 48 The diagram is shown in Figures 44 to 48 Describe in the context of Figures 44 to 48 Cross-sectional views of a semiconductor device 1200 at various stages of fabrication are illustrated.

[0132] As reference Figure 21 As described, processing is performed at blocks 2002, 2004, 2006, 2008, and 2010. Referring to blocks 4302 and Figure 44 A first opening 4402 and a second opening 4404 are formed through the first dielectric layer 320 to the gate layer 310. The first opening 4402 is formed to expose the upper surface of the gate layer 310. The second opening 4404 is formed to expose the sidewall surface of the gate layer 310. The first opening 4402 and the second opening 4404 can be formed using appropriate photolithography and etching processes (e.g., using a photoresist 4410).

[0133] Reference box 4304 and Figure 45 , first metal layer 1224 is formed in first opening 4402 and second opening 4404 and on and over gate layer 310. First metal layer 1224 is conformally deposited on and over the upper surface of first dielectric layer 320, along the sidewall surfaces of first dielectric layer 320 defining first opening 4402, on and over the upper surface of gate layer 310 exposed by first opening 4402, and along the sidewall surfaces of first dielectric layer 320 and gate layer 310 defining second opening 4404. Any suitable deposition process may be used to deposit first metal layer 1224. First metal layer 1224 may include or be the material described above.

[0134] Reference box 4306 and Figure 46 , the first metal layer 1224 is patterned. The first metal layer 1224 is patterned to remove the first metal layer 1224 from the second opening 4404 through the first dielectric layer 320. The first metal layer 1224 may be patterned using appropriate photolithography and etching processes (eg, using photoresist 4602).

[0135] Reference box 4308 and Figure 47 , second metal layer 1226 is formed on and over first metal layer 1224 and along the sidewall surfaces of gate layer 310 in second opening 4404. Second metal layer 1226 is conformally deposited on and over first metal layer 1224 and along the sidewall surfaces of first dielectric layer 320 and gate layer 310 defining second opening 4404. Any suitable deposition process may be used to deposit second metal layer 1226. Second metal layer 1226 may include or be the material described above.

[0136] Reference box 4310 and Figure 48 , the first metal layer 1224 and the second metal layer 1226 are patterned into the gate electrical contact 1222. The first metal layer 1224 and the second metal layer 1226 can be patterned using appropriate photolithography and etching processes (e.g., using photoresist 4802). Figure 3 As described, processing continues at blocks 2022 , 2024 , and 2026 .

[0137] Figure 49 Made based on some examples Figure 13 Flowchart of method 4900 of semiconductor device 1300. Figure 49 Method 4900 by Figures 50 to 53 The diagram is shown in Figures 50 to 53 Describe in the context of Figures 50 to 53 Cross-sectional views of a semiconductor device 1300 at various stages of fabrication are illustrated.

[0138] Processing as reference Figure 21 The blocks 2002, 2004, 2006 and the reference Figure 34 The above blocks 3302 and 3304 are performed (the first metal layer 1324 is used as the first metal layer 524). Figure 50 , the first metal layer 1324 and the gate layer 310 are patterned, such as having an opening 5002 therethrough. This patterning forms the sidewall surface of the gate layer 310, which will form part of the gate structure. The first metal layer 1324 and the gate layer can be patterned using appropriate photolithography and etching processes (e.g., using photoresist 5004).

[0139] Reference box 4904 and Figure 51 , second metal layer 1326 is formed on and above gate layer 310 and first metal layer 1324. Second metal layer 1326 is formed in opening 5002 and along the sidewall surfaces of gate layer 310. Any suitable deposition process may be used to deposit second metal layer 1326. Second metal layer 1326 may include or be the materials described above.

[0140] Reference box 4906 and Figure 52 , the first metal layer 1324 and the second metal layer 1326 are patterned into a gate electrical contact 1322, and the gate layer 310 is patterned. The first metal layer 1324, the second metal layer 1326, and the gate layer 310 can be patterned using appropriate photolithography and etching processes (e.g., using photoresist 5202). The patterning of the second metal layer 1326, the first metal layer 1324, and the gate layer 310 can form a gate electrical contact 1322 that is self-aligned with the gate layer 310.

[0141] Reference box 4908 and Figure 53 , a first dielectric layer 320 is formed on and above the barrier layer 308 and along the gate electrical contact 1322. The gate electrical contact 1322 can be exposed through the upper surface of the first dielectric layer 320. The first dielectric layer 320 can be deposited using any suitable deposition process. The material(s) of the first dielectric layer 320 can be as described above. The first dielectric layer 320 can be planarized, such as by CMP, which can cause the gate electrical contact 1322 to be exposed through the upper surface of the first dielectric layer 320. As described in reference Figure 3 As described, processing continues at blocks 2022 , 2024 , and 2026 .

[0142] Figure 54 Made based on some examples Figure 16 5400 of a method for a semiconductor device 1600 . Figure 54 Method 5400 by Figures 55 to 57 The diagram is shown in Figures 55 to 57 Describe in the context of Figures 55 to 57 Cross-sectional views of a semiconductor device 1600 at various stages of fabrication are illustrated.

[0143] As reference Figure 21 As described, processing is performed at blocks 2002, 2004, 2006, 2008, and 2010. Referring to blocks 5402 and Figure 55 An opening 5502 is formed through the first dielectric layer 320 to the gate layer 310. The opening 5502 is formed to expose the upper surface and sidewall surfaces of the gate layer 310. The opening 5502 can be formed using appropriate photolithography and etching processes (eg, using a photoresist 5504).

[0144] Reference box 5404 and Figure 56, metal layer 1622 is formed in opening 5502, on and above the upper surface of gate layer 310, and along the sidewall surfaces of gate layer 310. Metal layer 1622 is conformally deposited on and above the upper surface of first dielectric layer 320, along the sidewall surfaces of first dielectric layer 320 defining opening 5502, and on and above the upper surface and sidewall surfaces of gate layer 310 exposed by opening 5502. Metal layer 1622 may be deposited using any suitable deposition process. Metal layer 1622 may include or be the materials described above.

[0145] Referring to box 5406, a thermal process is performed. The thermal process can be an annealing process (e.g., high temperature thermal annealing or laser annealing), or can be any process performed at a high temperature (e.g., deposition or etching). The process temperature of the thermal process can be higher than 600°C, such as in the range of 600°C to 800°C. The thermal process can cause more spikes in the metal layer 1622 in the sidewall surface of the gate layer 310 compared to the upper surface of the gate layer 310. The thermal process can be performed subsequently in method 5400. A thermal process can also be performed to activate dopants, such as dopants in the gate layer 310. The activation temperature can depend on how the dopants are introduced. For example, activation of dopants introduced by ion implantation can be performed at a higher temperature than dopants introduced during epitaxial growth.

[0146] Reference box 5408 and Figure 57 , the metal layer 1622 is patterned into a gate electrical contact 1622. The metal layer 1622 may be patterned using appropriate photolithography and etching processes (eg, using photoresist 5702). Figure 3 As described, processing continues at blocks 2022 , 2024 , and 2026 .

[0147] Figure 58 Made based on some examples Figure 18 5800 of a method for semiconductor device 1800 . Figure 58 Method 5800 by Figures 59 to 61 The diagram is shown in Figures 59 to 61 Describe in the context of Figures 59 to 61 Cross-sectional views of a semiconductor device 1800 at various stages of fabrication are illustrated.

[0148] As reference Figure 21 and Figure 22 As described, processing is performed at blocks 2002, 2004, 2006, 2008, 2010, and 2012. Figure 58, dopants are implanted into a portion of gate layer 310 exposed through opening 2202. The implanted dopants form highly doped regions 1802 in gate layer 310. For example, to implant the dopants, photoresist 5902 is deposited (e.g., by spin coating) on ​​and / or over semiconductor substrate 302 (e.g., on and / or over gate layer 310 and first dielectric layer 320) and patterned using photolithography. Photoresist 5902 is patterned to have openings 5904 to expose a portion of gate layer 310 where highly doped regions 1802 are to be formed (further exposed through opening 2202). Utilizing patterned photoresist 5902, using patterned photoresist 5902 as a mask, an implantation process is performed to implant dopants into gate layer 310, thereby forming highly doped regions 1802. After the implantation process, photoresist 5902 is removed, such as by ashing. Dopants and concentrations may be as described above. Implanting the highly doped region 1802 may permit easier formation of low energy barrier height junctions.

[0149] Reference box 5804 and Figure 60 , metal layer 1822 is formed in opening 2202 and on and above the upper surface of gate layer 310. Metal layer 1822 is conformally deposited on and above the upper surface of first dielectric layer 320, along the sidewall surfaces of first dielectric layer 320 defining opening 2202, and on and above the upper surface of gate layer 310 exposed by opening 2202. Metal layer 1822 may be deposited using any suitable deposition process. Metal layer 1822 may include or be the materials described above.

[0150] Reference box 5806 and Figure 61 , the metal layer 1822 is patterned into a gate electrical contact 1822. The metal layer 1822 can be patterned using appropriate photolithography and etching processes (e.g., using photoresist 6102). Thus, a single metal deposition process and a single patterning process can be used to form the gate electrical contact 1822. As shown in FIG. Figure 3 As described, processing continues at blocks 2022 , 2024 , and 2026 .

[0151] In any of the foregoing methods, the source electrical contact 342 and the drain electrical contact 344 can be formed after forming the gate layer 310 in a gate first process, or before forming the gate layer 310 in a gate last process. In such examples, block 2022 can be performed first, followed by forming an opening through the first dielectric layer 320, and then forming the gate layer 310 through the opening.

[0152] Any of the foregoing methods may also be modified to form dielectric layer 1902, such as Figure 19As shown. The dielectric layer 1902 can be deposited or formed on the gate layer 310 after the gate layer 310 is deposited and before the first metal layer is deposited. For example, the dielectric layer 1902 can be formed on Figure 21 on gate layer 310 in (wherein first dielectric layer 320 is subsequently formed on and over dielectric layer 1902) or formed on Figure 34 310 in the embodiment of the present invention (wherein the first metal layer 524 is formed on and above the dielectric layer 1902). The dielectric layer 1902 may be deposited or formed by oxidation, PECVD, atomic layer deposition (ALD), etc. Any etching used to form the opening in which the first metal layer is to be formed may expose the dielectric layer 1902 instead of the gate layer 310 (e.g., in the embodiment of the present invention). Figure 22 and Figure 28 Any etching (e.g., in Figure 24 、 Figure 30 、 Figure 35 ) The dielectric layer 1902 may be removed from where the second metal layer contacts the gate layer 310. In some examples, the dielectric layer 1902 may be removed from where the second metal layer contacts the gate layer 310. Figure 59 An etching process is performed before or after the implantation of the gate electrical contact to remove dielectric layer 1902 from where the second metal portion of the gate electrical contact contacts gate layer 310, with photoresist 5902 further serving as a mask for the etching process. In some examples, the second metal layer or the second metal portion of the gate electrical contact contacts sidewall surfaces of gate layer 310, and therefore, further etching may not be required for the second metal layer or the second metal portion to remove dielectric layer 1902 to contact gate layer 310. Other modifications to these methods are possible.

[0153] As used herein, the term "couple" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, if the intermediate component C does not change the functional relationship between device A and device B, device A is coupled to device B via the intermediate component C, such that device B is controlled by device A via the control signal generated by device A.

[0154] Additionally, in this specification, the recitation “based on” means “based at least in part on.” Thus, if X is based on Y, then X may be a function of Y and any number of other factors.

[0155] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform the function, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be programmable through the device's firmware and / or software, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0156] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components, or to the termination thereof.

[0157] Circuits or devices described herein as including certain components may instead be adapted to be coupled with these components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacturing (e.g., by an end user and / or a third party) to form the described structure.

[0158] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used with little or no change to the remaining circuitry. For example, field effect transistors ("FETs") (such as n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion mode devices, extended drain mode devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0159] The control input of a transistor and its current terminals may be mentioned in the claims. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0160] References herein to a FET being “on” or “enabled” mean that the FET’s conduction channel is present and drain current can flow through the FET. References herein to a FET being “off” or “disabled” mean that the conduction channel is absent and, therefore, drain current cannot flow through the FET. However, an “off” FET can allow current to flow through the transistor’s body diode.

[0161] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available before the components were replaced. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can be replaced by multiple resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component can be replaced by multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0162] Although some elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other example embodiments, more or fewer features may be incorporated into the integrated circuit. In addition, some or all features illustrated as external to the integrated circuit may be included in the integrated circuit, and / or some features illustrated as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0163] The foregoing use of the term "ground" includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0164] In this specification, unless otherwise stated, “about,” “approximately,” or “substantially” before a parameter means within a range of + / - 10% of the parameter, or if the parameter is zero, within a reasonable range around zero.

[0165] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

[0166] Although various examples have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device comprising: Semiconductor substrate; a drain electrical contact on the semiconductor substrate; a source electrical contact on the semiconductor substrate; a barrier layer over a channel region of the semiconductor substrate between the drain electrical contact and the source electrical contact; a gate layer above the barrier layer, the gate layer comprising a first semiconductor portion and a second semiconductor portion; as well as A gate electrical contact contacts the gate layer, the gate electrical contact comprising a first metal portion and a second metal portion, the first metal portion forming a first junction with the first semiconductor portion, the second metal portion forming a second junction with the second semiconductor portion, the first junction and the second junction having different energy barrier heights.

2. The semiconductor device of claim 1, wherein the first junction has a first energy barrier height, the second junction has a second energy barrier height, the first energy barrier height is at least 1.7 electron volts (eV), and the second energy barrier height is less than 1.7 eV.

3. The semiconductor device according to claim 1, wherein: The first junction is a Schottky junction; and The second junction is an ohmic junction.

4. The semiconductor device according to claim 1, wherein: The first junction is a first Schottky junction; and The second junction is a second Schottky junction. 5 . The semiconductor device of claim 1 , wherein the first metal portion comprises a metal material different from a metal material of the second metal portion.

6. The semiconductor device of claim 5 , wherein the first metal portion and the second metal portion include at least one of the following: titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), titanium tungsten aluminum (TiWAl), or titanium aluminum nitride (TiAlN).

7. The semiconductor device of claim 1 , wherein the first metal portion and the second metal portion comprise the same metal material, the metal material comprising at least one of the following: titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), titanium tungsten aluminum (TiWAl), or titanium aluminum nitride (TiAlN).

8. The semiconductor device according to claim 5, wherein: The first metal portion is above a first surface of the gate layer parallel to a surface of the barrier layer, the first metal portion being above the first semiconductor portion at the first surface; and The second metal portion is over the first surface, the second metal portion contacting the second semiconductor portion at the first surface. 9 . The semiconductor device of claim 8 , wherein the second metal portion is laterally outside an active region of the semiconductor substrate, the gate layer being on the active region.

10. The semiconductor device according to claim 8, wherein: the second metal portion being adjacent the source electrical contact over the first surface; and The source electrical contact is notched on a side adjacent to the gate layer and corresponding to a location in the channel length direction where the second metal portion contacts the first surface.

11. The semiconductor device according to claim 5, wherein: The first metal portion is above a first surface of the gate layer parallel to a surface of the barrier layer, the first metal portion being above the first semiconductor portion at the first surface; and The second metal portion is along a second surface of the gate layer that faces a different direction than the first surface, and the second metal portion contacts the second semiconductor portion at the second surface. 12 . The semiconductor device of claim 11 , wherein the second metal portion is laterally outside an active region of the semiconductor substrate, the gate layer being on the active region.

13. The semiconductor device according to claim 11, wherein: The second surface is adjacent to the source electrical contact; and The source electrical contact is notched on a side adjacent to the gate layer and corresponding to a location in the channel length direction where the second metal portion contacts the second surface.

14. The semiconductor device according to claim 1, wherein: The first metal portion and the second metal portion include the same metal material; The first metal portion is above a first surface of the gate layer parallel to a surface of the barrier layer, the first metal portion being above the first semiconductor portion at the first surface; and The second metal portion is along a second surface of the gate layer that faces a different direction than the first surface, and the second metal portion contacts the second semiconductor portion at the second surface. 15 . The semiconductor device of claim 14 , wherein the second metal portion is laterally outside of an active region of the semiconductor substrate, the gate layer being on the active region.

16. The semiconductor device according to claim 1, wherein: The first metal portion and the second metal portion include the same metal material; the second semiconductor portion includes a dopant, a concentration of the dopant in the second semiconductor portion being greater than a concentration of the dopant in the first semiconductor portion; The first metal portion is above a first surface of the gate layer parallel to a surface of the barrier layer, the first metal portion being above the first semiconductor portion at the first surface; and The second metal portion is over the first surface, the second metal portion contacting the second semiconductor portion at the first surface. 17 . The semiconductor device of claim 1 , further comprising a dielectric layer between the first metal portion and the first semiconductor portion.

18. A method comprising: forming a patterned gate layer over the barrier layer, the barrier layer being over the channel layer over the semiconductor substrate, the patterned gate layer comprising a first semiconductor portion and a second semiconductor portion; as well as A gate electrical contact is formed to contact the patterned gate layer, the gate electrical contact comprising a first metal portion and a second metal portion, a first energy barrier height being an energy barrier height of a junction between the first metal portion and the first semiconductor portion, a second energy barrier height being an energy barrier height of a junction between the second metal portion and the second semiconductor portion, and the first energy barrier height being greater than the second energy barrier height.

19. The method according to claim 18, further comprising: forming a first dielectric layer over the patterned gate layer; as well as forming a first opening through the first dielectric layer, the first opening being above the patterned gate layer, wherein forming the gate electrical contact comprises: forming a first metal layer in the first opening; forming a second opening through the first metal layer to the patterned gate layer; forming a second metal layer in the second opening and contacting the patterned gate layer; and The second metal layer and the first metal layer are patterned into the gate electrical contact, a remaining portion of the first metal layer is the first metal portion, and a remaining portion of the second metal layer is the second metal portion.

20. The method of claim 19, wherein: The first opening leads to the patterned gate layer; and The first metal layer in the first opening contacts the patterned gate layer.

21. The method of claim 19, further comprising forming a second dielectric layer over the patterned gate layer, wherein: the first dielectric layer being formed over the second dielectric layer; The first opening leads to the second dielectric layer; The first metal layer in the first opening contacts the second dielectric layer; and The second opening is formed through the second dielectric layer.

22. The method of claim 18, further comprising: forming a first dielectric layer over the patterned gate layer; as well as forming a first opening through the first dielectric layer and leading to the patterned gate layer, and a second opening through the first dielectric layer, the first opening being above the patterned gate layer and the second opening leading to the patterned gate layer, wherein forming the gate electrical contact comprises: forming a first metal layer in the first opening and the second opening; removing the first metal layer from the second opening; forming a second metal layer in the second opening and contacting the patterned gate layer; and The second metal layer and the first metal layer are patterned into the gate electrical contact, a remaining portion of the first metal layer is the first metal portion, and a remaining portion of the second metal layer is the second metal portion.

23. The method of claim 22, wherein: The first opening leads to the patterned gate layer; and The first metal layer in the first opening contacts the patterned gate layer.

24. The method of claim 22, further comprising forming a second dielectric layer over the patterned gate layer, wherein: the first dielectric layer being formed over the second dielectric layer; The first opening leads to the second dielectric layer; The first metal layer in the first opening contacts the second dielectric layer; and Removing the first metal layer from the second opening further removes the second dielectric layer exposed by the second opening.

25. The method of claim 18, wherein: Forming the patterned gate layer includes forming a gate layer; Forming the gate electrical contact comprises: forming a first metal layer above the gate layer; patterning the first metal layer; and forming a second metal layer over the gate layer and a remaining portion of the first metal layer; and Forming the patterned gate layer and the gate electrical contact includes patterning the second metal layer and the remaining portion of the first metal layer into the gate electrical contact and patterning the gate layer into the patterned gate layer, the remaining patterned portion of the first metal layer being the first metal portion, and the remaining patterned portion of the second metal layer being the second metal portion.

26. The method of claim 18, further comprising: forming a dielectric layer over the patterned gate layer; as well as forming a first opening through the dielectric layer to the patterned gate layer, the first opening exposing an upper surface of the patterned gate layer and a sidewall surface of the patterned gate layer, wherein forming the gate electrical contact comprises: forming a metal layer in the first opening, wherein a first portion of the metal layer contacts the upper surface of the patterned gate layer, and a second portion of the metal layer contacts the sidewall surface of the patterned gate layer; as well as A thermal process is performed on the metal layer, the first portion of the metal layer is the first metal portion, and the second portion of the metal layer is the second metal portion.

27. The method of claim 18, further comprising: forming a dielectric layer over the patterned gate layer; forming an opening through the dielectric layer to the patterned gate layer; as well as Dopants are implanted into the second semiconductor portion of the patterned gate layer and through the opening, wherein forming the gate electrical contact includes forming a metal layer in the opening and contacting the patterned gate layer, the first metal portion includes a first portion of the metal layer, and the second metal portion includes a second portion of the metal layer.

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