Semiconductor device

Abstract

A semiconductor device includes a substrate having a first surface and a second surface; an active pattern extending on the first surface of the substrate, the active pattern having a first conductivity type impurity region and a second conductivity type impurity region, the first conductivity type impurity region and the second conductivity type impurity region being in contact with each other; a semiconductor pattern stacked on a portion of the active pattern between the first conductivity type impurity region and the second conductivity type impurity region; a non-active gate structure extending across a portion of the active pattern between the first conductivity type impurity region and the second conductivity type impurity region, the non-active gate structure surrounding the semiconductor pattern; a first contact portion passing through the substrate from the second surface of the substrate and connected to the first conductivity type impurity region; and a second contact portion passing through the substrate from the second surface of the substrate and connected to the second conductivity type impurity region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0099755 filed in the Korean Intellectual Property Office on July 31, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices. Background Art

[0004] As the demand for achieving high performance, high speed and / or multi-functions of semiconductor devices increases, the integration of semiconductor devices is increasing. In order to overcome the limitations of operating characteristics caused by the reduction in size of planar metal oxide semiconductor FETs (MOSFETs), efforts have been made to develop a semiconductor device including a full-surround gate field effect transistor, which includes a finFET having a fin-type channel and a nanosheet surrounded by a gate. Summary of the invention

[0005] Example embodiments of the inventive concepts provide a semiconductor device having improved electrical characteristics and reliability.

[0006] An example embodiment of the present invention provides a semiconductor device, including: a substrate having a first surface and a second surface opposite to the first surface; an active pattern on the first surface of the substrate, the active pattern extending in a first direction, the active pattern having a first conductive type impurity region and a second conductive type impurity region arranged along the first direction, the first conductive type impurity region and the second conductive type impurity region contacting each other; a semiconductor pattern stacked on a portion of the active pattern between the first conductive type impurity region and the second conductive type impurity region of the active pattern, the semiconductor patterns being spaced apart from each other in a vertical direction; a non-active gate structure extending across a portion of the active pattern between the first conductive type impurity region and the second conductive type impurity region of the active pattern in a second direction, the second direction intersecting the first direction, and the non-active gate structure surrounding the semiconductor pattern; a first contact portion passing through the substrate from the second surface of the substrate, the first contact portion being connected to the first conductive type impurity region; and a second contact portion passing through the substrate from the second surface of the substrate, the second contact portion being connected to the second conductive type impurity region.

[0007] An example embodiment of the present inventive concept also provides a semiconductor device, including: a substrate having a first surface and a second surface opposite to the first surface; an active pattern extending on the first surface of the substrate, the active pattern extending in a first direction, the active pattern having a first conductive type impurity region and a second conductive type impurity region arranged along the first direction, the first conductive type impurity region and the second conductive type impurity region contacting each other; a semiconductor pattern stacked on a portion of the active pattern between the first conductive type impurity region and the second conductive type impurity region, the semiconductor patterns being spaced apart from each other in a vertical direction; and an inactive gate structure extending in a second direction across a portion of the active pattern between the first conductive type impurity region and the second conductive type impurity region. The invention relates to a semiconductor pattern, wherein the first conductive type epitaxial pattern and the second conductive type epitaxial pattern are respectively on two side surfaces of the semiconductor pattern in the first direction, and the first conductive type epitaxial pattern and the second conductive type epitaxial pattern are respectively on the first conductive type impurity region and the second conductive type impurity region of the active pattern; an interlayer insulating layer on the first surface of the substrate, the interlayer insulating layer covering the first conductive type epitaxial pattern and the second conductive type epitaxial pattern; a first contact portion passing through the interlayer insulating layer, the first contact portion being connected to the first conductive type epitaxial pattern; and a second contact portion passing through the substrate from the second surface of the substrate, the second contact portion being connected to the second conductive type impurity region of the active pattern.

[0008] An example embodiment of the present invention also provides a semiconductor device, including: a substrate having a first surface and a second surface opposite to the first surface, the substrate having a first device and a second device on a first device region and a second device region on the first surface of the substrate, respectively. The first device may include: a first active pattern extending on the first surface of the substrate in a first direction; a first semiconductor pattern stacked on the first active pattern and spaced apart from each other in a vertical direction; an active gate structure extending across the first active pattern in a second direction, the second direction intersecting the first direction, and the active gate structure surrounding the first semiconductor pattern; a pair of source / drain patterns on both sides of the first semiconductor pattern in the first direction, the pair of source / drain patterns being connected to both sides of the first semiconductor pattern, respectively; and a gate structure extending in the second direction, the gate structure surrounding the first semiconductor pattern. The second device may include: a second active pattern extending on the first surface of the substrate in the first direction, the second active pattern having a first conductive type impurity region and a second conductive type impurity region arranged in the first direction, the first conductive type impurity region and the second conductive type impurity region contacting each other; a second semiconductor pattern stacked on a portion of the second active pattern between the first conductive type impurity region and the second conductive type impurity region of the second active pattern, the second semiconductor patterns being spaced apart from each other in a vertical direction; a non-active gate structure extending across a portion of the second active pattern between the first conductive type impurity region and the second conductive type impurity region of the second active pattern, the non-active gate structure surrounding the second semiconductor pattern; and a first contact and a second contact connected to the first conductive type impurity region and the second conductive type impurity region, respectively. At least one of the first contact and the second contact is connected to the first conductive type impurity region and the second conductive type impurity region, respectively, from the second surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a plan view of a semiconductor device according to some example embodiments of the inventive concept;

[0011] Figure 2 It is taken along line I-I' Figure 1 A cross-sectional view of a first device region A of a semiconductor device;

[0012] Figure 3A and Figure 3B It is taken along line II1-II1' and line II2-II2' Figure 1 A cross-sectional view of a first device region A of a semiconductor device;

[0013] Figure 4It is taken along line III-III' Figure 1 A cross-sectional view of a second device region B of a semiconductor device;

[0014] Figure 5A and Figure 5B It is taken along line IV1a-IV1a' and line IV2b-IV2b' Figure 1 A cross-sectional view of a second device region B of a semiconductor device;

[0015] Fig. 6A and Figure 6B It is taken along line IV2a-IV2a' and line IV1b-IV1b' Figure 1 A cross-sectional view of a second device region B of a semiconductor device;

[0016] Figure 7 , Fig. 8A , Figure 8B , Fig.9A and Fig. 9B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concept;

[0017] Fig.10 , Fig.11A and Fig. 11B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concept;

[0018] Fig.12 , Fig.13A and Fig. 13B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concept;

[0019] Fig.14 , Fig.15A and Fig. 15B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concept; and

[0020] Fig.16 , Fig.17A and Fig. 17B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0021] Hereinafter, various exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0022] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance for the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the numerical value or shape. When a range is specified, the range includes all values ​​therebetween (e.g., increments of 0.1%).

[0023] In addition, for example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, e.g., ABC, AB, BC, and AC.

[0024] Figure 1 are plan views of semiconductor devices according to some example embodiments of the inventive concepts. Figure 2 It is taken along line I-I' Figure 1 A cross-sectional view of a first device region A of a semiconductor device. Figure 3A and Figure 3B It is taken along line II1-II1' and line II2-II2' Figure 1 A cross-sectional view of a first device region A of a semiconductor device. Figure 4 It is taken along line III-III' Figure 1 A cross-sectional view of a second device region B of a semiconductor device.

[0025] First, refer to Figure 1 , Figure 2 and Figure 4 , the semiconductor device 100 according to some example embodiments may have a first device region A and a second device region B arranged in a horizontal direction (e.g., a D1 direction or a D2 direction). The first device region A may also be referred to as a "logic region" in which the logic device 100A is formed, and the second device region B may also be referred to as a "peripheral circuit region" in which the passive device 100B is formed.

[0026] refer to Figure 2 , Figure 3A and Figure 3B as well as Figure 1A logic device 100A of a semiconductor device 100 according to some example embodiments may include a substrate 201, a plurality of active patterns 105 extending on a first device region A of the substrate 201 along a first direction (e.g., D1 direction), and a separation pattern SP separating each of the plurality of active patterns 105 into a first active pattern 105A and a second active pattern 105B.

[0027] The semiconductor device 100 according to some example embodiments may further include a gate structure GS crossing the first active pattern 105A and the second active pattern 105B and extending in a second direction (e.g., D2 direction), a dummy gate structure DG extending in the second direction (e.g., D2 direction) along ends of the plurality of first active patterns 105A and the plurality of second active patterns 105B from both sides of the separation pattern SP, and first and second source / drain patterns 130A and 130B disposed on the first and second active patterns 105A and 105B on both sides of the gate structure GS. Here, the gate structure GS may also be referred to as an "active gate structure" included in the transistor, and the dummy gate structure DG may also be referred to as a "non-active gate structure" not included in the transistor.

[0028] The substrate 201 according to some example embodiments may include an insulating material layer prepared after removing a semiconductor substrate for forming a device (e.g., 100A and 100B). In some example embodiments, the substrate 201 may include an oxide layer. For example, the substrate 201 may be formed of a flowable oxide (FOX), a toner silazane (TOSZ), an undoped silica glass (USG), a borosilicate glass (BSG), a phosphosilicate glass (PSG), a borophosphosilicate glass (BPSG), a high-density plasma (HDP) oxide, a plasma-enhanced oxide (PEOX), a flowable CVD (FCVD) oxide, or a combination thereof. The substrate 201 may be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin coating process.

[0029] The active pattern 105 may have a fin-type structure protruding from the insulating substrate 201 in a third direction (e.g., D3 direction) and extending in a first direction (e.g., D1 direction). The active pattern 105 may be a pattern obtained by partially etching a semiconductor substrate. However, as described above, the active pattern 105 may have a structure obtained by removing a portion of the semiconductor substrate below the active pattern 105. Therefore, the active pattern 105 according to some example embodiments may include a semiconductor material that is the same as the semiconductor material of the semiconductor substrate. For example, the active pattern 105 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In some example embodiments, the active pattern 105 may be an N-type impurity region for a P-MOS transistor, or a P-type impurity region for an N-MOS transistor, but the inventive concept is not limited thereto.

[0030] The device isolation layer 110 may be disposed on the insulating substrate 201 to define the active pattern 105. For example, the device isolation layer 110 may include silicon oxide, or a silicon oxide-based insulating material. The device isolation layer 110 may be a trench isolation defining the active pattern 105.

[0031] refer to Figure 1 , Figure 2 , Figure 3A and Figure 3B , the active pattern 105 may have a fin structure extending from the first surface of the insulating substrate 201 in a first direction (e.g., D1 direction). A plurality of semiconductor patterns 125 may be disposed on the active pattern 105 to be spaced apart from each other in a direction perpendicular to the first surface of the insulating substrate 201 (i.e., a third direction (e.g., D3 direction)). The active pattern 105 and the plurality of semiconductor patterns 125 may be provided as a multi-channel layer of a transistor. In some example embodiments, the number of the plurality of semiconductor patterns 125 is exemplified as three, but there is no particular limitation on the number thereof. For example, the plurality of semiconductor patterns 125 may include silicon (Si) or silicon germanium (SiGe).

[0032] like Figure 1 As shown, the logic device 100A according to some example embodiments may include a plurality of gate structures GS extending in a second direction (e.g., D2 direction). As described above, the plurality of gate structures GS may be arranged to respectively intersect the first active pattern 105A and the second active pattern 105B separated by the separation pattern SP in the first direction (e.g., D1 direction).

[0033] refer to Figure 2 and Figure 3B, the gate structure GS may include a gate spacer 141, a gate insulating film 142 and a gate electrode 145 sequentially disposed between the gate spacers 141, and a gate capping layer 147 disposed on the gate electrode 145. For example, the gate spacer 141 may include an insulating material such as SiOCN, SiON, SiCN, or SiN. The gate insulating film 142 may be formed of, for example, a silicon oxide film, a high-k dielectric film, or a combination thereof. The high-k dielectric film may include a material having a dielectric constant higher than that of the silicon oxide film (e.g., about 10 to 25). For example, the high-k dielectric film may include a material selected from hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, and a combination thereof, but the inventive concept is not limited thereto. The gate electrode 145 may include a conductive material, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. In some example embodiments, the gate electrode 145 may be a multilayer including two or more films. The gate capping layer 147 may include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon nitride oxide.

[0034] The logic device 100A according to some example embodiments may be arranged according to the separation pattern SP, and may include a power transmission structure for supplying power to each transistor unit from the second surface (i.e., the rear surface) of the insulating substrate 201. The power transmission structure according to some example embodiments may include a buried conductive structure 150 arranged on the separation pattern SP in a second direction (e.g., D2 direction), and a conductive through structure 170 extending from the second surface toward the first surface of the substrate 201, the conductive through structure 170 being connected to the buried conductive structure 150.

[0035] In some example embodiments, Figure 2 As shown, the buried conductive structure 150 may extend to the first surface of the insulating substrate 201, and the power transmission structure 170 may pass through the insulating substrate 201 from the first surface of the insulating substrate 201 to respectively contact the bottom surface of the buried conductive structure 150. The conductive through structure 170 may receive power from the second interconnection line M2a located on the second surface of the insulating substrate 201, and may supply power to the source / drain patterns 130A and 130B of the logic device 100A through the buried conductive structure 150. In some example embodiments, the buried conductive structure 150 may be electrically connected to the source / drain patterns 130A and 130B through the first interconnection line M1a of the first interconnection structure 210, the power line.

[0036] The buried conductive structure 150 may include a conductive material 155 and a conductive barrier 152 surrounding a bottom surface and side surfaces of the conductive material 155. In some example embodiments, the buried conductive structure 150 may further include an insulating liner 151 surrounding the conductive barrier 152. The conductive through-structure 170 may include a conductive material 175 and a conductive barrier 172 surrounding a top surface and side surfaces of the conductive material 175.

[0037] For example, the conductive materials 155 and 175 may include Cu, Co, Mo, Ru, W, or alloys thereof. In some example embodiments, the conductive materials 155 and 175 may include different conductive materials. For example, the conductive barriers 152 and 172 may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof. For example, the insulating liner 151 may include SiO 2 , SiN, SiCN, SiC, SiCOH, SiON, Al 2 O 3 , AlN, or a combination thereof.

[0038] In some example embodiments, the dummy gate structures DG located at both sides of the separation pattern SP may include components similar to those of the gate structure GS. Each of the dummy gate structures DG may include a gate spacer 141, a gate insulating film 142, a gate electrode 145, and a gate capping layer 147. However, as described above, the dummy gate structures may be located at the ends of the first active pattern 105A and the second active pattern 105B. Accordingly, as Figure 2 As shown, a portion of the dummy gate structure DG may extend to the device isolation layer 110 along the cross-section of the first active pattern 105A and the second active pattern 105B.

[0039] The first source / drain pattern 130A and the second source / drain pattern 130B according to some example embodiments may be disposed on regions of the first active pattern 105A and the second active pattern 105B located on both sides of the gate structure GS. The first source / drain pattern 130A and the second source / drain pattern 130B may be connected to both ends of the plurality of semiconductor patterns 125 in the first direction (e.g., D1 direction), respectively. The gate electrode 145 may have a portion 145' extending in the second direction (e.g., D2 direction) to intersect the first active pattern 105A and the second active pattern 105B and surround the plurality of semiconductor patterns 125. The gate insulating film 142 may also have a portion 142' extending between the plurality of semiconductor patterns 125 and the gate electrode portion 145'. As described above, the semiconductor device 100 according to some example embodiments may be included in a full surround gate type field effect transistor.

[0040] The first source / drain pattern 130A and the second source / drain pattern 130B may include epitaxial patterns selectively epitaxially grown (SEG) from the recessed surfaces of the first active pattern 105A and the second active pattern 105B, and the side surfaces of the plurality of semiconductor patterns 125 at both sides of the gate structure GS. For example, the first source / drain pattern 130A and the second source / drain pattern 130B may be Si, SiGe, or Ge, and may have N-type or P-type conductivity. In some example embodiments, when the first source / drain pattern 130A is an N-type source / drain, the first source / drain pattern 130A may include silicon (Si) doped with N-type impurities such as phosphorus (P), nitrogen (N), arsenic (As), and / or antimony (Sb). When the second source / drain pattern 130B is a P-type source / drain, the second source / drain pattern 130B may include silicon doped with N-type impurities such as boron (B), indium (In), gallium (Ga), and / or boron trifluoride (BF 3 ) or silicon germanium (SiGe) with P-type impurities such as silicon (Si) or silicon germanium (SiGe).

[0041] The first source / drain pattern 130A and the second source / drain pattern 130B may have different shapes along a crystallographically stable surface during growth. For example, the N-type first source / drain pattern 130A may have a hexagonal cross section or a polygonal cross section with a gentle angle (see Figure 3A ), and the P-type second source / drain pattern 130B may have a pentagonal cross-section (see Figure 5B ).

[0042] As described above, the semiconductor device 100 according to some example embodiments may have a first device region A and a second device region B arranged in different regions in a horizontal direction. The second device region B may include a passive device 100B included in a peripheral circuit. The passive device 100B according to some example embodiments may be formed by a series of processes combined with the process of forming the above-described logic device 100A, and thus there may be a correlation between the corresponding components.

[0043] Figure 4 It is taken along line III-III' Figure 1 A cross-sectional view of a second device region B of a semiconductor device. Figure 5A and Figure 5B It is taken along line IV1a-IV1a' and line IV2b-IV2b' Figure 1 A cross-sectional view of a second device region B of a semiconductor device. Fig. 6A and Figure 6B It is taken along line IV2a-IV2a' and line IV1b-IV1b' Figure 1 A cross-sectional view of a second device region B of a semiconductor device.

[0044] refer to Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B According to some example embodiments, the passive device 100B of the semiconductor device 100 may include an active pattern 205 disposed on a second device region B of a substrate 201 in a first direction (e.g., D1 direction), a semiconductor pattern 125 stacked on a portion of the active pattern 205 and spaced apart from each other in a vertical third direction (e.g., D3 direction), a non-active gate structure NG extending in a second direction (e.g., D2 direction) and surrounding the semiconductor pattern 125, and a first conductive type epitaxial pattern 230A and a second conductive type epitaxial pattern 230B respectively disposed on two side surfaces of the semiconductor pattern 125 on both sides of the non-active gate structure NG.

[0045] The active pattern 205 of the passive device 100B may have a first conductive type impurity region 205A and a second conductive type impurity region 205B in contact with each other. The first conductive type impurity region 205A and the second conductive type impurity region 205B may be provided as impurity regions included in the passive device. For example, the first conductive type impurity region 205A and the second conductive type impurity region 205B may be formed using a selective ion implantation process on the active pattern 205 of the passive device 100B (e.g., the second device region B of the semiconductor substrate).

[0046] like Figure 4 As shown, the semiconductor pattern 125 may be stacked on a contact portion (i.e., on a bonding interface) between the first conductive type impurity region 205A and the second conductive type impurity region 205B of the active pattern 205 and spaced apart from each other in a vertical direction. In some example embodiments, the bonding interface between the first conductive type impurity region 205A and the second conductive type impurity region 205B may extend substantially vertically from an upper surface to a lower surface of the active pattern 205.

[0047] The non-active gate structure NG may be located on a contact portion between the first conductive type impurity region 205A and the second conductive type impurity region 205B of the active pattern 205 .

[0048] Each of the plurality of non-active gate structures NG may be a structure corresponding to the gate structure GS, but may be understood as a dummy structure that does not participate in driving the device. The plurality of non-active gate structures NG according to some example embodiments may have components similar to those of the gate structure GS of the logic device 100A, and the corresponding components may include the same material.

[0049] refer to Figure 4 , Fig. 6A and Figure 6B as well as Figure 2and Figure 3B , each of the plurality of non-active gate structures NG may include a gate electrode 145 surrounding the semiconductor pattern 125, a gate insulating film 142 between the semiconductor pattern 125 and the gate electrode 145, a gate spacer 141 disposed on both sidewalls of a portion of the gate electrode 145 located on the uppermost semiconductor pattern, and a gate capping layer 147 disposed on the gate electrode 145 between the gate spacers 141, and may include the same material as that of a corresponding component of the gate structure GS of the logic device 100A. In some example embodiments, the non-active gate structure NG may have a width W2 in a first direction (e.g., D1 direction) that is wider than a width W1 of the gate structure GS of the logic device 100A in the first direction.

[0050] The semiconductor pattern 125 of the passive device 100B may be a layer formed using the same process as that of the semiconductor pattern 125 of the logic device 100A. The semiconductor patterns 125 of the two devices 100A and 100B may be located at the same level and may include substantially the same semiconductor material. An ion implantation process for forming impurity regions 205A and 205B in the active pattern 205 may be performed before forming the semiconductor pattern 125. In some example embodiments, the semiconductor pattern 125 may be retained as a semiconductor layer that is not intentionally doped.

[0051] The first conductive type epitaxial pattern 230A and the second conductive type epitaxial pattern 230B may be respectively disposed on the first conductive type impurity region 205A and the second conductive type impurity region 205B of the active pattern 205. The first conductive type epitaxial pattern 230A and the second conductive type epitaxial pattern 230B may be respectively connected to both side surfaces of the semiconductor pattern 125 in a first direction (e.g., D1 direction). For example, the first conductive type epitaxial pattern 230A and the first conductive type impurity region 205A may be N-type regions, and the second conductive type epitaxial pattern 230B and the second conductive type impurity region 205B may be P-type regions.

[0052] The first conductive type epitaxial pattern 230A and the second conductive type epitaxial pattern 230B can be formed using the process of forming the first source / drain pattern 130A and the second source / drain pattern 130B of the logic device 100A. For example, the first conductive type epitaxial pattern 230A can be formed together with the first source / drain pattern 130A. Similarly, the second conductive type epitaxial pattern 230B can be formed together with the second source / drain pattern 130B. In some example embodiments, the first conductive type epitaxial pattern 230A and the first source / drain pattern 130A may be N-type epitaxial patterns having the same composition. The second conductive type epitaxial pattern 230B and the second source / drain pattern 130B may be P-type epitaxial patterns having the same composition. As described above, such a process can be performed by a selective epitaxial growth (SEG) process. However, depending on the state of each crystal plane on which the epitaxial layer is grown, etc., there may be a distribution (variation in quality and size) of the grown epitaxial layer. The first conductive type epitaxial pattern 230A and the second conductive type epitaxial pattern 230B have their own resistance in addition to the resistance occurring at the interface with the first conductive type impurity region 205A and the second conductive type impurity region 205B. Due to such a resistance element, the diode component between the first conductive type epitaxial pattern 230A and the second conductive type epitaxial pattern 230B can have a relatively high operating voltage and a high probability of occurrence of distribution.

[0053] In order to solve such a problem, in some example embodiments, a solution of omitting one of the first conductive type epitaxial pattern 230A and the second conductive type epitaxial pattern 230B from the electrical path of the diode being driven may be proposed. This solution may be achieved by adjusting the arrangement of the first contact portion 280A and the second contact portion 280B.

[0054] For example, refer to Figure 4 , Figure 5A and Figure 5B , the first contact 280A may pass through the interlayer insulating layer 160 to be connected to the first conductive type epitaxial pattern 230A, and the second contact 280B may pass through the insulating substrate 201 from the second surface (i.e., the lower surface) of the insulating substrate 201 to be directly connected to the second conductive type impurity region 205B of the active pattern 205. Unlike the first contact 280A, the second contact 280B may be directly connected to the second conductive type impurity region 205B without passing through the second conductive type epitaxial pattern 230B, so that the operating voltage of the passive device 100B can be reduced by the amount of the resistance element of the second conductive type epitaxial pattern 230B.

[0055] The second contact 280B according to some example embodiments may be formed during a series of backside processes (eg, a process of forming the conductive through structure 170 and a process of forming the second interconnection structure 220 ) after performing a frontside process of forming the logic device 100A and the passive device 100B on the semiconductor substrate.

[0056] For example, each of the first contact 280A and the second contact 280B may include a conductive material 285 and a conductive barrier 282 surrounding the side surface and the bottom surface of the conductive material 285. In some example embodiments, the first contact 280A may include a metal-semiconductor compound layer 283 formed on the first conductive type epitaxial pattern 230A to improve the contact resistance. The metal-semiconductor compound layer 283 may be formed on the surface of the first conductive type epitaxial pattern 230A outside the conductive barrier 282. For example, the conductive material 285 may include Cu, Co, Mo, Ru, W, or an alloy thereof. For example, the conductive barrier 282 may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof. For example, the metal-semiconductor compound layer 283 may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0057] The semiconductor device 100 according to some example embodiments may further include a first source / drain pattern 130A and a second source / drain pattern 130B in the first device region A, and an interlayer insulating layer 160 disposed on the device isolation layer 110 in the second device region B to cover the first conductive type epitaxial pattern 230A and the second conductive type epitaxial pattern 230B. For example, the interlayer insulating layer 160 may include FOX, TOSZ, USG, BSG, PSG, BPSG, PETEOS, FSG, HDP oxide, PEOX, FCVD oxide, or a combination thereof. The interlayer insulating layer 160 may be formed using a chemical vapor deposition process, a flowable CVD process, or a spin coating process. The semiconductor device 100 according to some example embodiments may further include an intermediate insulating layer 191 covering the interlayer insulating layer 160 and the gate structures GS, DG, and NG. The intermediate insulating layer 191 may include an insulating material similar to that of the interlayer insulating layer 160.

[0058] refer to Figure 2 and Figure 4 , the source / drain contact 180A and the first contact 280A may pass through not only the interlayer insulating layer 160 but also the intermediate insulating layer 191 to be connected to the first source / drain pattern 130A and the second source / drain pattern 130B and the first conductive type epitaxial pattern 230A, respectively. Figure 3B , the gate contact 180B may pass through the intermediate insulating layer 191 and the gate capping layer 147 to be connected to the gate electrode 145 .

[0059] In a manner similar to the first contact 280A and the second contact 280B, the source / drain contact 180A and the gate contact 180B may include a conductive material 185 and a conductive barrier 182 surrounding the side and end surfaces of the conductive material 185. For example, the conductive material 185 may include Cu, Co, Mo, Ru, W, or an alloy thereof. For example, the conductive barrier 182 may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof. In some example embodiments, the source / drain contact 180A may include a metal-semiconductor compound layer 183 formed on the first source / drain pattern 130A and the second source / drain pattern 130B to improve contact resistance.

[0060] The semiconductor device 100 according to some example embodiments may have a double-sided interconnect structure including an upper interconnect structure 210 and a lower interconnect structure 220. The double-sided interconnect structure may be applied across the first device region A and the second device region B, and may be configured to electrically connect the logic device 100A and the passive device 100B to each other. The upper interconnect structure 210 may be disposed on the upper surface of the semiconductor device 100, and the lower interconnect structure 220 may be disposed on the lower surface of the semiconductor device 100.

[0061] In some example embodiments, the upper interconnect structure 210 may include a plurality of (e.g., two) upper insulating layers 211, and first and second upper metal lines M1a and M1b and first and second upper vias V1a and V1b formed in the upper insulating layer 211. For example, each interconnect layer (indicating a combination of a corresponding metal line and an associated via) may be formed using a dual damascene process. The upper interconnect layer located in the first device region A may include a first upper metal line M1a and a first upper via V1a, and the upper interconnect layer located in the second device region B may include a second upper metal line M1b and a second upper via V1b. The upper interconnect layer may be configured such that the logic device 100A and the passive device 100B are connected to each other.

[0062] The insulating protection film (or etching stop film) 197 may be disposed on the second surface (or lower surface) of the insulating substrate 201. The insulating protection film 197 may be disposed to surround the contact region of the conductive penetration structure 170 protruding from the second surface of the insulating substrate 201. The lower interconnect structure 220 may be disposed on the insulating protection film 197. The lower interconnect structure 220 may include a lower insulating layer 221, and a first lower metal line M2a and a second lower metal line M2b formed in the lower insulating layer 221. The first lower metal line M2a may be disposed to be connected to a power line of the conductive penetration structure 170. The second lower metal line M2b may be disposed to be connected to a signal line of the second contact portion 280B. In some example embodiments, the lower interconnect structure 220 located in the second device region B may further include an additional interconnect layer, and may be configured so that the logic device 100A and the passive device 100B are connected to each other together with the supply of the power line. In some example embodiments, the insulating protection film 197 and the first insulating layer 211 and the second insulating layer 221 may include different insulating materials. For example, the insulating protection film 197 may include AlN or SiN, and the upper insulating layer 211 and the lower insulating layer 221 may include SiO 2 .

[0063] For example, in some example embodiments, at least one of the first contact 280A and the second contact 280B of the passive device 100B may be changed to have a back contact structure directly connected to the first conductive type impurity region 205A or the second conductive type impurity region 205B. Such a change may limit and / or prevent the adverse effects (e.g., resistance elements and distribution) of the first conductive type epitaxial pattern 230A or the second conductive type epitaxial pattern 230B causing various resistance elements, thereby reducing the operating voltage of the passive device 100B and greatly improving the distribution of the operating voltage.

[0064] The present inventive concept can be implemented in various modified example embodiments. For example, the solution of improving resistance by changing at least one contact portion to have a back contact structure can also be advantageously implemented in passive devices having various structures. By changing both the first contact portion and the second contact portion to have a back contact structure (see Fig.12 , Fig.14 and Fig.16 ), the operating voltage and distribution can be greatly improved. In some example embodiments, the conductive type epitaxial pattern can be omitted.

[0065] Figure 7 , Fig. 8A , Figure 8B , Fig.9A and Fig. 9B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts.

[0066] refer to Figure 7 , Fig. 8A , Figure 8B , Fig.9A and Fig. 9B , except that an active region 202 having a desired (and / or predetermined) area exists below the active pattern 205, and a metal-semiconductor compound layer 283' is disposed on an upper end of the second contact portion 280B', the passive device 100C according to some example embodiments may be understood as similar to Figure 1 , Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B The passive device 100B shown is similar. Unless otherwise described, reference may be made to Figure 1 , Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B The description of the same or similar components of the passive device 100B shown in FIG. 1 may be used to understand the other components.

[0067] The passive device 100C according to some example embodiments may also have an active region 202 having a desired (and / or predetermined) area below the active pattern 205. The first conductive type impurity region 205A and the second conductive type impurity region 205B of the active pattern 205 may extend to corresponding regions of the active region 202 in a vertically downward direction, respectively. In the present example embodiment, the extended first conductive type impurity region 205A' and the second conductive type impurity region 205B' may have a region extending in a vertical direction to correspond to the thickness of the active region. Therefore, a second contact 280B' having a back contact structure may be formed relatively easily. The second contact 280B' may extend from the second surface of the substrate 201 and may be selected so that its end is positioned within the active region 202 or the active pattern 205.

[0068] refer to Fig. 8A and Figure 8B, the active pattern 205 may have a structure extending on the active region 202 along a first direction (e.g., D1 direction). The active region 202 may be understood as a structure provided by a portion of a semiconductor substrate (not shown). For example, in a manufacturing process, an ion implantation process may be used to form a first conductive type impurity region 205A' and a second conductive type impurity region 205B' having a first depth in a semiconductor substrate, and an active pattern 205 having a height lower than the first depth may be formed by patterning the ion implantation region. The active region 202 may be a structure obtained by subsequently removing at least a portion of the active pattern 205 in which the impurity regions 205A' and 205B' are not formed from the lower surface of the semiconductor substrate. This partial removal process may be performed by chemical mechanical polishing (CMP) and / or an etching process.

[0069] In some example embodiments, in a similar manner to the first contact 280A, the second contact 280B' may include a metal-semiconductor compound layer 283' formed on the second conductive type impurity region 205B' to improve contact resistance. The metal-semiconductor compound layer 283' may be formed on the surface of the second conductive type impurity region 205B' outside the conductive barrier 282. For example, the metal-semiconductor compound layer 283' may include cobalt silicide (CoSi x ), nickel silicide (NiSi x ) or manganese silicide (MnSi x ), but the inventive concept is not limited thereto.

[0070] Fig.10 , Fig.11A and Fig. 11B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts.

[0071] refer to Fig.10 , Fig.11A and Fig. 11B , except that the active region 202 and a portion of the semiconductor substrate 101 remain below the active pattern 205, the metal-semiconductor compound layer 283′ is disposed on the upper end of the second contact portion 280B″, and the second contact portion 280B″ further includes an insulating liner 281 for electrical insulation from the semiconductor substrate 101, the passive device 100D according to some example embodiments may be understood as Figure 1 , Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B Unless otherwise described, reference may be made to the passive device 100B shown in FIG. Figure 1 , Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B The description of the same or similar components of the passive device 100B shown in FIG. 1 may be used to understand the other components.

[0072] In some example embodiments, not only the active region 202 but also another region 101 of the semiconductor substrate (i.e., a region 101 of the semiconductor substrate that is not ion-implanted) may remain under the active pattern 205. As described above, the remaining semiconductor substrate 101 may be obtained by adjusting the thickness removed during the CMP and / or etching process. In some example embodiments, the remaining semiconductor substrate 101 may replace an insulating substrate (e.g., Fig. 8A and Figure 8B 201).

[0073] In some example embodiments, the second contact portion 280B" may be configured to pass through the semiconductor substrate 101, and thus may further include an insulating liner 281 to provide electrical insulation from the semiconductor substrate 101. The second contact portion 280B" may include a conductive plug 285, a conductive barrier 282 covering the upper surface and side surfaces of the conductive plug 285, and an insulating liner 281 disposed between the conductive barrier 282 and at least the semiconductor substrate 101. For example, the insulating liner 281 may include SiO 2 , SiN, SiCN, SiC, SiCOH, SiON, Al 2 O 3 , AlN, or a combination thereof. In a manner similar to the previous example embodiment (see Figure 8B ), the second contact portion 280B" according to some example embodiments may include a metal-semiconductor compound layer 283' on an upper end thereof.

[0074] Fig.12 , Fig.13A and Fig. 13B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts.

[0075] refer to Fig.12 , Fig.13A and Fig. 13B , except that the first conductivity type epitaxial pattern (eg, Figure 7 230A) and a second conductivity type epitaxial pattern (eg, Figure 7 230B), and both the first contact portion 280A and the second contact portion 280B extend from the lower surface of the insulating substrate 201, the passive device 100E according to some example embodiments may be understood as Figure 1 , Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B Unless otherwise described, reference may be made to the passive device 100B shown in FIG. Figure 1 , Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B The description of the same or similar components of the passive device 100B shown in FIG. 1 may be used to understand other components of some example embodiments.

[0076] In some example embodiments, both the first contact 280A and the second contact 280B may have a back contact structure extending from the second surface (or lower surface) of the insulating substrate 201. In a similar manner to the second contact 280B, the first contact 280A may pass through the insulating substrate 201 to be connected to the first conductive type impurity region 205A from the second surface of the insulating substrate 201. Both the first contact 280A and the second contact 280B may be directly connected to the first conductive type impurity region 205A and the second conductive type impurity region 205B, respectively.

[0077] In some example embodiments, the first conductive type epitaxial pattern 230A and the second conductive type epitaxial pattern 230B may be omitted. Figure 2 The first source / drain pattern and the second source / drain pattern (“100A” in FIG. Figure 1 and Figure 2 In the process (recess process and selective epitaxial growth process) of "130A and 130B" in FIG. 1 , the first conductive type epitaxial pattern 230A and the second conductive type epitaxial pattern 230B can be omitted by masking the second device region B where the passive device 100E is to be formed.

[0078] For example, Fig.13A and Fig. 13B As shown, the passive device 100E according to some example embodiments may include a fin structure FS extending on the active pattern 205 in a first direction (eg, D1 direction). The fin structure FS may be understood as a first source / drain pattern and a second source / drain pattern ( Figure 1 and Figure 2 The structure existing in the operation before “ 130A and 130B” in FIG. 1 is formed in the entire device region of the semiconductor device (ie, after the dummy gate structure is formed and before the recess process).

[0079] The fin structure FS may have a structure in which a plurality of first semiconductor layers 121 and a plurality of second semiconductor layers 125 are alternately stacked. The plurality of first semiconductor layers 121 may be sacrificial layers that may be selectively removed, and the plurality of second semiconductor layers 125 may include a semiconductor layer used as a logic device ( Figure 2The semiconductor pattern of the channel in the "100A" in FIG. Figure 2 Each of the second semiconductor layers 125 according to some example embodiments may be understood as a Figure 2 The semiconductor pattern 125 extends to a layer structure on the active pattern 205 at both sides of the non-active gate structure NG.

[0080] In some example embodiments, the first semiconductor layer 121 and the second semiconductor layer 125 may include semiconductor materials having different compositions. The first semiconductor layer 121 and the second semiconductor layer 125 may have different germanium composition ratios (e.g., 0% to 60%). For example, the first semiconductor layer 121 may include silicon germanium, and the second semiconductor layer 125 may include silicon.

[0081] refer to Fig.12 , the non-active gate structure NG may include a first portion 140A located on the uppermost semiconductor layer among the second semiconductor layers 125, and a second portion 140B connected to the first portion 140A and disposed between the first semiconductor layers 121. The width Wa of the second portion 140B of the non-active gate structure NG in the first direction (e.g., D1 direction) may be wider than the width W2 of the first portion 140A of the non-active gate structure NG in the first direction (e.g., D1 direction). When forming the gate structure (i.e., Figure 2 When the first semiconductor layer 121 (sacrificial layer) is removed in the process of forming the gate structures GS and DG in the logic device 100A, since there are no first conductive type epitaxial patterns and second conductive type epitaxial patterns ( Figure 4 230A and 230B), so this form can be understood as a structure formed by additionally removing the second semiconductor layer 125.

[0082] Fig.14 , Fig.15A and Fig. 15B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts.

[0083] refer to Fig.14 , Fig.15A and Fig. 15B , except that an active region 202 having a desired (and / or predetermined) area exists below the active pattern 205, and a metal-semiconductor compound layer 283' is disposed on an upper end of the second contact portion 280B', the passive device 100F according to some example embodiments may be understood as similar to Fig.12 , Fig.13A and Fig. 13B The passive device 100E shown is similar. Unless otherwise described, reference may be made to Fig.12 , Fig.13A and Fig. 13B The description of the same or similar components of the passive device 100E shown in the figure can be used to understand the other components.

[0084] With Figure 7 In a similar manner to the illustrated example embodiment, the passive device 100F according to some example embodiments may also have an active region 202 having a desired (and / or predetermined) area below the active pattern 205. The first conductive type impurity region 205A and the second conductive type impurity region 205B of the active pattern 205 may respectively have areas extending in a vertical downward direction to corresponding areas of the active region 202. The first contact 280A' and the second contact 280B' may extend from the second surface of the substrate 201 and may be selected so that ends thereof are positioned within the active region 202 or the active pattern 205.

[0085] refer to Fig.15A and Fig. 15B , the active pattern 205 may have a structure extending in a first direction (eg, D1 direction) on the active region 202. The active region 202 may be understood as a structure provided by a portion of a semiconductor substrate (not shown).

[0086] In some example embodiments, the first contact 280A' and the second contact 280B' may include a metal-semiconductor compound layer 283' formed on the first conductive type impurity region 205A' and the second conductive type impurity region 205B', respectively. The first contact 280A' and the second contact 280B' may use the metal-semiconductor compound layer 283' to improve contact resistance with the first conductive type impurity region 205A and the second conductive type impurity region 205B. For example, the metal-semiconductor compound layer 283' may include cobalt silicide (CoSi x ), nickel silicide (NiSi x ) or manganese silicide (MnSi x ), but the inventive concept is not limited thereto.

[0087] Fig.16 , Fig.17A and Fig. 17B are cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts.

[0088] refer to Fig.16 , Fig.17A and Fig. 17B, except that the active region 202 and a portion of the semiconductor substrate 101 remain below the active pattern 205, the metal-semiconductor compound layer 283′ is disposed on the upper end of the second contact portion 280B″, and the second contact portion 280B″ further includes an insulating liner 281 for electrical insulation from the semiconductor substrate 101, the passive device 100G according to some example embodiments may be understood as Fig.12 , Fig.13A and Fig. 13B Unless otherwise described, reference may be made to the passive device 100E shown in FIG. Fig.12 , Fig.13A and Fig. 13B The description of the same or similar components of the passive device 100E shown in the figure can be used to understand the other components.

[0089] In some example embodiments, not only the active region 202 but also another region 101 of the semiconductor substrate (i.e., a region 101 of the semiconductor substrate that is not ion-implanted) may remain under the active pattern 205. In some example embodiments, the remaining semiconductor substrate 101 may replace an insulating substrate (e.g., Figure 4 201).

[0090] In some example embodiments, the second contact portion 280B" may be configured to pass through the semiconductor substrate 101, and thus may further include an insulating liner 281 to provide electrical insulation from the semiconductor substrate 101. The second contact portion 280B" may include a conductive plug 285, a conductive barrier 282 covering the upper surface and side surfaces of the conductive plug 285, and an insulating liner 281 disposed between the conductive barrier 282 and at least the semiconductor substrate 101. In a manner similar to the previous example embodiments (see Fig.14 ), the first contact 280A" and the second contact 280B" according to some example embodiments may include a metal-semiconductor compound layer 283' on upper ends thereof.

[0091] according to Fig.12 , Fig.14 and Fig.16 In some embodiments, the first contact portion and the second contact portion can be changed to back contacts directly connected to the first conductive type impurity region and the second conductive type impurity region, respectively, and the first conductive type epitaxial pattern or the second conductive type epitaxial pattern causing various resistance elements can be structurally omitted, thereby reducing the operating voltage and greatly improving the distribution of the operating voltage.

[0092] According to the above exemplary embodiments, at least one of the two contacts can be changed to a back contact directly connected to the first conductive type impurity region or the second conductive type impurity region. Such a change can limit and / or prevent the influence of the first conductive type epitaxial pattern or the second conductive type epitaxial pattern causing various resistance elements, thereby reducing the operating voltage and greatly improving the distribution of the operating voltage.

[0093] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: a substrate having a first surface and a second surface opposite to the first surface; an active pattern on the first surface of the substrate, the active pattern extending in a first direction, the active pattern having a first conductivity type impurity region and a second conductivity type impurity region arranged along the first direction, the first conductivity type impurity region and the second conductivity type impurity region contacting each other; a semiconductor pattern stacked on a portion of the active pattern between the first conductive type impurity region and the second conductive type impurity region, the semiconductor patterns being spaced apart from each other in a vertical direction; a non-active gate structure extending across the portion of the active pattern between the first conductivity type impurity region and the second conductivity type impurity region of the active pattern in a second direction, the second direction intersecting the first direction, and the non-active gate structure surrounding the semiconductor pattern; a first contact portion, passing through the substrate from the second surface of the substrate, the first contact portion being connected to the first conductive type impurity region; as well as A second contact portion passes through the substrate from the second surface of the substrate, and the second contact portion is connected to the second conductive type impurity region.

2. The semiconductor device according to claim 1, wherein The substrate includes a layer of insulating material.

3. The semiconductor device according to claim 2, wherein: Each of the first contact portion and the second contact portion includes a conductive plug, and a conductive stopper covering an upper surface and a side surface of the conductive plug.

4. The semiconductor device according to claim 3, wherein: The first conductive type impurity region and the second conductive type impurity region respectively have a first metal-semiconductor compound layer and a second metal-semiconductor compound layer, the first metal-semiconductor compound layer and the second metal-semiconductor compound layer are respectively on surfaces of the first conductive type impurity region and the second conductive type impurity region, the surfaces of the first metal-semiconductor compound layer and the second metal-semiconductor compound layer are respectively in contact with the first contact portion and the second contact portion, and The conductive barriers of the first contact and the second contact are respectively between the first metal-semiconductor compound layer and the second metal-semiconductor compound layer and the conductive plug.

5. The semiconductor device according to claim 1, wherein The semiconductor patterns are second semiconductor layers extending onto the active patterns at both sides of the inactive gate structure, and The semiconductor device further includes a first semiconductor layer on the active pattern at both sides of the inactive gate structure and between the active pattern and the second semiconductor layer, wherein a composition of the first semiconductor layer is different from a composition of the second semiconductor layer.

6. The semiconductor device according to claim 5, wherein: The inactive gate structure has a first portion on an uppermost semiconductor layer among the second semiconductor layers, and a second portion connected to the first portion, and the second portion is between the active pattern and the second semiconductor layer and between adjacent second semiconductor layers among the second semiconductor layers, and A width of each of the second portions of the non-active gate structure in the first direction is greater than a width of the first portion of the non-active gate structure in the first direction.

7. The semiconductor device according to claim 5, wherein: The first semiconductor layer and the second semiconductor layer are not intentionally doped with conductive type impurities.

8. The semiconductor device according to claim 1, further comprising: an active region on the first surface of the substrate, wherein the active pattern extends on the active area in the first direction, and The first conductive type impurity region and the second conductive type impurity region of the active pattern extend to corresponding regions of the active region, respectively.

9. The semiconductor device according to claim 8, wherein: The first contact portion extends from the second surface of the substrate into the active area or the active pattern, and The second contact extends from the second surface of the substrate into the active region or the active pattern.

10. The semiconductor device according to claim 8, wherein The substrate is a semiconductor substrate, and Each of the first contact portion and the second contact portion includes a conductive plug, a conductive barrier covering an upper surface and a side surface of the conductive plug, and an insulating spacer between the conductive barrier and the substrate.

11. The semiconductor device according to claim 1, wherein The inactive gate structure includes a gate electrode extending in the second direction and surrounding each of the semiconductor patterns, and a gate insulating film between the semiconductor pattern and the gate electrode.

12. A semiconductor device comprising: a substrate having a first surface and a second surface opposite to the first surface; an active pattern on the first surface of the substrate, the active pattern extending in a first direction, the active pattern having a first conductivity type impurity region and a second conductivity type impurity region arranged along the first direction, the first conductivity type impurity region and the second conductivity type impurity region contacting each other; a semiconductor pattern stacked on a portion of the active pattern between the first conductive type impurity region and the second conductive type impurity region, the semiconductor patterns being spaced apart from each other in a vertical direction; a non-active gate structure extending across the portion of the active pattern between the first conductivity type impurity region and the second conductivity type impurity region in a second direction, the second direction intersecting the first direction, and the non-active gate structure surrounding the semiconductor pattern; A first conductive type epitaxial pattern and a second conductive type epitaxial pattern, respectively on two side surfaces of the semiconductor pattern in the first direction, the first conductive type epitaxial pattern and the second conductive type epitaxial pattern respectively on the first conductive type impurity region and the second conductive type impurity region of the active pattern; an interlayer insulating layer on the first surface of the substrate, the interlayer insulating layer covering the first conductive type epitaxial pattern and the second conductive type epitaxial pattern; a first contact portion, passing through the interlayer insulating layer, the first contact portion being connected to the first conductive type epitaxial pattern; as well as A second contact portion passes through the substrate from the second surface of the substrate, the second contact portion being connected to the second conductive type impurity region of the active pattern.

13. The semiconductor device according to claim 12, further comprising: an active region on the first surface of the substrate, wherein the active pattern extends on the active area in the first direction, and The first conductive type impurity region and the second conductive type impurity region of the active pattern extend to corresponding regions of the active region, respectively.

14. The semiconductor device according to claim 13, wherein: The substrate is a semiconductor substrate, and The second contact portion includes a conductive plug, a conductive barrier covering an upper surface and a side surface of the conductive plug, and an insulating spacer between the conductive barrier and the substrate.

15. The semiconductor device according to claim 12, further comprising: a first interconnect structure on the interlayer insulating layer, the first interconnect structure comprising a first interconnect layer connected to the first contact portion; as well as A second interconnect structure on the second surface of the substrate, the second interconnect structure comprising a second interconnect layer connected to the second contact.

16. The semiconductor device according to claim 12, wherein: The semiconductor pattern is not intentionally doped with conductive type impurities.

17. A semiconductor device comprising: a substrate having a first surface and a second surface opposite to the first surface, and the substrate having first devices and second devices on first device regions and second device regions on the first surface of the substrate, respectively, Wherein, the first device comprises: a first active pattern extending on the first surface of the substrate in a first direction; first semiconductor patterns stacked on the first active patterns and spaced apart from each other in a vertical direction; an active gate structure extending across the first active pattern in a second direction, the second direction intersecting the first direction, and the active gate structure surrounding the first semiconductor pattern; a pair of source / drain patterns, at both sides of the first semiconductor pattern in the first direction, the pair of source / drain patterns being connected to both sides of the first semiconductor pattern, respectively; and a gate structure extending in the second direction, the gate structure surrounding the first semiconductor pattern, The second device comprises: a second active pattern extending on the first surface of the substrate in the first direction, the second active pattern having a first conductivity type impurity region and a second conductivity type impurity region arranged in the first direction, the first conductivity type impurity region and the second conductivity type impurity region contacting each other; a second semiconductor pattern stacked on a portion of the second active pattern between the first conductive type impurity region and the second conductive type impurity region, the second semiconductor patterns being spaced apart from each other in the vertical direction; an inactive gate structure extending across the portion of the second active pattern between the first conductivity type impurity region and the second conductivity type impurity region, the inactive gate structure surrounding the second semiconductor pattern; and A first contact portion and a second contact portion are connected to the first conductive type impurity region and the second conductive type impurity region, respectively, and At least one of the first contact and the second contact is connected to the first conductivity type impurity region and the second conductivity type impurity region, respectively, from the second surface of the substrate.

18. The semiconductor device according to claim 17, wherein: The width of the inactive gate structure of the second device in the first direction is greater than the width of the active gate structure of the first device in the first direction.

19. The semiconductor device according to claim 17, wherein: The first contact and the second contact pass through the substrate from the second surface of the substrate and are connected to the first conductive type impurity region and the second conductive type impurity region, respectively.

20. The semiconductor device according to claim 17, wherein The second device also includes: a first conductivity type epitaxial pattern and a second conductivity type epitaxial pattern, respectively on both side surfaces of the second semiconductor pattern in the first direction, the first conductivity type epitaxial pattern and the second conductivity type epitaxial pattern respectively on the first conductivity type impurity region and the second conductivity type impurity region of the second active pattern; and an interlayer insulating layer on the first surface of the substrate, the interlayer insulating layer covering the first conductive type epitaxial pattern and the second conductive type epitaxial pattern, The first contact portion passes through the interlayer insulating layer and is connected to the first conductive type epitaxial pattern, and the second contact portion passes through the substrate from the second surface of the substrate and is connected to the second conductive type impurity region.

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