Super junction MOSFET with fast reverse recovery and preparation method and chip thereof

Abstract

The present application belongs to the technical field of power devices, and provides a super junction MOSFET with fast reverse recovery, a preparation method thereof, and a chip thereof. The gate dielectric layer on the N-type drift region is arranged to have a concave structure, and a first polysilicon layer is formed at the bottom of the groove of the gate dielectric layer. An isolation layer located on the first polysilicon layer is formed in the groove of the gate dielectric layer. The source layer contacts the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, the gate dielectric layer, and the isolation layer. The drain layer is formed on the back side of the N-type substrate. The isolation layer is used to transfer the potential of the source layer to the first polysilicon layer when the super junction MOSFET is reversely connected, so that the conductive channel in the N-type drift region is opened, the reverse current is shunted, and the current of the body diode in the device is reduced, thereby achieving the purpose of reducing the reverse recovery current of the body diode.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to a super junction MOSFET with fast reverse recovery, a preparation method thereof, and a chip. Background Art

[0002] Planar super junction metal-oxide-semiconductor field-effect transistor (Super Junction Metal-Oxide-SemiconductorField-Effect Transistor, Planar super junction MOSFET) has the characteristics of low on-resistance and high voltage resistance, and is often used in high voltage scenarios. However, due to the presence of parasitic body diodes, in high-frequency applications, there will be large reverse recovery current and charge, resulting in large reverse recovery losses, which affects its use in high-frequency circuits. Summary of the invention

[0003] In order to solve the above technical problems, the embodiments of the present application provide a super junction MOSFET with fast reverse recovery and a preparation method and chip thereof, aiming to improve the reverse recovery capability of planar super junction MOSFET devices.

[0004] A first aspect of an embodiment of the present application provides a super junction MOSFET with fast reverse recovery, comprising:

[0005] N-type substrate;

[0006] A first P column, an N-type drift region, and a second P column are formed on the front surface of the N-type substrate; wherein the N-type drift region is located between the first P column and the second P column;

[0007] A first P-type base region and a second P-type base region, wherein the first P-type base region is formed on the first P column, and the second P-type base region is formed on the second P column;

[0008] a first N-type source region and a second N-type source region, wherein the first N-type source region is located in a groove of the first P-type base region, and the second N-type source region is located in a groove of the second P-type base region;

[0009] A gate dielectric layer and a first polysilicon layer, wherein the gate dielectric layer has a concave structure, the gate dielectric layer is located on the N-type drift region, and is in contact with the first P-type base region, the second P-type base region, the first N-type source region, and a portion of the second N-type source region, and the first polysilicon layer is located at the bottom of the groove of the gate dielectric layer;

[0010] an isolation layer, wherein the isolation layer is located in the groove of the gate dielectric layer and on the first polysilicon layer;

[0011] a source layer, contacting the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, the gate dielectric layer and the isolation layer;

[0012] A drain layer, formed on the back side of the N-type substrate;

[0013] The isolation layer is used to transfer the potential of the source layer to the first polysilicon layer when the super junction MOSFET is reversely connected.

[0014] In some embodiments, the isolation layer includes an insulating dielectric layer and a second polysilicon layer, the second polysilicon layer contacts the source layer, the second polysilicon layer is isolated from the first polysilicon layer by the insulating dielectric layer, and the first polysilicon layer is connected to the gate electrode.

[0015] In some embodiments, the thickness of the second polysilicon layer is less than the thickness of the first polysilicon layer, and the thickness of the insulating dielectric layer is less than the thickness of the second polysilicon layer.

[0016] In some embodiments, the isolation layer includes an N-type doping region and a P-type doping region, and the N-type doping region is located between the P-type doping region and the first polysilicon layer.

[0017] In some embodiments, the first polysilicon layer, the N-type doping region, and the P-type doping region are stacked, and the thickness of the N-type doping region is equal to the thickness of the P-type doping region, and the thickness of the N-type doping region and the thickness of the P-type doping region are less than the thickness of the first polysilicon layer.

[0018] In some embodiments, the isolation layer is a Schottky diode, an anode of the Schottky diode is connected to the source layer, and a cathode of the Schottky diode is connected to the first polysilicon layer.

[0019] In some embodiments, the thickness of the isolation layer is the same as the thickness of the first polysilicon layer.

[0020] In some embodiments, the groove of the gate dielectric layer is a structure that is narrow at the top and wide at the bottom.

[0021] A second aspect of the embodiment of the present application further provides a method for preparing a super junction MOSFET with fast reverse recovery, the method comprising:

[0022] Epitaxially forming an N-type drift layer on the front side of the N-type substrate;

[0023] Processing the N-type drift layer to obtain a first P column, an N-type drift region, and a second P column; wherein the N-type drift region is located between the first P column and the second P column;

[0024] Performing P-type ion implantation on the first P column and the first region of the N-type drift region to form a first P-type base region, and performing P-type ion implantation on the second P column and the second region of the N-type drift region to form a second P-type base region; wherein the first region and the second region of the N-type drift region are arranged opposite to each other and do not contact each other;

[0025] The first P-type base region is subjected to an N-type ion implantation process to form a first N-type source region and a first P-type base region with a concave structure, and the second P-type base region is subjected to an N-type ion implantation process to form a second N-type source region and a second P-type base region with a concave structure; wherein the first N-type source region is located in a groove of the first P-type base region, and the second N-type source region is located in a groove of the second P-type base region;

[0026] Forming a gate dielectric layer with a concave structure on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, and the N-type drift region, and depositing a polysilicon material at the bottom of the groove of the gate dielectric layer to form a first polysilicon layer;

[0027] forming an isolation layer on the first polysilicon layer; the isolation layer is located in the groove of the gate dielectric layer;

[0028] forming a source layer in contact with the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, the gate dielectric layer and the isolation layer, and forming a drain layer on the back side of the N-type substrate;

[0029] The isolation layer is used to transfer the potential of the source layer to the first polysilicon layer when the super junction MOSFET is reversely connected.

[0030] A third aspect of the embodiments of the present application further provides a chip, comprising a super junction MOSFET with fast reverse recovery as described in any of the above embodiments.

[0031] Beneficial effects of the embodiments of the present application: The present application sets an isolation layer in the groove of the gate dielectric layer of the planar super junction MOSFET, and makes the isolation layer contact with the first polysilicon layer and the source layer. When the device is reversely connected (the source electrode is connected to a positive potential, the drain electrode is connected to a negative potential, and the gate electrode is connected to a 0 potential), the isolation layer transmits the source positive voltage signal to the gate, so that the MOSFET conductive channel is opened, the current of the parasitic body diode is shunted, and the reverse recovery current and charge of the body diode are greatly reduced, thereby optimizing the reverse recovery characteristics of the device without affecting the forward conduction characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the structure of a super junction MOSFET with fast reverse recovery provided in an embodiment of the present application Figure 1 ;

[0033] Figure 2 Schematic diagram of the structure of a super junction MOSFET with fast reverse recovery provided in an embodiment of the present application Figure 2 ;

[0034] Figure 3a A third structural diagram of a super junction MOSFET with fast reverse recovery provided in an embodiment of the present application;

[0035] Figure 3b A fourth structural diagram of a super junction MOSFET with fast reverse recovery provided in an embodiment of the present application;

[0036] Figure 3c Structural schematic diagram 5 of a super junction MOSFET with fast reverse recovery provided in an embodiment of the present application;

[0037] Figure 4a Schematic diagram of the structure of a super junction MOSFET with fast reverse recovery provided in an embodiment of the present application Figure 6 ;

[0038] Figure 4b Schematic diagram of the structure of a super junction MOSFET with fast reverse recovery provided in an embodiment of the present application Figure 7 ;

[0039] Figure 4c Schematic diagram of the structure of a super junction MOSFET with fast reverse recovery provided in an embodiment of the present application Figure 8 ;

[0040] Figure 5a A schematic diagram of the simulation structure of a conventional planar superjunction MOSFET provided in an embodiment of the present application;

[0041] Figure 5b In the embodiment of this application Figure 2 A schematic diagram of a simulation structure of a super junction MOSFET structure with fast reverse recovery is shown;

[0042] Figure 5c In the embodiment of this application Figure 3a A schematic diagram of a simulation structure of a super junction MOSFET structure with fast reverse recovery is shown;

[0043] Figure 6 It is a comparison diagram of the simulation results of the output characteristic curves of the traditional planar super junction MOSFET and the super junction MOSFET with fast reverse recovery in the embodiment of the present application;

[0044] Figure 7 It is a comparison diagram of the breakdown voltage simulation results of the conventional planar super junction MOSFET and the super junction MOSFET with fast reverse recovery in the embodiment of the present application;

[0045] Figure 8 It is a comparison diagram of transfer characteristic curve simulation results of a conventional planar super junction MOSFET and a super junction MOSFET with fast reverse recovery in an embodiment of the present application;

[0046] Fig. 9 It is a comparison diagram of reverse recovery curve simulation results of a conventional planar super junction MOSFET and a super junction MOSFET with fast reverse recovery in an embodiment of the present application;

[0047] Fig.10 It is a schematic flow chart of a method for preparing a super junction MOSFET with fast reverse recovery provided in an embodiment of the present application;

[0048] Fig.11 is a schematic diagram of forming an N-type drift layer on an N-type substrate provided by an embodiment of the present application;

[0049] Fig.12 is a schematic diagram of forming a first P column, an N-type drift region, and a second P column provided in an embodiment of the present application;

[0050] Fig.13 is a schematic diagram of forming a first P-type base region, a second P-type base region, a first N-type source region, and a second N-type source region provided in an embodiment of the present application;

[0051] Fig.14 It is a schematic diagram of forming a gate dielectric layer, a first polysilicon layer, and an isolation layer provided in an embodiment of the present application;

[0052] Fig.15 It is a schematic diagram of etching the gate dielectric layer, the first polysilicon layer, and the isolation layer to form a concave gate dielectric layer according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0055] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0056] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0057] Due to the presence of parasitic body diodes, planar superjunction MOSFETs will have large reverse recovery currents and charges in high-frequency applications, resulting in large reverse recovery losses, which affects their use in high-frequency circuits.

[0058] In order to solve the above technical problems, the present application embodiment provides a super junction MOSFET with fast reverse recovery, see Figure 1 As shown, the super junction MOSFET with fast reverse recovery in this embodiment includes: an N-type substrate 110, a first P-column 121, an N-type drift region 123, a second P-column 122, a first P-type base region 124, a second P-type base region 126, a first N-type source region 125, a second N-type source region 127, a gate dielectric layer 130, a first polysilicon layer 140, an isolation layer 150, a source layer 160, and a drain layer 170.

[0059] The first P column 121, the N-type drift region 123, and the second P column 122 are formed on the front surface of the N-type substrate 110; the N-type drift region 123 is located between the first P column 121 and the second P column 122. The first P-type base region 124 is formed on the first P column 121, and the second P-type base region 126 is formed on the second P column 122; the first N-type source region 125 is located in the groove of the first P-type base region 124, and the second N-type source region 127 is located in the groove of the second P-type base region 126. The gate dielectric layer 130 has a concave structure and is located on the N-type drift region 123. The gate dielectric layer 130 contacts the first P-type base region 124, the second P-type base region 126, the first N-type source region 125, and a portion of the second N-type source region 127. The first polysilicon layer 140 is located at the bottom of the groove of the gate dielectric layer 130; the isolation layer 150 is located in the groove of the gate dielectric layer 130 and is located on the first polysilicon layer 140. The source layer 160 is in contact with the first N-type source region 125, the second N-type source region 127, the first P-type base region 124, the second P-type base region 126, the gate dielectric layer 130 and the isolation layer 150; the drain layer 170 is formed on the back side of the N-type substrate 110.

[0060] like Figure 1 As shown, the source layer 160 is in a concave structure, the groove of the source layer 160 is directed toward the drain layer 170, the source layer 160 is connected to the source electrode, the drain layer 170 is connected to the drain electrode, the first polysilicon layer 140 is connected to the gate electrode, the gate dielectric layer 130, the first polysilicon layer 140, and the isolation layer 150 are located in the groove of the concave structure, and the gate dielectric layer 130 in a concave structure (upper concave structure) is embedded in the concave structure of the source layer 160 (lower concave structure), and the vertical portion of the gate dielectric layer 130 is in contact with the source layer 160.

[0061] In the embodiment of the present application, the isolation layer 150 is used to transfer the potential of the source layer 160 to the first polysilicon layer 140 when the super junction MOSFET is reversely connected.

[0062] Specifically, in this embodiment, by arranging an isolation layer 150 in the groove of the gate dielectric layer 130 of the planar super junction MOSFET, and making the isolation layer 150 contact the first polysilicon layer 140 and the source layer 160, when the device is connected forward, the source layer 160 and the first polysilicon layer 140 are isolated by the isolation layer 150, and the source layer 160 and the first polysilicon layer 140 do not affect each other, and will not affect the forward conduction characteristics of the device. When the device is reversely conducted, the isolation layer 150 transmits the positive voltage signal provided by the source electrode to the gate, so that the MOSFET conductive channel is opened, the current of the parasitic body diode is shunted, and the reverse recovery current and charge of the body diode are greatly reduced, and the reverse recovery characteristics of the device are optimized without affecting the forward conduction characteristics of the device.

[0063] In one embodiment of the present application, Figure 2 As shown, the isolation layer 150 may include an insulating dielectric layer 151 and a second polysilicon layer 152. The second polysilicon layer 152 is in contact with the source layer 160, the second polysilicon layer 152 is isolated from the first polysilicon layer 140 by the insulating dielectric layer 151, and the first polysilicon layer 140 is connected to the gate electrode.

[0064] In this embodiment, the second polysilicon layer 152 is isolated from the first polysilicon layer 140 by the insulating dielectric layer 151. When the device is forwardly connected, the potential of the source layer 160 is transferred to the second polysilicon layer 152. At this time, the potential of the source layer 160 is small and is smaller than the potential of the gate electrode. Since the insulating dielectric layer 151 is provided between the second polysilicon layer 152 and the first polysilicon layer 140, the second polysilicon layer 152 and the first polysilicon layer 140 do not affect each other, and will not affect the forward conduction characteristics of the device. When the device is reverse-conducted, the potential of the second polysilicon layer 152 is greater than the potential of the first polysilicon layer 140. Since the thickness of the insulating dielectric layer 151 is relatively small, the potential of the second polysilicon layer 152 can be transferred to the first polysilicon layer 140. The insulating dielectric layer 151 transfers the positive voltage signal provided by the source electrode to the gate, so that the MOSFET conductive channel is opened, the current of the parasitic body diode is diverted, and the reverse recovery current and charge of the body diode are greatly reduced. On the basis of not affecting the forward conduction characteristics of the device, the reverse recovery characteristics of the device are optimized.

[0065] In one embodiment, the material of the insulating dielectric layer 151 may be the same as that of the gate dielectric layer 130 .

[0066] In one embodiment, the insulating dielectric layer 151 may be made of hafnium oxide material or silicon oxide material.

[0067] In one embodiment, Figure 2 As shown, the second polysilicon layer 152 is located directly above the first polysilicon layer 140 , the second polysilicon layer 152 and the first polysilicon layer 140 are isolated by the insulating dielectric layer 151 , and the thickness of the second polysilicon layer 152 is less than the thickness of the first polysilicon layer 140 .

[0068] In one embodiment, Figure 2 As shown, the width of the second polysilicon layer 152, the width of the first polysilicon layer 140 and the width of the insulating dielectric layer 151 are the same, the thickness of the second polysilicon layer 152 is less than the thickness of the first polysilicon layer 140, and the thickness of the insulating dielectric layer 151 is less than the thickness of the second polysilicon layer 152.

[0069] In one embodiment, the thickness of the insulating dielectric layer 151 is one tenth of the thickness of the first polysilicon layer 140 .

[0070] In the embodiment of the present application, the gate is divided into two parts, an upper part and an lower part, separated by a thin insulating layer in the middle, and the first polysilicon layer 140 located in the lower layer is connected to the gate signal, and the second polysilicon layer 152 located in the upper layer is connected to the source signal, so that without affecting the forward conduction characteristics of the device, when the device is reversely conducted, the second polysilicon layer 152 located in the upper layer connected to the positive potential of the source can transfer the positive potential to the first polysilicon layer 140 located in the lower layer, so as to partially open the conductive channel, shunt the current, reduce the current in the body diode, thereby reducing the reverse recovery current of the body diode, and improving the reverse recovery capability of the device.

[0071] In one embodiment of the present application, Figure 3a As shown, the isolation layer 150 in this embodiment may include an N-type doping region 153 and a P-type doping region 154 , wherein the N-type doping region 153 is located between the P-type doping region 154 and the first polysilicon layer 140 .

[0072] In one embodiment, Figure 3a As shown, the first polysilicon layer 140, the N-type doping region 153 and the P-type doping region 154 are stacked, and the thickness of the N-type doping region 153 is equal to the thickness of the P-type doping region 154, and the thickness of the N-type doping region 153 and the thickness of the P-type doping region 154 are less than the thickness of the first polysilicon layer 140.

[0073] In the embodiment of the present application, the N-type doping region 153 and the P-type doping region 154 form a PN junction and are located above the first polysilicon layer 140. The N-type doping region 153 contacts the first polysilicon layer 140, and the P-type doping region 154 located in the upper layer is connected to the source signal. When the device is forward connected, the potential of the source layer 160 is small and smaller than the potential of the gate electrode. The N-type doping region 153 and the P-type doping region 154 form a PN junction reverse connection, and the source layer 160 and the first polysilicon layer 140 do not affect each other, and will not affect the forward conduction characteristics of the device. When the device is reversely conducted (the source electrode is connected to a positive potential, the drain electrode is connected to a negative potential, and the gate electrode is connected to a 0 potential), the P-type doping region 154 located in the upper layer connected to the positive potential of the source can transfer the positive potential to the first polysilicon layer 140 located in the lower layer, so as to partially open the conductive channel, shunt the current, reduce the current in the body diode, thereby reducing the reverse recovery current of the body diode, and improving the reverse recovery capability of the device.

[0074] In one embodiment, Figure 3bAs shown, the N-type doping region 153 and the P-type doping region 154 can be mutually embedded concave-convex structures to increase the contact area between the N-type doping region 153 and the P-type doping region 154, which is beneficial for the source layer 160 to input a larger current to the first polysilicon layer 140 via the PN junction formed by the N-type doping region 153 and the P-type doping region 154, thereby improving the switching characteristics of the super junction MOSFET.

[0075] In one embodiment, Figure 3c As shown, the N-type doping region 153 may be an X-shaped structure, and the P-type doping region 154 and the N-type doping region 153 are embedded with each other.

[0076] In one embodiment, in the groove of the gate dielectric layer 130 , the distribution density of the N-type doping regions 153 of the “X”-shaped structure on both sides of the groove of the gate dielectric layer 130 is smaller than the distribution density of the N-type doping regions 153 of the “X”-shaped structure in the center of the groove.

[0077] For example, the entire groove of the gate dielectric layer 130 is divided into three equal parts to obtain a left groove part, a middle groove part and a right groove part. The left groove part and the right groove part can respectively include three N-type doping regions 153 with an "X"-shaped structure, and the middle groove part can respectively include five N-type doping regions 153 with an "X"-shaped structure, so that the distribution density of the N-type doping regions 153 with an "X"-shaped structure on both sides of the groove is smaller than the distribution density of the N-type doping regions 153 with an "X"-shaped structure in the center of the groove, so as to further increase the contact area between the source layer 160 and the N-type doping region 153, and increase the contact area between the N-type doping region 153 and the P-type doping region 154, which is beneficial for the source layer 160 to input a larger current to the first polysilicon layer 140 via the PN junction composed of the N-type doping region 153 and the P-type doping region 154, thereby improving the switching characteristics of the super junction MOSFET.

[0078] In one embodiment, the height of the N-type doping region 153 of the "X"-shaped structure on both sides of the groove of the gate dielectric layer 130 is smaller than the height of the N-type doping region 153 of the "X"-shaped structure in the center of the groove, so that the PN junction contact area on both sides of the groove of the gate dielectric layer 130 is smaller than the PN junction contact area in the center of the groove of the gate dielectric layer 130.

[0079] In one embodiment of the present application, Figure 4a As shown, the isolation layer 150 in this embodiment may also be a Schottky diode, the anode 156 of the Schottky diode is connected to the source layer 160 , and the cathode 155 of the Schottky diode is connected to the first polysilicon layer 140 .

[0080] In the embodiment of the present application, a unidirectionally conductive Schottky diode is arranged above the first polysilicon layer 140, and the cathode 155 of the Schottky diode is connected to the first polysilicon layer 140, and the anode 156 of the Schottky diode is connected to the source layer 160. When the device is forward-conducting, the Schottky diode is reverse-biased, which does not affect the forward conduction characteristics of the device. When the device is reverse-conducting, the Schottky diode is turned on. At this time, the positive potential of the source layer 160 is conducted to the first polysilicon layer 140, so that the conductive channel is opened, the reverse current is shunted, and the current in the device body diode is reduced, thereby achieving the purpose of reducing the reverse recovery current of the device body diode and improving the reverse recovery capability of the device.

[0081] In one embodiment, the anode 156 of the Schottky diode is a Schottky metal material, and the cathode 155 of the Schottky diode is an N-type doped material.

[0082] In one embodiment, Figure 4b As shown, the anode 156 and cathode 155 of the Schottky diode can be mutually embedded concave-convex structures to increase the contact area between the cathode 155 of the Schottky diode and the anode 156 of the Schottky diode, which is beneficial for the source layer 160 to input a larger current to the first polysilicon layer 140 via the Schottky diode composed of the cathode 155 of the Schottky diode and the anode 156 of the Schottky diode, thereby improving the switching characteristics of the super junction MOSFET.

[0083] In one embodiment, Figure 4c As shown, the anode 156 of the Schottky diode may be a "X"-shaped structure, and the anode 156 of the Schottky diode and the cathode 155 of the Schottky diode are embedded with each other.

[0084] In one embodiment, in the groove of the gate dielectric layer 130 , the distribution density of the Schottky diode anodes in the “X” shape on both sides of the groove of the gate dielectric layer 130 is less than the distribution density of the Schottky diode anodes in the “X” shape in the center of the groove of the gate dielectric layer 130 .

[0085] For example, the entire groove of the gate dielectric layer 130 is divided into three equal parts to obtain a left groove part, a middle groove part and a right groove part. The left groove part and the right groove part can respectively include three Schottky diode anodes with an "X" structure, and the middle groove part can respectively include five Schottky diode anodes with an "X" structure, so that the distribution density of the Schottky diode anodes with an "X" structure on both sides of the groove is smaller than the distribution density of the Schottky diode anodes with an "X" structure in the center of the groove, so as to further increase the contact area between the source layer 160 and the anode 156 of the Schottky diode, and increase the contact area between the cathode 155 of the Schottky diode and the anode 156 of the Schottky diode, which is beneficial for the source layer 160 to input a larger current to the first polysilicon layer 140 via the Schottky diode composed of the cathode 155 of the Schottky diode and the anode 156 of the Schottky diode, thereby improving the switching characteristics of the super junction MOSFET.

[0086] In one embodiment, the height of the Schottky diode anode in the "X" shape on both sides of the groove of the gate dielectric layer 130 is smaller than the height of the Schottky diode anode in the "X" shape in the center of the groove, so that the area of ​​the Schottky contact on both sides of the groove of the gate dielectric layer 130 is smaller than the area of ​​the Schottky contact in the center of the groove of the gate dielectric layer 130.

[0087] In one embodiment, the thickness of the isolation layer 150 in this embodiment is the same as the thickness of the first polysilicon layer 140 .

[0088] In one embodiment, the groove of the gate dielectric layer 130 in this embodiment has a structure that is narrow at the top and wide at the bottom.

[0089] In this embodiment, by setting the groove of the gate dielectric layer 130 to be narrow at the top and wide at the bottom, a first polysilicon layer 140 with a larger width is set at the bottom of the groove of the gate dielectric layer 130, and an isolation layer 150 with a smaller width is set above the groove of the gate dielectric layer 130, and the width of the isolation layer 150 gradually increases from the source layer 160 to the drain layer 170, which is beneficial to the isolation between the source layer 160 and the first polysilicon layer 140 when the device is positively connected, and reduces the impact on the forward conduction characteristics of the device. In addition, when the device is reversely conducted, the potential of the source layer 160 can transfer the positive potential to the first polysilicon layer 140 located at the lower layer, which can reduce the voltage division loss of the potential in the isolation layer 150, thereby partially opening the conductive channel, shunting the current, reducing the current in the body diode, thereby reducing the reverse recovery current of the body diode, and improving the reverse recovery capability of the device.

[0090] In one embodiment, the N-type drift region 123 between the first P-type base region 124 and the second P-type base region 126 is made of N-type 3C—SiC material.

[0091] In this embodiment, by setting the semiconductor material of the N-type drift region 123 between the first P-type base region 124 and the second P-type base region 126 to an N-type 3C-SiC material, and performing N-type ion doping treatment on the first P-type base region 124 and the second P-type base region 126, the heat dissipation of the parasitic BJT region in the device can be further increased, the misconduction of the BJT device can be suppressed, and the avalanche resistance of the device can be increased.

[0092] In some embodiments, the first P-type base region 124 and the second P-type base region 126 are P-type 3C-SiC materials.

[0093] In some embodiments, both ends of the horizontal portion of the first N-type source region 125 are in contact with the first P-type base region 124 , and PN junctions are formed between both ends of the horizontal portion of the first N-type source region 125 and the first P-type base region 124 .

[0094] In some embodiments, both ends of the horizontal portion of the second N-type source region 127 are in contact with the second P-type base region 126 , and PN junctions are formed between both ends of the horizontal portion of the second N-type source region 127 and the second P-type base region 126 .

[0095] In some embodiments, the vertical portions of the first N-type source region 125 and the second N-type source region 127 are trapezoidal structures, and the widths of the vertical portions of the first N-type source region 125 and the second N-type source region 127 gradually increase in the direction from the drain layer 170 to the source layer 160 to adjust the current density distribution on both sides of the first N-type source region 125 and the second N-type source region 127 to improve the avalanche resistance of the device.

[0096] Figure 5a This is a schematic diagram of the simulation structure of a traditional planar superjunction MOSFET. Figure 5b In the embodiment of this application Figure 2 The super junction MOSFET structure with fast reverse recovery shown in FIG. Figure 2 The schematic diagram of the simulation structure of the structure) is shown in Figure 2. Figure 5c In the embodiment of this application Figure 3a The super junction MOSFET structure with fast reverse recovery shown in FIG. Figure 3a The following table 1 shows the simulation structure of the conventional planar super junction MOSFET and the embodiment of the present application. Figure 2 Structure and Figure 3a The characteristic parameters of the structure, combined with Figure 5b , Figure 5cAs shown in Table 1, the present application arranges the first polysilicon layer 140 and the isolation layer 150 in the concave gate dielectric layer 130, and makes the isolation layer 150 contact the source layer 160 and the first polysilicon layer 140 respectively, so that the isolation layer 150 transfers the potential of the source layer 160 to the first polysilicon layer 140 when the super junction MOSFET is reversely connected, thereby optimizing the reverse recovery characteristics of the super junction MOSFET without affecting its forward conduction characteristics, especially Figure 3a The structure can reduce the reverse recovery current (Irrm) by 57%, the reverse recovery time (Trr) by 28%, and the reverse recovery charge (Qrr) by 69%, making Figure 2 Structure and Figure 3a The structure can be applied to high-voltage and high-frequency circuits. Among them, IDsat in Table 1 is the saturated drain current, Ron is the on-resistance, BV is the breakdown voltage, and Vth is the threshold voltage. The super-junction MOSFET with fast reverse recovery in the embodiment of the present application does not reduce the static characteristics of the device, and its saturated drain current (IDsat), on-resistance (Ron), breakdown voltage (BV), and threshold voltage (Vth) do not change significantly.

[0097] Table 1:

[0098]

[0099] Figure 6 The output characteristic curve simulation results comparison diagram of the traditional planar super junction MOSFET and the super junction MOSFET with fast reverse recovery in the embodiment of the present application, wherein the horizontal axis is the source-drain voltage VDS, the vertical axis is the source-drain current IDS, and the curve Prop1 (red dotted line) is the output characteristic curve of the super junction MOSFET with fast reverse recovery in the embodiment of the present application. Figure 2 The output characteristic curve simulation results of the structure, curve Prop2 (blue dotted line) is the embodiment of this application Figure 3a The output characteristic curve simulation results of the structure, curve Conv (black solid line) is the output characteristic curve simulation result of the traditional planar super junction MOSFET.

[0100] Figure 7 : This is a comparison chart of the breakdown voltage simulation results of the traditional planar super junction MOSFET and the super junction MOSFET with fast reverse recovery in the embodiment of the present application, wherein the abscissa is the source-drain voltage VDS, the ordinate is the source-drain current IDS, and the curve Prop1 (red dotted line) is the embodiment of the present application. Figure 2 The breakdown voltage simulation results of the structure, curve Prop2 (blue dashed line) is the embodiment of this application Figure 3a The curve Conv (black solid line) is the breakdown voltage simulation result of the traditional planar super junction MOSFET. Figure 7As shown, the breakdown voltages of the conventional planar super junction MOSFET and the super junction MOSFET with fast reverse recovery in the embodiment of the present application are almost the same.

[0101] Figure 8 : is a comparison chart of the transfer characteristic curve simulation results of the traditional planar super junction MOSFET and the super junction MOSFET with fast reverse recovery in the embodiment of the present application. Figure 8 The curve Prop1 (red dashed line) in the embodiment of this application is Figure 2 Simulation results of the transfer characteristic curve of the structure, Figure 8 The curve Prop2 (blue dashed line) in the embodiment of this application is Figure 3a Simulation results of the transfer characteristic curve of the structure, Figure 8 The curve Conv (black solid line) in is the simulation result of the transfer characteristic curve of the traditional planar super junction MOSFET.

[0102] Fig. 9 The reverse recovery curve simulation results of the conventional planar super junction MOSFET and the super junction MOSFET with fast reverse recovery in the embodiment of the present application are compared under the test conditions of power supply voltage VDD=400V and voltage between gate and source VGS=10V. Fig. 9 The horizontal axis is the reverse recovery time, and the vertical axis is the current IF; Fig. 9 The curve Prop1 (red dashed line) in the embodiment of this application is Figure 2 The reverse recovery curve simulation results of the structure, Fig. 9 The curve Prop2 (blue dashed line) in the embodiment of this application is Figure 3a The reverse recovery curve simulation results of the structure, Fig. 9 The curve Conv (black solid line) in is the simulation result of the reverse recovery curve of the traditional planar super junction MOSFET.

[0103] As shown in Table 1, Figure 6 , Figure 7 , Figure 8 and Fig. 9 As shown, the super junction MOSFET with fast reverse recovery in the embodiment of the present application does not reduce the static characteristics of the device, and its saturated drain current (IDsat), on-resistance (Ron), breakdown voltage (BV), and threshold voltage (Vth) do not change significantly. However, the reverse recovery current is significantly reduced, and the reverse recovery time is also significantly reduced.

[0104] The present application also provides a method for preparing a super junction MOSFET with fast reverse recovery, see Fig.10 As shown, the preparation method in this embodiment includes steps S100 to S700.

[0105] In step S100 , an N-type drift layer is epitaxially formed on the front surface of the N-type substrate 110 .

[0106] Combination Fig.11 As shown, an N-type drift layer 120 may be formed on the front surface of the N-type substrate 110 by an epitaxial growth process, and the thickness of the N-type drift layer 120 is greater than the thickness of the N-type substrate 110 .

[0107] In some embodiments, the thickness of the N-type substrate 110 may be 3-10 um.

[0108] In some embodiments, the doping concentration of N-type doping ions in the N-type substrate 110 may be 1e 20 cm-3.

[0109] In some embodiments, the thickness of the N-type drift layer 120 epitaxially grown on the front side of the N-type substrate 110 in step S100 may be 20-60 um.

[0110] In some embodiments, in step S100, the doping concentration of N-type doping ions in the N-type drift layer 120 epitaxially grown on the front side of the N-type substrate 110 may be 1e 15 ~1e 17 cm -3 .

[0111] In step S200 , the N-type drift layer is processed to obtain a first P column 121 , an N-type drift region 123 , and a second P column 122 .

[0112] In this embodiment, the N-type drift region 123 is located between the first P column 121 and the second P column 122 .

[0113] Combination Fig.12 As shown, deep grooves can be formed by etching the two side areas of the first N-type drift region 123, and then P-type semiconductor materials are epitaxially grown in the deep grooves to form the first P column 121 and the second P column 122 respectively, and the N-type drift region 123 is located between the first P column 121 and the second P column 122.

[0114] In some embodiments, the first P column 121 and the second P column 122 may also be formed by implanting P-type doping ions into regions on both sides of the N-type drift layer.

[0115] In some embodiments, the widths of the N-type drift region 123 , the first P column 121 , and the second P column 122 are the same.

[0116] In some embodiments, the doping concentration of the P-type doping ions in the first P column 121 and the second P column 122 may be 1e 15 ~1e 17 cm -3 .

[0117] In step S300 , P-type ion implantation is performed on the first P column 121 and the first region of the N-type drift region 123 to form a first P-type base region 124 , and P-type ion implantation is performed on the second P column 122 and the second region of the N-type drift region 123 to form a second P-type base region 126 .

[0118] In this embodiment, combined with Fig.13 As shown, the first area and the second area of ​​the N-type drift region 123 are arranged relatively to each other, and the first area and the second area of ​​the N-type drift region 123 do not contact each other. Through the P-type ion implantation process, a first P-type base region 124 can be formed on the first P column 121, and a second P column 122 base region can be formed on the second P column 122. The width of the first P-type base region 124 gradually increases from the first P column 121 upward, and the width of the second P-type base region 126 gradually increases from the second P column 122 upward.

[0119] In some embodiments, an N-type drift region 123 can be formed by continuing to epitaxially grow N-type material on the first P column 121, the N-type drift region 123, and the second P column 122, and P-type dopant ions are injected into partial regions on the left and right sides of the N-type drift region 123 to form a first P-type base region 124, an N-type drift region 123, and a second P-type base region 126, so that the first P-type base region 124 is formed on the first P column 121, the second P-type base region 126 is formed on the second P column 122, and a corresponding N-type drift region 123 is also formed between the first P-type base region 124 and the second P-type base region 126.

[0120] In step S400, the first P-type base region 124 is implanted with an N-type ion to form a first N-type source region 125 and a first P-type base region 124 with a concave structure, and the second P-type base region 126 is implanted with an N-type ion to form a second N-type source region 127 and a second P-type base region 126 with a concave structure.

[0121] In this embodiment, combined with Fig.13 As shown, N-type ion implantation can be performed on the central areas of the first P-type base region 124 and the second P-type base region 126 respectively to obtain a first N-type source region 125 and a second N-type source region 127, and the first P-type base region 124 is made to have a concave structure, and the second P-type base region 126 is also made to have a concave structure, the first N-type source region 125 is located in the groove of the first P-type base region 124, and the second N-type source region 127 is located in the groove of the second P-type base region 126.

[0122] In step S500, a gate dielectric layer 130 with a concave structure is formed on the first N-type source region 125, the second N-type source region 127, the first P-type base region 124, the second P-type base region 126, and the N-type drift region 123, and polysilicon material is deposited at the bottom of the groove of the gate dielectric layer 130 to form a first polysilicon layer 140.

[0123] In step S600 , an isolation layer 150 is formed on the first polysilicon layer 140 ; ​​the isolation layer 150 is located in the groove of the gate dielectric layer 130 .

[0124] In the present application embodiment, combined Fig.14 As shown, gate dielectric material, polysilicon material and isolation material can be deposited in sequence on the first N-type source region 125, the second N-type source region 127, the first P-type base region 124, the second P-type base region 126 and the N-type drift region 123 to form a stacked gate dielectric layer 130, a first polysilicon layer 140 and an isolation layer 150, and then the gate dielectric material, polysilicon material and isolation material on the partial surfaces of the first N-type source region 125, the second N-type source region 127, the first P-type base region 124 and the second P-type base region 126 are etched so that the gate dielectric layer 130 is located on the N-type drift region 123 and partial areas of the first P-type base region 124, the second P-type base region 126, the first N-type source region 125 and the second N-type source region 127. Fig.15 As shown, a gate dielectric material is formed on the side surfaces of the first polysilicon layer 140 and the isolation layer 150 , thereby forming a gate dielectric layer 130 with a concave structure.

[0125] In step S700 , a source layer 160 is formed in contact with the first N-type source region 125 , the second N-type source region 127 , the first P-type base region 124 , the second P-type base region 126 , the gate dielectric layer 130 and the isolation layer 150 , and a drain layer 170 is formed on the back side of the N-type substrate 110 .

[0126] In this embodiment, the device structure after forming the source layer 160 and the drain layer 170 is as follows: Figure 1 As shown, the first polysilicon layer 140 is located at the bottom of the groove of the gate dielectric layer 130; the isolation layer 150 is located in the groove of the gate dielectric layer 130 and is located on the first polysilicon layer 140. The source layer 160 is in contact with the first N-type source region 125, the second N-type source region 127, the first P-type base region 124, the second P-type base region 126, the gate dielectric layer 130 and the isolation layer 150; the drain layer 170 is formed on the back side of the N-type substrate 110.

[0127] In the embodiment of the present application, when the device is forward connected, the source layer 160 and the first polysilicon layer 140 are isolated by the isolation layer 150, and the source layer 160 and the first polysilicon layer 140 do not affect each other, and will not affect the forward conduction characteristics of the device. When the super junction MOSFET is reversely connected (the source electrode is connected to a positive potential, the drain electrode is connected to a negative potential, and the gate electrode is connected to a 0 potential), the isolation layer 150 transfers the potential of the source layer 160 to the first polysilicon layer 140. The isolation layer 150 transfers the positive voltage signal provided by the source electrode to the gate, so that the MOSFET conductive channel is opened, the current of the parasitic body diode is shunted, and the reverse recovery current and charge of the body diode are greatly reduced. On the basis of not affecting the forward conduction characteristics of the device, the reverse recovery characteristics of the device are optimized.

[0128] In some embodiments, Figure 2 As shown, the isolation layer 150 may include an insulating dielectric layer 151 and a second polysilicon layer 152. The second polysilicon layer 152 is in contact with the source layer 160, the second polysilicon layer 152 is isolated from the first polysilicon layer 140 by the insulating dielectric layer 151, and the first polysilicon layer 140 is connected to the gate electrode.

[0129] In some embodiments, Figure 3a As shown, the isolation layer 150 may include an N-type doping region 153 and a P-type doping region 154 , wherein the N-type doping region 153 is located between the P-type doping region 154 and the first polysilicon layer 140 .

[0130] In some embodiments, Figure 4a As shown, the isolation layer 150 may also be a Schottky diode, an anode 156 of the Schottky diode is connected to the source layer 160 , and a cathode 155 of the Schottky diode is connected to the first polysilicon layer 140 .

[0131] An embodiment of the present application also provides a chip, comprising a super junction MOSFET with fast reverse recovery as in any of the above embodiments.

[0132] In this embodiment, the chip includes a chip substrate, on which one or more super junction MOSFETs with fast reverse recovery are arranged. The super junction MOSFET with fast reverse recovery can be prepared by the preparation method in any of the above embodiments, or the super junction MOSFET with fast reverse recovery in any of the above embodiments can be arranged on the chip substrate.

[0133] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit with a super junction MOSFET with fast reverse recovery.

[0134] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0135] The beneficial effects of the embodiments of the present application are as follows: by setting the gate dielectric layer 130 on the N-type drift region 123 to have a concave structure, and forming the first polysilicon layer 140 at the bottom of the groove of the gate dielectric layer 130, an isolation layer 150 located on the first polysilicon layer 140 is formed in the groove of the gate dielectric layer 130, the source layer 160 is in contact with the first N-type source region 125, the second N-type source region 127, the first P-type base region 124, the second P-type base region 126, the gate dielectric layer 130 and the isolation layer 150, the drain layer 170 is formed on the back side of the N-type substrate 110, and the isolation layer 150 is used to transfer the potential of the source layer 160 to the first polysilicon layer 140 when the super junction MOSFET is reversely connected, so that the conductive channel in the N-type drift region 123 is opened, the reverse current is shunted, and the current of the body diode in the device is reduced, thereby achieving the purpose of reducing the reverse recovery current of the body diode.

[0136] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0137] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0138] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0139] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0140] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A super junction MOSFET with fast reverse recovery, characterized in that: include: N-type substrate; A first P column, an N-type drift region, and a second P column are formed on the front surface of the N-type substrate; wherein the N-type drift region is located between the first P column and the second P column; A first P-type base region and a second P-type base region, wherein the first P-type base region is formed on the first P-pillar, and the second P-type base region is formed on the second P-pillar; a first N-type source region and a second N-type source region, wherein the first N-type source region is located in a groove of the first P-type base region, and the second N-type source region is located in a groove of the second P-type base region; A gate dielectric layer and a first polysilicon layer, wherein the gate dielectric layer has a concave structure, the gate dielectric layer is located on the N-type drift region, and is in contact with the first P-type base region, the second P-type base region, the first N-type source region, and a portion of the second N-type source region, and the first polysilicon layer is located at the bottom of the groove of the gate dielectric layer; an isolation layer, the isolation layer being located in the groove of the gate dielectric layer and on the first polysilicon layer; the isolation layer comprising an N-type doping region and a P-type doping region, the N-type doping region being located between the P-type doping region and the first polysilicon layer; a source layer, contacting the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, the gate dielectric layer and the isolation layer; A drain layer, formed on the back side of the N-type substrate; The isolation layer is used to transfer the potential of the source layer to the first polysilicon layer when the super junction MOSFET is reversely connected.

2. The super junction MOSFET with fast reverse recovery according to claim 1, characterized in that: The first polysilicon layer, the N-type doping region and the P-type doping region are stacked, and the thickness of the N-type doping region is equal to the thickness of the P-type doping region, and the thickness of the N-type doping region and the thickness of the P-type doping region are less than the thickness of the first polysilicon layer.

3. A super junction MOSFET with fast reverse recovery, characterized in that: include: N-type substrate; A first P column, an N-type drift region, and a second P column are formed on the front surface of the N-type substrate; wherein the N-type drift region is located between the first P column and the second P column; A first P-type base region and a second P-type base region, wherein the first P-type base region is formed on the first P column, and the second P-type base region is formed on the second P column; a first N-type source region and a second N-type source region, wherein the first N-type source region is located in a groove of the first P-type base region, and the second N-type source region is located in a groove of the second P-type base region; A gate dielectric layer and a first polysilicon layer, wherein the gate dielectric layer has a concave structure, the gate dielectric layer is located on the N-type drift region, and is in contact with the first P-type base region, the second P-type base region, the first N-type source region, and a portion of the second N-type source region, and the first polysilicon layer is located at the bottom of the groove of the gate dielectric layer; an isolation layer, the isolation layer being located in the groove of the gate dielectric layer and on the first polysilicon layer; the isolation layer being a Schottky diode, the anode of the Schottky diode being connected to the source layer, and the cathode of the Schottky diode being connected to the first polysilicon layer; a source layer, contacting the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, the gate dielectric layer and the isolation layer; A drain layer, formed on the back side of the N-type substrate; The isolation layer is used to transfer the potential of the source layer to the first polysilicon layer when the super junction MOSFET is reversely connected.

4. The super junction MOSFET with fast reverse recovery according to any one of claims 1 to 3, characterized in that: The thickness of the isolation layer is the same as that of the first polysilicon layer.

5. The super junction MOSFET with fast reverse recovery according to any one of claims 1 to 3, characterized in that: The groove of the gate dielectric layer is a structure that is narrow at the top and wide at the bottom.

6. A method for preparing a super junction MOSFET with fast reverse recovery, characterized in that: The preparation method comprises: Epitaxially forming an N-type drift layer on the front side of the N-type substrate; Processing the N-type drift layer to obtain a first P column, an N-type drift region, and a second P column; wherein the N-type drift region is located between the first P column and the second P column; Performing P-type ion implantation on the first region of the N-type drift region and the first P column to form a first P-type base region, and performing P-type ion implantation on the second region of the N-type drift region and the second P column to form a second P-type base region; wherein the first region and the second region of the N-type drift region are arranged opposite to each other and do not contact each other; The first P-type base region is subjected to an N-type ion implantation process to form a first N-type source region and a first P-type base region with a concave structure, and the second P-type base region is subjected to an N-type ion implantation process to form a second N-type source region and a second P-type base region with a concave structure; wherein the first N-type source region is located in a groove of the first P-type base region, and the second N-type source region is located in a groove of the second P-type base region; Forming a gate dielectric layer with a concave structure on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, and the N-type drift region, and depositing a polysilicon material at the bottom of the groove of the gate dielectric layer to form a first polysilicon layer; An isolation layer is formed on the first polysilicon layer; the isolation layer is located in the groove of the gate dielectric layer; the isolation layer includes an N-type doping region and a P-type doping region, and the N-type doping region is located between the P-type doping region and the first polysilicon layer; A source layer is formed in contact with the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, the gate dielectric layer and the isolation layer, and a drain layer is formed on the back side of the N-type substrate; wherein the isolation layer is used to transfer the potential of the source layer to the first polysilicon layer when the super junction MOSFET is reversely connected.

7. A chip, characterized in that: It comprises a super junction MOSFET with fast reverse recovery as claimed in any one of claims 1 to 5.

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