Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, wherein the semiconductor device comprises: a semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body further comprises a well region and a first region; a gate groove is arranged on the first surface, and the gate groove extends from the first surface to the semiconductor body; a gate structure located in the gate groove and on the first surface; a second insulating layer located on a side of the gate structure away from the semiconductor body, and a side of the second insulating layer away from the semiconductor body protrudes toward a side away from the semiconductor body; a source electrode located on the first surface; and a drain electrode located on the second surface. The source electrode of the present invention can be fully filled, and there will be no gap between the source electrode and the second insulating layer, thereby effectively improving the performance and reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Currently, for trench metal oxide semiconductor field effect transistor (MOSFET) semiconductor devices, after the gate is formed, the gate needs to be etched. After the gate is etched, the side away from the semiconductor body presents a morphology of sharp protrusions on both sides and a concave middle area. This morphology will cause the side of the interlayer dielectric layer away from the semiconductor body to also present a morphology of sharp protrusions on both sides and a concave middle area, thereby resulting in insufficient source metal filling and a gap between the source and the interlayer dielectric layer, affecting the performance and reliability of the semiconductor device. Summary of the invention

[0003] The present invention provides a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle to solve the problem that the side of the interlayer dielectric layer away from the semiconductor body presents sharp protrusions on both sides and a concave middle area, thereby causing insufficient source metal filling.

[0004] In a first aspect, the present invention provides a semiconductor device, wherein the semiconductor device comprises:

[0005] A semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region, a first area and a first insulating layer, the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; a gate trench is arranged on the first surface, the gate trench extends from the first surface to the semiconductor body, and the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the semiconductor body and the first area are arranged to be of a first conductivity type, and the well region is arranged to be of a second conductivity type;

[0006] a gate located on a side of the first insulating layer away from the semiconductor body;

[0007] A second insulating layer is located on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body is raised toward a side away from the semiconductor body;

[0008] a source electrode located on the first surface;

[0009] A drain is located on the second surface.

[0010] Optionally, a surface of the second insulating layer away from the semiconductor body is a convex arc surface.

[0011] Optionally, the gate includes a first gate portion and a second gate portion connected, the first gate portion is located at the bottom of the gate groove; the second gate portion is located on a side of the first gate portion away from the bottom of the gate groove; and a side of the second gate portion away from the first gate portion is a convex arc surface.

[0012] Optionally, the source is located on the first surface of the semiconductor body, the source is electrically connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

[0013] Optionally, a source trench is provided on the first surface, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further comprises a third insulating layer; the third insulating layer is located on the bottom surface and sidewalls of the source trench;

[0014] The source is located on the first surface of the semiconductor body, the source is electrically connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

[0015] Optionally, the semiconductor device further comprises a source trench structure; the source trench structure is located on a side of the third insulating layer away from the semiconductor body;

[0016] The source groove structure includes a first source groove portion and a second source groove portion connected to each other, the first source groove portion is located at the bottom of the source groove, and the second source groove portion is located on the side of the first source groove portion away from the bottom of the source groove; and a side of the second source groove portion away from the first source groove portion is a convex arc surface; the source is located on the side of the source groove structure away from the semiconductor body.

[0017] Optionally, a height of the second gate portion exceeding the gate trench is in a range of 50 nm to 500 nm.

[0018] In a second aspect, the present invention provides a method for preparing a semiconductor device, wherein the method comprises:

[0019] A semiconductor body is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region, a first area and a first insulating layer, the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; a gate trench is arranged on the first surface, the gate trench extends from the first surface to the semiconductor body, and the first insulating layer is located on the bottom surface and sidewall of the gate trench; the semiconductor body and the first area are set to be of a first conductivity type, and the well region is set to be of a second conductivity type;

[0020] forming a gate on a side of the first insulating layer away from the semiconductor body;

[0021] A second insulating layer is formed on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body is raised toward a side away from the semiconductor body;

[0022] forming a source electrode on the first surface;

[0023] A drain electrode is formed on the second surface.

[0024] Optionally, forming a gate on a side of the first insulating layer away from the semiconductor body includes:

[0025] forming a first gate portion at a bottom of the gate trench;

[0026] forming a second gate portion on a side of the first gate portion away from the bottom of the gate trench;

[0027] Etching the second gate portion so that a vertical projection of the second gate portion on the first surface coincides with a vertical projection of the first gate portion on the first surface;

[0028] A wet etching back process is performed on a side of the second gate portion away from the first gate portion.

[0029] Optionally, forming a source electrode on the first surface includes:

[0030] A source electrode is formed on the first surface of the semiconductor body. The source electrode is electrically connected to the first region, and a vertical projection of the source electrode on the first surface covers a vertical projection of the second insulating layer on the first surface.

[0031] Optionally, the semiconductor body further includes a third insulating layer; providing the semiconductor body and forming a source electrode on the first surface includes:

[0032] Forming a source trench on the first surface; the source trench extends from the first surface into the semiconductor body;

[0033] forming a third insulating layer on the bottom surface and sidewalls of the source trench;

[0034] A source electrode is formed on the first surface of the semiconductor body. The source electrode is electrically connected to the first region, and a vertical projection of the source electrode on the first surface covers a vertical projection of the second insulating layer on the first surface.

[0035] Optionally, the semiconductor device further includes a source trench structure, the source trench structure includes a first source trench portion and a second source trench portion; after forming a third insulating layer on the bottom surface and sidewall of the source trench and forming a source on the first surface of the semiconductor body, the step includes:

[0036] forming a first source trench portion at the bottom of the source trench;

[0037] A second source groove portion is formed on a side of the first source groove portion away from the bottom of the source groove; a side of the second source groove portion away from the first source groove portion is a convex arc surface;

[0038] A source is formed on a side of the second source trench portion away from the semiconductor body. The source is electrically connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

[0039] In a third aspect, the present invention provides a power module, which includes a substrate and at least one semiconductor device provided in the first aspect, wherein the substrate is used to carry the semiconductor device.

[0040] In a fourth aspect, the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0041] The power conversion circuit includes a circuit board and at least one semiconductor device as provided in the first aspect above, and the semiconductor device is electrically connected to the circuit board.

[0042] In a fifth aspect, the present invention provides a vehicle, comprising a load and a power conversion circuit as provided in the fourth aspect above, the power conversion circuit being used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0043] In the technical solution of the present invention, the second insulating layer is used as an interlayer dielectric layer. After being formed, the side away from the semiconductor body is raised toward the side away from the semiconductor body, thereby changing the morphology of the second insulating layer. The source electrode can be fully filled, and there will be no gap between the source electrode and the second insulating layer. Thus, the performance and reliability of the semiconductor device are effectively improved.

[0044] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0047] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0048] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0049] Figure 4 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0050] Figure 5-Figure 10 It is a structural diagram corresponding to each step of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0051] Fig.11 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0052] Figure 12-14 It is a structural diagram corresponding to some steps of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0053] Fig.15 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0054] Fig.16 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0055] Figure 17-Figure 18 It is a structural diagram corresponding to some steps of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0056] Fig.19 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0057] Figure 20-21 It is a structural diagram corresponding to some steps of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0058] Fig. 22 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0059] Figure 23-Figure 34 It is a structural diagram corresponding to each step in a flowchart of another method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0062] In order to solve the problem that the side of the interlayer dielectric layer away from the semiconductor body in the MOSFET semiconductor device is etched to present sharp protrusions on both sides and a concave middle area, thereby causing insufficient source metal filling, and improve the reliability of the MOSFET semiconductor device, the embodiment of the present invention provides the following technical solutions:

[0063] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, Figure 3 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, such as Figure 1-Figure 3As shown, the semiconductor device includes: a semiconductor body 1; the semiconductor body 1 includes a first surface 101 and a second surface 102 arranged opposite to each other, the semiconductor body 1 also includes a well region 13, a first region 14 and a first insulating layer 16, the first region 14 is arranged on the first surface 101, and the well region 13 is arranged on a side of the first region 14 away from the first surface 101. The first surface 101 is provided with a gate trench, and the gate trench extends from the first surface 101 into the semiconductor body 1. The first insulating layer 16 is located on the bottom surface and sidewall of the gate trench; the semiconductor body 1 and the first region 14 are set to the first conductivity type, and the well region 13 is set to the second conductivity type. A gate 2 is located on the side of the first insulating layer 16 away from the semiconductor body 1. A second insulating layer 3 is located on the side of the gate 2 away from the semiconductor body 1, and the vertical projection of the second insulating layer 3 on the first surface 101 covers the vertical projection of the gate 2 on the first surface 101. The side of the second insulating layer 3 away from the semiconductor body 1 is raised to the side away from the semiconductor body 1. A source 4 is located on the first surface 101. A drain 5 is located on the second surface 102.

[0064] A semiconductor device according to an embodiment of the present invention comprises Figure 1 The single trench MOSFET semiconductor device shown and Figure 2 and Figure 3 A double trench MOSFET semiconductor device is shown.

[0065] Alternatively, if Figure 1-Figure 3 As shown, the semiconductor body 1 may further include a second region 15, the doping concentration of the second region 15 is greater than the doping concentration of the well region 13, and a good ohmic contact may be formed with the source 4. The MOSFET semiconductor device may further include an ohmic contact region 6, the ohmic contact region 6 is located on the first surface 101 and the side of the second insulating layer 3 away from the semiconductor body 1, and the ohmic contact region 6 may enable the source 4 to form a good ohmic contact with the semiconductor body 1. Exemplarily, the ohmic contact region 6 may be an alloy ohmic contact region of titanium (Ti) and titanium nitride (TiN).

[0066] It should be noted that the MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 13 is a P-type well region, the first region 14 is an N++ doped region, and the second region 15 is a P++ doped region. For a P-channel MOSFET semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 13 is an N-type well region, the first region 14 is a P++ doped region, and the second region 15 is an N++ doped region.

[0067] For example, in Figure 1-Figure 3 In the embodiment, the semiconductor body 1 further includes a substrate 11 and an epitaxial layer 12. For an N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate, and the epitaxial layer 12 includes an N-epitaxial layer. For a P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate, and the epitaxial layer 12 includes a P-epitaxial layer. In some embodiments of the present invention, the semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 12 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 11, and the epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0068] like Figure 1-Figure 3 As shown, the source 4 in the embodiment of the present invention is electrically connected to the first region 14. The first insulating layer 16 can be located on the bottom surface and sidewalls of the gate trench. It can also be located on the bottom surface and sidewalls of the gate trench and extend to the first surface 101, and the vertical projection of the first insulating layer 16 on the first surface 101 can coincide with the vertical projection of the second insulating layer 3 on the first surface 101. The second insulating layer 3 is an interlayer dielectric layer. After formation, the side away from the semiconductor body 1 is raised toward the side away from the semiconductor body 1, thereby changing the morphology of the second insulating layer 3. The source 4 can be fully filled, and there will be no gap between the source 4 and the second insulating layer 3.

[0069] In the technical solution of the embodiment of the present invention, the second insulating layer 3 is used as an interlayer dielectric layer, and after being formed, the side away from the semiconductor body 1 is raised toward the side away from the semiconductor body 1, thereby changing the morphology of the second insulating layer 3. The source electrode 4 can be fully filled, and there will be no gap between the source electrode 4 and the second insulating layer 3. Thus, the performance and reliability of the semiconductor device are effectively improved.

[0070] Optionally, based on the above embodiments, continue to refer to Figure 1-Figure 3 For the single trench MOSFET semiconductor device and the double trench MOSFET semiconductor device, the side of the second insulating layer 3 away from the semiconductor body 1 is a convex arc surface.

[0071] Specifically, the second insulating layer 3 is used as an interlayer dielectric layer, and after being formed, the side away from the semiconductor body 1 is a convex arc surface, thereby changing the morphology of the second insulating layer 3. The source electrode 4 can be fully filled, and there is no gap between the source electrode 4 and the second insulating layer 3. Therefore, the performance and reliability of the semiconductor device are effectively improved.

[0072] Optionally, based on the above embodiments, continue to refer to Figure 1-Figure 3For a single trench MOSFET semiconductor device and a double trench MOSFET semiconductor device, the gate 2 includes a first gate portion 21 and a second gate portion 22 connected to each other, the first gate portion 21 is located at the bottom of the gate trench; the second gate portion 22 is located on a side of the first gate portion 21 away from the bottom of the gate trench; and a side of the second gate portion 22 away from the first gate portion 21 is a convex arc surface.

[0073] Specifically, the gate 2 includes a first gate portion 21 and a second gate portion 22 connected to each other, the second gate portion 22 is located on a side of the first gate portion 21 away from the bottom of the gate trench, and the side of the second gate portion 22 away from the first gate portion 21 is a convex arc surface, ensuring that after the second insulating layer 3 is formed, the side away from the semiconductor body 1 is also a convex arc surface, thereby changing the morphology of the second insulating layer 3. The source 4 can be fully filled, and there will be no gap between the source 4 and the second insulating layer 3. Thereby effectively improving the performance and reliability of the semiconductor device.

[0074] Optionally, based on the above embodiments, continue to refer to Figure 1 For a single trench MOSFET semiconductor device, the source 4 is located on the first surface 101 of the semiconductor body 1 , the source 4 is electrically connected to the first region 14 , and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the second insulating layer 3 on the first surface 101 .

[0075] Specifically, for a single trench MOSFET semiconductor device, the gate 2 is a trench gate structure, that is, the gate 2 is located in the gate trench and can extend beyond the gate trench. The semiconductor body 1 of the single trench MOSFET semiconductor device does not need to be provided with a source trench, and the source 4 is located on the first surface 101 of the semiconductor body 1. The source 4 can be a metal electrode, and the source 4 is electrically connected to the first region 14. The manufacturing process of the single trench MOSFET semiconductor device is simple, which can effectively simplify the manufacturing process of the MOSFET semiconductor device, thereby effectively reducing the time cost.

[0076] Optionally, based on the above embodiments, continue to refer to Figure 2 and Figure 3 For a double trench MOSFET semiconductor device, a source trench 18 is provided on the first surface 101, and the source trench 18 extends from the first surface 101 into the semiconductor body 1. The semiconductor body 1 further includes a third insulating layer 17; the third insulating layer 17 is located on the bottom surface and sidewalls of the source trench 18. The source 4 is located on the first surface 101 of the semiconductor body 1, the source 4 is electrically connected to the first region 14, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the second insulating layer 3 on the first surface 101.

[0077] Specifically, for a double trench MOSFET semiconductor device, the gate 2 is a trench gate structure, that is, the gate 2 is located in the gate trench and can extend beyond the gate trench. The first surface 101 of the semiconductor body 1 needs to be provided with a source trench 18, and the bottom and sidewalls of the source trench 18 are provided with a third insulating layer 17. Figure 3 As shown, the source trench 18 may not be filled with the source trench structure 7. Figure 2 As shown, the source trench 18 may be filled with a source trench structure 7, and the source trench structure 7 may be metal or polysilicon, etc. The provision of the source trench 18 may effectively alleviate the high electric field distribution at the first insulating layer 16. The source trench 18 may be located inside the second region 15.

[0078] Optionally, based on the above embodiments, continue to refer to Figure 2 For a double trench MOSFET semiconductor device, the semiconductor device further includes a source trench structure 7. The source trench structure 7 is located on the side of the third insulating layer 17 away from the semiconductor body 1. The source trench structure 7 includes a first source trench portion 71 and a second source trench portion 72 connected, the first source trench portion 71 is located at the bottom of the source trench, and the second source trench portion 72 is located on the side of the first source trench portion 71 away from the bottom of the source trench. And the side of the second source trench portion 72 away from the first source trench portion 71 is a convex arc surface. The source 4 is located on the side of the source trench structure 7 away from the semiconductor body 1.

[0079] Specifically, for a double trench MOSFET semiconductor device, the source trench may be filled with a source trench structure 7. The source trench structure 7 may include a first source trench portion 71 and a second source trench portion 72, wherein the first source trench portion 71 is located at the bottom of the source trench, and the second source trench portion 72 is located at a side of the first source trench portion 71 away from the bottom of the source trench.

[0080] For the currently existing double-trench MOSFET semiconductor devices, after the source trench structure 7 is formed, the source trench structure 7 needs to be etched. After the source trench structure 7 is etched, the side away from the semiconductor body 1 presents a morphology of sharp protrusions on both sides and a concave middle area, which leads to insufficient filling of the source 4. There is a gap between the source 4 and the source trench structure 7, which affects the performance and reliability of the semiconductor device.

[0081] According to the technical solution of the embodiment of the present invention, for a double-trench MOSFET semiconductor device, the source trench structure 7 includes a first source trench portion 71 and a second source trench portion 72 connected to each other, and a side of the second source trench portion 72 away from the first source trench portion 71 is a convex arc surface. The source 4 can be fully filled, and there will be no gap between the source 4 and the source trench structure 7. This effectively improves the performance and reliability of the semiconductor device.

[0082] Optionally, based on the above embodiments, continue to refer to Figure 1-Figure 3 , the semiconductor body 1 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0083] Specifically, a MOSFET semiconductor device composed of a silicon carbide semiconductor body or a gallium nitride semiconductor body has the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of the semiconductor device.

[0084] Optionally, based on the above embodiments, continue to refer to Figure 1-Figure 3 , the height of the second gate portion 22 beyond the gate trench is in the range of 50nm-500nm.

[0085] Specifically, the side of the second gate portion 22 away from the semiconductor body 1 is an arc surface, and the vertical distance between the highest point of the side of the second gate portion 22 away from the semiconductor body 1 and the first surface 101 can be set to be in the range of 50nm-500nm. If the height of the second gate portion 22 is set too high, there may be a risk of short circuit between the gate 2 and the source 4. If the height of the second gate portion 22 is set too low, it may cause a decrease in the threshold voltage of the MOSFET semiconductor device, thereby affecting the switching speed and current control capability of the MOSFET semiconductor device. To a certain extent, the overall performance of the MOSFET semiconductor device will be reduced.

[0086] Figure 4 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, such as Figure 4 As shown, the method includes:

[0087] S100: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a well region, a first region and a first insulating layer, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; a gate trench is arranged on the first surface, and the gate trench extends from the first surface to the semiconductor body; the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the semiconductor body and the first region are set to the first conductivity type, and the well region is set to the second conductivity type.

[0088] Specifically, Figure 5As shown, a semiconductor body 1 is first provided, and the semiconductor body 1 may include a substrate 11 and an epitaxial layer 12. In some embodiments of the present invention, the semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. A semiconductor layer is formed on one side of the substrate 11 by a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE) to form the epitaxial layer 12.

[0089] The semiconductor body 1 may further include a well region 13, a first region 14, and a second region 15. The well region 13, the first region 14, and the second region 15 are formed on the side of the epitaxial layer 12 away from the substrate 11 by processes such as doping, and then the doped impurities are activated by an annealing process. A gate trench 19 is formed on the first surface 101 by processes such as photolithography and etching, and the gate trench 19 may penetrate the well region 13 and the first region 14 and extend into the epitaxial layer 12. The first insulating layer 16 may be located on the bottom surface and side walls of the gate trench 19. It may also be located on the bottom surface and side walls of the gate trench 19 and extend to the first surface 101.

[0090] The MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate, the epitaxial layer 12 includes an N-epitaxial layer, the well region 13 is a P-type well region, the first region 14 is an N++ doped region, and the second region 15 is a P++ doped region. For a P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate, the epitaxial layer 12 includes a P-epitaxial layer, the well region 13 is an N-type well region, the first region 14 is a P++ doped region, and the second region 15 is an N++ doped region.

[0091] S110: forming a gate on a side of the first insulating layer away from the semiconductor body.

[0092] Specifically, Figure 6 As shown, a first gate portion 21 is formed at the bottom of the gate trench, and a side of the first gate portion 21 away from the bottom of the gate trench can be flush with the first surface 101. Exemplarily, the first gate portion 21 can be a polysilicon gate portion. A second gate portion 22 is formed on a side of the first gate portion 21 away from the bottom of the gate trench, and the second gate portion 22 can be located on the first surface 101, and the vertical projection of the second gate portion 22 on the first surface 101 can coincide with the vertical projection of the first gate portion 21 on the first surface 101. Exemplarily, the second gate portion 22 can also be a polysilicon gate portion.

[0093] S120: forming a second insulating layer on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body protrudes toward a side away from the semiconductor body.

[0094] Specifically, Figure 7 As shown, a second insulating layer 3 is formed on the side of the gate 2 away from the semiconductor body 1. Exemplarily, the second insulating layer 3 may be a silicon oxide insulating layer. The second insulating layer 3 serves as an interlayer dielectric layer. After formation, the side away from the semiconductor body 1 is convex toward the side away from the semiconductor body 1, thereby changing the morphology of the second insulating layer 3. Optionally, the second insulating layer 3 serves as an interlayer dielectric layer. After formation, the side away from the semiconductor body 1 is a convex arc surface.

[0095] S130: forming a source electrode on the first surface.

[0096] Specifically, Figure 8 As shown, for a single trench MOSFET semiconductor device, exemplary, metal is deposited on the first surface 101 to form a source 4. The source 4 is electrically connected to the first region 14, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the second insulating layer 3 on the first surface 101.

[0097] like Fig. 9 and Fig.10 As shown, for a double trench MOSFET semiconductor device, the gate 2 is a trench gate structure, that is, the gate 2 is located in the gate trench and can extend beyond the gate trench. A source trench 18 needs to be provided on the first surface 101 of the semiconductor body 1, and a third insulating layer 17 is provided on the bottom and sidewalls of the source trench 18. Fig.10 As shown, the source trench 18 may not be filled with the source trench structure 7. The source 4 is located on the first surface 101 of the semiconductor body 1, and the source 4 is electrically connected to the first region 14. Fig. 9 As shown, the source trench 18 may be filled with a source trench structure 7, the source 4 is located on a side of the source trench structure 7 away from the semiconductor body 1, and the source 4 is electrically connected to the first region 14. Exemplarily, the source trench structure 7 may be made of metal or polysilicon.

[0098] S140: forming a drain electrode on the second surface.

[0099] Specifically, Figure 1-Figure 3 As shown, for the single trench MOSFET semiconductor device and the double trench MOSFET semiconductor device, the drain 5 is formed on the second surface 102 . Exemplarily, the drain 5 is formed by depositing metal on the second surface 102 .

[0100] In the technical solution of the embodiment of the present invention, the second insulating layer 3 is used as an interlayer dielectric layer, and after being formed, the side away from the semiconductor body 1 is raised toward the side away from the semiconductor body 1, thereby changing the morphology of the second insulating layer 3. The source electrode 4 can be fully filled, and there will be no gap between the source electrode 4 and the second insulating layer 3. Thus, the performance and reliability of the semiconductor device are effectively improved.

[0101] Optionally, based on the above embodiments, Fig.11 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.11 As shown, the method includes:

[0102] S200: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a well region, a first region and a first insulating layer, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; a gate trench is arranged on the first surface, and the gate trench extends from the first surface to the semiconductor body; the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the semiconductor body and the first region are set to the first conductivity type, and the well region is set to the second conductivity type.

[0103] S210 : forming a first gate portion at the bottom of the gate trench.

[0104] Specifically, Fig.12 As shown, a first gate portion 21 is formed at the bottom of the gate trench, and a surface of the first gate portion 21 away from the bottom of the gate trench may be flush with the first surface 101. Exemplarily, the first gate portion 21 may be a polysilicon gate portion.

[0105] S220 : forming a second gate portion on a side of the first gate portion away from the bottom of the gate trench.

[0106] Specifically, Fig.13 As shown, the second gate portion 22 may be formed on a side of the first gate portion 21 away from the bottom of the gate trench and on the entire surface of the first surface 101 .

[0107] S230: performing an etching process on the second gate portion so that a vertical projection of the second gate portion on the first surface coincides with a vertical projection of the first gate portion on the first surface.

[0108] Specifically, Fig.14 As shown, the second gate portion 22 is wet-etched so that the vertical projection of the second gate portion 22 on the first surface 101 after etching coincides with the vertical projection of the first gate portion 21 on the first surface 101 .

[0109] S240: performing a wet etching back process on a side of the second gate portion away from the first gate portion.

[0110] In the embodiment of the present invention, the wet etch back can accurately control the etching rate and the shape of the formed microstructure.

[0111] Specifically, Figure 6 As shown, a wet etching back treatment is performed on the side of the second gate portion 22 away from the first gate portion 21, and the wet etching back can make the side of the second gate portion 22 away from the first gate portion 21 a convex arc surface. The technical solution of the embodiment of the present invention, after the second gate portion 22 is etched, a wet etching back treatment is added to the side of the second gate portion 22 away from the first gate portion 21, and the microstructure shape of the side of the second gate portion 22 away from the first gate portion 21 can be controlled by the wet etching back treatment. The side of the second gate portion 22 away from the first gate portion 21 is controlled to be a convex arc surface. The second insulating layer 3 serves as an interlayer dielectric layer, and after formation, the side thereof away from the semiconductor body 1 is also a convex arc surface, thereby changing the morphology of the second insulating layer 3. The source 4 can be fully filled, and there will be no gap between the source 4 and the second insulating layer 3. Thereby effectively improving the performance and reliability of the semiconductor device.

[0112] S250: forming a second insulating layer on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body protrudes toward a side away from the semiconductor body.

[0113] S260: forming a source electrode on the first surface.

[0114] S270: forming a drain on the second surface.

[0115] Optionally, based on the above embodiments, for a single trench MOSFET semiconductor device, Fig.15 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.15 As shown, the method includes:

[0116] S300: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a well region, a first region and a first insulating layer, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; a gate trench is arranged on the first surface, and the gate trench extends from the first surface to the semiconductor body; the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the semiconductor body and the first region are set to the first conductivity type, and the well region is set to the second conductivity type.

[0117] S310: forming a gate on a side of the first insulating layer away from the semiconductor body.

[0118] S320: forming a second insulating layer on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body protrudes toward a side away from the semiconductor body.

[0119] S330: forming a source electrode on the first surface of the semiconductor body, wherein the source electrode is electrically connected to the first region, and a vertical projection of the source electrode on the first surface covers a vertical projection of the second insulating layer on the first surface.

[0120] Specifically, Figure 8 As shown, for a single trench MOSFET semiconductor device, illustratively, metal is deposited on the first surface 101 to form a source 4. The source 4 is electrically connected to the first region 14, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the second insulating layer 3 on the first surface 101. The manufacturing process of the single trench MOSFET semiconductor device is simple, which can effectively simplify the manufacturing process of the MOSFET semiconductor device, thereby effectively reducing the time cost.

[0121] S340: forming a drain on the second surface.

[0122] Optionally, based on the above embodiments, for the double trench MOSFET semiconductor device, the semiconductor body further includes a third insulating layer. Fig.16 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.16 As shown, the method includes:

[0123] S400: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a well region, a first region and a first insulating layer, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; a gate trench is arranged on the first surface, and the gate trench extends from the first surface to the semiconductor body; the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the semiconductor body and the first region are set to the first conductivity type, and the well region is set to the second conductivity type.

[0124] S410: forming a gate on a side of the first insulating layer away from the semiconductor body.

[0125] S420: forming a second insulating layer on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body protrudes toward a side away from the semiconductor body.

[0126] S430: forming a source trench on the first surface; the source trench extends from the first surface into the semiconductor body.

[0127] Specifically, Fig.17 As shown, a source trench 18 is formed on the first surface 101 by photolithography and etching processes, and the source trench 18 passes through the second region 15 .

[0128] S440: forming a third insulating layer on the bottom surface and sidewalls of the source trench.

[0129] Specifically, Fig.18 As shown, a third insulating layer 17 is formed on the bottom and sidewalls of the source trench 18. Exemplarily, the third insulating layer 17 may be a silicon oxide insulating layer.

[0130] S450: forming a source electrode on the first surface of the semiconductor body, wherein the source electrode is electrically connected to the first region, and a vertical projection of the source electrode on the first surface covers a vertical projection of the second insulating layer on the first surface.

[0131] Specifically, Fig.10 As shown, a source 4 is formed on the first surface 101 of the semiconductor body 1. Exemplarily, a metal is deposited on the first surface 101 of the semiconductor body 1 to form the source 4. The source 4 is electrically connected to the first region 14, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the second insulating layer 3 on the first surface 101. At the same time, the provision of the source trench 18 can effectively alleviate the high electric field distribution at the first insulating layer 16.

[0132] S460: forming a drain on the second surface.

[0133] Optionally, on the basis of the above embodiments, for the double trench MOSFET semiconductor device, the semiconductor device further includes a source trench structure, and the source trench structure includes a first source trench portion and a second source trench portion. Fig.19 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.19 As shown, the method includes:

[0134] S500: Provide a semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a well region, a first region and a first insulating layer, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; a gate trench is arranged on the first surface, and the gate trench extends from the first surface to the semiconductor body; the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the semiconductor body and the first region are set to the first conductivity type, and the well region is set to the second conductivity type.

[0135] S510: forming a gate on a side of the first insulating layer away from the semiconductor body.

[0136] S520: forming a second insulating layer on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body protrudes toward a side away from the semiconductor body.

[0137] S530: forming a source trench on the first surface; the source trench extends from the first surface into the semiconductor body.

[0138] S540: forming a third insulating layer on the bottom surface and sidewalls of the source trench.

[0139] S550: forming a first source trench portion at the bottom of the source trench.

[0140] Specifically, Fig. 20 As shown, a first source trench portion 71 is formed at the bottom of the source trench, and a surface of the first source trench portion 71 away from the bottom of the source trench may be flush with the first surface 101. Exemplarily, the first source trench portion 71 may be a polysilicon source trench portion.

[0141] S560: forming a second source trench portion on a side of the first source trench portion away from the bottom of the source trench; a side of the second source trench portion away from the first source trench portion is a convex arc surface.

[0142] Specifically, Fig.21 As shown, a second source groove portion 72 is formed on the side of the first source groove portion 71 away from the bottom of the source groove. The second source groove portion 72 can be first deposited on the entire first surface 101, and then the side of the second source groove portion 72 away from the first source groove portion 71 is a convex arc surface through wet etching and wet etching back. The side of the second source groove portion 72 away from the first source groove portion 71 is a convex arc surface, the source 4 can be fully filled, and there will be no gap between the source 4 and the second source groove portion 72. Thereby effectively improving the performance and reliability of the semiconductor device.

[0143] S570: forming a source electrode on a side of the second source trench portion away from the semiconductor body, the source electrode being electrically connected to the first region, and a vertical projection of the source electrode on the first surface covering a vertical projection of the second insulating layer on the first surface.

[0144] Specifically, Fig. 9 As shown, a source 4 is formed on a side of the second source trench 72 away from the semiconductor body 1 , the source 4 is electrically connected to the first region 14 , and a vertical projection of the source 4 on the first surface 101 covers a vertical projection of the second insulating layer 3 on the first surface 101 .

[0145] S580: forming a drain on the second surface.

[0146] Optionally, based on the above embodiments, Fig. 22 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig. 22 As shown, the method includes:

[0147] S600: Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a well region, a first region and a first insulating layer, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; a gate trench is arranged on the first surface, and the gate trench extends from the first surface to the semiconductor body; the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the semiconductor body and the first region are set to the first conductivity type, and the well region is set to the second conductivity type.

[0148] Specifically, a MOSFET semiconductor device composed of a silicon carbide semiconductor body or a gallium nitride semiconductor body has the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of the semiconductor device.

[0149] S610: forming a gate on a side of the first insulating layer away from the semiconductor body.

[0150] S620: forming a second insulating layer on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body protrudes toward a side away from the semiconductor body.

[0151] S630: forming a source electrode on the first surface.

[0152] S640: forming a drain on the second surface.

[0153] Optionally, Figure 23-Figure 34 is a structural diagram corresponding to each step in a flowchart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.23 As shown, an epitaxial layer 12 is first formed on one side of the substrate 11 by an epitaxial process. Fig.24 As shown, a well region 13 and a first region 14 are formed on the side of the epitaxial layer 12 away from the substrate 11 by doping and other processes. Fig.25 As shown, a source trench 18 and a gate trench 19 are formed on the first surface. Fig.26 As shown, the second region 15 is formed by doping in the well region 13 and the epitaxial layer 12 around the source trench 18. Fig. 27As shown, an insulating layer 8 is formed on the bottom surface and side wall of the gate trench 19 and the source trench 18, and an insulating layer 8 is also formed on the first surface. The insulating layer 8 on the bottom surface and side wall of the source trench 18 is equivalent to the third insulating layer provided in any of the above embodiments, and the insulating layer 8 on the bottom surface and side wall of the gate trench 19 is equivalent to the first insulating layer provided in any of the above embodiments. Fig.28 As shown in FIG. 1 , a conductive layer 9 is formed on the side of the insulating layer 8 away from the substrate 11. Fig.29 As shown, the conductive layer 9 is etched, and the conductive layer 9 in the gate groove is equivalent to the first gate portion provided in any of the above embodiments, and the conductive layer 9 outside the gate groove and located in the gate groove on the side away from the substrate 11 is equivalent to the second gate portion provided in any of the above embodiments. The conductive layer 9 in the source groove is equivalent to the first source groove portion provided in any of the above embodiments, and the conductive layer 9 outside the source groove and located in the source groove on the side away from the substrate 11 is equivalent to the second source groove portion provided in any of the above embodiments. Fig.30 As shown, the conductive layer 9 is wet-etched back so that the side of the conductive layer 9 away from the substrate 11 is a convex arc surface. Fig.31 As shown, a second insulating layer 3 is formed on the side of the conductive layer 9 away from the substrate 11 and the first surface. Fig.32 As shown, the second insulating layer 3 and part of the insulating layer 8 are etched. Fig.33 As shown, an ohmic contact 6 and a source 4 are formed. Fig.34 As shown, a drain electrode 5 is formed.

[0154] An embodiment of the present invention provides a power module, wherein the power module includes a substrate and at least one semiconductor device provided by any of the above embodiments of the present invention, and the substrate is used to carry at least one semiconductor device provided by any of the above embodiments of the present invention.

[0155] The power module provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0156] An embodiment of the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.

[0157] The power conversion circuit includes a circuit board and at least one semiconductor device provided by any one of the above embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0158] The power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0159] An embodiment of the present invention provides a vehicle, wherein the vehicle includes a load and a power conversion circuit provided by any one of the above embodiments of the present invention, and the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it into the load.

[0160] The vehicle provided in any of the above embodiments of the present invention includes the power conversion circuit provided in any of the above embodiments of the present invention, and the power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, so the vehicle provided in any of the above embodiments of the present invention has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0161] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0162] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region, a first area and a first insulating layer, the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; a gate trench is arranged on the first surface, the gate trench extends from the first surface to the semiconductor body, and the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the semiconductor body and the first area are set to a first conductivity type, and the well region is set to a second conductivity type; A gate located on a side of the first insulating layer away from the semiconductor body; a second insulating layer located on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body protrudes toward a side away from the semiconductor body; a source electrode located on the first surface; a drain electrode located on the second surface; The gate includes a first gate portion and a second gate portion connected to each other, the first gate portion is located at the bottom of the gate groove; the second gate portion is located on a side of the first gate portion away from the bottom of the gate groove; and a side of the second gate portion away from the first gate portion is a convex arc surface.

2. The semiconductor device according to claim 1, wherein: A surface of the second insulating layer away from the semiconductor body is a convex arc surface.

3. The semiconductor device according to claim 1, wherein: The source is located on the first surface of the semiconductor body, the source is electrically connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

4. The semiconductor device according to claim 1, wherein: The first surface is provided with a source trench, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further comprises a third insulating layer; the third insulating layer is located on the bottom surface and sidewalls of the source trench; The source is located on the first surface of the semiconductor body, the source is electrically connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

5. The semiconductor device according to claim 4, characterized in that It also includes a source trench structure; the source trench structure is located on a side of the third insulating layer away from the semiconductor body; The source groove structure includes a first source groove portion and a second source groove portion connected, the first source groove portion is located at the bottom of the source groove, and the second source groove portion is located on the side of the first source groove portion away from the bottom of the source groove; and the side of the second source groove portion away from the first source groove portion is a convex arc surface; the source is located on the side of the source groove structure away from the semiconductor body.

6. The semiconductor device according to claim 1, wherein: The height of the second gate portion beyond the gate trench is in the range of 50nm-500nm.

7. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region, a first area and a first insulating layer, the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; a gate trench is arranged on the first surface, the gate trench extends from the first surface to the semiconductor body, and the first insulating layer is located on the bottom surface and sidewall of the gate trench; the semiconductor body and the first area are set to a first conductivity type, and the well region is set to a second conductivity type; A gate is formed on a side of the first insulating layer away from the semiconductor body, A second insulating layer is formed on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; and a side of the second insulating layer away from the semiconductor body is raised toward a side away from the semiconductor body; forming a source electrode on the first surface; forming a drain electrode on the second surface; Forming a gate on a side of the first insulating layer away from the semiconductor body includes: forming a first gate portion at a bottom of the gate trench; forming a second gate portion on a side of the first gate portion away from a bottom of the gate trench; performing etching processing on the second gate portion so that a vertical projection of the second gate portion on the first surface coincides with a vertical projection of the first gate portion on the first surface; A wet etching back process is performed on a side of the second gate portion away from the first gate portion.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: Forming a source electrode on the first surface includes: A source is formed on the first surface of the semiconductor body. The source is electrically connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

9. The method for preparing a semiconductor device according to claim 7, characterized in that: The semiconductor body further includes a third insulating layer; providing the semiconductor body and forming a source electrode on the first surface includes: Forming a source trench on the first surface; the source trench extending from the first surface into the semiconductor body; forming the third insulating layer on the bottom surface and sidewalls of the source trench; The source is formed on the first surface of the semiconductor body, the source is electrically connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The semiconductor device further comprises a source trench structure, wherein the source trench structure comprises a first source trench portion and a second source trench portion; After forming the third insulating layer on the bottom surface and the sidewall of the source trench and forming the source on the first surface of the semiconductor body, the step of: forming the first source trench portion at the bottom of the source trench; The second source groove portion is formed on a side of the first source groove portion away from the bottom of the source groove; a side of the second source groove portion away from the first source groove portion is a convex arc surface; A source is formed on a side of the second source trench away from the semiconductor body, the source is electrically connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

11. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 6, wherein the substrate is used for carrying the semiconductor device.

12. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is electrically connected to the circuit board.

13. A vehicle, characterized in that: It comprises a load and a power conversion circuit as claimed in claim 12, wherein the power conversion circuit is used to convert alternating current and / or direct current into alternating current and / or direct current and then input the converted alternating current and / or direct current into the load.

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