Semiconductor device terminal structure and preparation method thereof, and semiconductor device

Abstract

The invention provides a semiconductor device terminal structure, a preparation method thereof and a semiconductor device, and belongs to the technical field of semiconductor devices. According to the semiconductor device terminal structure, a sunken structure is etched in the middle of a drift layer, first doped regions are arranged on the side wall and the corner, close to a main junction region, of the sunken structure, and second doped regions are arranged on the side wall and the corner, close to a cutting channel region, of the sunken structure. And a third doped region is arranged on the drift layer of the main junction region. A terminal structure is arranged at the bottom of the sunken structure. And a buried layer which is higher than the terminal structure is arranged in the drift layer. And a field plate is arranged in the sunken structure. The first doped region and the second doped region are both directly connected with the terminal structure, so that the first doped region is directly connected with the third doped region, and the effects of the field plate and the buried layer are matched; therefore, the terminal structure of the semiconductor device has the effects of preventing the main junction from being broken down in advance, preventing the cutting channel region from being broken down in advance, blocking cathode potential and blocking leakage current.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor device terminal structure and a preparation method thereof, and a semiconductor device comprising the semiconductor device terminal structure. Background Art

[0002] When semiconductor devices are in the blocking state, they mainly bear voltage through the depletion region formed by the pn junction (main junction) in the main junction area under reverse bias. According to Poisson's equation, the peak value of the electric field strength in the depletion region is located near the pn junction; when the peak value of the electric field strength reaches the critical breakdown electric field strength of the semiconductor material, the device will be broken down. In the actual preparation process, since cylindrical junctions and spherical junctions are formed at the edges and corners of the pn junction, the electric field near the cylindrical junction and spherical junction is more concentrated under the curvature effect, and the electric field strength is much greater than the electric field strength of the parallel plane junction in the middle area. The edges and corners will break down before the parallel plane junction, resulting in the breakdown voltage of the device being much lower than the ideal situation.

[0003] In order to alleviate the problem of premature breakdown due to reduced device blocking ability caused by curvature effect at the edge and corners of the pn junction, the industry often adds a terminal structure around the pn junction. The introduced terminal structure can disperse the electric field originally gathered at the edge of the main junction, reduce the electric field strength at the edge of the main junction, and make the device breakdown voltage closer to the ideal value of the parallel plane junction.

[0004] The current junction termination technology is relatively mature for silicon materials. However, for the third-generation wide bandgap semiconductor materials, such as silicon carbide materials, firstly, due to the extremely low diffusion coefficient of impurities in silicon carbide materials, the doping of silicon carbide materials is often performed through high-temperature ion implantation to form a shallow pn junction, resulting in a smaller radius of curvature of the pn junction of the silicon carbide power device, making it easier for the electric field to concentrate, and further reducing the blocking ability of the device and the protection ability of the junction terminal. Second, in a high-voltage, high-temperature, and high-humidity environment, charge accumulation, moisture corrosion, ion migration, and other phenomena will occur at the terminal, and the electrode on the front of the device and the cutting path may be short-circuited. At this time, the cutting path and the back electrode, and the main junction and the back electrode need to withstand the blocking voltage of the device. The traditional terminal structure only protects the main junction and ignores the protection of the cutting path area, resulting in an increase in the leakage current in the cutting path area or premature breakdown in the cutting path area, and the breakdown voltage of the device is lower than the ideal value. Third, on the outside of the junction terminal and at the edge of the device (i.e., the cutting path area of ​​the device), when the device is in the blocking state, the potential of the cutting path area is equal to the bus voltage, while the electrode potential in the middle of the front side of the device is 0V, which means that there is a huge potential difference between the electrode and the cutting path. Air breakdown may occur between the front electrode and the cutting path, causing the device to burn out. Summary of the invention

[0005] Based on the above technical problems, the present invention provides a semiconductor device terminal structure, which has the functions of increasing the device breakdown voltage, preventing the main junction from being broken down prematurely, preventing the cutting path area from being broken down prematurely, blocking the cathode potential and blocking the leakage current.

[0006] Specifically, in order to achieve the above purpose, the present invention adopts the following technical solutions: A semiconductor device terminal structure, comprising a substrate and a drift layer located on the substrate; the middle part of the drift layer is recessed toward the substrate to form a recessed structure; the recessed structure has a first side wall and a second side wall; a first doped region is arranged on the first side wall and at a corner where the first side wall is connected to the bottom of the recessed structure; a second doped region is arranged on the second side wall and at a corner where the second side wall is connected to the bottom of the recessed structure; a buried layer is arranged in the drift layer around the recessed structure; the first doped region and the second doped region are both in direct contact with the buried layer; in the direction from the substrate to the drift layer, the height of the buried layer is higher than the height of the bottom of the recessed structure; an insulating dielectric layer is filled inside the recessed structure; Field plates are arranged on the inner sides of one side wall and the second side wall; the field plates are isolated from the first doping region and the second doping region by the insulating dielectric layer; a terminal structure is arranged at the bottom of the recessed structure; the first doping region and the second doping region are in direct contact with the terminal structure; a third doping region is arranged on the upper layer of the drift layer in the main junction area of ​​the semiconductor device, and the height of the third doping region is higher than the height of the buried layer along the direction from the substrate to the drift layer; the first doping region is in direct contact with the third doping region; the doping types of the substrate and the drift layer are both the first doping type; the doping types of the first doping region, the second doping region, the third doping region, the buried layer and the terminal structure are all the second doping type.

[0007] In a preferred embodiment, the recessed structure is a groove whose bottom surface is parallel to the substrate.

[0008] In a preferred solution, the terminal structure is a field limiting ring, a junction terminal extension structure, a field plate, or a combination of several of them.

[0009] In a preferred embodiment, the substrate is at least one of a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, a gallium oxide substrate, a diamond substrate, and an aluminum nitride substrate; or / and the material of the field plate is a metal material or a semiconductor material.

[0010] The present invention also provides a method for preparing the semiconductor device terminal structure described in any one of the above schemes, comprising the following steps: S1. growing a drift layer on a substrate; forming a buried layer in the drift layer; S2, forming a concave structure in the middle of the drift layer; S3, forming a first doping region on a first side wall of the recessed structure close to the main junction region, and forming a second doping region on a second side wall close to the cutting track region; forming a terminal structure at the bottom of the recessed structure; and forming a third doping region in an upper layer of the drift layer of the main junction region; S4, depositing an insulating medium on the structure obtained in step S3, etching away the insulating medium inside the recessed structure, and retaining the insulating medium on the sidewall and bottom of the recessed structure; S5, forming a field plate in the recessed structure; S6. Depositing an insulating dielectric on the structure obtained in step S5 to fill the recessed structure, and etching to form an insulating dielectric layer.

[0011] In a preferred solution, step S1 includes the following steps: growing a first drift layer on the substrate, forming the buried layer on the upper surface of the first drift layer, and forming a second drift layer on the upper surface of the buried layer; the second drift layer and the first drift layer have the same doping type.

[0012] The present invention also provides a semiconductor device comprising the semiconductor device terminal structure.

[0013] In a preferred embodiment, a fourth doping region is provided on the upper layer of the drift layer located in the cutting path area of ​​the semiconductor device; along the direction from the substrate to the drift layer, the height of the fourth doping region is higher than the height of the buried layer; the doping type of the fourth doping region is the same as the doping type of the first doping region.

[0014] In a preferred solution, the drift layer includes a first drift layer and a second drift layer, the first drift layer is located between the substrate and the buried layer, the second drift layer is located above the buried layer, and the second drift layer and the first drift layer have the same doping type.

[0015] In a preferred embodiment, an anode is deposited on the upper surface of the drift layer located in the main junction region of the semiconductor device, the insulating dielectric layer extends from the inside of the recessed structure to the upper surface of the drift layer, and the field plate extends from the inner side of the first side wall to the upper surface of the insulating dielectric layer located in the main junction region until it contacts the anode.

[0016] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) In the semiconductor device terminal structure provided in the present invention, a recessed structure deeper than the buried layer (deeper than the third doped region located in the main junction region) is etched in the middle of the drift layer, and a first doped region is arranged at the sidewall and corner of the recessed structure close to the main junction region, and a terminal structure directly connected to the first doped region is arranged at the bottom of the recessed structure, thereby preventing the main junction from being broken down prematurely.

[0017] (2) By setting a grounded or floating field plate inside the recessed structure, the electric field distribution inside the device is modulated to alleviate the electric field concentration near the main junction and the corner of the first doped region, further alleviating the problem of reduced device breakdown voltage.

[0018] (3) By setting a second doped region on the sidewalls and corners of the recessed structure close to the cutting path area, setting a terminal structure directly connected to the second doped region at the bottom of the recessed structure, and cooperating with a grounded or floating field plate set inside the recessed structure, the problem of premature breakdown of the cutting path area caused by a short circuit between the cutting path surface and the anode metal can be solved.

[0019] (4) The buried layer set in the main junction area and the cutting track area can isolate the cathode potential and block the leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure prepared in step S1 of Example 3 of the present invention; Figure 2 A schematic diagram of the structure prepared in step S2 of Example 3 of the present invention; Figure 3 A schematic diagram of the structure prepared in step S3 of Example 3 of the present invention; Figure 4 A schematic diagram of the structure prepared in step S4 of Example 3 of the present invention; Figure 5 A schematic diagram of the structure prepared in step S5 of Example 3 of the present invention; Figure 6 A schematic diagram of a semiconductor device terminal structure prepared in step S6 of embodiment 3 of the present invention; Figure 7 A schematic diagram of the structure of a semiconductor device provided by the present invention; Figure 8 A schematic structural diagram of another semiconductor device provided by the present invention; Fig. 9 A schematic structural diagram of another semiconductor device provided by the present invention; Fig.10 A schematic structural diagram of another semiconductor device provided by the present invention; Fig.11 A schematic structural diagram of another semiconductor device provided by the present invention; Fig.12 A schematic structural diagram of another semiconductor device provided by the present invention; Fig.13 A schematic structural diagram of another semiconductor device provided by the present invention; Fig.14A schematic structural diagram of another semiconductor device provided by the present invention; Fig.15 A schematic structural diagram of another semiconductor device provided by the present invention.

[0021] In the figure: 1, substrate; 2, drift layer; 21, first drift layer; 22, second drift layer; 31, first doping region; 32, second doping region; 33, third doping region; 34, fourth doping region; 4, buried layer; 5, insulating dielectric layer; 6, field plate; 7, terminal structure; 8, cathode; 9, anode; A, main junction region; B, terminal region; C, cutting track region. DETAILED DESCRIPTION

[0022] The following content is combined with the embodiments to clearly and completely describe the technical solution of the present application so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made to the following implementation modes by those of ordinary skill in the art without creative work belongs to the protection scope of the present application.

[0023] Directional terms described in this application, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", etc., indicate directions or positional relationships based on directions or positional relationships in the drawings of the specification, or directions or positional relationships in which the products of this application are usually placed when in use, and are only for the convenience of describing and understanding the product structure of this application. Therefore, directional terms cannot be understood as limiting this application. In this application, unless otherwise clearly defined, expressions such as "upper", "above", "above", and "upper surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is higher in level than the second feature. Expressions such as "lower", "below", "below", and "lower surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is lower in level than the second feature. Ordinal numbers used in this application, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0024] Example 1 Reference Figures 5 and 6A semiconductor device terminal structure includes a substrate 1 and a drift layer 2 located on the substrate 1. The middle part of the drift layer 2 is recessed toward the substrate 1 to form a recessed structure. The recessed structure has a first side wall and a second side wall. A first doping region 31 is arranged on the first side wall and at the corner where the first side wall is connected to the bottom of the recessed structure. A second doping region 32 is arranged on the second side wall and at the corner where the second side wall is connected to the bottom of the recessed structure. A buried layer 4 is arranged in the drift layer 2 around the recessed structure. The first doping region 31 is in direct contact with the buried layer 4 located in the main junction area of ​​the semiconductor device. The second doping region 32 is in direct contact with the buried layer 4 located in the cutting path area of ​​the semiconductor device. When the current flows from the substrate 1 to the drift layer 2, the height of the buried layer 4 is higher than the height of the bottom of the recessed structure. The recessed structure is filled with an insulating dielectric layer 5. Field plates 6 are arranged on the inner sides of the first side wall and the second side wall. The field plate 6 and the first doping region 31, and the field plate 6 and the second doping region 32 are isolated by the insulating dielectric layer 5. A terminal structure 7 is provided at the bottom of the recessed structure. The first doping region 31 and the second doping region 32 are in direct contact with the terminal structure 7. A third doping region 33 is provided on the upper layer of the drift layer 2 located in the main junction region of the semiconductor device. In the direction from the substrate 1 to the drift layer 2, the height of the third doping region 33 is higher than the height of the buried layer 4. The third doping region 33 is in direct contact with the first doping region 31. Among them, the doping types of the substrate 1 and the drift layer 2 are both the first doping type; the doping types of the first doping region 31, the second doping region 32, the third doping region 33, the buried layer 4, and the terminal structure 7 are all the second doping type.

[0025] As an example, the substrate 1 is at least one of a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, a gallium oxide substrate, a diamond substrate, and an aluminum nitride substrate.

[0026] As an example, in some embodiments, the recessed structure is a groove whose bottom surface is parallel to the substrate. In other embodiments, the shape of the recessed structure is not limited in any way.

[0027] As an example, the material of the field plate 6 is a metal material (such as aluminum, copper, nickel, etc.) or a semiconductor material (such as polysilicon).

[0028] As an example, the terminal structure 7 is one or a combination of a field limiting ring (Field Limiting Ring, FLR), a junction termination extension structure (Junction Termination Extension, JTE), and a field plate (Field Plate, FP). Figure 6 , Figure 7 As shown, the terminal structure 7 is a field limiting ring. Figure 8 As shown, the terminal structure 7 is a junction terminal extension structure. Fig. 9 As shown, the terminal structure 7 is a combination of a field limiting ring and a junction terminal extension structure. Fig.10 As shown, the terminal structure 7 is a combination of a junction terminal extension structure and a floating field plate 6. Fig.11 As shown, the terminal structure 7 directly in contact with the first doped region 31 is a field limiting ring, and the terminal structure 7 directly in contact with the second doped region 32 is a junction terminal extension structure; that is, the terminal structure close to the main junction area of ​​the semiconductor device and the terminal structure close to the cutting road area can be the same or different.

[0029] As an example, the doping types of the substrate 1 and the drift layer 2 are both n-type, and the doping types of the first doping region 31, the second doping region 32, the third doping region 33, the buried layer 4, and the terminal structure 7 are p-type. Alternatively, the doping types of the substrate 1 and the drift layer 2 are both p-type, and the doping types of the first doping region 31, the second doping region 32, the third doping region 33, the buried layer 4, and the terminal structure 7 are n-type.

[0030] Example 2 Reference Figure 7 to Figure 12 , a semiconductor device, divided into a main junction region A, a terminal region B and a cutting path region C, wherein the terminal region B comprises the semiconductor device terminal structure in embodiment 1. A cathode 8 is deposited on the surface of the substrate 1 facing away from the drift layer 2. An anode 9 is deposited on the upper surface of the third doping region 33 (or the drift layer 2) located in the main junction region A. Continue to refer to Fig.12 A fourth doping region 34 is provided on the upper layer of the drift layer 2 in the cutting street region C. The doping type of the fourth doping region 34 is the same as the doping type of the first doping region 31. The fourth doping region 34 can further reduce the risk of breakdown in the cutting street region C.

[0031] As an example, the doping depth of the third doping region 33 in the direction from the drift layer 2 to the substrate 1 can be adjusted. For example, the doping depth of the third doping region 33 makes the third doping region 33 directly contact the buried layer 4 (e.g. Fig.13 as shown).

[0032] As an example, the doping depth of the fourth doping region 34 in the direction from the drift layer 2 to the substrate 1 can be adjusted. For example, the doping depth of the fourth doping region 34 makes the fourth doping region 34 directly contact the buried layer 4 (eg Fig.14 as shown).

[0033] As an example, the drift layer 2 is divided into a first drift layer 21 and a second drift layer 22, the first drift layer 21 is located between the substrate 1 and the buried layer 4, and the second drift layer 22 is located above the buried layer 4. The second drift layer 22 and the first drift layer 21 have the same doping type but different doping concentrations. The doping depth of the third doping region 33 is such that the third doping region 33 is not in direct contact with the buried layer 4 (e.g., Figures 7 to 12 As shown), at this time, the second drift layer 22 of the main junction region A acts as a current diffusion layer, which can enhance the conduction capability of the device.

[0034] As an example, the drift layer 2 is divided into a first drift layer 21 and a second drift layer 22, the first drift layer 21 is located between the substrate 1 and the buried layer 4, and the second drift layer 22 is located above the buried layer 4. The second drift layer 22 and the first drift layer 21 have the same doping type and different doping concentrations. The doping depth of the fourth doping region 34 is such that the fourth doping region 34 is not in direct contact with the buried layer 4 (e.g. Fig.12 As shown), at this time, the second drift layer 22 in the cutting channel area C acts as a current diffusion layer, which can enhance the conduction capability of the device.

[0035] As an example, the insulating dielectric layer 5 extends from the inside of the recessed structure to the upper surface of the drift layer 2. The field plate 6 extends from the inner side of the first sidewall of the recessed structure to the upper surface of the insulating dielectric layer 5 located in the main junction region A, and periodically contacts the anode 9 in three-dimensional space (e.g. Fig.15 As shown, Fig.15 For the convenience of observation, the interior of the recessed structure is not completely filled with an insulating dielectric layer to achieve the purpose of grounding.

[0036] Example 3 Reference Figure 1 to Figure 6 , a method for preparing a semiconductor device terminal structure, comprising the following steps: S1. growing a drift layer on a substrate; forming a buried layer in the drift layer; S2, forming a concave structure in the middle of the drift layer; S3, forming a first doping region on a first side wall of the recessed structure close to the main junction region, and forming a second doping region on a second side wall close to the cutting track region; forming a terminal structure at the bottom of the recessed structure; and forming a third doping region in an upper layer of the drift layer of the main junction region; S4, depositing an insulating medium on the structure obtained in step S3, etching away the insulating medium inside the recessed structure, and retaining the insulating medium on the sidewall and bottom of the recessed structure; S5, depositing a field plate material in the recessed structure, and etching to form a field plate; S6. Depositing an insulating dielectric on the structure obtained in step S5 to fill the recessed structure, and etching to form an insulating dielectric layer.

[0037] As an example, the method of forming the buried layer in the drift layer in step S1 is ion implantation, molecular beam epitaxy or chemical vapor deposition.

[0038] As an example, step S1 includes the following steps: growing a first drift layer on a substrate, growing a buried layer on an upper surface of the first drift layer by molecular beam epitaxy, and forming a second drift layer on an upper surface of the buried layer by secondary epitaxy; the first drift layer and the second drift layer are collectively referred to as drift layers. The second drift layer and the first drift layer have the same doping type but different doping concentrations.

[0039] As an example, the etching method in step S2 is dry etching or wet etching.

[0040] As an example, in step S3 , the method for forming the first doping region, the second doping region, and the third doping region is ion implantation or secondary epitaxy; and the method for forming the terminal structure is ion implantation.

[0041] As an example, the method for depositing the insulating medium in step S4 is chemical vapor deposition, and the method for etching the insulating medium is dry etching or wet etching. Step S6 adopts the same method as step S4.

[0042] As an example, the method for depositing the field plate material in step S5 is chemical vapor deposition. When etching the deposited field plate material, only the field plate structure of the sidewall of the recessed structure (such as Fig. 9 As shown), the field plate structure on the sidewall and bottom of the recessed structure can also be retained at the same time (as shown Fig.10 as shown).

[0043] As an example, in step S5, the field plate is formed on the surface of the insulating dielectric layer on the side wall of the recessed structure. In step S6, the insulating dielectric layer on the upper surface of the drift layer is etched away.

[0044] Example 4 A method for preparing a semiconductor device, comprising the method of steps S1 to S6 in embodiment 3, further comprising the following steps: S7, depositing anode metal on the upper surface of the structure obtained in step S6 by chemical deposition, and performing wet etching to obtain an anode; and depositing cathode metal on the lower surface of the substrate by chemical deposition to obtain a cathode.

[0045] In a further preferred embodiment, step S3 further includes forming a fourth doping region in the upper layer of the drift layer in the cutting track region. As an example, the fourth doping region is formed by ion implantation or secondary epitaxy.

[0046] In a further preferred embodiment, the field plate located above the drift layer in the main junction region is retained during etching in step S5, and the field plate extends from the surface of the insulating dielectric layer on the side wall of the recessed structure to the upper surface of the insulating dielectric layer in the main junction region (the insulating dielectric layer in the main junction region is located on the upper surface of the drift layer and is the dielectric layer that is not etched during etching in step S4).

[0047] The above-described embodiments are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various changes and modifications. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A semiconductor device terminal structure, characterized in that: The invention comprises a substrate and a drift layer located on the substrate; the middle part of the drift layer is recessed toward the substrate to form a recessed structure; the recessed structure has a first side wall and a second side wall; a first doped region is arranged on the first side wall and at a corner where the first side wall is connected to the bottom of the recessed structure; a second doped region is arranged on the second side wall and at a corner where the second side wall is connected to the bottom of the recessed structure; a buried layer is arranged in the drift layer around the recessed structure; the first doped region and the second doped region are both in direct contact with the buried layer; in the direction from the substrate to the drift layer, The height of the buried layer is higher than the height of the bottom of the recessed structure; the recessed structure is filled with an insulating dielectric layer; the first sidewall and the second sidewall are both provided with field plates on their inner sides; the field plates are isolated from the first doped region and the second doped region by the insulating dielectric layer; a terminal structure is provided at the bottom of the recessed structure; the first doped region and the second doped region are both in direct contact with the terminal structure; a third doped region is provided on the upper layer of the drift layer in the main junction region of the semiconductor device, and the height of the third doped region is higher than the height of the buried layer along the direction from the substrate to the drift layer; The first doping region is in direct contact with the third doping region; the doping types of the substrate and the drift layer are both the first doping type; the doping types of the first doping region, the second doping region, the third doping region, the buried layer, and the terminal structure are all the second doping type.

2. The semiconductor device terminal structure according to claim 1, characterized in that: The recessed structure is a groove whose bottom surface is parallel to the substrate.

3. The semiconductor device terminal structure according to claim 1, characterized in that: The terminal structure is one or a combination of a field limiting ring, a junction terminal extension structure, and a field plate.

4. The semiconductor device terminal structure according to claim 1, characterized in that: The substrate is at least one of a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, a gallium oxide substrate, a diamond substrate, and an aluminum nitride substrate; or / and the material of the field plate is a metal material or a semiconductor material.

5. The method for preparing a semiconductor device terminal structure according to any one of claims 1 to 4, characterized in that: The following steps are involved: S1. growing a drift layer on a substrate; forming a buried layer in the drift layer; S2, forming a concave structure in the middle of the drift layer; S3, forming a first doping region on a first side wall of the recessed structure close to the main junction region, and forming a second doping region on a second side wall close to the cutting track region; forming a terminal structure at the bottom of the recessed structure; and forming a third doping region in an upper layer of the drift layer of the main junction region; S4, depositing an insulating medium on the structure obtained in step S3, etching away the insulating medium inside the recessed structure, and retaining the insulating medium on the sidewall and bottom of the recessed structure; S5, forming a field plate in the recessed structure; S6. Depositing an insulating dielectric on the structure obtained in step S5 to fill the recessed structure, and etching to form an insulating dielectric layer.

6. The preparation method according to claim 5, characterized in that: Step S1 includes the following steps: growing a first drift layer on the substrate, forming the buried layer on the upper surface of the first drift layer, and forming a second drift layer on the upper surface of the buried layer; the second drift layer and the first drift layer have the same doping type.

7. A semiconductor device, characterized in that: A semiconductor device terminal structure comprising any one of claims 1 to 4.

8. The semiconductor device according to claim 7, characterized in that A fourth doping region is arranged on the upper layer of the drift layer located in the cutting path area of ​​the semiconductor device; along the direction from the substrate to the drift layer, the height of the fourth doping region is higher than the height of the buried layer; the doping type of the fourth doping region is the same as the doping type of the first doping region.

9. The semiconductor device according to claim 8, characterized in that The drift layer includes a first drift layer and a second drift layer, the first drift layer is located between the substrate and the buried layer, the second drift layer is located on the buried layer, and the second drift layer and the first drift layer have the same doping type.

10. The semiconductor device according to claim 7, wherein: An anode is deposited on the upper surface of the drift layer located in the main junction area of ​​the semiconductor device, the insulating dielectric layer extends from the inside of the recessed structure to the upper surface of the drift layer, and the field plate extends from the inner side of the first side wall to the upper surface of the insulating dielectric layer located in the main junction area until it contacts the anode.

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