A MOSFET device and its manufacturing method and layout arrangement structure

Abstract

The present invention provides a MOSFET device, a manufacturing method, and a layout structure thereof, relating to the field of semiconductor technology. A P-type buried layer is disposed within an N-type voltage-resistant layer between the bottom of the trench and the substrate. The P-type buried layer is electrically connected to the source electrode, thereby resolving the problem of insufficient electric field protection at the bottom of the trench gate and effectively protecting the gate dielectric layer under high drain voltages. Furthermore, because there is a gap between the P-type buried layer and the bottom of the trench, current can flow between the bottom of the trench and the P-type buried layer, eliminating the problem of the P-type buried layer design hindering current flow. This, in turn, comprehensively improves the operating performance of the MOSFET device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a MOSFET device, a manufacturing method thereof, and a layout structure thereof. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] The main structure for electronic devices to realize various functions is the integrated circuit, and MOSFET devices are important electronic components of integrated circuits.

[0004] Wide bandgap semiconductor trench MOSFET devices have become a major development direction in the semiconductor field due to their excellent characteristics in high-power applications.

[0005] Existing wide bandgap semiconductor trench MOSFET devices still have deficiencies, and their structure and manufacturing methods need to be further optimized to improve their performance. Summary of the Invention

[0006] In view of the above problems, this application provides a MOSFET device and its manufacturing method and layout structure, which are used to improve the working performance of the MOSFET device. The specific solution is as follows:

[0007] A first aspect of the present application provides a MOSFET device, the MOSFET device comprising: a substrate;

[0008] An N-type voltage-resistant layer located on one side of the substrate; a drain located on a side of the substrate away from the N-type voltage-resistant layer;

[0009] A P-type well region, a source region, and a trench gate are provided on a surface of the N-type voltage-resistant layer facing away from the substrate; the trench gate comprises a trench and a gate located in the trench, with a gate dielectric layer between the gate and the trench;

[0010] The source region includes an N-type source region and a P-type source region; the N-type source region is located on a side of the P-type well region away from the substrate, the P-type source region is located on both sides of the trench, and the trench runs through the N-type source region and the P-type well region;

[0011] a source electrode in contact with the N-type source region and the P-type source region;

[0012] A P-type buried layer is located in the N-type voltage-resistant layer and between the bottom of the trench and the substrate; the P-type buried layer is electrically connected to the source, and there is a gap between the P-type buried layer and the bottom of the trench.

[0013] Preferably, in the above MOSFET device, the width of the P-type buried layer is equal to the width of the trench;

[0014] Or, the width of the P-type buried layer is smaller than the width of the trench;

[0015] Alternatively, the width of the P-type buried layer is greater than the width of the trench.

[0016] Preferably, in the above MOSFET device, in a direction parallel to the plane where the substrate is located, there is a gap between the geometric center of the P-type buried layer and the geometric center of the bottom of the trench.

[0017] Preferably, in the above MOSFET device, the MOSFET device further comprises: a P-type ground layer;

[0018] The P-type ground layer is in contact with the P-type buried layer and the P-type source region respectively.

[0019] Preferably, in the above MOSFET device, the MOSFET device further comprises:

[0020] An N-type current diffusion region is located between the P-type well region and the P-type buried layer, wherein the N-type current diffusion region has the same doping type as the N-type voltage-withstanding layer, and the doping concentration of the N-type current diffusion region is greater than or equal to the doping concentration of the N-type voltage-withstanding layer.

[0021] Preferably, in the above MOSFET device, the N-type current diffusion region at least partially wraps the P-type buried layer.

[0022] Preferably, in the above MOSFET device, the MOSFET device further comprises: a P-type ground layer; the P-type ground layer is in contact with the P-type buried layer and the P-type source region respectively;

[0023] The N-type current diffusion region is located at least between one of the sidewalls of the trench and the P-type source region.

[0024] Preferably, in the above MOSFET device, the MOSFET device further comprises: a P-type ground layer;

[0025] The P-type ground layer is in contact with the P-type buried layer and the P-type source region respectively;

[0026] The N-type current diffusion region is located on a side of the P-type ground layer facing away from the substrate.

[0027] Preferably, in the above MOSFET device, a surface of the P-type source region facing away from the substrate and a surface of the N-type source region facing away from the substrate are located in the same plane.

[0028] Preferably, in the above MOSFET device, a surface of the P-type source region facing away from the substrate is located between the first surface and the second surface;

[0029] The first surface is the surface of the N-type source region facing away from the substrate, and the second surface is the surface of the P-type well region facing the substrate.

[0030] Preferably, in the above MOSFET device, the distance between the surface of the P-type source region facing away from the substrate and the substrate is smaller than the distance between the surface of the P-type well region facing the substrate and the substrate;

[0031] The source electrode forms a Schottky contact with the sidewall of the exposed N-type current diffusion region.

[0032] Preferably, in the above-mentioned MOSFET device, the P-type source region includes at least two sub-P-type source regions arranged in sequence and spaced apart in the length extension direction of the trench, and / or the P-type buried layer includes at least two sub-P-type buried layers arranged in sequence and spaced apart in the length extension direction of the trench.

[0033] Preferably, in the above MOSFET device, the shape of the sub-P-type source region is square, triangle, polygon or circle; the shape of the sub-P-type buried layer is square, triangle, polygon or circle.

[0034] Preferably, in the above MOSFET device, the MOSFET device further comprises: a P-type ground layer;

[0035] The sub-P-type buried layer is connected to at least one of the sub-P-type source regions via the P-type grounding layer.

[0036] Preferably, in the above MOSFET device, the P-type ground layers located on both sides of the trench are arranged alternately or symmetrically.

[0037] Preferably, in the above MOSFET device, in the P-type ground layers located on both sides of the trench, at least one sub-P-type source region is spaced between two adjacent P-type ground layers in the length extension direction of the trench.

[0038] Preferably, in the above MOSFET device, a length extension direction of the P-type ground layer intersects with a length extension direction of the trench.

[0039] Preferably, in the above MOSFET device, in the length extension direction of the trench, the N-type source regions and the P-type source regions are alternately arranged in sequence;

[0040] Alternatively, the orthographic projection of the N-type source region on the substrate surrounds the orthographic projection of the P-type source region on the substrate.

[0041] Preferably, in the above MOSFET device, the P-type source region is in contact with the sidewall of the trench and the P-type buried layer.

[0042] Preferably, in the above-mentioned MOSFET device, when the P-type source region includes at least two sub-P-type source regions arranged in sequence in the length extension direction of the trench, at least one of the sub-P-type source regions is in contact with the side wall of the trench and the P-type buried layer.

[0043] Preferably, in the above MOSFET device, a length extension direction of the trench intersects with a length extension direction of the P-type buried layer.

[0044] Preferably, in the above MOSFET device, the MOSFET device further comprises: a P-type layer;

[0045] One side of the P-type layer is located at the bottom of the channel, and the other side extends toward the side where the substrate is provided and at least penetrates the P-type buried layer.

[0046] A second aspect of the present application provides a method for manufacturing a MOSFET device, the method comprising:

[0047] providing a substrate;

[0048] forming an N-type voltage-resistant layer on one side of the substrate;

[0049] forming a P-type well region, a source region, and a P-type buried layer in the N-type voltage-resistant layer;

[0050] A trench gate is formed; the trench gate includes a trench and a gate located in the trench, with a gate dielectric layer between the gate and the trench; the source region includes an N-type source region and a P-type source region; the N-type source region is located on a side of the P-type well region facing away from the substrate, the P-type source region is located on both sides of the trench, and the trench penetrates the N-type source region and the P-type well region; the P-type buried layer is located between the bottom of the trench and the substrate; and a gap is formed between the P-type buried layer and the bottom of the trench;

[0051] A source and a drain are formed; the drain is located on a side of the substrate away from the N-type voltage-resistant layer, the source is in contact with the N-type source region and the P-type source region, and the P-type buried layer is electrically connected to the source.

[0052] A third aspect of the present application provides a layout structure of a MOSFET device, wherein the layout structure of the MOSFET device comprises: a plurality of MOSFET cells;

[0053] The cross-sectional shapes of the MOSFET cell are different at different positions.

[0054] By means of the above technical solution, the present application provides a MOSFET device and its manufacturing method and layout structure, in which a P-type buried layer is arranged in the N-type voltage-resistant layer between the bottom of the trench and the substrate, and the P-type buried layer is electrically connected to the source, thereby solving the problem of insufficient electric field protection at the bottom of the trench and achieving effective protection of the gate dielectric layer under high drain voltage; and since there is a gap between the P-type buried layer and the bottom of the channel, the current can also flow between the bottom of the trench and the P-type buried layer, and there is no problem of the design of the P-type buried layer hindering the flow of current, thereby comprehensively improving the working performance of the MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

[0056] Figure 1 A schematic cross-sectional and top view of a MOSFET device provided by an embodiment of the present invention;

[0057] Figure 2 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention;

[0058] Figure 3 A schematic cross-sectional and top view of another MOSFET device provided by an embodiment of the present invention;

[0059] Figure 4 A schematic cross-sectional and top view of another MOSFET device provided by an embodiment of the present invention;

[0060] Figure 5 An embodiment of the present invention provides a Figure 2 Schematic diagram of the current path of the MOSFET device;

[0061] Figure 6 A schematic cross-sectional and top view of another MOSFET device provided by an embodiment of the present invention;

[0062] Figure 7 A schematic cross-sectional and top view of another MOSFET device provided by an embodiment of the present invention;

[0063] Figure 8 A schematic cross-sectional and top view of another MOSFET device provided by an embodiment of the present invention;

[0064] Figure 9 A schematic cross-sectional view of a MOSFET device provided by an embodiment of the present invention;

[0065] Figure 10 A schematic cross-sectional and top view of another MOSFET device provided by an embodiment of the present invention;

[0066] Figure 11 A schematic cross-sectional and top view of another MOSFET device provided by an embodiment of the present invention;

[0067] Figure 12 A schematic cross-sectional and top view of another MOSFET device provided by an embodiment of the present invention;

[0068] Figure 13 A schematic cross-sectional view of another MOSFET device provided by an embodiment of the present invention;

[0069] Figure 14 A schematic cross-sectional view of another MOSFET device provided by an embodiment of the present invention;

[0070] Figure 15 A schematic cross-sectional view of another MOSFET device provided by an embodiment of the present invention;

[0071] Figure 16 A schematic top view of a MOSFET device provided by an embodiment of the present invention;

[0072] Figure 17 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0073] Figure 18 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0074] Figure 19 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0075] Figure 20 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0076] Figure 21 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0077] Figure 22 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0078] Figure 23 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0079] Figure 24 An embodiment of the present invention provides a Figure 23 A schematic cross-sectional view along the cutting line C;

[0080] Figure 25 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0081] Figure 26 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0082] Figure 27 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0083] Figure 28 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0084] Figure 29 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0085] Figure 30 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0086] Figure 31 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0087] Figure 32 An embodiment of the present invention provides a Figure 31 Schematic diagram of the comprehensive cross section of the middle cutting line A and cutting line B;

[0088] Figure 33 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0089] Figure 34 An embodiment of the present invention provides a Figure 33 Schematic diagram of the cross section along the middle cutting line A;

[0090] Figure 35 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0091] Figure 36 An embodiment of the present invention provides a Figure 35 Schematic diagram of the comprehensive cross section of the middle cutting line A and cutting line B;

[0092] Figure 37 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0093] Figure 38 An embodiment of the present invention provides a Figure 37 Schematic diagram of the comprehensive cross section of the middle cutting line A and cutting line B;

[0094] Figure 39 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0095] Figure 40 An embodiment of the present invention provides a Figure 39 Schematic diagram of the comprehensive cross section of the middle cutting line A and cutting line B;

[0096] Figure 41 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0097] Figure 42 An embodiment of the present invention provides a Figure 41 Schematic diagram of the comprehensive cross section of the middle cutting line A and cutting line B;

[0098] Figure 43 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0099] Figure 44 An embodiment of the present invention provides a Figure 43 Schematic diagram of the cross section along the middle cutting line A;

[0100] Figure 45 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0101] Figure 46 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0102] Figure 47 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0103] Figure 48 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0104] Figure 49 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0105] Figure 50 A schematic top view of another MOSFET device provided by an embodiment of the present invention;

[0106] Figure 51 A schematic diagram showing different cross-sectional shapes of a MOSFET cell at different positions provided by an embodiment of the present invention;

[0107] Figure 52 A schematic top view of a layout structure of a MOSFET device provided in an embodiment of the present invention;

[0108] Figure 53 A schematic top view of another MOSFET device layout structure provided by an embodiment of the present invention;

[0109] Figure 54 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0110] Figure 55 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0111] Figure 56 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0112] Figure 57 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0113] Figure 58 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0114] Figure 59 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0115] Figure 60 An embodiment of the present invention provides a Figure 54 、 Figure 55 、 Figure 56 、 Figure 57 and Figure 59 A schematic cross-sectional view along the cutting line D;

[0116] Figure 61 An embodiment of the present invention provides a Figure 53 、 Figure 55 and Figure 57 A schematic cross-sectional view along cutting line F;

[0117] Figure 62 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0118] Figure 63 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0119] Figure 64 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0120] Figure 65 A schematic top view of a layout structure of another MOSFET device provided in an embodiment of the present invention;

[0121] Figure 66 A schematic flow chart of a method for manufacturing a MOSFET device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0122] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation methods of the present application are only used to explain the specific embodiments of the present application and are not intended to limit the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0123] Ultra-wide bandgap semiconductor materials with band gaps wider than those of silicon carbide (SiC) and gallium nitride (GaN) include gallium oxide (Ga2O3), diamond, and aluminum nitride (AlN). These wide- and ultra-wide-bandgap semiconductor materials have attracted widespread attention within the industry due to their exceptional properties. Compared to traditional silicon materials, these materials offer advantages in physical properties such as band gap width, critical breakdown electric field strength, and electron saturation drift velocity. Power devices fabricated from these materials, such as diodes and transistors, exhibit superior electrical properties, enabling them to meet the high-power, high-voltage, high-frequency, and high-temperature requirements that silicon-based devices cannot meet. These materials represent a path to surpassing Moore's Law, and are therefore widely used in new energy sectors (photovoltaics, energy storage, charging stations, electric vehicles, etc.), driving the "new energy revolution."

[0124] Wide- and ultra-wide-bandgap semiconductors, with their superior optical and electrical properties, are considered an exciting and challenging new research area. The wide bandgap enables device applications in many harsh environments. For example, in geothermal energy production and oil and gas extraction, higher drilling speeds and lower failure rates can be achieved. High-temperature operation allows electronic sensors in aluminum and steel mills, as well as coal- and gas-fired power plants, to operate at higher temperatures, thereby improving the energy efficiency of these industrial processes.

[0125] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0126] It should be noted that the directional words appearing in the present invention are based on the relative position relationship shown in the drawings and cannot be used as an absolute limitation to the present application.

[0127] refer to Figure 1 , Figure 1 A schematic cross-sectional view and top view of a MOSFET device provided by an embodiment of the present invention, Figure 1 a is the corresponding cross-sectional diagram, Figure 1 b is the corresponding top view; Figure 2 , Figure 2 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention, Figure 2 a is the corresponding cross-sectional diagram, Figure 2 b is the corresponding top view; Figure 3 , Figure 3 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention, Figure 3 a is the corresponding cross-sectional diagram, Figure 3 b is the corresponding top view; Figure 4 , Figure 4 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention, Figure 4 a is the corresponding cross-sectional diagram, Figure 4 b is a corresponding top view. The MOSFET device provided by the embodiment of the present invention includes: a substrate 11.

[0128] An N-type voltage-resistant layer 12 is located on one side of the substrate 11 ; and a drain 13 is located on a side of the substrate 11 away from the N-type voltage-resistant layer 12 .

[0129] A P-type well region 14, a source region and a trench gate are arranged on the surface of the N-type voltage-resistant layer 12 on the side away from the substrate 11; the trench gate includes a trench and a gate 15 located in the trench, and a gate dielectric layer 16 is provided between the gate 15 and the trench.

[0130] The source region includes an N-type source region 17 and a P-type source region 18 ; the N-type source region 17 is located on the side of the P-type well region 14 away from the substrate 11 , and the P-type source region 18 is located on both sides of the trench, which runs through the N-type source region 17 and the P-type well region 14 .

[0131] A source electrode 19 is in contact with the N-type source region 17 and the P-type source region 14 .

[0132] A P-type buried layer 20 is located in the N-type voltage-resistant layer 12 and between the bottom of the trench and the substrate 11 ; the P-type buried layer 20 is electrically connected to the source, and a gap exists between the P-type buried layer 20 and the bottom of the trench.

[0133] Specifically, in the embodiment of the present invention, the P-type source region 18 is located on both sides of the trench, and the implantation depth of the P-type source region 18 is relatively deep, which can shield a portion of the potential from the drain 13; on this basis, a P-type buried layer 20 is provided in the N-type voltage-resistant layer 12 between the bottom of the trench and the substrate 11. The P-type buried layer 20 is electrically connected to the source, solving the problem of insufficient protection of the P-type source region 18 against the electric field at the bottom of the trench, improving the protection effect of the electric field at the bottom of the trench, and achieving effective protection of the gate dielectric layer under high drain voltage. Figure 5 , Figure 5 An embodiment of the present invention provides a Figure 2 Schematic diagram of the current path of the MOSFET device. Since there is a gap between the P-type buried layer 20 and the bottom of the channel, the current can also flow between the bottom of the trench and the P-type buried layer 20. There is no problem of the design of the P-type buried layer 20 hindering the flow of current, thereby comprehensively improving the working performance of the MOSFET device.

[0134] In an optional embodiment of the present invention, reference Figure 6 , Figure 6 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention, Figure 6 a is the corresponding cross-sectional diagram, Figure 6 b is the corresponding top view; Figure 7 , Figure 7 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention, Figure 7 a is the corresponding cross-sectional diagram, Figure 7 b is the corresponding top view; Figure 8 , Figure 8 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention, Figure 8 a is the corresponding cross-sectional diagram, Figure 8 b is a corresponding top view. The width of the P-type buried layer 20 is equal to the width of the trench; or, the width of the P-type buried layer 20 is smaller than the width of the trench; or, the width of the P-type buried layer 20 is larger than the width of the trench.

[0135] In a direction parallel to the plane where the substrate 11 is located, there is a gap between the geometric center of the P-type buried layer 20 and the geometric center of the bottom of the trench.

[0136] Specifically, in the embodiment of the present invention, Figure 6 As shown, the width of the P-type buried layer 20 is smaller than the width of the trench, that is, L1 < L2; Figure 7 As shown in FIG, the width of the P-type buried layer 20 is greater than the width of the trench, that is, L3>L4. Figure 8As shown, there is a gap between the geometric center of the P-type buried layer 20 and the geometric center of the bottom of the trench in a direction parallel to the plane of the substrate 11. It can be understood that the geometric center of the P-type buried layer 20 is offset to the right by a distance relative to the geometric center of the bottom of the trench.

[0137] That is, in the embodiments of the present invention, the positional and dimensional relationship between the P-type buried layer 20 and the trench can be freely varied, which indirectly reflects the structural diversity of the MOSFET device in the technical solution of this application. Specifically, the P-type buried layer 20 can be equal to, wider than, or narrower than the width of the trench, and this is not limited in the embodiments of the present invention. Furthermore, the relative position of the P-type buried layer 20 and the trench can be varied, for example, offset to the left or right.

[0138] Based on the structure in which the width of the P-type buried layer 20 is greater than the width of the trench, the MOSFET device can have better gate oxide reliability; based on the structure in which the width of the P-type buried layer 20 is less than the width of the trench, the MOSFET device can have better conduction performance; based on the structure in which the P-type buried layer 20 can be offset left and right relative to the trench position, the MOSFET device structure can have greater process tolerance and simplify the process difficulty.

[0139] In an optional embodiment of the present invention, Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 As shown, the MOSFET device further includes: a P-type ground layer 22 .

[0140] The P-type ground layer 22 contacts the P-type buried layer 20 and the P-type source region 18 respectively.

[0141] Specifically, in the embodiment of the present invention, the electrical connection between the P-type buried layer 20 and the P-type source region 18 can be achieved by providing a P-type ground layer 22 in contact with both, thereby improving the stability of the electrical connection between the P-type buried layer 20 and the P-type source region 18. In some structural solutions, the MOSFET device may not need to provide a P-type ground layer 22, and it is sufficient to ensure that the P-type buried layer 20 and the P-type source region 18 are electrically connected. The specific electrical connection method can be determined according to actual conditions.

[0142] In an optional embodiment of the present invention, Figure 1 、 Figure 2 、 Figure 4-Figure 8As shown, the MOSFET device further includes an N-type current diffusion region 21 located between the P-type well region 14 and the P-type buried layer 20. The N-type current diffusion region 21 has the same doping type as the N-type voltage-withstanding layer 12, and the doping concentration of the N-type current diffusion region 21 is greater than or equal to the doping concentration of the N-type voltage-withstanding layer 12.

[0143] Specifically, in the embodiment of the present invention, when the doping concentration of the N-type current diffusion region 21 is equal to the doping concentration of the N-type voltage-withstanding layer 12, the N-type current diffusion region 21 plays the same role as the N-type voltage-withstanding layer 12. When the doping concentration of the N-type current diffusion region 21 is greater than the doping concentration of the N-type voltage-withstanding layer 12, the relatively high doping of the N-type current diffusion region 21 can reduce the width of the depletion region, thereby increasing the current conduction path and enhancing the conduction capability of the MOSFET device.

[0144] In an optional embodiment of the present invention, reference Figure 9 , Figure 9 The cross-sectional view of a MOSFET device provided by an embodiment of the present invention is as follows: the N-type current diffusion region 21 at least partially wraps the P-type buried layer 20 .

[0145] Specifically, in the embodiment of the present invention, when the doping concentration of the N-type current diffusion region 21 is greater than the doping concentration of the N-type voltage-resistant layer 12, the design of the N-type current diffusion region 21 at least partially wrapping the P-type buried layer 20 can further enhance the conduction capability of the MOSFET device. Figure 9 As shown, the N-type current diffusion region 21 completely wraps the P-type buried layer 20 for illustration.

[0146] In an optional embodiment of the present invention, reference Figure 10 , Figure 10 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention, Figure 10 a is the corresponding cross-sectional diagram, Figure 10 b is the corresponding top view; Figure 11 , Figure 11 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention, Figure 11 a is the corresponding cross-sectional diagram, Figure 11 b is the corresponding top view; Figure 12 , Figure 12 A schematic cross-sectional view and top view of another MOSFET device provided by an embodiment of the present invention, Figure 12 a is the corresponding cross-sectional diagram, Figure 12b is a corresponding top view. The MOSFET device further includes: a P-type ground layer 22; the P-type ground layer 22 contacts the P-type buried layer 20 and the P-type source region 18; and the N-type current diffusion region 21 is located between at least one sidewall of the trench and the P-type source region 18, or the N-type current diffusion region 21 is located on a side of the P-type ground layer 22 facing away from the substrate 11.

[0147] Specifically, in the embodiment of the present invention, Figure 10 As shown, the P-type ground layer 22 is located on the left side of the trench and at the bottom of the trench, and the N-type current diffusion region 21 is located on the right side of the trench; Figure 11 As shown, the P-type ground layer 22 is located on the right side of the trench and at the bottom of the trench, and the N-type current diffusion region 21 is located on the left side of the trench; Figure 12 As shown, the P-type ground layer 22 is located at the bottom of the trench, and the N-type current diffusion region 21 is located on the left and right sides of the trench; Figure 2 As shown, the N-type current diffusion region 21 is located on the side of the P-type ground layer 22 facing away from the substrate.

[0148] In the embodiment of the present invention, the position and number of N-type current diffusion regions 21 can be flexibly adjusted. Locations with N-type current diffusion regions 21 have higher current density, while locations without N-type current diffusion regions 21 have lower current density, or even no current at all due to the presence of P-type ground layer 22. In the embodiment of the present invention, by adjusting the distribution of N-type current diffusion regions 21 and P-type ground layer 22 and their proportions within the overall layout (the layout opening positions and opening area ratios), current and heat distribution can be controlled to enhance short-circuit, surge, and UIS avalanche withstand capabilities. For example, one-side conduction, two-side conduction, or no conduction on either side can be achieved.

[0149] It should be noted that Figure 10-12 Only some relative positional relationships between the N-type current diffusion region 21 and the P-type ground layer 22 are illustrated. The relative positional relationship between the N-type current diffusion region 21 and the P-type ground layer 22 may have other variations, and may be reasonably designed based on the desired purpose.

[0150] In an optional embodiment of the present invention, Figure 11-12 As shown, the surface of the P-type source region 18 facing away from the substrate 11 and the surface of the N-type source region 17 facing away from the substrate 11 are located in the same plane. Figure 13 , Figure 13 A cross-sectional schematic diagram of another MOSFET device provided by an embodiment of the present invention, referring to Figure 14 , Figure 14A cross-sectional schematic diagram of another MOSFET device provided in an embodiment of the present invention, wherein the surface of the P-type source region 18 facing away from the substrate 11 is located between the first surface and the second surface; the first surface is the surface of the N-type source region 17 facing away from the substrate 11, and the second surface is the surface of the P-type well region 14 facing the substrate 11.

[0151] Specifically, in the embodiment of the present invention, Figure 13 As shown, the surface of the P-type source region 18 facing away from the substrate 11 and the surface of the P-type well region 14 facing away from the substrate 11 are located in the same plane. This design can increase the contact area between the source 19 and the P-type source region 18 and the N-type source region 17, thereby achieving the purpose of reducing the cell size. Figure 14 As shown, the surface of the P-type source region 18 facing away from the substrate 11 and the surface of the P-type well region 14 facing the substrate 11 are located in the same plane. This design can increase the depth of ion implantation in the P-type source region 18 and save the implantation energy of the P-type source region 18.

[0152] In an optional embodiment of the present invention, reference Figure 15 , Figure 15 A schematic cross-sectional view of another MOSFET device provided by an embodiment of the present invention. The distance between the surface of the P-type source region 18 facing away from the substrate 11 and the substrate 11 is smaller than the distance between the surface of the P-type well region 14 facing the substrate 11 and the substrate; the source electrode 19 forms a Schottky contact with the sidewall of the exposed N-type current diffusion region 21.

[0153] Specifically, in the embodiment of the present invention, Figure 15 As shown, the relationship H1 < H2 exists, that is, the distance between the surface of the P-type source region 18 facing away from the substrate 11 and the substrate 11 is smaller than the distance between the surface of the P-type well region 14 facing the substrate 11 and the substrate. At this time, part of the sidewall of the N current diffusion region 21 forms a Schottky contact with the source 19, forming a Schottky diode 23 between the two, thereby improving the freewheeling characteristics of the MOSFET device in the third quadrant.

[0154] In an optional embodiment of the present invention, reference Figure 16 , Figure 16 A schematic top view of a MOSFET device according to an embodiment of the present invention is provided. Figure 17 , Figure 18 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 18 , Figure 18 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 19 , Figure 19A schematic top view of another MOSFET device provided by an embodiment of the present invention. The P-type source region 18 includes at least two sub-P-type source regions spaced apart in sequence along the lengthwise extension direction of the trench, and / or the P-type buried layer 20 includes at least two sub-P-type buried layers spaced apart in sequence along the lengthwise extension direction of the trench.

[0155] Specifically, in the embodiment of the present invention, Figure 16 As shown, the P-type source region 18 is continuous in the longitudinal extension direction of the trench, and the P-type buried layer 20 includes at least two segments of sub-P-type buried layers arranged in sequence in the longitudinal extension direction of the trench; Figure 17-Figure 19 As shown, the P-type source region 18 includes at least two sub-P-type source regions arranged in sequence along the length extension direction of the trench, and the P-type buried layer 20 includes at least two sub-P-type buried layers arranged in sequence along the length extension direction of the trench.

[0156] The shape of the sub-P type source region 18 includes but is not limited to a square, triangle, polygon or circle; the shape of the sub-P type buried layer 20 includes but is not limited to a square, triangle, polygon or circle. Figure 17 As shown, the sub-P-type source region is in the shape of a square; Figure 18 As shown, the sub-P-type source region is a triangle; Figure 19 As shown, the shape of the sub-P-type source region is a semicircle.

[0157] Optional, reference Figure 20 , Figure 20 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 21 , Figure 21 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 22 , Figure 22 A schematic top view of another MOSFET device provided by an embodiment of the present invention. Figure 20 As shown, the P-type source region 18 is continuous in the longitudinal extension direction of the trench, and the P-type buried layer 20 is continuous in the longitudinal extension direction of the trench, and the P-type ground layer 22 includes at least two segments of sub-P-type ground layers arranged in sequence in the longitudinal extension direction of the trench; Figure 21 and Figure 22 As shown, the P-type source region 18 includes at least two sub-P-type source regions arranged in sequence and spaced apart in the length extension direction of the groove, the P-type buried layer 20 is continuous in the length extension direction of the groove, and the P-type ground layer 22 includes at least two sub-P-type ground layers arranged in sequence and spaced apart in the length extension direction of the groove.

[0158] refer to Figure 23 , Figure 23 A schematic top view of another MOSFET device provided by an embodiment of the present invention. Figure 23 The cross-sectional diagram along the cutting line A is shown in Figure 2 As shown in a; Figure 23 The cross-sectional view along the cutting line B is shown in FIG. Figure 1 As shown in a; Figure 23 The cross-sectional view along the cutting line C is shown in FIG. Figure 24 As shown, Figure 24 An embodiment of the present invention provides a Figure 23 A schematic cross-sectional view along the cutting line C; Figure 23 The cross-sectional diagram along the cutting line D is shown in FIG. Figure 3 As shown in a.

[0159] like Figure 17 、 Figure 18 、 Figure 21 as well as Figure 23 As shown, the MOSFET device further includes: a P-type grounding layer 22; the sub-P-type buried layer is connected to at least one of the sub-P-type source regions via the P-type grounding layer 22.

[0160] As can be seen from the above description, in the embodiment of the present invention, the P-type buried layer 20 and the P-type source region 18 can be continuously present along the length extension direction of the trench, or can be arranged in at least two sections spaced apart from each other. The shapes of the P-type buried layer 20 and the P-type source region 18 can be square, triangular, hexagonal, circular, or other shapes. The P-type ground layer 22 can be adjusted based on the continuity of the P-type buried layer 20 and the P-type source region 18, as long as the P-type buried layer 20 is connected to at least one sub-P-type source region through the P-type ground layer 22.

[0161] In an optional embodiment of the present invention, reference Figure 25 , Figure 25 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 26 , Figure 26 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 27 , Figure 27 A schematic top view of another MOSFET device provided by an embodiment of the present invention. The P-type ground layers 22 located on either side of the trench are arranged alternately or symmetrically. Within the P-type ground layers 22 located on either side of the trench, at least one sub-P-type source region is spaced between adjacent two P-type ground layers 22 along the length of the trench.

[0162] Specifically, in the embodiment of the present invention, Figure 17As shown, the P-type ground layers 22 on both sides of the groove are arranged symmetrically; Figure 25 and Figure 26 As shown, the P-type ground layers 22 on both sides of the groove are arranged alternately; Figure 27 As shown, one of the P-type ground layers 22 is in contact with two adjacent sub-P-type buried layers at the same time.

[0163] Further, such as Figure 17 、 Figure 25 、 Figure 26 and Figure 27 As shown, in the P-type ground layers 22 located on both sides of the trench, in the length extension direction of the trench, at least one sub-P-type source region is spaced between two adjacent P-type ground layers 22 .

[0164] Optionally, in another embodiment of the present invention, referring to Figure 28 , Figure 28 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 29 , Figure 29 This is a top view of another MOSFET device provided by an embodiment of the present invention. The length extension direction of the P-type ground layer 22 intersects with the length extension direction of the trench.

[0165] Specifically, in the embodiment of the present invention, the connection method between the P-type ground layer 22 and the P-type source region 18 and the P-region buried layer 20 can be a horizontal connection, an inclined connection, a cross connection or a M-shaped connection, etc., which is not limited in the embodiment of the present invention. The pattern of the P-type ground layer 22 can be determined based on factors such as the actual layout.

[0166] Optionally, in another embodiment of the present invention, referring to Figure 30 , Figure 30 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 31 , Figure 31 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 32 , Figure 32 An embodiment of the present invention provides a Figure 31 Schematic diagram of the comprehensive cross section of cutting line A and cutting line B, refer to Figure 33 , Figure 33 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 34 , Figure 34 An embodiment of the present invention provides a Figure 33Schematic cross-sectional view of the center cutting line A. Along the longitudinal extension direction of the trench, the N-type source regions 17 and the P-type source regions 18 are alternately arranged; or, the orthographic projection of the N-type source regions 17 on the substrate 11 surrounds the orthographic projection of the P-type source regions 18 on the substrate 11.

[0167] Specifically, in the embodiment of the present invention, Figure 30 As shown in the longitudinal extension direction of the trench, the N-type source regions 17 and the P-type source regions 18 are arranged alternately in sequence. Figure 31 and 33 As shown, the orthographic projection of the N-type source region 17 on the substrate 11 surrounds the orthographic projection of the P-type source region 18 on the substrate 11. That is, in the embodiment of the present invention, the N-type source regions 17 and the P-type source regions 18 can be arranged alternately or the N-type source region 17 can surround the P-type source region 18. In the solution where the N-type source region 17 surrounds the P-type source region 18, the purpose of saving area and reducing the cell pitch can be achieved.

[0168] Optionally, in another embodiment of the present invention, referring to Figure 35 , Figure 35 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 36 , Figure 36 An embodiment of the present invention provides a Figure 35 Schematic diagram of the comprehensive cross section of cutting line A and cutting line B, refer to Figure 37 , Figure 37 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 38 , Figure 38 An embodiment of the present invention provides a Figure 37 Schematic diagram of the comprehensive cross section of cutting line A and cutting line B, refer to Figure 39 , Figure 39 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 40 , Figure 40 An embodiment of the present invention provides a Figure 39 Schematic diagram of the comprehensive cross section of cutting line A and cutting line B, refer to Figure 41 , Figure 41 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 42 , Figure 42 An embodiment of the present invention provides a Figure 41 Schematic diagram of the comprehensive cross section of cutting line A and cutting line B, refer to Figure 43 , Figure 43 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 44 , Figure 44An embodiment of the present invention provides a Figure 43 Schematic cross-sectional view along center cut line A. The P-type source region 18 contacts the sidewalls of the trench and the P-type buried layer 20. When the P-type source region 18 includes at least two sub-P-type source regions spaced apart in the longitudinal direction of the trench, at least one of the sub-P-type source regions contacts the sidewalls of the trench and the P-type buried layer 20.

[0169] Specifically, in an embodiment of the present invention, by making the P-type source region 18 contact the side wall of the trench and the P-type buried layer 20, or making at least one of the sub-P-type source regions contact the side wall of the trench and the P-type buried layer 20, the P-type source region 18 or the sub-P-type source region can play the role of the P-type ground layer 22. At this time, the P-type ground layer 22 can be omitted, thereby achieving the purpose of further saving area and reducing the cell spacing.

[0170] refer to Figure 45 , Figure 45 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 46 , Figure 46 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 47 , Figure 47 A schematic top view of another MOSFET device provided in an embodiment of the present invention, referring to Figure 48 , Figure 48 A schematic top view of another MOSFET device provided by an embodiment of the present invention.

[0171] In the case where the P-type ground layer 22 is not provided, Figure 45 and Figure 46 As shown, the P-type source region 18 includes at least two sub-P-type source regions arranged in sequence along the longitudinal extension direction of the trench, and the P-type buried layer 20 is continuous along the longitudinal extension direction of the trench, wherein at least one of the sub-P-type source regions is in contact with the sidewall of the trench and the P-type buried layer 20. Figure 47 and Figure 48 As shown, the P-type source region 18 includes at least two sub-P-type source regions arranged in sequence and spaced apart in the length extension direction of the trench, and the P-type buried layer 20 includes at least two sub-P-type buried layers arranged in sequence and spaced apart in the length extension direction of the trench, wherein at least one of the sub-P-type source regions is in contact with the side wall of the trench and the P-type buried layer 20.

[0172] In an optional embodiment of the present invention, reference Figure 49 , Figure 49 A schematic top view of another MOSFET device provided by an embodiment of the present invention. Figure 49The cross-sectional diagram along the cutting line A is shown in Figure 2 As shown in a; Figure 49 The cross-sectional view along the cutting line B is shown in FIG. Figure 1 As shown in a; Figure 49 The cross-sectional view along the cutting line C is shown in FIG. Figure 24 As shown; Figure 49 The cross-sectional diagram along the cutting line D is shown in FIG. Figure 3 As shown in a, the length extension direction of the trench intersects with the length extension direction of the P-type buried layer 20.

[0173] In general, the structure of the MOSFET device provided in the embodiment of the present invention has a variety of designs and is not limited to a specific structure. It can be determined according to actual needs and is not limited in the embodiment of the present invention.

[0174] In an optional embodiment of the present invention, reference Figure 50 , Figure 50 A schematic top view of another MOSFET device provided by an embodiment of the present invention. The MOSFET device further includes: a P-type layer 24; one side of the P-type layer 24 is located at the bottom of the channel, and the other side extends toward the side where the substrate 11 is provided and at least penetrates the P-type buried layer 20.

[0175] Specifically, in the embodiment of the present invention, a P-type layer 24 is provided, and a super junction structure is formed based on the P-type layer 24 plus the P-type source 18 on the left and right sides and the N-type current diffusion region 21 between the P-type layer 24 and the P-type source 18, thereby improving the working performance of the MOSFET device.

[0176] Based on the above embodiments of the present invention, another embodiment of the present invention further provides a layout structure of a MOSFET device, wherein the layout structure of the MOSFET device includes: a plurality of MOSFET cells; the cross-sectional shapes of the MOSFET cells at different positions are different.

[0177] Specifically, in the embodiments of the present invention, refer to Figure 51 , Figure 51 A schematic diagram of different cross-sectional shapes of a MOSFET cell at different positions provided by an embodiment of the present invention. By adjusting the distribution position and proportion of different types of cross-sections in the layout structure of the MOSFET device, such as Figure 51 As shown, the current flow path and heat generation location of the MOSFET device can be dispersed when the device is working, avoiding excessive heat concentration and causing the device to burn out prematurely.

[0178] refer to Figure 52 , Figure 52 A schematic top view of a layout structure of a MOSFET device provided by an embodiment of the present invention, with reference to Figure 53 , Figure 53 A schematic top view of another MOSFET device layout structure provided by an embodiment of the present invention, referring to Figure 54 , Figure 54 A schematic top view of another layout structure of a MOSFET device provided in an embodiment of the present invention, referring to Figure 55 , Figure 55 A schematic top view of another layout structure of a MOSFET device provided in an embodiment of the present invention, referring to Figure 56 , Figure 56 A schematic top view of another layout structure of a MOSFET device provided in an embodiment of the present invention, referring to Figure 57 , Figure 57 A schematic top view of another layout structure of a MOSFET device provided in an embodiment of the present invention, referring to Figure 58 , Figure 58 A schematic top view of another layout structure of a MOSFET device provided in an embodiment of the present invention, referring to Figure 59 , Figure 59 A top view schematically illustrating a layout structure of another MOSFET device provided in an embodiment of the present invention. Figures 52-59 The cross-sectional view along the cutting line A is shown in 2a. Figures 52-59 The cross-sectional view along the cutting line B is shown in FIG. Figure 1 As shown in a; Figures 52-59 The cross-sectional view along the cutting line C is shown in FIG. Figure 24 As shown; Figures 52-59 The cross-sectional diagram along the cutting line D is shown in FIG. Figure 3 As shown in a; Figure 54 、 Figure 55 、 Figure 56 、 Figure 57 and Figure 59 The cross-sectional view along the cutting line E is shown in FIG. Figure 60 As shown, Figure 60 An embodiment of the present invention provides a Figure 54 、 Figure 55 、 Figure 56 、 Figure 57 and Figure 59 A schematic cross-sectional view along the cutting line D; Figure 53 、 Figure 55 and Figure 57 The cross-sectional view along the cutting line F is shown in FIG. Figure 61 As shown, Figure 61 An embodiment of the present invention provides a Figure 53 、 Figure 55 and Figure 57A schematic cross-section along cutting line F. The MOSFET cell is a hexagonal cell. By adjusting the distribution and proportion of different cross-section types in the MOSFET device layout, the current flow path and heat generation location during MOSFET device operation can be dispersed, preventing excessive heat concentration from causing premature device burnout.

[0179] refer to Figure 62 , Figure 62 A schematic top view of another layout structure of a MOSFET device provided in an embodiment of the present invention, referring to Figure 63 , Figure 63 A schematic top view of another layout structure of a MOSFET device provided in an embodiment of the present invention, referring to Figure 64 , Figure 64 A schematic top view of another layout structure of a MOSFET device provided in an embodiment of the present invention, referring to Figure 65 , Figure 65 A top view schematically illustrating a layout structure of another MOSFET device provided in an embodiment of the present invention. Figures 62-65 The cross-sectional view along the cutting line A is shown in 2a. Figures 62-65 The cross-sectional view along the cutting line B is shown in FIG. Figure 1 As shown in a; Figures 62-65 The cross-sectional view along the cutting line C is shown in FIG. Figure 24 As shown; Figure 63 and Figure 65 The cross-sectional diagram along the cutting line F is shown in FIG. Figure 61 The MOSFET cell is a square cell. By adjusting the distribution and proportion of different types of cross-sections in the MOSFET device layout structure, the current flow path and heat generation location during MOSFET device operation can be dispersed, preventing excessive heat concentration from causing premature device burnout.

[0180] Based on the above embodiment of the present invention, another embodiment of the present invention further provides a method for manufacturing a MOSFET device, referring to Figure 66 , Figure 66 A schematic flow chart of a method for manufacturing a MOSFET device according to an embodiment of the present invention. The method for manufacturing a MOSFET device according to an embodiment of the present invention includes:

[0181] S101: Provide a substrate 11.

[0182] S102 : forming an N-type voltage-resistant layer 12 on one side of the substrate 11 .

[0183] S103 : forming a P-type well region 14 , a source region and a P-type buried layer 20 in the N-type voltage-resistant layer 12 .

[0184] S104: forming a trench gate; the trench gate includes a trench and a gate 15 located in the trench, with a gate dielectric layer 16 between the gate 15 and the trench; the source region includes an N-type source region 17 and a P-type source region 18; the N-type source region 17 is located on the side of the P-type well region 14 away from the substrate 11, and the P-type source region 18 is located on both sides of the trench, and the trench passes through the N-type source region 17 and the P-type well region 14; the P-type buried layer 20 is located between the bottom of the trench and the substrate 11; and there is a gap between the P-type buried layer 20 and the bottom of the channel.

[0185] S105: forming a source 19 and a drain 13; the drain 13 is located on the side of the substrate 11 away from the N-type voltage-resistant layer 12, the source 19 contacts the N-type source region 17 and the P-type source region 18, and the P-type buried layer 20 is electrically connected to the source.

[0186] Specifically, in the embodiment of the present invention, functional film layers such as the P-type buried layer 20 are formed first, and then the trench gate is formed, so that the width of the trench and the width of the P-type buried layer 20 are decoupled from each other. This can not only further reduce the width of the trench and the cell size of the MOSFET device to improve the conduction performance of the MOSFET device, but also make the MOSFET device have better process compatibility.

[0187] For example, assuming the trench width is 1 μm, if ion implantation is performed in the trench, the width of the implanted P-type buried layer 20 cannot exceed 1 μm. However, if the implantation is performed on a flat surface before trench etching, the trench width does not need to be considered. The trench width does not affect the width of the P-type buried layer 20. In other words, the width of the P-type buried layer 20 and the trench width are not coupled to each other and can be freely designed.

[0188] Conversely, if a MOSFET device design requires a P-type buried layer 20 with a width of at least 2 μm, then if a trench is formed first and then the P-type buried layer 20 is formed, the trench width must be at least 2 μm. However, using the fabrication method of this technical solution, the trench width can be reduced to only 1 μm, thus reducing the size of the MOSFET device cell based on the width of this technical solution by at least 1 μm. This allows more MOSFET device cells (or more conduction units) to fit on a chip of the same area, resulting in better conduction performance.

[0189] The above is a detailed introduction to a MOSFET device provided by the present invention, its manufacturing method, and its layout structure. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

[0190] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0191] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that the process, method, article, or apparatus comprising a series of elements inherent to the elements, or also including elements inherent to these processes, methods, articles, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0192] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A MOSFET device, characterized in that: The MOSFET device comprises: substrate; An N-type voltage-resistant layer located on one side of the substrate; a drain located on a side of the substrate away from the N-type voltage-resistant layer; A P-type well region, a source region, and a trench gate are provided on a surface of the N-type voltage-resistant layer facing away from the substrate; the trench gate comprises a trench and a gate located in the trench, with a gate dielectric layer between the gate and the trench; The source region includes an N-type source region and a P-type source region; the N-type source region is located on a side of the P-type well region away from the substrate, the P-type source region is located on both sides of the trench, and the trench runs through the N-type source region and the P-type well region; a source electrode in contact with the N-type source region and the P-type source region; a P-type buried layer located in the N-type voltage-resistant layer and between the bottom of the trench and the substrate; the P-type buried layer is electrically connected to the source, and a gap is formed between the P-type buried layer and the bottom of the trench; The P-type source region contacts the sidewall of the trench and the P-type buried layer.

2. The MOSFET device according to claim 1, wherein The width of the P-type buried layer is equal to the width of the trench; Or, the width of the P-type buried layer is smaller than the width of the trench; Alternatively, the width of the P-type buried layer is greater than the width of the trench.

3. The MOSFET device according to claim 1, wherein In a direction parallel to the plane where the substrate is located, there is a gap between the geometric center of the P-type buried layer and the geometric center of the bottom of the trench.

4. The MOSFET device according to claim 1, wherein The MOSFET device further includes: a P-type ground layer; The P-type ground layer is in contact with the P-type buried layer and the P-type source region respectively.

5. The MOSFET device according to claim 1, wherein The MOSFET device further comprises: An N-type current diffusion region is located between the P-type well region and the P-type buried layer, wherein the N-type current diffusion region has the same doping type as the N-type voltage-withstanding layer, and the doping concentration of the N-type current diffusion region is greater than or equal to the doping concentration of the N-type voltage-withstanding layer.

6. The MOSFET device according to claim 5, characterized in that The N-type current diffusion region at least partially wraps the P-type buried layer.

7. The MOSFET device according to claim 5, wherein: The MOSFET device further comprises: a P-type ground layer; the P-type ground layer is in contact with the P-type buried layer and the P-type source region respectively; The N-type current diffusion region is located at least between one of the sidewalls of the trench and the P-type source region.

8. The MOSFET device according to claim 5, wherein: The MOSFET device further includes: a P-type ground layer; The P-type ground layer is in contact with the P-type buried layer and the P-type source region respectively; The N-type current diffusion region is located on a side of the P-type ground layer facing away from the substrate.

9. The MOSFET device according to claim 1, wherein: A surface of the P-type source region facing away from the substrate and a surface of the N-type source region facing away from the substrate are located in the same plane.

10. The MOSFET device according to claim 1, wherein: The surface of the P-type source region facing away from the substrate is located between the first surface and the second surface; The first surface is the surface of the N-type source region facing away from the substrate, and the second surface is the surface of the P-type well region facing the substrate.

11. The MOSFET device according to claim 1, wherein: The distance between the surface of the P-type source region facing away from the substrate and the substrate is smaller than the distance between the surface of the P-type well region facing the substrate and the substrate; The source electrode forms a Schottky contact with the sidewall of the exposed N-type current diffusion region.

12. The MOSFET device according to claim 1, wherein: The P-type source region includes at least two sub-P-type source regions arranged in sequence along the length extension direction of the trench, and / or the P-type buried layer includes at least two sub-P-type buried layers arranged in sequence along the length extension direction of the trench.

13. The MOSFET device according to claim 12, wherein: The shape of the sub-P-type source region is a square, a triangle, a polygon or a circle; the shape of the sub-P-type buried layer is a square, a triangle, a polygon or a circle.

14. The MOSFET device according to claim 12, wherein: The MOSFET device further includes: a P-type ground layer; The sub-P-type buried layer is connected to at least one of the sub-P-type source regions via the P-type grounding layer.

15. The MOSFET device according to claim 14, wherein: The P-type ground layers located on both sides of the trench are arranged alternately or symmetrically.

16. The MOSFET device according to claim 14, wherein: In the P-type ground layers located on both sides of the trench, at least one sub-P-type source region is spaced between two adjacent P-type ground layers in the length extension direction of the trench.

17. The MOSFET device according to claim 14, wherein: A length extension direction of the P-type ground layer intersects with a length extension direction of the trench.

18. The MOSFET device according to claim 1, wherein: In the longitudinal extension direction of the trench, the N-type source regions and the P-type source regions are alternately arranged in sequence; Alternatively, the orthographic projection of the N-type source region on the substrate surrounds the orthographic projection of the P-type source region on the substrate.

19. The MOSFET device according to claim 1, wherein: When the P-type source region includes at least two sub-P-type source regions that are sequentially spaced apart in the length extension direction of the trench, at least one of the sub-P-type source regions is in contact with the sidewall of the trench and the P-type buried layer.

20. The MOSFET device according to claim 1, wherein A length extension direction of the trench intersects with a length extension direction of the P-type buried layer.

21. The MOSFET device according to any one of claims 1 to 20, characterized in that: The MOSFET device further includes: a P-type layer; One side of the P-type layer is located at the bottom of the trench, and the other side extends toward the side where the substrate is provided and at least penetrates the P-type buried layer.

22. A method for manufacturing a MOSFET device, characterized in that: Used to prepare the MOSFET device according to any one of claims 1 to 21, the manufacturing method of the MOSFET device comprising: providing a substrate; forming an N-type voltage-resistant layer on one side of the substrate; forming a P-type well region, a source region, and a P-type buried layer in the N-type voltage-resistant layer; A trench gate is formed; the trench gate includes a trench and a gate located in the trench, with a gate dielectric layer between the gate and the trench; the source region includes an N-type source region and a P-type source region; the N-type source region is located on a side of the P-type well region facing away from the substrate, the P-type source region is located on both sides of the trench, and the trench penetrates the N-type source region and the P-type well region; the P-type buried layer is located between the bottom of the trench and the substrate; and a gap is formed between the P-type buried layer and the bottom of the trench; A source and a drain are formed; the drain is located on a side of the substrate away from the N-type voltage-resistant layer, the source is in contact with the N-type source region and the P-type source region, and the P-type buried layer is electrically connected to the source.

23. A layout structure of a MOSFET device, characterized in that: The MOSFET device is the MOSFET device according to any one of claims 1 to 21, and the layout structure of the MOSFET device comprises: a plurality of MOSFET cells; The cross-sectional shapes of the MOSFET cell are different at different positions.

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