Device structure, forming method thereof and device layout

Abstract

Gate layouts and / or devices that implement gate support structures (e.g., gate strips) in non-active regions (e.g., isolation regions) and methods of making the same are described herein. Exemplary gate support structures are connected to at least two gates (e.g., in some embodiments, two to six) disposed in the non-active region. The at least two gates extend longitudinally in a first direction, and the gate support structure extends longitudinally in a second direction different from the first direction. A gate support structure and at least two gates may be disposed on a substrate isolation structure, such as a shallow trench isolation (STI) structure. A composition and / or configuration of the gate support structure may be the same as or different from a composition and / or configuration of the at least two gates. The embodiment of the invention also relates to a device structure, a forming method thereof and a device layout.

Description

Technical Field

[0001] Embodiments of the present application relate to a device structure and a method for forming the same, as well as a device layout. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a device structure, comprising: forming an active region in a device region, wherein the active region extends longitudinally along a first direction and extends laterally along a second direction; forming an isolation structure in the device region and an isolation region, wherein the isolation structure in the device region is adjacent to the active region; and forming a first gate above the isolation structure in the active region and the device region, forming a second gate above the isolation structure in the isolation region, and forming a third gate above the isolation structure in the isolation region, wherein the first gate and the second gate extend longitudinally along the second direction, the third gate extends longitudinally along the first direction, and the third gate is connected to at least two of the second gates.

[0004] Other embodiments of the present application provide a device structure, including: a first gate, extending longitudinally along a first direction in a device region, wherein the first gate is arranged above an isolation structure and an active region, the first gate has a first height above the isolation structure, the first gate has a second height above the active region, and the first height is greater than the second height; a second gate, extending longitudinally along the first direction in the isolation region, wherein the second gate is arranged above the isolation structure, the second gate has a third height above the isolation structure, and the third height is greater than the second height; and a gate support bar, extending longitudinally along a second direction in the isolation region, wherein the second direction is different from the first direction, the gate support bar is arranged above the isolation structure, and the gate support bar is connected to at least two of the second gates.

[0005] Some further embodiments of the present application provide a device layout, including: a first active gate line, a second active gate line, a first dummy gate line, and a second dummy gate line, which are longitudinally oriented along a first direction; a dummy gate support bar, which is longitudinally oriented along a second direction different from the first direction, wherein the dummy gate support bar extends from the first dummy gate line to the second dummy gate line along the second direction; and an active area, which is longitudinally oriented along the second direction, wherein the first active gate line and the second active gate line are arranged above the active area. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a flowchart of part or all of a method for manufacturing a device having a gate support structure according to various aspects of an embodiment of the present disclosure.

[0008] FIG. 2A to FIG. 8A The device (eg, a gate-all-around transistor or a fin field effect transistor) according to various aspects of the embodiments of the present disclosure is manufactured at various stages (such as with Figure 1 A top view of part or all of the method (those related to the method).

[0009] Figures 2B to 8B The devices according to various aspects of the embodiments of the present disclosure are respectively along FIG. 2A to FIG. 8A A cross-sectional view of part or all of line BB.

[0010] Figures 2C to 8C The devices according to various aspects of the embodiments of the present disclosure are respectively along FIG. 2A to FIG. 8A A cross-sectional view of part or all of line CC.

[0011] Figures 2D to 8D The devices according to various aspects of the embodiments of the present disclosure are respectively along FIG. 2A to FIG. 8A A cross-sectional view of part or all of line DD.

[0012] Figures 3E to 8E The devices according to various aspects of the embodiments of the present disclosure are respectively along FIG. 3A to FIG. 8A A cross-sectional view of part or all of line EE.

[0013] Figures 3F to 8F The devices according to various aspects of the embodiments of the present disclosure are respectively along FIG. 3A to FIG. 8A A cross-sectional view of part or all of line FF.

[0014] Figure 7G to Figure 8G The devices according to various aspects of the embodiments of the present disclosure are respectively along 7A to 8A A cross-sectional view of part or all of line GG.

[0015] Figures 9 to 12 According to various aspects of the embodiments of the present disclosure FIG. 2A to FIG. 8A The device is experiencing FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3D Different top views of part or all of the image after relevant processing.

[0016] Fig.13A Top views and cross-sectional views of part or all of a device without a gate support structure according to various aspects of the embodiments of the present disclosure are provided.

[0017] Fig. 13B Top views and cross-sectional views of part or all of a device having a gate support structure according to various aspects of the embodiments of the present disclosure are provided.

[0018] FIG. 14A to FIG. 14C A device having a gate support structure configured and arranged according to design rules according to various aspects of the embodiments of the present disclosure (which can be configured according to Figure 1 Method to manufacture) some or all of the various views.

[0019] Fig.15 is a flowchart of part or all of a method for manufacturing a device having a gate support structure according to various aspects of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The disclosed embodiments generally relate to gate layouts for devices, such as gate layouts for gate-all-around (GAA) transistors, and the resulting devices.

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the disclosed embodiments. The specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted and formed, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be directly contacted. In addition, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "under", "upward", "downward", "top", "bottom" and their derivatives (e.g., "horizontally", "downward", "upward", etc.) are used to facilitate understanding of the relationship between one component and another component of the disclosed embodiments. Spatial relative terms are intended to cover different orientations of devices including components. In addition, when describing a numerical value or a numerical range with "about", "approximately", etc., as understood by those of ordinary skill in the art, the term is intended to cover a numerical value within a reasonable range taking into account the changes inherent in the manufacturing period. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the numerical values, the numerical values ​​or ranges of numerical values ​​encompass a reasonable range including the described numerical values, such as within + / - 10% of the described numerical values. For example, a material layer having a thickness of "about 5nm" may include a size range from 4.5nm to 5.5nm, where the manufacturing tolerance associated with the deposited material layer known to those of ordinary skill in the art is + / - 10%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] This article describes a gate layout and / or device and a method for manufacturing the same that implements a gate support structure (e.g., a gate strip) to reduce stripping, collapse, bending, etc. of a gate in a non-active region (e.g., an isolation region). An exemplary gate support structure is connected to at least two gates (e.g., in some embodiments, two to six) disposed in a non-active region. At least two gates extend longitudinally in a first direction, and the gate support structure extends longitudinally in a second direction different from the first direction. The gate support structure and at least two gates may be disposed on a substrate isolation structure (such as a shallow trench isolation (STI) structure). The gate support structure may be formed simultaneously with at least two gates. The composition and / or configuration of the gate support structure may be the same or different from the composition and / or configuration of at least two gates. In some embodiments, the gate support structure and at least two gates may be polysilicon strips and polysilicon gates, respectively. In some embodiments, the gate support structure and at least two gates each include a gate dielectric and a gate electrode. In some embodiments, the gate support structure and at least two gates are formed simultaneously with the gate (i.e., active gate) of the transistor. The active gate may extend longitudinally in the first direction. In some embodiments, the gate support structure and at least two gates are formed at a different time than the active gates. The size of the gate support structure and / or the spacing between the gate support structure and other structures (e.g., source / drain contacts, gate isolation structures, etc.) can be configured to minimize the risk of electrical shorts and / or minimize residual defects.

[0023] Figure 11 is a flowchart of part or all of a method 100 for manufacturing a device with a gate support structure according to various aspects of an embodiment of the present disclosure. In box 105, the method 100 includes forming a first gate extending longitudinally in a first direction above an active area region. The active area region includes an active area, and the active area may include and / or be processed to have a channel structure and a source / drain, wherein the channel structure is disposed between the corresponding source / drain. The first gate may be disposed on the channel structure. In some embodiments, the active area region is a device region. In box 110, the method 100 includes forming a second gate extending longitudinally in a first direction above a non-active area region. The non-active area region has no active area, and the non-active area region may include and / or be processed to have an isolation structure, such as a substrate isolation structure. The second gate may be disposed on the isolation structure. In some embodiments, the isolation structure is also located in the active area region, the isolation structure may define and / or surround the active area, and the first gate may be disposed on the isolation structure. In some embodiments, the non-active area region is an isolation region. In frame 115, method 100 includes forming a gate support bar extending longitudinally in a second direction above the non-active region. The second direction is different from the first direction, and the gate support bar is connected to at least two second gates. The gate support bar can be arranged on the isolation structure. In some embodiments, the active region extends longitudinally in the second direction. In some embodiments, the gate support bar is a third gate. In some embodiments, the first gate, the second gate, and the third gate are formed simultaneously. The disclosed embodiments contemplate additional processing. Additional steps may be provided before, during, and after method 100, and for additional embodiments of method 100, some of the steps described may be moved, replaced, or eliminated. The following discussion shows various embodiments of devices that can be manufactured according to method 100.

[0024] FIG. 2A to FIG. 8A The device 200 according to various aspects of the embodiments of the present disclosure is in various manufacturing stages (such as Figure 1 Top views of portions or all of those related to method 100). Figures 2B to 8B The device 200 according to various aspects of the embodiments of the present disclosure is respectively along FIG. 2A to FIG. 8A A cross-sectional view (e.g., y-cut) of part or all of line BB. Figures 2C to 8C The device 200 according to various aspects of the embodiments of the present disclosure is respectively along FIG. 2A to FIG. 8A A cross-sectional view (e.g., x-cut) of part or all of line CC. Figures 2D to 8D The device 200 according to various aspects of the embodiments of the present disclosure is respectively along FIG. 2A to FIG. 8A A cross-sectional view (eg, x-cut) of line DD. Figures 3E to 8E The device 200 according to various aspects of the embodiments of the present disclosure is respectively along FIG. 3A to FIG. 8AA cross-sectional view of part or all of line EE (e.g., y-cut). Figures 3F to 8F The device 200 according to various aspects of the embodiments of the present disclosure is respectively along FIG. 3A to FIG. 8A A cross-sectional view (e.g., x-cut) of part or all of line FF. Figure 7G to Figure 8G The device 200 according to various aspects of the embodiments of the present disclosure is respectively along 7A to 8A A cross-sectional view (e.g., x-cut) of part or all of line GG. Figures 9 to 12 The device 200 according to various aspects of the embodiments of the present disclosure undergoes FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3D Different top views of part or all of the image after relevant processing. Fig.13A Top views and cross-sectional views of part or all of a device 200 without a gate support structure are provided according to various aspects of embodiments of the present disclosure. Fig. 13B Top views and cross-sectional views of a portion or all of a device 200 having a gate support structure according to various aspects of the present disclosure are provided. FIG. 2A to FIG. 8A , Figures 2B to 8B , Figures 2C to 8C , Figures 2D to 8D , Figures 3E to 8E , Figures 3F to 8F , Figures 7G to 8G , Figures 9 to 12 , Fig.13A and Fig. 13B , for ease of description and understanding, and for clarity, has been simplified to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the device 200.

[0025] The device 200 may include a device region 202A, a device region 202B, and an isolation region 204 between the device region 202A and the device region 202B. As described herein, the device 200 may be processed to form transistors, such as GAA transistors, in the device region 202A and the device region 202B. In some embodiments, the device region 202A is processed to form an n-type GAA transistor therein, and the device region 202B is processed to form a p-type GAA transistor therein, or vice versa. In some embodiments, the device region 202A and / or the device region 202B are processed to form an n-type GAA transistor and a p-type GAA transistor therein. In such an embodiment, the device region 202A and the device region 202B may include complementary metal oxide semiconductor (CMOS) transistors. The isolation region 204 is configured to electrically isolate the device region 202A and the device region 202B. For example, the isolation region 204 may electrically isolate the transistors of the device region 202A from the transistors of the device region 202B.

[0026] refer to FIG. 2A to FIG. 2D , a fin manufacturing process may be implemented to form fins extending from a substrate (wafer) 206, such as fins 208A and fins 208B (also referred to as fin structures, fin elements, etc.) extending from the substrate 206. The fin 208A is disposed in the device region 202A, and the fin 208B is disposed in the device region 202B. The fin 208A and the fin 208B extend substantially parallel to each other along the x-direction, having a length in the x-direction, a width in the y-direction, and a height in the z-direction. For example, the fin 208A has a width W1, and the fin 208B has a width W2. In the depicted embodiment, the fin 208A and the fin 208B have the same width (i.e., the width W1 is the same as the width W2), and the fin 208A is aligned with the middle of the fin 208B along the x-direction. Therefore, the fin 208A and the fin 208B are aligned and / or overlap along the x-direction. In some embodiments, fin 208A and fin 208B have different widths (ie, width W1 is greater than or less than width W2), and fin 208A is aligned with the middle, top, or bottom of fin 208B along the x-direction. Fig. 9 , width W2 is less than width W1, some fins 208B are aligned with and / or overlap with fins 208A, and some fins 208B are not aligned with and do not overlap with fins 208A. Fig. 9 In the embodiment, the topmost fin 208B and the bottommost fin 208B are not aligned with and do not overlap the corresponding fin 208A, one of the middle fins 208B is aligned with the middle of the corresponding fin 208A and overlaps the corresponding fin 208A, and one of the middle fins 208B is aligned with the top of the corresponding fin 208A and overlaps the corresponding fin 208A. In some embodiments, one or more of the fins 208B may overlap the corresponding fin 208A without being aligned with the middle, top, or bottom thereof. Various alignment and / or width configurations of the fins 208A and fins 208B are contemplated by the disclosed embodiments.

[0027] Reference again FIG. 2A to FIG. 2D, each of the fins 208A and fins 208B includes a substrate portion and a semiconductor layer stack portion disposed above the substrate portion. The substrate portion includes a mesa 206' (also referred to as a substrate extension portion, a fin portion of the substrate 206, a substrate fin portion, an etched substrate portion, etc.). In the depicted embodiment, the substrate 206 includes silicon. The substrate 206 may alternatively or additionally include: another element semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination thereof. In some embodiments, the substrate 206 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. The substrate 206 (including the mesa 206') may include various doped regions, such as a p-well and an n-well. The n-well is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The p-well is doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, the substrate 206 includes doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions can be formed directly on and / or in the substrate 206, for example, to provide a p-well structure, an n-well structure, a dual-well structure, a raised structure, or a combination thereof. An ion implantation process, a diffusion process, and / or other suitable doping processes can be performed to form the various doped regions.

[0028] The semiconductor layer stack portion includes a semiconductor layer stack 210 having a semiconductor layer 215 and a semiconductor layer 220. Each semiconductor layer stack 210 is disposed above a corresponding mesa 206' of a substrate 206 and includes a corresponding semiconductor layer 215 and a corresponding semiconductor layer 220. The semiconductor layer 215 and the semiconductor layer 220 are vertically stacked (e.g., along the z direction) in a staggered or alternating configuration from the top surface of the substrate 206. The composition of the semiconductor layer 215 and the composition of the semiconductor layer 220 are different to achieve etching selectivity and / or different oxidation rates during processing. For example, the semiconductor layer 215 and the semiconductor layer 220 include different materials, composition atomic percentages, composition weight percentages, thicknesses, other characteristics, or combinations thereof to achieve desired etching selectivity. In the depicted embodiment, the semiconductor layer 220 includes silicon and the semiconductor layer 215 includes silicon germanium. With such a composition, the semiconductor layer 215 can have a first etching rate to the etchant, and the semiconductor layer 220 can have a second etching rate to the etchant, wherein the first etching rate and the second etching rate are different. In some embodiments, semiconductor layer 220 includes silicon germanium having a different atomic percentage of germanium than the atomic percentage of germanium of semiconductor layer 215. In some embodiments, semiconductor layer 215 and / or semiconductor layer 220 include n-type dopants and / or p-type dopants. The disclosed embodiments contemplate semiconductor layer 215 and semiconductor layer 220 having any combination of semiconductor materials that provide a desired etch selectivity and / or desired performance characteristics (e.g., a material that maximizes current flow).

[0029] As described further below, semiconductor layer 220 or a portion thereof forms a channel region of a transistor in device 200. FIG. 2A to FIG. 2D , each semiconductor layer stack 210 includes four semiconductor layers 215 and four semiconductor layers 220. Therefore, the semiconductor layer stack 210 includes four semiconductor layer pairs disposed above the substrate 206, each of the semiconductor layer pairs having a corresponding semiconductor layer 215 and a corresponding semiconductor layer 220. After processing, this configuration can produce a transistor with four channels of the device 200. In some embodiments, the semiconductor layer stack 210 includes more or fewer semiconductor layers, depending on, for example, the number of channels and / or design requirements desired for the transistor of the device 200. For example, the semiconductor layer stack 210 may include two to ten semiconductor layers 220. The thickness of the semiconductor layer 215 and the semiconductor layer 220 may be selected based on manufacturing and / or device performance considerations. For example, the thickness of the semiconductor layer 215 is configured to provide a desired distance (or spacing) between adjacent channels (e.g., between the semiconductor layers 220), and the thickness of the semiconductor layer 220 is configured to provide a desired channel thickness.

[0030] The fabrication of the fins 208A and fins 208B may include: forming a semiconductor layer stack precursor over the substrate 206; and performing a photolithography process and / or an etching process to pattern the semiconductor layer stack precursor and / or the substrate 206. In some embodiments, forming the semiconductor layer stack precursor includes epitaxially growing semiconductor layers 215 and semiconductor layers 220 in a staggered and alternating configuration over the substrate 206. For example, a first of the semiconductor layers 215 is epitaxially grown on the substrate 206, a first of the semiconductor layers 220 is epitaxially grown on the first of the semiconductor layers 215, a second of the semiconductor layers 215 is epitaxially grown on the first of the semiconductor layers 220, and so on, until a desired number of semiconductor layers 215 and semiconductor layers 220 for the semiconductor layer stack 210 are provided. The epitaxial growth may be achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or combinations thereof.

[0031] The photolithography process may include: forming a resist layer (e.g., by spin coating) over a semiconductor layer stack precursor; performing a pre-exposure baking process; performing an exposure process using a mask; performing a post-exposure baking process; and performing a development process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), wherein the mask blocks, transmits, and / or reflects radiation to the resist layer, depending on the mask pattern and / or mask type (e.g., binary mask, phase shift mask, or EUV mask) of the mask, so that an image is projected onto the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiation energy, the exposed portion of the resist layer undergoes a chemical change, and the exposed (or unexposed) portion of the resist layer dissolves during the development process, depending on the characteristics of the resist layer and the characteristics of the developer used in the development process. After development, the patterned resist layer includes a resist pattern corresponding to the mask. The etching process uses the patterned resist layer as an etching mask to remove portions of the semiconductor layer stack precursor and / or substrate 206. In some embodiments, the patterned resist layer is formed above a mask layer disposed above the semiconductor layer stack precursor, a first etching process removes portions of the mask layer to form a patterned layer (e.g., a patterned hard mask layer), and a second etching process uses the patterned layer as an etching mask to remove portions of the semiconductor layer stack precursor and / or substrate 206. The etching process is dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process is a reactive ion etching (RIE) process. After etching, the patterned resist layer can be removed, for example, by a resist stripping process or other suitable processes.

[0032] In some embodiments, the fin 208A and the fin 208B are formed by a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer is a dielectric (SID) process, other double patterning processes, or a combination thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof. Such a process may also provide each of the fin 208A and the fin 208B with a corresponding semiconductor layer stack 210 over a corresponding mesa 206'. In some embodiments, a directed self-assembly (DSA) technique is implemented when patterning the semiconductor layer stack precursor. Furthermore, in some embodiments, the exposure process may implement maskless lithography, electron beam (e-beam) writing, ion beam writing, or a combination thereof for patterning the resist layer.

[0033] After forming the fins 208A and the fins 208B, a substrate isolation structure 225 may be formed over the substrate 206. The substrate isolation structure 225 may fill the lower portion of the trenches between the fins 208A, between the fins 208B, and between the fins 208A and the fins 208B. The substrate isolation structure 225 may surround portions of the fins 208A and the fins 208B, and portions of the fins 208A and the fins 208B that extend beyond the top surface of the substrate isolation structure 225 may be referred to as fin active regions. The substrate isolation structure 225 electrically isolates active device regions and / or passive device regions. For example, the substrate isolation structure 225 separates and electrically isolates the fins 208A, the fins 208B, and the fins 208A and the fins 208B (e.g., the fin 208A is isolated from the fin 208B by a corresponding one of the substrate isolation structures 225 that span the isolation region 204). The substrate isolation structure 225 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including, for example, silicon, oxygen, nitrogen, carbon, other suitable isolation components or combinations thereof) or combinations thereof. The substrate isolation structure 225 may have a multilayer structure. For example, the substrate isolation structure 225 may include a bulk dielectric (e.g., an oxide layer) located above a dielectric liner (e.g., silicon nitride, silicon oxide, silicon oxynitride, carbon oxynitride silicon or a combination thereof). In another example, the substrate isolation structure 225 may include a bulk dielectric located above a doped liner (such as a borosilicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner). The size and / or characteristics of the substrate isolation structure 225 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures or combinations thereof. For example, the substrate isolation structure 225 may be an STI.

[0034] Substrate isolation structure 225 may be formed by: depositing a liner layer (e.g., a dielectric layer) partially filling the trenches between the fins over device 200; depositing an oxide material filling the remaining portion of the trenches over device 200 (e.g., over the liner layer); and performing a planarization process. A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed until a planarization stop layer, such as top semiconductor layer 220, is reached and exposed. In some embodiments, the planarization process removes the mask layer, any liner layer, any oxide material, or a combination thereof, located on and / or above the top surfaces of fins 208A and fins 208B. The remaining portions of the liner layer and the oxide material form a liner and a bulk dielectric of substrate isolation structure 225, respectively. The liner may cover the sidewalls of the trench (formed by the sidewalls of the fins) and the bottom of the trench (formed by substrate 206). The liner layer may be formed by atomic layer deposition (ALD), CVD, physical vapor deposition (PVD), or a combination thereof. The oxide material may be formed by flowable CVD (FCVD), a high aspect ratio deposition (HARP) process, a high density plasma CVD (HDPCVD), or a combination thereof. In some embodiments, when the substrate isolation structure 225 is formed, an annealing process is performed.

[0035] Then, the substrate isolation structure 225 may be recessed and / or etched back so that the fins 208A and 208B protrude from the substrate isolation structure 225. FIG. 2A to FIG. 2D In the process, the substrate isolation structure 225 is etched back until it is below the semiconductor layer stack 210. In some embodiments, the height of the substrate isolation structure 225 is less than or equal to the height of the mesa 206' (e.g., relative to the top surface of the substrate 206). In some embodiments, the etching process selectively removes the substrate isolation structure 225 relative to the semiconductor layer stack 210. For example, the etching process etches / removes the substrate isolation structure 225 without negligible etching / removal of the semiconductor layer 220, the semiconductor layer 215, and the mesa 206'. An etchant for the etching process can be selected that etches the dielectric material at a higher rate than the semiconductor material. The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the etching process removes the mask / patterning layer of the fin 208A and / or the fin 208B. In some embodiments, the mask / patterning layer is used as an etching mask during the etching process.

[0036] refer to FIG. 3A to FIG. 3F, forming a dummy gate 230A over a portion of the fin 208A in the device region 202A, forming a dummy gate 230B over a portion of the fin 208B in the device region 202B, and forming a dummy gate 230C over the substrate isolation structure 225 in the isolation region 204. The dummy gates 230A-230C extend longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the fin 208A and the fin 208B. For example, the dummy gates 230A-230C extend substantially parallel to each other along the y-direction, having a length in the y-direction, a width in the x-direction, and a height in the z-direction. The dummy gate 230A may have a width W3, the dummy gate 230B may have a width W4, and the dummy gate 230C may have a width W5. Each of the widths W3, W4, and W5 may be less than the width of the active region (e.g., less than the width W1 of the fin 208A and / or the width W2 of the fin 208B). In the depicted embodiment, width W3, width W4, and width W5 are the same. In some embodiments, width W3, width W4, width W5, or a combination thereof are different. For example, width W5 can be different from (e.g., less than or greater than) width W3 and / or width W4 (i.e., the width of the dummy gate in the device region is different from the width of the dummy gate in the isolation region). In another example, width W3 is different from (e.g., less than or greater than) width W4 (i.e., different device regions have different dummy gate widths).

[0037] Along the fin transverse direction (see e.g. Figure 3B ), the dummy gate 230A is disposed on the top and sidewalls of the fin 208A, the dummy gate 230A wraps the channel region (C) of the fin 208A, and the dummy gate 230A is disposed above the top of the substrate isolation structure 225. In addition, the dummy gate 230B is disposed on the top and sidewalls of the fin 208B, the dummy gate 230B wraps the channel region of the fin 208B, and the dummy gate 230B is disposed above the top of the substrate isolation structure 225. Along the longitudinal direction of the fin (see, for example Figure 3C), the dummy gate 230A is disposed above the top of the corresponding channel region of the fin 208A, and the dummy gate 230A is disposed between the corresponding source / drain regions (S / D) of the fin 208A. In addition, the dummy gate 230B is disposed above the top of the corresponding channel region of the fin 208B, and the dummy gate 230B is disposed between the corresponding source / drain regions of the fin 208B. Because the dummy gates in the device region 202A and the device region 202B are formed above the fin and the substrate isolation structure, the dummy gates in the device region 202A and the device region 202B can have varying heights. For example, the dummy gate 230A and the dummy gate 230B can have a height h2 above the fin 208A and the fin 208B, respectively, and a height h1 above the substrate isolation structure 225. The height h1 is located between the top surface of the substrate isolation structure 225 and the top surfaces of the dummy gates 230A and 230B, and the height h2 is located between the top surfaces of the fins 208A and 208B and the top surfaces of the dummy gates 230A and 230B, and the height h2 is smaller than the height h1.

[0038] The dummy gate 230C is disposed on top of the substrate isolation structure 225 in the fin lateral direction and the fin longitudinal direction (see, for example, Figure 3D ). In order to prevent the peeling and / or collapse of the dummy gate 230C in the isolation region 204, a gate support structure is inserted in the isolation region 204 between the dummy gates 230C. For example, a dummy gate is formed above the substrate isolation structure 225 in the isolation region 204, and the dummy gate extends along the longitudinal direction of the fin (e.g., the x direction) to connect at least two dummy gates 230C. In the depicted embodiment, the dummy gate 230D extends longitudinally along the x direction and connects the two dummy gates 230C, so that the dummy gate 230D has a length in the x direction, a width in the y direction, and a height in the z direction. The dummy gate 230D may have a width W6, and the dummy gate 230D may have a height h1. In the depicted embodiment, the width W6 is the same as the width W4, the width W5, and the width W3. In some embodiments, the width W6 is different from the width W5, the width W4, the width W3, or a combination thereof. For example, in order to increase the structural support of the dummy gate 230C, the width W6 may be greater than the width W5.

[0039] In the depicted embodiment, the dummy gate 230D is not aligned with the active area of ​​the device area and does not overlap with the active area of ​​the device area. Therefore, the dummy gate 230D can be offset away from the active area along the y direction by a distance, such as a distance d1 between the dummy gate 230D and a corresponding fin along the y direction (e.g., the corresponding fin 208A and / or the corresponding fin 208B) and a distance d2 between the dummy gate 230D and another corresponding fin along the y direction (e.g., the corresponding fin 208A and / or the corresponding fin 208B). In some embodiments, the dummy gate 230D is aligned in the middle, top, or bottom with the fin 208A and / or the fin 208B along the x direction. For example, referring to Fig.10 , the dummy gate 230D may be aligned midway between the fin 208A and the fin 208B, such as where the fin 208A and the fin 208B are aligned midway and the dummy gate 230D has an overlap ov1 with the fin 208A and / or the fin 208B. Fig.10 In the embodiment where the width W6 is less than the width W1 and / or the width W2, the overlap ov1 is equal to the width W6. In the embodiment where the width W6 is greater than the width W1 and / or the width W2, the overlap ov1 is equal to the width W1 and / or the width W2. In another example, referring to Fig.11 , the dummy gate 230D may overlap the corresponding fin 208A and / or the corresponding fin 208B without being aligned in the middle, top, or bottom thereof. Fig.11 In the embodiment, the dummy gate 230D has an overlap ov2 with the fin 208A and / or the fin 208B, and the overlap ov2 is less than the width W6. In some embodiments, the dummy gate 230D is aligned in the middle, top, or bottom of the fin 208A, but not in the middle, top, or bottom of the fin 208B. In such an embodiment, the dummy gate 230D may overlap with the fin 208A, and the dummy gate 230D may or may not overlap with the fin 208B. Various alignment and / or width configurations of the dummy gate 230D are contemplated in the disclosed embodiments.

[0040] In some embodiments, more than one dummy gate 230D is connected to two dummy gates 230C. In some embodiments, the dummy gate 230D is connected to more than two dummy gates 230C, such as two to six dummy gates 230C. Fig.12 , five dummy gates 230C instead of two dummy gates 230C may extend longitudinally in the y direction in the isolation region 204, and the dummy gate 230D may extend longitudinally in the x direction to connect the five dummy gates 230C. In such an example, the dummy gate 230D may be formed by the dummy gate 230D-1, the dummy gate 230D-2, the dummy gate 230D-3, the dummy gate 230D-4, and the portion of the dummy gate 230C that is merged together by the dummy gates 230D-1–230D-4.

[0041] Each of 230D- 4 connects and / or merges two corresponding dummy gates 230C together, and each of the dummy gates 230D- 1 - 230D- 4 may be referred to as a dummy sub-gate.

[0042] The dummy gates 230A-230D may also be referred to as dummy gate stacks. In some embodiments, the dummy gates 230A-230D include a polysilicon layer, and the dummy gates 230A-230D may be referred to as polysilicon gates. The dummy gates 230A-230D may be formed of a single layer (e.g., a polysilicon layer) or multiple layers (such as a dummy gate dielectric, a dummy gate electrode, and a hard mask). The dummy gate dielectric includes a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. For example, the dummy gate dielectric is a silicon oxide layer (e.g., SiO 2 layer). The dummy gate electrode includes a suitable dummy gate material, such as polysilicon, and the hard mask includes a suitable hard mask material, such as silicon nitride. In some embodiments, the dummy gates 230A-230D are formed simultaneously. For example, the dummy gates 230A-230D may be formed by: depositing a dummy gate dielectric layer over the device 200; depositing a dummy gate electrode layer over the dummy gate dielectric layer; depositing a hard mask layer over the dummy gate electrode layer; and performing a photolithography process and an etching process to pattern the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer. The remaining portions of the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer form the dummy gates 230A-230D. In some embodiments, when the hard mask layer, the dummy gate electrode layer, the dummy gate dielectric layer, or a combination thereof are patterned, the substrate isolation structure 225 may be recessed, which may produce a substrate isolation structure 225 having an isolation mesa 225' extending therefrom (see, e.g. Fig.13A and Fig. 13B ), and the dummy gates 230A-230D may be disposed on the isolation mesa 225'. In some embodiments, the dummy gates in the device region (e.g., dummy gates 230A and dummy gates 230B) and the dummy gates in the isolation region (e.g., dummy gates 230C and dummy gates 230D) are formed at different times (i.e., by different processes). In some embodiments, the dummy gates 230C and dummy gates 230D are formed at different times. In some embodiments, the dummy gates 230A and dummy gates 230B are formed at different times. In some embodiments, the dummy gates 230A-230D are formed at least partially simultaneously (e.g., using the same deposition process and / or etching process, but different photolithography processes).

[0043] refer to 4A to 4F, the fabrication of the device 200 may include forming gate spacers 232 along sidewalls of the dummy gates 230A-230D, thereby forming gate structures 240A-240D. Each of the gate structures 240A has a corresponding dummy gate 230A and a gate spacer 232, each of the gate structures 240B has a corresponding dummy gate 230B and a gate spacer 232, each of the gate structures 240C has a corresponding dummy gate 230C and a gate spacer 232, and the gate structure 240D has a dummy gate 230D and a gate spacer 232. Before, simultaneously with, or after forming the gate spacers 232, fin spacers may be formed along sidewalls of the source / drain regions of the fin 208A and / or the fin 208B. The gate spacer 232 is disposed adjacent to the dummy gates 230A-230D, and the fin spacer may be disposed adjacent to the semiconductor layer stack 210 in the source / drain regions of the fins 208A and 208B before the semiconductor layer stack 210 is removed. The gate spacer 232 and the fin spacer are formed by any suitable process and include a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or combinations thereof). For example, a spacer layer including silicon and nitrogen (such as a silicon nitride layer) is deposited over the device 200 and etched to form the gate spacer 232 and the fin spacer. In some embodiments, the gate spacer 232 and / or the fin spacer have a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon carbide. In some embodiments, the gate spacers 232 and / or the fin spacers include more than one spacer group, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or a combination thereof. In such embodiments, the various spacer groups may have different compositions and / or sizes.

[0044] The manufacture of the device 200 may also include: partially removing portions of the fins 208A and fins 208B (e.g., their source / drain regions not covered by the dummy gates 230A and dummy gates 230B) to form source / drain recesses / grooves; forming internal spacers 234 below the gate spacers 232 along the sidewalls of the semiconductor layer 215; and forming source / drain 245 in the source / drain recesses. Forming the source / drain recesses may include performing an etching process that removes the semiconductor stack 210 in the source / drain regions of the fins 208A and fins 208B, thereby exposing their mesas 206'. The etching process may also remove some but not all of the mesas 206', so that the source / drain recesses may extend below the top surface of the substrate isolation structure 225. The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. In some embodiments, the parameters of the etching process (e.g., the etchant thereof) are configured to selectively remove the semiconductor material (i.e., the semiconductor stack 210) without to negligible removal of the dielectric material (e.g., the hard mask of the dummy gates 230A-230D, the gate spacers 232, the fin spacers, the substrate isolation structure 225, etc.). In some embodiments, the parameters of the etching process (e.g., the etchant thereof) are configured to selectively remove the semiconductor material (i.e., the semiconductor stack 210) without to negligible removal of the polysilicon (e.g., the dummy gates 230A-230D) and the dielectric material.

[0045] Forming the internal spacer 234 may include a first etching process, a deposition process, and a second etching process. The first etching process may selectively etch the semiconductor layer 215, while negligibly etching the semiconductor layer 220, the mesa 206', the substrate isolation structure 225, the dummy gate 230A-230D, the gate spacer 232, the fin spacer, or a combination thereof. The first etching process is configured to laterally etch (e.g., along the x-direction and / or y-direction) the semiconductor layer 215 to form a gap between the semiconductor layer 220 and to form a gap between the mesa 206' and the semiconductor layer 220. The first etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the first etching process is an anisotropic etching having a horizontal etching rate greater than a vertical etching rate (e.g., a vertical etching rate of zero), and the anisotropic etching may substantially remove material in the horizontal direction while having negligible material removal in the vertical direction.

[0046] The deposition process may form an insulating material that fills the gaps between the semiconductor layers 220 and the gaps between the mesas 206' and the semiconductor layer 220, and the second etching process selectively etches the insulating material to form the internal spacer 234, without or negligibly etching the semiconductor layer 220, the mesas 206', the substrate isolation structure 225, the pseudo gates 230A-230D, the gate spacers 232, the fin spacers, or a combination thereof. In order to achieve etching selectivity during the second etching process, the composition of the insulating material (and therefore the internal spacer 234) is different from the composition of the semiconductor layer 220, the mesas 206', the substrate isolation structure 225, the pseudo gates 230A-230D, the gate spacers 232, or a combination thereof. The insulating material includes a dielectric material that includes silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or a combination thereof. For example, the insulating material is silicon nitride, silicon carbonitride, silicon carbon nitride oxide, silicon carbon oxide, other suitable materials, or a combination thereof. The second etching process is dry etching, wet etching, other suitable etching or a combination thereof.

[0047] The source / drain 245 includes a semiconductor material, and the source / drain 245 may be doped with an n-type dopant and / or a p-type dopant. In some embodiments (e.g., when forming part of an n-type transistor), the source / drain 245 may include silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., Si:C source / drain, Si:P source / drain, or Si:C:P source / drain). In some embodiments (e.g., when forming part of a p-type transistor), the source / drain 245 may include silicon germanium or germanium doped with boron, other p-type dopants, or combinations thereof (e.g., Si:Ge:B source / drain). In some embodiments, the source / drain 245 has a multilayer structure, such as two or more semiconductor layers with different compositions and / or different sizes / configurations. Different compositions may be achieved by using different semiconductor materials, different dopants, different atomic percentages of components, different dopant concentrations, or combinations thereof. In some embodiments, the source / drain 245 includes materials and / or dopants that achieve desired tensile stress and / or compressive stress in the channel region (e.g., semiconductor layer 220) of a transistor formed in device region 202A and / or device region 202B. The source / drain 245 has the same or different composition and / or material, depending on the configuration of their corresponding transistors. In some embodiments, device region 202A and / or device region 202B includes some source / drain 245 configured for n-type transistors (e.g., Si:C source / drain) and some source / drain 245 configured for p-type transistors (e.g., Si:Ge:B source / drain).

[0048] The source / drain 245 may be formed by an epitaxial process, which may include epitaxially growing a semiconductor material from the exposed semiconductor layer 220 and / or the mesa 206'. The semiconductor material is formed in the source / drain groove and may fill the source / drain groove. The epitaxial process may use a CVD deposition technique (e.g., remote plasma CVD (RPCVD), low pressure CVD (LPCVD), vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD) or a combination thereof), MBE, other suitable epitaxial processes or a combination thereof. The epitaxial process may use a gaseous precursor and / or a liquid precursor, which may interact with and / or adsorb on the composition of the semiconductor layer 220 and / or the mesa 206', but not interact with the composition of the internal spacer 234, the gate spacer 232, the CESL 252, the ILD layer 254 or a combination thereof. In some embodiments, the source / drain 245 is doped (i.e., in-situ) during deposition, for example, by adding a dopant to the source material of the epitaxial process. In some embodiments, the source / drain 245 is doped after its deposition, for example, by an ion implantation process. In some embodiments, an annealing process (e.g., rapid thermal annealing and / or laser annealing) is performed to activate the dopant in the source / drain 245. In some embodiments, where the source / drain 245 is configured for different transistors and has different compositions and / or materials, the source / drain 245 can be formed by different processing orders. For example, when a source / drain 245 for an n-type transistor is formed in an n-type transistor region, the p-type transistor region can be masked, and when a source / drain 245 for a p-type transistor is formed in a p-type transistor region, the n-type transistor region can be masked.

[0049] The fabrication of the device 200 may also include forming a dielectric layer 250 over the device 200, such as over the substrate isolation structure 225 and the epitaxial source / drain 245. The dielectric layer 250 may fill the spaces between adjacent source / drain 245 and the spaces between adjacent gate structures 240A-240D. For example, the dielectric layer 250 may fill the spaces between the gate spacers 232 of adjacent gate structures 240A-240D. Forming the dielectric layer 250 may include: depositing a contact etch stop layer (CESL) 252; depositing an interlayer dielectric (ILD) layer 254 over the CESL 252; and performing CMP and / or other planarization processes until reaching (exposing) the dummy gates 230A-230D. The planarization process may remove portions of the dummy gates 230A-230D, such as their hard masks, to expose the dummy gate electrodes below them, such as their polysilicon gates. In such an embodiment, the height of the dummy gates 230A-230D may be reduced by the planarization process. The CESL 252 and the ILD layer 254 are formed by CVD, other suitable methods, or a combination thereof. In some embodiments, the ILD layer 254 is formed by FCVD, HARP, HDPCVD, or a combination thereof.

[0050] The ILD layer 254 includes a dielectric material including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from tetraethyl orthosilicate (TEOS), BSG, PSG, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, benzocyclobutene-based (BCB) dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer 254 includes a low-k dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k<3.9). In some embodiments, the ILD layer 254 includes a dielectric material having a dielectric constant less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as porous silicon dioxide, silicon carbide, a carbon-doped oxide (e.g., having, for example, Si-CH 3 The CESL 252 may include a material different from the ILD layer 254, such as a dielectric material different from the dielectric material of the ILD layer 254. For example, in the case where the ILD layer 254 includes a low-k dielectric material containing silicon and oxygen, the CESL 252 may include silicon and nitrogen, such as silicon nitride or silicon oxynitride.

[0051] Go to FIG. 5A to FIG. 5F and 6A to 6F, a gate replacement process is performed to replace the dummy gates 230A-230D with metal gates, and a channel release process is performed to form a suspended channel layer in the channel regions of the fins 208A and 208B. FIG. 5A to FIG. 5F , gate openings 260A-260D are formed by removing the dummy gates 230A-230D respectively. The gate opening 260A exposes the channel region of the fin 208A, and the gate opening 260B exposes the channel region of the fin 208B. The gate opening 260C and the gate opening 260D expose the substrate isolation structure 225, and the gate opening 260D connects at least two gate openings 260C. For example, in Figure 5D In the embodiment, gate opening 260C (formed by removing dummy gate 230C) and gate opening 260D (formed by removing dummy gate 230D) are combined to form gate opening 260E. The width of gate opening 260E (e.g., the sum of length l and (width W5×2)) is greater than the width of gate opening 260C (e.g., width W5). In some embodiments, gate openings 260A-260C are referred to as vertical gate openings (or trenches), and gate opening 260D and / or gate opening 260E are referred to as horizontal gate openings (or trenches), gate stripe openings, gate support structure openings, or combinations thereof.

[0052] In some embodiments, the etching process selectively removes the dummy gates 230A-230D relative to the semiconductor stack 210, the substrate isolation structure 225, the gate spacers 232, the ILD layer 254, the CESL 252, or a combination thereof. In other words, the etching process removes the dummy gates 230A-230D without to negligible removal of the semiconductor stack 210, the substrate isolation structure 225, the gate spacers 232, the ILD layer 254, the CESL 252, or a combination thereof. For example, an etchant is selected that removes polysilicon (e.g., the dummy gates 230A-230D and / or their dummy gate electrodes) at a higher rate than semiconductor materials (e.g., semiconductor layers 220, semiconductor layers 215, and mesas 206') and dielectric materials (e.g., substrate isolation structure 225, gate spacers 232, ILD layer 254, CESL 252, etc.) (i.e., the etchant has a high etch selectivity relative to polysilicon). The etching process is dry etching, wet etching, other suitable etching or a combination thereof. In some embodiments, the patterned mask layer covers the ILD layer 254, the CESL 252, the gate spacer 232 or a combination thereof, and has openings therein exposing the dummy gates 230A-230D.

[0053] A channel release process may be implemented after forming the gate openings 260A-260D to provide a suspended channel layer. For example, the semiconductor layer 215 exposed by the gate openings 260A and 260B may be selectively removed to form gaps between the semiconductor layers 220 and between the semiconductor layers 220 and the mesas 206', thereby suspending the semiconductor layer 220 above the mesas 206'. Thus, the gate openings 260A and 260B extend between the semiconductor layers 220 and between the semiconductor layers 220 and the mesas 206'. In the depicted embodiment, four semiconductor layers 220 are stacked vertically in the z-direction, and the four semiconductor layers 206 provide a channel through which current can flow between the corresponding source / drain 245. Thus, the semiconductor layer 220 may be referred to as a channel layer 220' (or a suspended semiconductor layer 220').

[0054] In some embodiments, the etching process selectively removes the semiconductor layer 215 without to negligible removal of the mesa 206', the semiconductor layer 220, the substrate isolation structure 225, the gate spacer 232, the internal spacer 234, the dielectric layer 250, or a combination thereof. For example, an etchant is selected that etches / removes silicon germanium (i.e., the semiconductor layer 215) at a higher rate than silicon (i.e., the semiconductor layer 220 and the mesa 206') and the dielectric material (i.e., the substrate isolation structure 225, the gate spacer 232, the internal spacer 234, the CESL 252, the ILD layer 254, or a combination thereof) (i.e., the etchant has a high etching selectivity relative to silicon germanium). The etching process is a dry etch, a wet etch, other suitable etching, or a combination thereof. In some embodiments, before the etching process is performed, an oxidation process converts the semiconductor layer 215 into an oxidized silicon germanium component, and the etching process removes the oxidized silicon germanium component. In some embodiments, the profile of the channel layer 220' can be modified to provide a target size and / or target shape thereof. For example, the etching process can provide a channel layer 220' having a cylindrical profile (e.g., a nanowire), a rectangular profile (e.g., a nanobar), a sheet profile (e.g., a nanosheet), or any other suitable shape profile. In some embodiments, the channel layer 220' has nanoscale dimensions and can be referred to individually or collectively as a "nanostructure". The disclosed embodiments contemplate a channel layer 220' having any suitable dimensions, including sub-nanometer dimensions and / or ultra-nanometer dimensions.

[0055] refer to 6A to 6F, gate stacks 270A-270D are formed in gate openings 260A-260D, respectively. Gate stack 270A fills the gap between gate opening 260A, channel layer 220' in gate opening 260A, and the gap between channel layer 220' and mesa 206' in gate opening 260A. Gate stack 270B fills the gap between gate opening 260B, channel layer 220' in gate opening 260B, and the gap between channel layer 220' and mesa 206' in gate opening 260B. Gate stack 270C fills gate opening 260C, and gate stack 270D fills gate opening 260D. Along the longitudinal direction of the active area (see, e.g. Figure 6C ), the gate stack 270A and the gate stack 270B are disposed between the corresponding gate spacers 232, between the corresponding internal spacers 234, between the corresponding channel layers 220', and between the corresponding channel layers 220' and the corresponding mesas 206'. Along the lateral direction of the active area (e.g., in the YZ plane), the gate stack 270A and the gate stack 270B can surround and / or wrap the corresponding channel layer 220' (e.g., nanowire). In addition, the gate stack 270C is disposed between the corresponding gate spacers 232 and above the corresponding substrate isolation structure 225 along the longitudinal direction of the active area (see, for example, Fig. 6F ), and the gate stack 270D is disposed between the corresponding gate spacers 232 and above the corresponding substrate isolation structure 225 along the lateral direction of the active region (see, for example, Fig. 6E ). In the gate support region, the gate stack 270C and the gate stack 270D may be combined to form a gate stack 270E, which includes at least two gate stacks 270C and at least one gate stack 270D. The gate stack 270D and / or the gate stack 270E may be referred to as a gate bar, a horizontal gate bar, a gate support structure, or a combination thereof.

[0056] After the gate replacement process, each gate structure 240A includes a corresponding gate stack 270A and a gate spacer 232, each gate structure 240B includes a corresponding gate stack 270B and a gate spacer 232, each gate structure 240C includes a corresponding gate stack 270C and a gate spacer 232, the gate structure 240D includes a corresponding gate stack 270D and a gate spacer 232, and the gate structure 240E includes a gate stack 270E and a gate spacer 232. The gate stack 270A includes a corresponding gate dielectric 272A and a corresponding gate electrode 274A, the gate stack 270B includes a corresponding gate dielectric 272B and a corresponding gate electrode 274B, the gate stack 270C includes a corresponding gate dielectric 272C and a corresponding gate electrode 274C, and the gate stack 270D includes a gate dielectric 272D and a gate electrode 274D.

[0057] The gate dielectrics 272A-272D ​​are disposed on the channel layer 220', the mesa 206', the substrate isolation structure 225, or a combination thereof. The composition and / or configuration of the gate dielectrics 272A, 272B, 272C, 272D, or a combination thereof may be the same or different. The gate dielectrics 272A-272D ​​each include at least one dielectric gate layer, such as an interface layer and / or a high-k dielectric layer. The interface layer includes a dielectric material, such as SiO 2 、SiGeO x , HfSiO, SiON, other dielectric materials or combinations thereof. The high-k dielectric layer includes a high-k dielectric material, which generally refers to a dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide (k≈3.9), such as HfO 2 、HfSiO、HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x 、ZrO、ZrO 2 、ZrSiO 2 、AlO、AlSiO、Al 2 O 3 、TiO、TiO 2 、LaO、LaSiO、LaO 3 ,La 2 O 3 、 2 O 3 、 2 O 5 , Y 2 O 3 、SrTiO 3 、BaZrO、BaTiO 3 (BTO), (Ba,Sr)TiO3 (BST), Si 3 N 4 , HfO 2 -Al 2 O 3 , other high-k dielectric materials, or combinations thereof. For example, the gate dielectrics 272A-272D ​​may each include a hafnium-based oxide (eg, HfO 2 ) layer and / or zirconium-based oxide (e.g., ZrO 2 In some embodiments, the interface layer and / or the high-k dielectric layer has a multi-layer structure.

[0058] The gate electrodes 274A-274D are disposed above the gate dielectrics 272A-272D, respectively. The composition and / or configuration of the gate electrodes 274A, 274B, 274C, 274D, or a combination thereof may be the same or different. The gate electrodes 274A-274D include at least one conductive gate layer. The conductive gate layer includes a conductive material such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or a combination thereof. In some embodiments, the gate electrodes 274A-274D include a work function layer. The work function layer is a conductive layer adjusted to have a desired work function, such as an n-type work function or a p-type work function. The work function layer includes work function metals and / or their alloys, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi 2 、MoSi 2 、TaSi 2 、NiSi 2 , TaAl, TaAlC, TaSiAlC, TiAlN or a combination thereof. In some embodiments, the gate electrodes 274A-274D include a bulk layer above the gate dielectric and / or the work function layer. The bulk layer includes a suitable conductive material, such as Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or their alloys or a combination thereof. In some embodiments, the gate electrodes 274A-274D include a barrier (blocking) layer above the work function layer and / or the gate dielectric. The barrier layer includes a material that prevents or eliminates the diffusion and / or reaction of components between adjacent layers and / or promotes adhesion between adjacent layers (such as between the work function layer and the bulk layer). In some embodiments, the barrier layer includes a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides or a combination thereof.

[0059] The gate stacks 270A-270D are configured to achieve the desired functions according to the design requirements of the device 200. Therefore, the gate stacks 270A-270D may have different layers in the device region 202A, the device region 202B, and the isolation region 204, depending on their configurations, and the gate stacks 270A-270D may have different layers within the device region 202A, within the device region 202B, and within the isolation region 204, depending on their configurations. For example, the number, configuration, material, or combination of layers of the gate dielectrics 272A-272D ​​and / or gate electrodes 274A-274D corresponding to the first type transistor region (e.g., n-type transistor region) may be different from the number, configuration, material, or combination of layers of the gate dielectrics 272A-272D ​​and / or gate electrodes 274A-274D corresponding to the second type transistor region (e.g., p-type transistor region). In another example, the number, configuration, material, or combination of layers of the gate dielectric 272A and / or the gate electrode 274A in the device region 202A can be different from the number, configuration, material, or combination of layers of the gate dielectric 272B and / or the gate electrode 274B in the device region 202B. In yet another example, the number, configuration, material, or combination of layers of the gate dielectric and / or the gate electrode in the device region (e.g., the device region 202A and / or the device region 202B) can be different from the number, configuration, material, or combination of layers of the gate dielectric and / or the gate electrode in the isolation region (e.g., the isolation region 204). The gate stacks 270A-270D can include many other layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof.

[0060] Forming the gate stack 270A-270D may include: depositing a gate dielectric material (e.g., an interfacial layer and / or a high-k dielectric layer) that partially fills the gate openings 260A-260D; depositing a gate electrode material (e.g., a work function layer, a barrier layer, a bulk layer, etc.) that fills the remaining portion of the gate openings 260A-260D; and performing a planarization process to remove a portion of the gate dielectric material located above the dielectric layer 250 and / or a portion of the gate electrode material located above the dielectric layer 250. In some embodiments, the manufacture of the device 200 may also include: etching back the gate stack 270A-270D; and forming a hard mask (e.g., a self-aligned cap (SAC) structure) over the etched back gate stack 270A-270D. The hard mask includes a different material from the dielectric layer 250 and / or a subsequently formed dielectric layer to achieve etching selectivity. In some embodiments, the hard mask includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, the hard mask includes metal and oxygen and / or nitrogen, such as aluminum oxide (e.g., AlO or Al 2 O 3 ), aluminum nitride (eg, AlN), aluminum oxynitride (eg, AlON), zirconium oxide, zirconium nitride, hafnium oxide (eg, HfO or HFO 2 ), zirconium aluminum oxide (e.g., ZrAlO), other metal oxides, other metal nitrides, or combinations thereof.

[0061] refer to FIG. 7A to FIG. 7G , fabrication of the device 200 may include: forming a dielectric layer 280 above the device 200 (e.g., above the dielectric layer 250 and the gate stacks 270A-270D); and forming a source / drain contact isolation structure 285 above the dielectric layer 280. The dielectric layer 280 may be configured and formed in a manner similar to the dielectric layer 250. For example, the dielectric layer 280 may include an ILD layer above the CESL. The source / drain contact isolation structure 285 extends longitudinally along the longitudinal direction of the fin (e.g., along the x-direction), such that the source / drain contact isolation structure 285 has a length in the x-direction, a width in the y-direction, and a height in the z-direction. Along the lateral directions of the active area (see, e.g., Fig. 7A ), the source / drain contact isolation structure 285 has a width W7, which may be smaller than the spacing between the fins 208A and / or the spacing between the fins 208B. Fig. 7A ), the source / drain contact isolation structure 285 spans the device region 202A, the device region 202B and the isolation region 204.

[0062] In the gate support region of the isolation region 204 (i.e., the region of the isolation region 204 where the gate structure 240D is inserted to improve the structural integrity of the gate structure 240C), the source / drain contact isolation structure 285 is widened to prevent electrical shorts, which may be caused by unintended electrical and / or physical connections between the gate stack 270D and subsequently formed source / drain contacts. For example, the intermediate source / drain contact isolation structure 285 of the device 200 has a widened portion 285' above the gate structure 240D. The widened portion 285' has a width W8 greater than the width W7 in the lateral direction of the active area. The width W8 is also greater than the width of the gate stack 270D (e.g., the width W6) to ensure that the subsequently formed source / drain contacts are sufficiently spaced apart from the gate stack 270D. In the depicted embodiment (see, e.g., Fig. 7E ), the widening portion 285' is disposed above the gate stack 270D and covers the gate stack 270D, and the widening portion 285' extends laterally beyond the two sidewalls of the gate stack 270D. For example, the widening portion 285' may extend beyond the first sidewall and the second sidewall of the gate stack 270D by distances d3 and d4, respectively. The distance d3 may be the same as or different from the distance d4. The length of the widening portion 285' (e.g., along the x-direction) may be configured such that the widening portion 285' is disposed above the gate structure 240E and covers the gate structure 240E (i.e., the gate structure 240D combined with the portion of the gate structure 240C connected thereto). In some embodiments, the length of the widening portion 285' is greater than or equal to the sum of the length of the gate stack 270D and the sum of the widths of at least two gate stacks 270C (e.g., length = length l + (2×width W5)). In some embodiments, the length of the widening portion 285' is greater than or equal to the length of the gate stack 270D.

[0063] The source / drain contact isolation structure 285 includes an electrically insulating material, such as a dielectric material. The composition of the source / drain isolation structure 285 is different from the composition of the dielectric layer 280 and / or the composition of the dielectric layer 250 to achieve selective etching / removal therebetween. For example, the source / drain isolation structure 285 is formed by a dielectric material different from the dielectric material of the dielectric layer 280 and / or the dielectric material of the dielectric layer 250. In some embodiments, the source / drain contact isolation structure 285 is formed by a dielectric material including silicon and oxygen, carbon, nitrogen, or a combination thereof. For example, the source / drain contact isolation structure 285 can be formed by silicon oxide, silicon oxycarbide, silicon nitride, silicon oxycarbonitride, or a combination thereof. In some embodiments, the source / drain contact isolation structure 285 is formed by a dielectric material including boron and oxygen, carbon, nitrogen, or a combination thereof. For example, the source / drain contact isolation structure 285 can be formed by boron nitride. In some embodiments, the source / drain contact isolation structure 285 is formed of a dielectric material including metal and oxygen, carbon, nitrogen, or a combination thereof. In some embodiments, the source / drain contact isolation structure 285 is formed by: depositing a source / drain contact isolation material over the dielectric layer 280; and patterning the source / drain contact isolation material (e.g., by forming a patterned mask layer over the source / drain contact isolation material, and etching / removing the source / drain contact isolation material exposed by the opening in the patterned mask layer). The disclosed embodiments contemplate source / drain contact isolation layers (collectively referred to as source / drain contact isolation structures 285) having various patterns and / or width variations, depending on the layout of the active regions (e.g., fins 208A, 208B), the layout of the active gates (e.g., gate structures 240A, 240B and / or gate stacks 270A, 270B), the layout of the dummy gates (e.g., gate structures 240C and / or gate stacks 270C), the layout of the gate support structures (e.g., gate structures 240D and / or gate stacks 270D), or a combination thereof. In some embodiments, the dielectric layer 280 is omitted, and the source / drain contact isolation structures 285 are formed directly on and physically contact the dielectric layer 250 and / or gate stacks 270A-270D.

[0064] refer to FIG. 8A to FIG. 8G , the fabrication of the device 200 may include forming source / drain contacts 290A-290C, which may be physically and / or electrically isolated from each other by the source / drain contact isolation structure 285. The source / drain contacts 290A-290C extend along the gate longitudinal direction (e.g., along the y-direction), such that the source / drain contacts 290A-290C have a length in the y-direction, a width in the x-direction, and a height in the z-direction. Along the longitudinal direction of the active region (see, e.g., Fig. 8A), source / drain contact 290A has a width smaller than the spacing between gate structures 240A, source / drain contact 290B has a width smaller than the spacing between gate structures 240B, and source / drain contact 290C has a width smaller than the spacing between gate structures 240C. Fig. 8A ), the source / drain contacts 290A-290C have a length that is less than or equal to the spacing between the source / drain contact isolation structures 285. In the depicted embodiment, each of the source / drain contacts 290A-290C is located between and physically contacts a first one of the source / drain contact isolation structures 285 and a second one of the source / drain contact isolation structures 285.

[0065] The source / drain contacts 290A may extend through the dielectric layer 292, the dielectric layer 280, the dielectric layer 250, or a combination thereof to the corresponding source / drain 245 in the device region 202A (see, e.g., Figure 8B and Figure 8C ). Source / drain contacts 290B may extend through dielectric layer 292, dielectric layer 280, dielectric layer 250, or a combination thereof to the corresponding source / drain 245 in device region 202B. Source / drain contacts 290C may extend through dielectric layer 292, dielectric layer 280, dielectric layer 250, or a combination thereof to substrate isolation structure 225 in isolation region 204 (see, e.g., Fig. 8E , Fig.8F and Figure 8G ). In the depicted embodiment, the source / drain contact 290C extends into the substrate isolation structure 225, such that the source / drain contact 290C extends below the bottom of the gate stack 270C and / or the gate stack 270D. In some embodiments, the source / drain contact 290C may stop at the substrate isolation structure 225 and not extend into the substrate isolation structure 225. Because the source / drain contact isolation structure 285 has a widened portion 285' in the gate support region of the isolation region 204, the source / drain contacts 290C are separated by a first distance (e.g., width W8) in the gate support region (see, e.g. Fig. 8E ) and are separated by a second distance (eg, width W7) in the gate unsupported region (see, e.g. Figure 8G). Enlarging the spacing between the source / drain contacts 290C in the gate support region ensures that sufficient spacing is located between the source / drain contacts 290C and the gate stack 270D (e.g., distance d3 and / or distance d4), thereby reducing the risk of the source / drain contacts 290C being electrically and / or physically connected to the gate stack 270D and causing a short circuit. In some embodiments, the distance d5 between the gate stack 270C and the source / drain contact 290C (i.e., in the gate unsupported region of the isolation region 204) is less than the distance d3 and / or distance d4 between the gate stack 270D and the source / drain contact 290C (i.e., in the gate support region).

[0066] The source / drain contacts 290A-290C include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, a low resistivity metal composition, an alloy thereof, or a combination thereof. In the depicted embodiment, the source / drain contacts 290A-290C include tungsten, ruthenium, cobalt, an alloy thereof, or a combination thereof. For example, the source / drain contacts 290A-290C may be tungsten contacts, ruthenium contacts, or cobalt contacts. The source / drain contacts 290A-290C may have the same or different configurations and / or compositions. The source / drain contacts 290A-290C may be formed by: forming a dielectric layer 292 over the source / drain contact isolation structure 285 and the dielectric layer 280; forming a source / drain contact opening extending through the dielectric layer 292, the dielectric layer 280, the dielectric layer 250, or a combination thereof to expose the source / drain 245 or the substrate isolation structure 225; depositing at least one conductive material filling the source / drain contact opening over the dielectric layer 292; and performing a planarization process to remove any conductive material disposed over the top of the source / drain contact isolation structure 285 and / or the dielectric layer 292. The planarization process may be performed until the source / drain contact isolation structure 285 and / or the dielectric layer 292 are reached and exposed. The remaining portion of the conductive material forms a metal plug and, in some embodiments, a metal liner for the source / drain contacts 290A-290C. In some embodiments, before depositing at least one conductive material in the source / drain contact openings, a silicidation process is performed to form a silicide layer over the source / drain 245 .

[0067] In some embodiments, forming the source / drain contact openings includes: forming a patterned mask layer over the dielectric layer 292 having openings therein that overlaps the source / drain 245 in the device region 202A, the source / drain 245 in the device region 202B, and the substrate isolation structure 225 in the isolation region 204; and selectively etching the dielectric material (e.g., dielectric layer 292, dielectric layer 280, dielectric layer 250, or a combination thereof) exposed by the openings of the patterned mask layer without negligible etching of the semiconductor material (e.g., source / drain 245). In the depicted embodiment, because the substrate isolation structure 225 is formed of dielectric material, the etching can remove portions of them, thereby allowing the source / drain contact openings in the isolation region 204 to extend into the substrate isolation structure 225. In some embodiments, the etching is configured to stop when reaching and / or exposing the source / drain 245. The etching is dry etching, wet etching, other suitable etching, or a combination thereof. One or more deposition processes may be performed to form a conductive material filling the source / drain contact openings.

[0068] exist FIG. 8A to FIG. 8G, the device 200 includes a transistor in a device region 202A and a transistor in a device region 202B. For example, in the device region 202A, the transistor may include a corresponding channel layer 220', a corresponding source / drain 245, and a corresponding gate structure 240A (e.g., a corresponding gate stack 270A and a corresponding gate spacer 232). The corresponding gate structure 240A is disposed between the corresponding source / drain 245 along the x-direction, and the internal spacer 234 is disposed between the corresponding gate structure 240A and the corresponding source / drain 245. In addition, the corresponding gate stack 270A engages the corresponding channel layer 220', and the corresponding channel layer 220' extends between the corresponding source / drain 245 along the x-direction. The corresponding gate structure 240A is disposed on at least two sides of the corresponding channel layer 220'. For example, the respective gate structure 240A has a respective gate dielectric 272A and a respective gate electrode 274A that may surround the respective channel layer 220' (e.g., in a YZ cross-sectional view). In the device region 202B, the transistor may include the respective channel layer 220', the respective source / drain 245, and the respective gate structure 240B (e.g., the respective gate stack 270B and the respective gate spacer 232). The respective gate structure 240B is disposed between the respective source / drain 245 along the x-direction, and the internal spacer 234 is disposed between the respective gate structure 240B and the respective source / drain 245. In addition, the respective gate stack 270B engages the respective channel layer 220', and the respective channel layer 220' extends between the respective source / drain 245 along the x-direction. The respective gate structure 240B is disposed on at least two sides of the respective channel layer 220'. For example, the respective gate structure 240B has a respective gate dielectric 272B and a respective gate electrode 274B that may surround the respective channel layer 220 ′ (eg, in a YZ cross-sectional view).

[0069] Applying a voltage to the gate stack 270A and / or the gate stack 270B can enable current to flow through the corresponding channel layer 220' between the corresponding source / drain 245. Therefore, the gate structures 240A, 240B that form part of the transistor can be referred to as active gate structures, and the gate stacks 270A, 270B that form part of the transistor can be referred to as active gate stacks and / or active gates. "Active gate structure", "active gate stack" and "active gate" generally refer to electrically functional gate structures (and / or gate stacks), while "dummy gate structure" generally refers to electrically non-functional gate structures (and / or gate stacks). The dummy gate structure can mimic the physical characteristics of the active gate structure, such as the physical dimensions and / or layers of the active gate structure, but is electrically inoperable (i.e., applying a voltage to the dummy gate structure does not enable current to flow through the channel and / or between the source / drain). In the depicted embodiment, the device 200 includes a dummy gate structure in the isolation region 204, such as their gate structure 240C and / or gate stack 270C. In addition, because the source / drain contact 290C is connected to the substrate isolation structure 225, rather than the conductive member, the source / drain contact 290C can be referred to as a dummy source / drain contact. The gate structure 240C, their gate stack 270C, the source / drain contact 290C, or a combination thereof can enable a substantially uniform processing environment (e.g., by reducing (or preventing) CMP-induced dishing effects).

[0070] The device 200 also includes a gate support structure, such as their gate structure 240D and / or gate stack 270D, which may also be referred to as a gate support bar and / or a dummy gate support bar (because their gate structure 240D and / or gate stack 270D are dummy gate structures). The gate support structure may improve the reliability and / or structural integrity of the device 200 in the isolation region 204. Fig.13A and Fig. 13B, gate structures 240A (and / or their gate stacks 270A) and gate structures 240B (and / or their gate stacks 270B) are formed over two active regions (e.g., channel regions of fins 208A and fins 208B, respectively, which may include corresponding channel layers 220') and substrate isolation structures 225. Because gate structures 240A and gate structures 240B can be well bonded to the active regions, gate structures 240A and gate structures 240B are anchored and structurally supported by the active regions, which prevents collapse and / or bowing of gate structures 240A and gate structures 240B, even though gate heights may increase with scaled IC technology nodes. Such anchoring also provides gate structures 240A and gate structures 240B with varying heights (e.g., height h1 and height h2) along their lengths, which further reduces collapse and / or bowing. In contrast, gate structure 240C is formed over substrate isolation structure 225. Because gate structure 240C may not adhere well to substrate isolation structure 225 (e.g., dielectric material versus semiconductor material), and gate structure 240C has a greater overall height (i.e., gate structure 240C has height h1 along its length because gate structure 240C is also not disposed over an active area), gate structure 240C may undesirably delaminate, bow, collapse, or a combination thereof from substrate isolation structure 225, such as Fig.13A . This degrades device performance, device reliability, device yield, or a combination thereof. This problem may be exacerbated by (inadvertent or intentional) etching of the substrate isolation structure 225, which causes the gate structure 240C to be supported by the isolation mesa 225', which is narrower than the substrate isolation structure 225 and provides even less structural stability for the gate structure 240C. By inserting gate support structures (e.g., their gate structures 240D and / or gate stacks 270D) into the isolation region 204, the gate structures 240C are provided with additional support and / or anchoring, which can reduce and / or prevent their collapse and / or bending, such as Fig. 13B The gate support structure can be easily integrated into existing device manufacturing processes. Different embodiments may have different advantages, and no particular advantage is necessarily required by any embodiment.

[0071] A gate support structure such as described herein may be integrated into a device and / or device layout according to a set of design rules. FIG. 14A to FIG. 14C , the device 300 having the gate support structure is configured and arranged according to a set of design rules, as further described below. Fig.14A is a top view of part or all of a device 300 according to various aspects of an embodiment of the present disclosure. Fig. 14B The device 300 according to various aspects of the embodiments of the present disclosure is Fig.14AA cross-sectional view of part or all of line BB.

[0072] Fig. 14C The device 300 according to various aspects of the embodiments of the present disclosure is Fig.14A 300 is similar to device 200 in many respects. Therefore, for the sake of clarity and simplicity, similar components of device 300 and device structure 200 are identified by the same reference numerals. For ease of description and understanding, this article discusses both FIG. 14A to FIG. 14C . It has been simplified for clarity. FIG. 14A to FIG. 14C , to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the device 300, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the device 300.

[0073] The device 300 includes: a region including an active region (e.g., device region 302A, device region 302B, and device region 302C) and a region not including an active region (i.e., a non-active region region, such as isolation region 304A, isolation region 304B, and isolation region 304C). Each of the device regions 302A-302C includes a corresponding active region (OD), a gate (G), and a source / drain contact (MD). The active region extends longitudinally along a first direction (e.g., an x-direction), the gate extends longitudinally along a second direction (e.g., a y-direction) different from the first direction, and the source / drain contact extends longitudinally along the second direction. The active region may include a channel structure (e.g., a stack of channel layers 220') disposed between source / drains (e.g., source / drain 245), and the gate may be disposed above the channel structure and engage the channel structure (e.g., the gate may wrap and / or surround the channel layer 220'). The gates and active regions may combine to form transistors in the device regions 302A-302C.

[0074] Device 300 may include one or more gate isolation structures (CPO or CMG). In the depicted embodiment, the gate isolation structure physically and / or electrically isolates gates of different device regions, such as physically and / or electrically isolating the gate of device region 302A from the gate of device region 302C. The gate isolation structure extends longitudinally along a first direction (i.e., a longitudinal direction of the active region). In some embodiments, the gate of device region 302A and the gate of device region 302C may be formed by a gate line cut into two gates, for example by replacing a portion of the gate line with an electrically insulating material (such as a dielectric material). Fig. 14C, the gate isolation structure may include a dielectric material 310 disposed between the gate of the device region 302A (e.g., the gate stack 270A-1 having the gate dielectric 272A-1 and the gate electrode 274A-1) and the gate of the device region 302C (e.g., the gate stack 270A-2 having the gate dielectric 272A-2 and the gate electrode 274A-2), which may be formed by replacing a portion of the corresponding gate (e.g., the corresponding gate stack 270A) with the dielectric material 310. The gate isolation structure may extend into the substrate isolation structure 225 so that the gate isolation structure extends below the bottom of the gate (e.g., beyond the gate stack 270A-1 and the gate stack 270A-2). The dielectric material 310 may be a single layer or multiple layers.

[0075] The device 300 may also include one or more active area isolation structures (CPODEs) that may replace portions of the gate. In the depicted embodiment, the active area isolation structures physically and / or electrically isolate active areas of different devices, such as physically and / or electrically isolating a first active area of ​​a first device in device region 302A from a second active area of ​​a second device in device region 302A. The active area isolation structures extend longitudinally along a second direction (i.e., a longitudinal direction of the gate. In such an embodiment, the active areas of the devices within a device region (such as device region 302A) may be formed, for example, by replacing the active area lines with an electrically insulating material (such as a dielectric material) and / or a portion of a gate line passing through the active area lines by an active area line cut into two active areas. Fig. 14B , the active area isolation structure may include a dielectric material 315 disposed between a first active region of a first device (e.g., its corresponding source / drain 245) and a second active region of a second device (e.g., its corresponding source / drain 245). The active area isolation structure (e.g., dielectric material 315) may extend into the substrate isolation structure 225, so that the active area isolation structure extends below the bottom of the source / drain 245 and / or the channel layer 220'. The dielectric material 315 may be a single layer or multiple layers.

[0076] Isolation region 304A is disposed between device region 302A and device region 302B, isolation region 304B is disposed adjacent to device region 302A and device region 302C, and isolation region 304C is disposed adjacent to device region 302C, so that device region 302A is disposed between isolation region 304A and isolation region 304B, and device region 302C is disposed between isolation region 304B and isolation region 304C. Isolation region 304A includes a corresponding gate, a corresponding source / drain contact, a source / drain contact isolation structure (CMD), and a corresponding gate support structure (HG1). Isolation region 304B includes a corresponding gate and a corresponding gate support structure (HG2), but does not include a source / drain contact and / or a source / drain contact isolation structure. The gate support structure extends longitudinally along a first direction (i.e., the longitudinal direction of the active region).

[0077] The dimensions and / or spacing corresponding to the gate support structures may be configured differently depending on whether the gate support structures are formed in regions with or without source / drain contacts. For example, the dimensions and / or spacing corresponding to the gate support structures (e.g., HG2) in isolation regions 304B and 304C without source / drain contacts may be relaxed relative to the dimensions and / or spacing corresponding to the gate support structures (e.g., HG1) in isolation regions 304A including source / drain contacts. In some embodiments, the length of the gate support structures in isolation regions 304B and / or 304C may be configured to be greater than the length of the gate support structures in isolation regions 304A. For example, the gate support structure in isolation region 304A may be connected to two gates, while the gate support structures in isolation regions 304B and / or 304C may be connected to two to six gates. In such an example, the length (e.g., along the x-direction) of the gate support structure in isolation region 304B and / or isolation region 304C can be approximately five times greater than the length (e.g., along the x-direction) of the gate support structure in isolation region 304A. In some embodiments, the gate support structures in isolation regions 304A-304C have a width (e.g., along the y-direction) of about 8 nm to about 12 nm (e.g., 10 nm), the length of the gate support structure in isolation region 304A is less than or equal to about 54 nm, and the length of the gate support structure in isolation region 304B and / or isolation region 304C is less than or equal to about 270 nm.

[0078] In some embodiments, in a region including gate support structures, the spacing y1 between the gate support structures along the y direction (e.g., along the gate longitudinal direction) is greater than the spacing between the gate support structures along the x direction (e.g., along the active region longitudinal direction). For example, the spacing y1 is about 4 to about 5 times greater than the spacing between the gate support structures along the x direction. In some embodiments, the spacing y2 is greater than or equal to about 224 nm, and the spacing between the gate support structures along the x direction is greater than about 48 nm.

[0079] In some embodiments, the spacing y2 between the gate support structure and the active region (e.g., their sidewalls) along the y direction is configured to reduce the risk of forming a short circuit between the gate support structure and the active region. For example, the spacing y2 can be greater than or equal to about 130nm. In some embodiments, the spacing y3 between the gate support structure and the end of the source / drain contact along the y direction is configured to reduce the risk of forming a short circuit between the gate support structure and the source / drain contact. For example, the spacing y3 can be greater than or equal to about 100nm. In some embodiments, the width W of the source / drain contact isolation structure (e.g., along the y direction) is configured to be about six to about nine times the width of the gate support structure in the isolation region 304A to reduce the risk of forming a short circuit between the gate support structure and the source / drain contact. For example, the gate support structure in the isolation region 304A can have a width (e.g., along the y direction) of about 8nm to about 12nm (e.g., 10nm), and the width y1 can be about 68nm to about 72nm.

[0080] In some embodiments, the interval y4 between the ends of the gate support structure and the active area isolation structure along the y direction is configured to reduce the risk of forming a short circuit between the gate support structure and the active area. For example, the interval y4 may be greater than or equal to about 135nm. In some embodiments, the interval x1 between the gate support structure and the active area isolation structure (e.g., their sidewalls) along the x direction is configured to reduce the risk of forming a short circuit between the gate support structure and the active area. For example, the interval x1 may be greater than or equal to about 94.5nm. In some embodiments, the interval y4 is about 1.25 to about 1.5 times greater than the interval x1. In some embodiments, the interval y4 between the gate support structure and the gate isolation structure (e.g., their sidewalls) along the y direction is configured to reduce the risk of forming a short circuit between the gate support structure and the active area. For example, the interval y5 may be greater than or equal to about 48nm. In some embodiments, the interval y6 between the gate support structure and the end of the gate along the y direction is configured to optimize the position of the gate support structure, and thus optimize the structural integrity of the gate. For example, the interval y5 may be greater than or equal to about 100nm.

[0081] Fig.15It is a flowchart of part or all of a method 400 for improving device reliability and structural integrity of a device according to various aspects of an embodiment of the present disclosure. In box 410, the method 400 includes receiving a device layout, the device layout having an active area line extending longitudinally in a first direction in an active area region, a first gate line extending longitudinally in a second direction different from the first direction above the active area line in the active area region, and a second gate line extending longitudinally in a second direction in a non-active area region. The first gate line can be an active gate line and represent an active gate, and the second gate line can be a dummy gate line and represent a dummy gate. The active area line can represent a channel region and / or a source / drain region. In box 415, the method 400 includes modifying the device layout by inserting a gate support bar in a non-active area region, the gate support bar extending longitudinally in a first direction and connecting at least two of the second gate lines. The gate support bar can be a dummy gate line and / or represent a dummy gate. In box 420, the method 400 includes manufacturing a device based on the modified device layout. The present disclosure embodiment contemplates additional processing. Additional steps may be provided before, during, and after the method 400 , and some of the described steps may be moved, replaced, or eliminated for additional embodiments of the method 400 .

[0082] The present disclosure provides many different embodiments. An exemplary method includes forming an active region in a device region. The active region extends longitudinally in a first direction and extends transversely in a second direction. The method also includes forming an isolation structure in the device region and the isolation region. The isolation structure in the device region is adjacent to the active region. In some embodiments, the active region includes a lower portion and an upper portion, wherein the isolation structure is adjacent to the lower portion of the active region, and the upper portion of the active region is disposed above the isolation structure and / or extends from the isolation structure. The method also includes forming a first gate above the isolation structure in the active region and the device region, forming a second gate above the isolation structure in the isolation region, and forming a third gate above the isolation structure in the isolation region. The first gate and the second gate extend longitudinally in the second direction, the third gate extends longitudinally in the first direction, and the third gate is connected to at least two of the second gates. In some embodiments, the first gate, the second gate, and the third gate are formed simultaneously. In some embodiments, there is a first spacing between the first gates, a first spacing between the second gates, the first gate has a first height above the active region, and the second gate has a second height above the isolation structure. The second height is greater than the first height.

[0083] In some embodiments, the method further includes forming a contact isolation structure above the first gate, the second gate, and the third gate. The contact isolation structure has a first width above the first gate along the second direction, and has a second width above the third gate along the second direction. The first width is less than the second width. In some embodiments, the contact isolation structure has a second width above the second gate. In some embodiments, the contact isolation structure is a first contact isolation structure, and the method further includes forming a second contact isolation structure above the first gate and the second gate. The second contact isolation structure extends longitudinally along the first direction, and the second contact isolation structure has a first width above the first gate along the second direction. The second contact isolation structure may also have a first width above the second gate.

[0084] In some embodiments, the method further includes forming a first source / drain contact in the device region and forming a second source / drain contact in the isolation region. The first source / drain contact and the second source / drain contact extend longitudinally along the second direction. The first source / drain contact is disposed on the active region, and the second source / drain contact is disposed on the isolation structure. The first source / drain contact is disposed between the first of the first gates and the second of the first gates, and the second source / drain contact is disposed between the first of the second gates and the second of the second gates. In some embodiments, the first spacing is located between the second source / drain contact and the first of the second gates along the first direction, and the second spacing is located between the second source / drain contact and the third gate along the second direction. The second spacing is greater than the first spacing.

[0085] In some embodiments, forming a first gate over an isolation structure in an active region and a device region, forming a second gate over an isolation structure in an isolation region, and forming a third gate over an isolation structure in an isolation region include: forming a first dummy gate stack extending longitudinally in a second direction over an isolation structure in an active region and a device region, forming a second dummy gate stack extending longitudinally in a second direction over an isolation structure in an isolation region, and forming a third dummy gate stack extending longitudinally in a second direction over an isolation structure in an isolation region. The third dummy gate stack is connected to at least two of the second dummy gate stacks. The method may further include: removing the first dummy gate stack, the second dummy gate stack, and the third dummy gate stack to form a first gate opening, a second gate opening, and a third gate opening, respectively. The first gate opening exposes the active region, the second gate opening exposes the isolation structure, and the third gate opening exposes the isolation structure. The third gate opening is connected to at least two of the second gate openings. The method may further include: forming a first gate stack over an active region in a first gate opening, forming a second gate stack over an isolation structure in a second gate opening, and forming a third gate stack over an isolation structure in a third gate opening. In some embodiments, the method further includes: before removing the first dummy gate stack, the second dummy gate stack, and the third dummy gate stack, forming a source / drain groove in the source / drain region of the active region, and forming a source / drain in the source / drain groove. The first gate opening can expose the channel region of the active region.

[0086] An exemplary device structure includes: a first gate extending longitudinally in a first direction in a device region; a second gate extending longitudinally in a first direction in an isolation region; and a gate support bar extending longitudinally in a second direction in the isolation region. The second direction is different from the first direction. The first gate is disposed above an isolation structure and an active region, the second gate is disposed above the isolation structure, and the gate support bar is disposed above the isolation structure. The first gate has a first height above the isolation structure, the first gate has a second height above the active region, and the first height is greater than the second height. The second gate has a third height above the isolation structure, and the third height is greater than the second height. The gate support bar is connected to at least two of the second gates.

[0087] In some embodiments, the gate support bar has a third height above the isolation structure. In some embodiments, the device region has no gate support bar extending longitudinally along the second direction. In some embodiments, the isolation region has no active region. In some embodiments, the active region includes a channel structure disposed between the first source / drain and the second source / drain, and at least one of the first gates is disposed above the channel structure and between the first source / drain and the second source / drain. The channel structure extends longitudinally along the second direction.

[0088] In some embodiments, the device structure further includes a source / drain contact isolation structure extending longitudinally along the second direction. The source / drain contact isolation structure is disposed above the first gate, the second gate, and the gate support bar. The source / drain contact isolation structure has a first width above the gate support bar along the first direction, and has a second width above the first gate along the first direction. The first width is greater than the second width.

[0089] In some embodiments, the device region is a first device region, the active region is a first active region, and the device structure further includes a fourth gate extending longitudinally along the first direction in the second device region. The fourth gate is disposed above the isolation structure and the second active region, the fourth gate has a fourth height above the isolation structure, the fourth gate has a fifth height above the second active region, and the fourth height is greater than the fifth height. The isolation region may be disposed between the first device region and the second device region along the second direction, and the third height is greater than the fifth height.

[0090] In some embodiments, the device structure further includes a source / drain contact isolation structure extending longitudinally along the second direction. The source / drain contact isolation structure is disposed above the first gate, the second gate, and the gate support bar. The source / drain contact isolation structure has a first width above the gate support bar along the first direction, and has a second width above the first gate along the first direction. The first width is greater than the second width. In some embodiments, the source / drain contact isolation structure has a second width above the second gate along the first direction.

[0091] In some embodiments, the device structure further includes a first source / drain contact disposed in the device region and a second source / drain contact disposed in the isolation region. At least one of the first source / drain contacts is disposed on and connected to the active region, and at least one of the second source / drain contacts is disposed on and extends into the isolation structure. In some embodiments, a first spacing along a first direction between the gate support bar and the second source / drain contact is greater than a second spacing along a second direction between the second gate and the second source / drain contact.

[0092] In some embodiments, a gate support strip is disposed in a gate support region of the isolation region, and the gate support strip includes a first gate spacer disposed along a first sidewall of the first gate stack. The first gate stack includes a first gate dielectric and a first gate electrode. The gate support strip may be connected to a first of the second gates and a second of the second gates. The first of the second gates includes a second gate spacer disposed along a second sidewall of the second gate stack, and the second gate stack includes a second gate dielectric and a second gate electrode. The second of the second gates includes a third gate stack having a third gate spacer disposed along a third sidewall of the third gate stack, and the third gate stack includes a third gate dielectric and a third gate electrode. In the gate support region along the first direction, the first gate dielectric may wrap the first gate electrode, and the first gate dielectric may form a first sidewall of the first gate stack. In the gate support region along the second direction, the first gate electrode may be disposed between the second gate electrode and the third gate electrode, the second gate dielectric may be disposed between the second gate electrode and one of the second gate spacers, and the third gate dielectric may be disposed between the third gate electrode and one of the third gate spacers.

[0093] An exemplary device layout includes a first active gate line, a second active gate line, a first dummy gate line, and a second dummy gate line oriented longitudinally in a first direction. The device layout also includes a dummy gate support bar oriented longitudinally in a second direction different from the first direction. The dummy gate support bar extends from the first dummy gate line to the second dummy gate line along the second direction. The device layout also includes an active area oriented longitudinally in the second direction. The first active gate line and the second active gate line are arranged above the active area. In some embodiments, the active area includes a first active area and a second active area, the first active gate line is arranged above the first active area, the second active gate line is arranged above the second active area, and the first dummy gate line and the second dummy gate line are arranged between the first active gate line and the second active gate line.

[0094] In some embodiments, the device layout further includes a first source / drain contact isolation line and a second source / drain contact isolation line oriented longitudinally along the second direction. The first source / drain contact isolation line is disposed above the first active gate line, the second active gate line, the first dummy gate line, and the second dummy gate line. The second source / drain contact isolation line is disposed above the first active gate line, the second active gate line, the first dummy gate line, the second dummy gate line, and the dummy gate support bar. The first source / drain contact isolation line has a first width above the first active gate line, the second active gate line, the first dummy gate line, and the second dummy gate line along the second direction. The second source / drain contact isolation line has a first width above the first active gate line and the second active gate line, and has a second width above the dummy gate support bar along the second direction. The second width is greater than the first width. In some embodiments, the second source / drain contact isolation line has a second width above the first dummy gate line and the second dummy gate line.

[0095] Some embodiments of the present application provide a method for forming a device structure, comprising: forming an active region in a device region, wherein the active region extends longitudinally along a first direction and extends laterally along a second direction; forming an isolation structure in the device region and an isolation region, wherein the isolation structure in the device region is adjacent to the active region; and forming a first gate above the isolation structure in the active region and the device region, forming a second gate above the isolation structure in the isolation region, and forming a third gate above the isolation structure in the isolation region, wherein the first gate and the second gate extend longitudinally along the second direction, the third gate extends longitudinally along the first direction, and the third gate is connected to at least two of the second gates.

[0096] In some embodiments, the method further comprises forming a contact isolation structure over the first gate, the second gate, and the third gate, wherein:

[0097] The contact isolation structure extends longitudinally along the first direction; and

[0098] The contact isolation structure has a first width along the second direction over the first gate and a second width along the second direction over the third gate, wherein the first width is smaller than the second width.

[0099] In some embodiments, the contact isolation structure is a first contact isolation structure, and the method further includes forming a second contact isolation structure above the first gate and the second gate, wherein:

[0100] The second contact isolation structure extends longitudinally along the first direction; and

[0101] The second contact isolation structure has the first width along the second direction above the first gate.

[0102] In some embodiments, the method also includes forming a first source / drain contact in the device area and forming a second source / drain contact in the isolation area, wherein: the first source / drain contact and the second source / drain contact extend longitudinally along the second direction; the first source / drain contact is arranged on the active area, and the second source / drain contact is arranged on the isolation structure; the first source / drain contact is arranged between the first one of the first gates and the second one of the first gates; and the second source / drain contact is arranged between the first one of the second gates and the second one of the second gates.

[0103] In some embodiments, a first spacer is located between the second source / drain contact and the first of the second gates along the first direction; and

[0104] A second interval is located between the second source / drain contact and the third gate along the second direction, wherein the second interval is greater than the first interval.

[0105] In some embodiments, the method further includes forming the first gate, the second gate, and the third gate simultaneously.

[0106] In some embodiments, forming the first gate over the isolation structure in the active region and the device region, forming the second gate over the isolation structure in the isolation region, and forming the third gate over the isolation structure in the isolation region comprises:

[0107] forming a first dummy gate stack extending longitudinally along the second direction over the isolation structures in the active region and the device region, forming a second dummy gate stack extending longitudinally along the second direction over the isolation structures in the isolation region, and forming a third dummy gate stack extending longitudinally along the second direction over the isolation structures in the isolation region, wherein the third dummy gate stack is connected to at least two of the second dummy gate stacks;

[0108] removing the first dummy gate stack, the second dummy gate stack, and the third dummy gate stack to form a first gate opening, a second gate opening, and a third gate opening, respectively, wherein the first gate opening exposes the active area, the second gate opening exposes the isolation structure, the third gate opening exposes the isolation structure, and the third gate opening is connected to at least two of the second gate openings; and

[0109] A first gate stack is formed over the active region in the first gate opening, a second gate stack is formed over the isolation structure in the second gate opening, and a third gate stack is formed over the isolation structure in the third gate opening.

[0110] In some embodiments, the method further comprises:

[0111] Before removing the first dummy gate stack, the second dummy gate stack and the third dummy gate stack, a source / drain groove is formed in the source / drain region of the active region, and a source / drain is formed in the source / drain groove, wherein the first gate opening exposes the channel region of the active region.

[0112] In some embodiments, the first gates have a first spacing therebetween, the second gates have the first spacing therebetween, the first gates have a first height above the active region, and the second gates have a second height above the isolation structure, wherein the second height is greater than the first height.

[0113] Other embodiments of the present application provide a device structure, including: a first gate, extending longitudinally along a first direction in a device region, wherein the first gate is arranged above an isolation structure and an active region, the first gate has a first height above the isolation structure, the first gate has a second height above the active region, and the first height is greater than the second height; a second gate, extending longitudinally along the first direction in the isolation region, wherein the second gate is arranged above the isolation structure, the second gate has a third height above the isolation structure, and the third height is greater than the second height; and a gate support bar, extending longitudinally along a second direction in the isolation region, wherein the second direction is different from the first direction, the gate support bar is arranged above the isolation structure, and the gate support bar is connected to at least two of the second gates.

[0114] In some embodiments, the gate support strip has a third height above the isolation structure.

[0115] In some embodiments, the active region includes a channel structure disposed between a first source / drain and a second source / drain, wherein at least one of the first gates is disposed above the channel structure and between the first source / drain and the second source / drain, and the channel structure extends longitudinally along the second direction.

[0116] In some embodiments, the device structure further includes a source / drain contact isolation structure extending longitudinally along the second direction, wherein:

[0117] The source / drain contact isolation structure is disposed above the first gate, the second gate and the gate support bar; and

[0118] The source / drain contact isolation structure has a first width along the first direction above the gate support strip, and the source / drain contact isolation structure has a second width along the first direction above the first gate, and the first width is greater than the second width.

[0119] In some embodiments, the device region is a first device region, the active region is a first active region, and the device structure further comprises:

[0120] a fourth gate extending longitudinally along the first direction in the second device region, wherein the fourth gate is disposed above the isolation structure and the second active region, the fourth gate has a fourth height above the isolation structure, the fourth gate has a fifth height above the second active region, and the fourth height is greater than the fifth height; and

[0121] The isolation region is disposed between the first device region and the second device region along the second direction, and the third height is greater than the fifth height.

[0122] In some embodiments, the device structure further comprises:

[0123] first source / drain contacts disposed in the device region, wherein at least one of the first source / drain contacts is disposed on and connected to the active region; and

[0124] Second source / drain contacts are disposed in the isolation region, wherein at least one of the second source / drain contacts is disposed on the isolation structure and extends into the isolation structure.

[0125] In some embodiments, the gate support strip is disposed in a gate support region of the isolation region;

[0126] The gate support strip comprises a first gate spacer disposed along a first sidewall of a first gate stack, wherein the first gate stack comprises a first gate dielectric and a first gate electrode;

[0127] the gate support strip being connected to a first one of the second gates and a second one of the second gates, wherein the first one of the second gates comprises a second gate spacer disposed along a second sidewall of a second gate stack, wherein the second gate stack comprises a second gate dielectric and a second gate electrode, and the second one of the second gates comprises a third gate stack having a third gate spacer disposed along a third sidewall of the third gate stack, wherein the third gate stack comprises a third gate dielectric and a third gate electrode;

[0128] The first gate dielectric wraps the first gate electrode in the gate supporting region along the first direction, and the first gate dielectric forms the first sidewall of the first gate stack; and

[0129] In the gate supporting region along the second direction, the first gate electrode is arranged between the second gate electrode and the third gate electrode, the second gate dielectric is arranged between the second gate electrode and one of the second gate spacers, and the third gate dielectric is arranged between the third gate electrode and one of the third gate spacers.

[0130] In some embodiments, the device region has no gate support strip extending longitudinally along the second direction.

[0131] Some further embodiments of the present application provide a device layout, including: a first active gate line, a second active gate line, a first dummy gate line, and a second dummy gate line, which are longitudinally oriented along a first direction; a dummy gate support bar, which is longitudinally oriented along a second direction different from the first direction, wherein the dummy gate support bar extends from the first dummy gate line to the second dummy gate line along the second direction; and an active area, which is longitudinally oriented along the second direction, wherein the first active gate line and the second active gate line are arranged above the active area.

[0132] In some embodiments, the device layout further comprises a first source / drain contact isolation line and a second source / drain contact isolation line oriented longitudinally along the second direction, wherein:

[0133] The first source / drain contact isolation line is disposed above the first active gate line, the second active gate line, the first dummy gate line, and the second dummy gate line;

[0134] The second source / drain contact isolation line is disposed above the first active gate line, the second active gate line, the first dummy gate line, the second dummy gate line and the dummy gate support bar;

[0135] The first source / drain contact isolation line has a first width along the second direction over the first active gate line, the second active gate line, the first dummy gate line, and the second dummy gate line; and

[0136] The second source / drain contact isolation line has a first width above the first active gate line and the second active gate line, and has a second width along the second direction above the dummy gate support strip, wherein the second width is greater than the first width.

[0137] In some embodiments, the second source / drain contact isolation line has the second width over the first dummy gate line and the second dummy gate line.

[0138] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a device structure, comprising: forming an active region in the device region, wherein the active region extends longitudinally along a first direction and laterally along a second direction; forming an isolation structure in the device region and the isolation region, wherein the isolation structure in the device region is adjacent to the active region; and A first gate is formed over the isolation structure in the active region and the device region, a second gate is formed over the isolation structure in the isolation region, and a third gate is formed over the isolation structure in the isolation region, wherein the first gate and the second gate extend longitudinally along the second direction, the third gate extends longitudinally along the first direction, and the third gate is connected to at least two of the second gates.

2. The method according to claim 1, further comprising forming a contact isolation structure over the first gate, the second gate and the third gate, wherein: The contact isolation structure extends longitudinally along the first direction; as well as The contact isolation structure has a first width along the second direction over the first gate and a second width along the second direction over the third gate, wherein the first width is smaller than the second width.

3. The method according to claim 2, wherein: The contact isolation structure is a first contact isolation structure, and the method further comprises forming a second contact isolation structure above the first gate and the second gate, wherein: The second contact isolation structure extends longitudinally along the first direction; and The second contact isolation structure has the first width along the second direction above the first gate.

4. The method of claim 1 , further comprising forming a first source / drain contact in the device region and forming a second source / drain contact in the isolation region, wherein: The first source / drain contact and the second source / drain contact extend longitudinally along the second direction; The first source / drain contact is disposed on the active region, and the second source / drain contact is disposed on the isolation structure; the first source / drain contact being disposed between a first one of the first gates and a second one of the first gates; and The second source / drain contact is disposed between a first one of the second gates and a second one of the second gates.

5. The method according to claim 4, wherein: a first spacer located along the first direction between the second source / drain contact and the first of the second gates; as well as A second interval is located between the second source / drain contact and the third gate along the second direction, wherein the second interval is greater than the first interval. The method according to claim 1 , further comprising forming the first gate, the second gate, and the third gate simultaneously.

7. The method according to claim 1, wherein: Forming the first gate over the isolation structure in the active region and the device region, forming the second gate over the isolation structure in the isolation region, and forming the third gate over the isolation structure in the isolation region comprises: forming a first dummy gate stack extending longitudinally along the second direction over the isolation structures in the active region and the device region, forming a second dummy gate stack extending longitudinally along the second direction over the isolation structures in the isolation region, and forming a third dummy gate stack extending longitudinally along the second direction over the isolation structures in the isolation region, wherein the third dummy gate stack is connected to at least two of the second dummy gate stacks; removing the first dummy gate stack, the second dummy gate stack, and the third dummy gate stack to form a first gate opening, a second gate opening, and a third gate opening, respectively, wherein the first gate opening exposes the active area, the second gate opening exposes the isolation structure, the third gate opening exposes the isolation structure, and the third gate opening is connected to at least two of the second gate openings; and A first gate stack is formed over the active region in the first gate opening, a second gate stack is formed over the isolation structure in the second gate opening, and a third gate stack is formed over the isolation structure in the third gate opening.

8. The method according to claim 7, further comprising: Before removing the first dummy gate stack, the second dummy gate stack and the third dummy gate stack, a source / drain groove is formed in the source / drain region of the active region, and a source / drain is formed in the source / drain groove, wherein the first gate opening exposes the channel region of the active region.

9. A device structure comprising: A first gate extending longitudinally along a first direction in the device region, wherein the first gate is disposed above the isolation structure and the active region, the first gate has a first height above the isolation structure, the first gate has a second height above the active region, and the first height is greater than the second height; a second gate extending longitudinally along the first direction in the isolation region, wherein the second gate is disposed above the isolation structure, the second gate has a third height above the isolation structure, and the third height is greater than the second height; and A gate support bar extends longitudinally in the isolation region along a second direction, wherein the second direction is different from the first direction, the gate support bar is disposed above the isolation structure, and the gate support bar is connected to at least two of the second gates.

10. A device layout comprising: The first active gate line, the second active gate line, the first dummy gate line and the second dummy gate line are longitudinally oriented along a first direction; a dummy gate support bar longitudinally oriented along a second direction different from the first direction, wherein the dummy gate support bar extends from the first dummy gate line to the second dummy gate line along the second direction; and An active area is longitudinally oriented along the second direction, wherein the first active gate line and the second active gate line are disposed above the active area.

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