Semiconductor structure and method for forming the same

Abstract

An embodiment of the present invention provides a semiconductor structure and a method for forming the same. The method includes providing a substrate having a gate structure thereon; forming a gate spacer on the sidewalls of the gate structure, wherein the steps of forming the gate spacer include forming a first spacer on the sidewalls of the gate structure; forming a second spacer on the sidewalls of the first spacer using a first reaction source gas in an oxygen-containing atmosphere; and forming a third spacer on the sidewalls of the second spacer using a second reaction source gas in an oxygen-helium mixed atmosphere, wherein the fluorine content in the first reaction source gas is higher than the fluorine content in the second reaction source gas. The above technical solution can improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] A metal oxide semiconductor transistor includes a gate structure and a gate sidewall formed on the sidewall of the gate structure and surrounding the gate structure. On the one hand, the gate sidewall can protect the gate structure; on the other hand, during the source and drain injection process, the gate sidewall can be used to prevent large doses of source and drain from being injected too close to the conductive channel, thereby causing misconduct between the source and drain.

[0003] As semiconductor manufacturing technology develops towards higher technology nodes, the size of the gate structure becomes smaller and smaller, and the conductive channel in the substrate below the gate structure becomes shorter and shorter. The gate sidewall that can reduce the leakage current between the source and the drain becomes particularly important, which puts higher requirements on the manufacturing process of the gate sidewall.

[0004] However, the electrical performance of the semiconductor structures formed so far still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the electrical performance of the semiconductor structure.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, wherein the substrate has a gate structure;

[0008] A gate sidewall is formed on the sidewall of the gate structure, and the steps of forming the gate sidewall include: forming a first sidewall on the sidewall of the gate structure; forming a second sidewall on the sidewall of the first sidewall by using a first reaction source gas in an oxygen-containing ambient atmosphere; and forming a third sidewall on the sidewall of the second sidewall by using a second reaction source gas in an ambient atmosphere of a mixed gas of oxygen and helium, wherein the fluorine content in the first reaction source gas is higher than the fluorine content in the second reaction source gas.

[0009] Optionally, the step of forming the second sidewall spacer on the sidewall of the first sidewall spacer by using the first reaction source gas in an oxygen-containing atmosphere includes:

[0010] forming a second spacer material layer on the substrate, wherein the second spacer material layer conformally covers the gate structure and the first spacer;

[0011] In an oxygen-containing ambient atmosphere, the first reaction source gas is used to remove the second spacer material layer located on the top of the gate structure and a portion of the substrate, and the remaining portion of the second spacer material layer is used as the second spacer.

[0012] Optionally, the first reaction source gas includes CH2F2 and CHF3, wherein the flow rate of CH2F2 is 30 sccm to 120 sccm, and the flow rate of CHF3 is 30 sccm to 120 sccm.

[0013] Optionally, the flow ratio of CH2F2 to CHF3 is 1:1.

[0014] Optionally, the flow rate of oxygen in the oxygen-containing ambient atmosphere is 0 to 150 sccm.

[0015] Optionally, the step of forming a third sidewall spacer on the sidewall of the second sidewall spacer by using a second reaction source gas in an ambient atmosphere of a mixed gas containing oxygen and helium includes:

[0016] forming a third spacer material layer on the substrate, wherein the third spacer material layer conformally covers the gate structure, the first spacer and the second spacer;

[0017] In an atmosphere containing a mixed gas of oxygen and helium, the second reaction source gas is used to remove the third spacer material layer located on the top of the gate structure and part of the substrate, and the remaining part of the third spacer material layer is used as the third spacer.

[0018] Optionally, the second reaction source gas includes CH 3 F, wherein the flow rate of CH 3 F is 30 sccm to 200 sccm.

[0019] Optionally, in an ambient atmosphere containing a mixed gas of oxygen and helium, the flow rate of oxygen is 0 sccm to 200 sccm, and the flow rate of helium is 0 sccm to 200 sccm.

[0020] Optionally, the material of the first sidewall spacer includes silicon oxide;

[0021] The second spacer and the third spacer are made of silicon nitride.

[0022] Optionally, a barrier layer is further formed on the substrate, and the gate structure is located on the barrier layer;

[0023] In the step of forming the gate spacer, a first etching selectivity ratio between the second spacer and the barrier layer is smaller than a second etching selectivity ratio between the third spacer and the barrier layer.

[0024] Optionally, the first etching selectivity ratio is 12.1;

[0025] The second etching selectivity ratio is 112.5.

[0026] Optionally, the thickness of the barrier layer is to

[0027] Optionally, the second sidewall and the third sidewall meet one or more of the following requirements:

[0028] The surface roughness of the second sidewall spacer is greater than the surface roughness of the third sidewall spacer;

[0029] The density of the second spacer is lower than that of the third spacer.

[0030] Accordingly, an embodiment of the present invention further provides a semiconductor structure, including:

[0031] substrate;

[0032] a gate structure, located on the substrate;

[0033] A gate spacer is formed on the sidewall of the gate structure, and the gate spacer includes: a first spacer located on the sidewall of the gate structure; a second spacer located on the sidewall of the first spacer; and a third spacer located on the sidewall of the second spacer;

[0034] The second side wall is formed by using a first reaction source gas in an oxygen-containing environment; the third side wall is formed by using a second reaction source gas in an oxygen-and-helium mixed gas environment, and the fluorine content in the first reaction source gas is higher than the fluorine content in the second reaction source gas.

[0035] Optionally, the second sidewall and the third sidewall satisfy one or more of the following conditions:

[0036] The surface roughness of the second sidewall spacer is greater than the surface roughness of the third sidewall spacer;

[0037] The density of the second spacer is lower than that of the third spacer.

[0038] Compared with the existing solutions, the technical solution of the embodiment of the present invention has the following advantages:

[0039] In the method for forming a semiconductor structure provided by an embodiment of the present invention, in the step of forming a gate sidewall on the sidewall of the gate structure, the ambient atmosphere of the second sidewall and the third sidewall and the fluorine content in the second reaction source gas are different. In this way, different etching selectivity ratios can be used to form the second sidewall and the third sidewall, so that the etching stop time of the second sidewall and the third sidewall can be controlled in a larger range, thereby improving the morphology of the gate sidewall and further improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figures 1 to 6 1 is a schematic diagram of the cross-sectional structure corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0041] As can be seen from the background art, the performance of currently formed semiconductor structures needs to be improved.

[0042] Research has found that in a method for forming a semiconductor structure, a two-step sidewall etching process is used to form gate sidewalls in the form of ONON (SIO2+SIN+SIO2+SIN) on both sides of the gate structure, wherein SIO2 and SIN are formed by thermal diffusion, which increases manufacturing costs.

[0043] In another method for forming a semiconductor structure, gate sidewalls in the form of ONN (SIO2+SIN+SIN) are formed on both sides of the gate structure. The gate sidewalls are usually formed by plasma etching, which will cause silicon depressions in the substrate (or silicon damage) and reduce the smoothness of the gate sidewalls, thereby reducing the electrical performance of the semiconductor structure.

[0044] To solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a gate structure thereon; forming a gate sidewall on the sidewall of the gate structure, the steps of forming the gate sidewall comprising: forming a first sidewall on the sidewall of the gate structure; in an oxygen-containing ambient atmosphere, using a first reaction source gas to form a second sidewall on the sidewall of the first sidewall; in an ambient atmosphere containing a mixed gas of oxygen and helium, using a second reaction source gas to form a third sidewall on the sidewall of the second sidewall, wherein the fluorine content in the first reaction source gas is higher than the fluorine content in the second reaction source gas.

[0045] The present invention makes different the ambient atmosphere of the second sidewall and the fluorine content in the second reaction source gas of the third sidewall during the step of forming the gate sidewall on the sidewall of the gate structure. In this way, different etching selectivity ratios can be used to form the second sidewall and the third sidewall, so that the etching stop time of the second sidewall and the third sidewall can be controlled in a wider range, thereby improving the morphology of the gate sidewall and further improving the electrical performance of the semiconductor structure.

[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below with reference to the accompanying drawings.

[0047] Figures 1 to 6 A schematic cross-sectional view of a semiconductor structure formation process according to an embodiment of the present invention.

[0048] See also Figure 1 , providing a substrate 100 having a gate structure 104 thereon.

[0049] In this embodiment, the substrate 100 can provide a process operation basis for the formation process of a semiconductor structure (such as CMOS).

[0050] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0051] In some embodiments, the base may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate where the fins are exposed. The isolation structure may cover part of the sidewalls of the fins, and the top of the isolation structure is lower than the top of the fins.

[0052] In this embodiment, the isolation structure serves to electrically isolate adjacent fins.

[0053] In some embodiments, the isolation structure may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

[0054] In this embodiment, the material of the isolation structure may be silicon oxide.

[0055] When the device is operating, the gate structure 104 is used to control the opening and closing of the conductive channel. In this embodiment, the gate structure 104 is a metal gate structure, which may include a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0056] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 104 to an external circuit.

[0057] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0058] In this embodiment, the gate electrode layer may include one or both of a work function layer and an electrode layer.

[0059] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.

[0060] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0061] The gate electrode layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0062] In this embodiment, the material of the gate electrode layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0063] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include the gate oxide layer.

[0064] In this embodiment, the gate structure 104 is described as a metal gate structure. In other embodiments, based on actual process requirements, the gate structure 104 may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0065] In this embodiment, in the step of providing the substrate, the substrate on both sides of the gate structure further has source and drain doping regions (not shown), and the gate structure exposes the source and drain doping regions.

[0066] The source-drain doped regions can be used as the source or drain of a field effect transistor. When the device is working, the source-drain doped regions can provide carriers.

[0067] See also Figures 2 to 6 , forming a gate spacer 120 on the sidewall of the gate structure 104 .

[0068] The gate spacer 120 is used to protect the gate structure 104 to improve the formation quality of the gate structure 104 .

[0069] In this embodiment, the gate spacer 120 has a stacked structure. For example, along a direction parallel to the surface of the substrate 100, the gate spacer 120 may include a first spacer 106, a second spacer 110, and a third spacer 114 arranged in sequence. In some other embodiments, the gate spacer 120 may have a single-layer structure.

[0070] In this embodiment, see Figures 2 to 6 The step of forming the gate spacer 120 on the sidewall of the gate structure 104 includes:

[0071] See also Figure 2 , forming a first spacer 106 on the sidewall of the gate structure 104 .

[0072] The first spacer 106 is used as a portion of the gate spacer 120 to protect the gate structure 104 .

[0073] In this embodiment, the material of the first spacer 106 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0074] As an example, the material of the first spacer 106 is silicon oxide.

[0075] In this embodiment, the method of forming the first sidewall 106 includes: forming a first sidewall material layer (not shown) on the substrate 100 that conformally covers the gate structure 104; removing the first sidewall material layer on the top of the gate structure 104 and the first sidewall material layer above a portion of the substrate 100, and using the remaining portion of the first sidewall material layer as the first sidewall 106.

[0076] In this embodiment, the thickness of the first sidewall material layer is to By making the thickness of the first spacer 106 greater than A protective layer can be formed on the sidewall of the gate structure 104 to protect the gate structure 104; by making the thickness of the first spacer material layer less than or equal to This can prevent the first spacer 106 on the sidewall of the gate structure 104 from being completely consumed during the subsequent formation of the second spacer and the third spacer, thereby reducing damage to the substrate 100 .

[0077] See also Figure 3 and Figure 4 In an oxygen-containing atmosphere, a first reaction source gas is used to form a second sidewall spacer 110 on the sidewall of the first sidewall spacer 106 .

[0078] The second spacer 110 is used as a portion of the gate spacer 120 to protect the gate structure 104 .

[0079] In this embodiment, the material of the second spacer 110 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0080] As an example, the material of the second spacer 110 is silicon nitride.

[0081] In this embodiment, the step of forming the second sidewall spacer 110 on the sidewall of the first sidewall spacer 106 by using the first reaction source gas in an oxygen-containing atmosphere includes:

[0082] See also Figure 3 , a second spacer material layer 108 is formed on the substrate 100 , and the second spacer material layer 108 conformally covers the gate structure 104 and the first spacer 106 .

[0083] The second spacer material layer 108 serves as a process basis for forming the second spacer 110 .

[0084] In this embodiment, a deposition process is used to form the second spacer material layer 108 on the substrate 100 .

[0085] In a specific embodiment, an atomic layer deposition (ALD) process is used to form the second spacer material layer 108 on the substrate 100 . Through multiple ALD cycles, the thickness uniformity of the second spacer material layer 108 can be improved.

[0086] In some other embodiments, any one or more deposition processes of a chemical vapor deposition process CVD and a physical vapor deposition process PVD may be used to form the second spacer material layer.

[0087] In this embodiment, the thickness of the second spacer material layer 108 is to By making the thickness of the second spacer material layer 108 greater than A protective layer can be formed on the sidewall of the gate structure 104 to protect the gate structure 104; by making the thickness of the second spacer material layer 108 less than or equal to While meeting performance requirements, the loss of the first sidewall 106 can be reduced, thereby avoiding damage to the substrate 100 .

[0088] See also Figure 4In an oxygen-containing ambient atmosphere, the first reaction source gas is used to remove the second spacer material layer 108 located on the top of the gate structure 104 and a portion of the substrate 100 , and the remaining portion of the second spacer material layer 108 is used as the second spacer 110 .

[0089] In a specific embodiment, the first reaction source gas includes CH2F2 and CHF3, so that during the process of removing the second spacer material layer 108, the second spacer material layer 108 and the first spacer 106 have high selectivity, thereby reducing the loss of the first spacer 106.

[0090] Furthermore, when CH2F2 and CHF3 are used as etching gases, a better sidewall shape can usually be obtained, and the inclination of the sidewall can be reduced (for example, the sidewall is more vertical), thereby improving the accuracy and performance of the structure.

[0091] In this embodiment, the flow rate of CH2F2 is 30 to 120 sccm, and the flow rate of CHF3 is 30 to 120 sccm, which makes the etching process more stable and improves the stability of the etching process.

[0092] In this embodiment, the flow ratio of CH2F2 and CHF3 is 1:1. By making the flow ratio of CH2F2 and CHF3 1:1, the mixing of CH2F2 and CHF3 is more uniform, reducing the etching unevenness caused by local concentration unevenness, which helps to improve the overall etching quality; and can effectively balance the concentration of the fluorine source to reduce the risk of non-selective etching.

[0093] In some other embodiments, the flow ratio and flow rate of CH2F2 and CHF3 can be set according to actual needs, and the present invention does not impose any limitation on this.

[0094] In this embodiment, the flow rate of oxygen in the oxygen-containing ambient atmosphere is 0 to 150 sccm.

[0095] By adjusting the oxygen flow rate to 0 to 150 sccm, the chemical reactivity of the etching atmosphere can be changed, thereby increasing the etching rate. In addition, an appropriate amount of oxygen can help form more vertical sidewalls, reduce the inclination of the sidewalls, and thus improve the structural accuracy after etching.

[0096] It should be noted that when forming the second side wall 110, due to the influence of the process, the second side wall 110 is not only formed on the side wall of the first side wall 106, but can also cover part of the top surface of the first side wall 106 to form a side wall with an arc-shaped slope. This situation also falls within the protection scope of the embodiments of the present invention.

[0097] See also Figure 5 and Figure 6In an atmosphere of a mixed gas containing oxygen and helium, a second reaction source gas is used to form a third sidewall spacer 114 on the sidewall of the second sidewall spacer 110 .

[0098] The third spacer 114 is used as a portion of the gate spacer 120 to protect the gate structure 104 .

[0099] In other words, the first spacer 106 , the second spacer 110 and the third spacer 114 serve as the gate spacer 120 , and together they protect the gate structure 104 .

[0100] In this embodiment, the material of the third spacer 114 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0101] As an example, the material of the third spacer 114 is silicon nitride.

[0102] In this embodiment, the step of forming the third sidewall spacer 114 on the sidewall of the second sidewall spacer 110 by using the second reaction source gas in an atmosphere of a mixed gas containing oxygen and helium includes:

[0103] A third spacer material layer 112 is formed on the substrate 100 . The third spacer material layer 112 conformally covers the gate structure 104 , the first spacer 106 , and the third spacer 114 .

[0104] The third spacer material layer 112 serves as a process basis for forming the third spacer 114 .

[0105] In this embodiment, a deposition process is used to form the third spacer material layer 112 on the substrate 100 .

[0106] In a specific embodiment, an atomic layer deposition (ALD) process is used to form the third spacer material layer 112 on the substrate 100 . Through multiple ALD cycles, the thickness uniformity of the third spacer material layer 112 can be improved.

[0107] In some other embodiments, any one or more deposition processes of a chemical vapor deposition process CVD and a physical vapor deposition process PVD may be used to form the third spacer material layer.

[0108] In this embodiment, the thickness of the third spacer material layer 112 is to By making the thickness of the third sidewall 114 greater than or equal to A protective layer can be formed on the sidewall of the gate structure 104 to protect the gate structure 104; by making the thickness of the third sidewall 114 less than or equal to While meeting performance requirements, the loss of the second sidewall 110 can be reduced, thereby avoiding damage to the substrate 100 .

[0109] See also Figure 6 In an ambient atmosphere of a mixed gas containing oxygen and helium, the second reaction source gas is used to remove the third spacer material layer 112 located on the top of the gate structure 104 and part of the substrate 100, and the remaining part of the third spacer material layer 112 is used as the third spacer 114.

[0110] In a specific embodiment, the second reaction source gas includes CH3F. Thus, during the process of removing the third spacer material layer 112, the third spacer material layer 112 and the first spacer 106 or the substrate 100 have high selectivity, thereby reducing the loss of the first spacer 106 or the substrate 100. In addition, the chemical properties of CH3F are relatively mild, which can reduce damage to the semiconductor structure and improve electrical performance and mechanical strength.

[0111] In addition, CH3F gas decomposes into CHx, F, and H+ in plasma. The ionic radical can break the Si-O bond, which requires the CFx group to react with Si to form a volatile by-product. However, the F ion concentration in CH3F plasma is low, and CFx easily reacts with Si-O to form Si-O-CHx. This polymer is thinner on silicon nitride, but forms very thick on silicon oxide, preventing further reaction.

[0112] In this embodiment, the flow rate of CH3F is 30 sccm to 200 sccm. By setting the flow rate of CH3F to 30 sccm to 200 sccm, the supply speed of CH3F is appropriate, which reduces the etching non-uniformity caused by local concentration non-uniformity and helps to improve the overall etching quality.

[0113] In this embodiment, in an ambient atmosphere containing a mixed gas of oxygen and helium, the flow rate of oxygen is 0 sccm to 200 sccm, and the flow rate of helium is 0 sccm to 200 sccm. By setting the flow rates of oxygen and helium, the etching process can be improved by diluting and improving the flow direction of the etching gas, thereby improving the effect and quality of the etching process.

[0114] It should be noted that when forming the third side wall 114, due to the influence of the process, the third side wall 114 is not only formed on the side wall of the second side wall 110, but can also cover part of the top surface of the second side wall 110 to form a side wall with an arc-shaped slope. This situation also falls within the protection scope of the embodiments of the present invention.

[0115] In this embodiment, the fluorine content in the first reaction source gas is higher than the fluorine content in the second reaction source gas. By making the fluorine content in the two steps different, the etching selectivity ratio can be changed, and the fluorine content in the second reaction source gas is less than the fluorine content in the first reaction source gas, which can reduce the etching rate for forming the third side wall, and can improve the etching selectivity and reduce damage to the film layer, for example, reducing damage to the substrate or the first side wall.

[0116] In this embodiment, the second side wall 110 and the third side wall 114 meet the following conditions: the surface roughness of the second side wall 110 is greater than the surface roughness of the third side wall 114. By making the surface roughness of the second side wall 110 greater, the adhesion of the surface of the second side wall 110 can be increased, which is conducive to reducing the difficulty of forming the third side wall 114.

[0117] Furthermore, the density of the second spacer 110 is lower than that of the third spacer 114 , which improves the formation quality of the gate spacer 120 , making the gate structure 104 more capable of controlling the channel and improving the switching characteristics of the device.

[0118] In this embodiment, the density of the third sidewall spacer 114 can be improved by increasing the temperature and / or pressure in the reaction chamber.

[0119] In a non-limiting example, when forming the second spacer 110 , the corresponding pressure is 30 mt to 40 mt, and when forming the third spacer 114 , the corresponding pressure is 50 mt to 60 mt.

[0120] During the actual manufacturing process, the inventors found that the thickness of SiO2 is relatively thin. During etching, there is a possibility that SiO2 is consumed or almost consumed, and the etching ions diffuse through SiO2 to the substrate surface, which will cause damage to the substrate surface.

[0121] For example, if the etching ions are oxygen ions, when the oxygen ions diffuse through SiO2 to the surface of the substrate, they will combine with the substrate to form new SiO2, resulting in silicon depressions at the interface between the substrate and the new SiO2, seriously reducing the performance of the semiconductor structure.

[0122] Based on this, see Figure 1 In the step of providing the substrate 100 , a barrier layer 102 is further formed on the substrate 100 , and the gate structure 104 is located on the barrier layer 102 .

[0123] The barrier layer 102 plays a role in protecting the surface of the substrate 100 , so that the surface of the substrate 100 is not affected by other substances (such as reaction source gases) during the process of forming the gate spacer 120 .

[0124] In this embodiment, a deposition process is used to form the barrier layer 102 on the substrate 100 .

[0125] In a specific embodiment, the barrier layer 102 is formed on the substrate 100 by using an atomic layer deposition (ALD) process. The thickness uniformity of the barrier layer 102 can be improved by performing multiple ALD cycles.

[0126] In some other embodiments, any one or more deposition processes of a chemical vapor deposition process CVD and a physical vapor deposition process PVD may be used to form the barrier layer.

[0127] In this embodiment, the material of the barrier layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0128] As an example, the material of the barrier layer 102 is silicon oxide.

[0129] In this embodiment, the thickness of the barrier layer 102 is to By making the thickness of the barrier layer 102 greater than or equal to In the step of forming the gate sidewall 120, the barrier layer 102 can always cover the surface of the substrate 100 to protect the substrate 100; by making the thickness of the barrier layer 102 less than or equal to While meeting performance requirements, the overall height of the semiconductor structure can be reduced, miniaturization of the semiconductor structure can be achieved, and resistance can be reduced, thereby improving the electrical performance of the semiconductor structure.

[0130] In this embodiment, when a barrier layer 102 is also formed on the substrate 100, in the step of forming the gate sidewall 120, the first etching selectivity ratio between the second sidewall 110 and the barrier layer 102 is less than the second etching selectivity ratio between the third sidewall 114 and the barrier layer 102. In this way, in the step of forming the third sidewall 114, the selectivity between the third sidewall 114 and the barrier layer 102 can be further increased, and the consumption of the barrier layer 102 can be reduced, so that the substrate 100 is always in a protected state, and the probability of damage to the substrate 100 is reduced.

[0131] In a specific embodiment, the first etching selectivity is 12.1. Thus, in the step of forming the second sidewall 110, by setting the etching selectivity between the second sidewall 110 and the barrier layer 102 to 12.1, damage to the barrier layer 102 can be reduced during the removal of the second sidewall 110, thereby reducing damage to the substrate 100, improving the morphology quality of the substrate 100, and thereby improving the performance of the formed semiconductor structure.

[0132] In a specific embodiment, the second etching selectivity is 112.5. Thus, in the step of forming the third sidewall spacer 114, by making the etching selectivity between the third sidewall spacer 114 and the barrier layer 102 112.5, the damage to the barrier layer 102 can be reduced during the process of removing the third sidewall spacer 114, thereby reducing the damage to the substrate 100, improving the morphology quality of the substrate 100, and thus improving the performance of the formed semiconductor structure.

[0133] It should be noted that, in the step of forming the third sidewall spacer 114 , a portion of the barrier layer 102 will be consumed, so that the actual thickness of the barrier layer 102 is smaller than the original thickness of the barrier layer 102 .

[0134] The embodiment of the present invention further provides a semiconductor structure, such as Figure 6 As shown, the semiconductor structure may include: a substrate 100; a gate structure 104, located on the substrate 100; a gate spacer 120, formed on the sidewall of the gate structure 104, and the gate spacer 120 includes: a first spacer 106, located on the sidewall of the gate structure 104; a second spacer 110, located on the sidewall of the first spacer 106; and a third spacer 114, located on the sidewall of the second spacer 110.

[0135] In this embodiment, the substrate 100 can provide a process operation basis for the formation process of a semiconductor structure (such as CMOS).

[0136] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0137] In some embodiments, the base may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate where the fins are exposed. The isolation structure may cover part of the sidewalls of the fins, and the top of the isolation structure is lower than the top of the fins.

[0138] In this embodiment, the isolation structure serves to electrically isolate adjacent fins.

[0139] In some embodiments, the isolation structure may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

[0140] In this embodiment, the material of the isolation structure may be silicon oxide.

[0141] When the device is operating, the gate structure 104 is used to control the opening and closing of the conductive channel. In this embodiment, the gate structure 104 is a metal gate structure, which may include a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0142] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 104 to an external circuit.

[0143] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0144] In this embodiment, the gate electrode layer may include one or both of a work function layer and an electrode layer.

[0145] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.

[0146] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0147] The gate electrode layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0148] In this embodiment, the material of the gate electrode layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0149] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include the gate oxide layer.

[0150] In this embodiment, the gate structure 104 is described as a metal gate structure. In other embodiments, based on actual process requirements, the gate structure 104 may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0151] In this embodiment, in the step of providing the substrate, the substrate on both sides of the gate structure further has source and drain doping regions (not shown), and the gate structure exposes the source and drain doping regions.

[0152] The source-drain doped region can be used as the source or drain of a field effect transistor. When the device is working, the source-drain doped region can provide a carrier source.

[0153] The gate spacer 120 is used to protect the gate structure 104 to improve the formation quality of the gate structure 104 .

[0154] In this embodiment, the gate spacer 120 is a stacked structure. For example, along a direction parallel to the surface of the substrate 100, the gate spacer 120 may include a first spacer 106, a second spacer 110, and a third spacer 114 arranged in sequence. In some other embodiments, the gate spacer may be a single-layer structure.

[0155] In this embodiment, the material of the first spacer 106 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0156] As an example, the material of the first spacer 106 is silicon oxide.

[0157] In this embodiment, the material of the second spacer 110 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0158] As an example, the material of the second spacer 110 is silicon nitride.

[0159] In this embodiment, the second sidewall spacer 110 is formed in an oxygen-containing atmosphere using the first reaction source gas. The specific formation process of the second sidewall spacer 110 can refer to the above example.

[0160] It should be noted that when forming the second side wall 110, due to the influence of the process, the second side wall 110 is not only formed on the side wall of the first side wall 106, but can also cover part of the top surface of the first side wall 106 to form a side wall with an arc-shaped slope. This situation also falls within the protection scope of the embodiments of the present invention.

[0161] In this embodiment, the material of the third spacer 114 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0162] As an example, the material of the third spacer 114 is silicon nitride.

[0163] In this embodiment, the third sidewall spacer 114 is formed in an atmosphere of a mixed gas containing oxygen and helium using the second reaction source gas. The specific formation process of the third sidewall spacer 114 can refer to the above example.

[0164] It should be noted that when forming the third side wall 114, due to the influence of the process, the third side wall 114 is not only formed on the side wall of the second side wall 110, but can also cover part of the top surface of the second side wall 110 to form a side wall with an arc-shaped slope. This situation also falls within the protection scope of the embodiments of the present invention.

[0165] In this embodiment, the fluorine content in the first reaction source gas is higher than the fluorine content in the second reaction source gas. By making the fluorine content in the two steps different, the etching selectivity ratio can be changed, and the fluorine content in the second reaction source gas is less than the fluorine content in the first reaction source gas, which can reduce the etching rate for forming the third side wall, and can improve the etching selectivity and reduce damage to the film layer, for example, reducing damage to the substrate or the first side wall.

[0166] In this embodiment, the surface roughness of the second sidewall 110 is greater than that of the third sidewall 114 . By making the surface roughness of the second sidewall 110 greater, the adhesion of the surface of the second sidewall 110 can be increased, which is conducive to reducing the difficulty of forming the third sidewall 114 .

[0167] Furthermore, the density of the second spacer 110 is lower than that of the third spacer 114 , which improves the formation quality of the gate spacer 120 , making the gate structure 104 more capable of controlling the channel and improving the switching characteristics of the device.

[0168] In this embodiment, the density of the third sidewall spacer 114 can be improved by increasing the temperature and / or pressure in the reaction chamber.

[0169] In a non-limiting example, when forming the second spacer 110 , the corresponding pressure is 30 mt to 40 mt, and when forming the third spacer 114 , the corresponding pressure is 50 mt to 60 mt.

[0170] Optionally, the semiconductor structure may further include: a barrier layer 102 located on the substrate 100 , and the gate structure 104 located on the barrier layer 102 .

[0171] The barrier layer 102 plays a role in protecting the surface of the substrate 100 , so that the surface of the substrate 100 is not affected by other substances (such as reaction source gases) during the process of forming the gate spacer 120 .

[0172] In this embodiment, the material of the barrier layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0173] As an example, the material of the barrier layer 102 is silicon oxide.

[0174] In this embodiment, the thickness of the barrier layer 102 is to By making the thickness of the barrier layer 102 greater than or equal to In the step of forming the gate sidewall 120, the barrier layer 102 can always cover the surface of the substrate 100 to protect the substrate 100; by making the thickness of the barrier layer 102 less than or equal to While meeting performance requirements, the overall height of the semiconductor structure can be reduced, miniaturization of the semiconductor structure can be achieved, and resistance can be reduced, thereby improving the electrical performance of the semiconductor structure.

[0175] In this embodiment, when a barrier layer 102 is also formed on the substrate 100, in the step of forming the gate sidewall 120, the first etching selectivity ratio between the second sidewall 110 and the barrier layer 102 is less than the second etching selectivity ratio between the third sidewall 114 and the barrier layer 102. In this way, in the step of forming the third sidewall 114, the selectivity between the third sidewall 114 and the barrier layer 102 can be further increased, and the consumption of the barrier layer 102 can be reduced, so that the substrate 100 is always in a protected state, and the probability of damage to the substrate 100 is reduced.

[0176] In a specific embodiment, the first etching selectivity is 12.1. Thus, in the step of forming the second sidewall 110, by setting the etching selectivity between the second sidewall 110 and the barrier layer 102 to 12.1, damage to the barrier layer 102 can be reduced during the removal of the second sidewall 110, thereby reducing damage to the substrate 100, improving the morphology quality of the substrate 100, and thereby improving the performance of the formed semiconductor structure.

[0177] In a specific embodiment, the second etching selectivity is 112.5. Thus, in the step of forming the third sidewall spacer 114, by making the etching selectivity between the third sidewall spacer 114 and the barrier layer 102 112.5, the damage to the barrier layer 102 can be reduced during the process of removing the third sidewall spacer 114, thereby reducing the damage to the substrate 100, improving the morphology quality of the substrate 100, and thus improving the performance of the formed semiconductor structure.

[0178] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a gate structure; A gate sidewall is formed on the sidewall of the gate structure, and the steps of forming the gate sidewall include: forming a first sidewall on the sidewall of the gate structure; forming a second sidewall on the sidewall of the first sidewall by using a first reaction source gas in an oxygen-containing ambient atmosphere; and forming a third sidewall on the sidewall of the second sidewall by using a second reaction source gas in an ambient atmosphere of a mixed gas of oxygen and helium, wherein the fluorine content in the first reaction source gas is higher than the fluorine content in the second reaction source gas.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the second sidewall spacer on the sidewall of the first sidewall spacer by using the first reaction source gas in an oxygen-containing ambient atmosphere includes: forming a second spacer material layer on the substrate, wherein the second spacer material layer conformally covers the gate structure and the first spacer; In an oxygen-containing ambient atmosphere, the first reaction source gas is used to remove the second spacer material layer located on the top of the gate structure and a portion of the substrate, and the remaining portion of the second spacer material layer is used as the second spacer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The first reaction source gas includes CH2F2 and CHF3, wherein the flow rate of CH2F2 is 30 sccm to 120 sccm, and the flow rate of CHF3 is 30 sccm to 120 sccm.

4. The method for forming a semiconductor structure according to claim 3, wherein: The flow ratio of CH2F2 and CHF3 is 1:

1.

5. The method for forming a semiconductor structure according to claim 1, wherein: The flow rate of oxygen in the oxygen-containing ambient atmosphere is 0 sccm to 150 sccm.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a third sidewall spacer on the sidewall of the second sidewall spacer by using a second reaction source gas in an atmosphere of a mixed gas containing oxygen and helium comprises: forming a third spacer material layer on the substrate, wherein the third spacer material layer conformally covers the gate structure, the first spacer and the second spacer; In an atmosphere containing a mixed gas of oxygen and helium, the second reaction source gas is used to remove the third spacer material layer located on the top of the gate structure and part of the substrate, and the remaining part of the third spacer material layer is used as the third spacer.

7. The method for forming a semiconductor structure according to claim 5, wherein: The second reaction source gas includes CH 3 F, wherein the flow rate of CH 3 F is 30 sccm to 200 sccm.

8. The method for forming a semiconductor structure according to claim 1, wherein: In an ambient atmosphere containing a mixed gas of oxygen and helium, the flow rate of oxygen is 0 sccm to 200 sccm, and the flow rate of helium is 0 sccm to 200 sccm.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first sidewall spacer includes silicon oxide; The second spacer and the third spacer are made of silicon nitride.

10. The method for forming a semiconductor structure according to claim 1, wherein: A barrier layer is also formed on the substrate, and the gate structure is located on the barrier layer; In the step of forming the gate spacer, a first etching selectivity ratio between the second spacer and the barrier layer is smaller than a second etching selectivity ratio between the third spacer and the barrier layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The first etching selectivity ratio is 12.1; The second etching selectivity ratio is 112.

5.

12. The method for forming a semiconductor structure according to claim 11, wherein: The thickness of the barrier layer is to 13. The method for forming a semiconductor structure according to claim 1, wherein: The second sidewall and the third sidewall meet one or more of the following requirements: The surface roughness of the second sidewall spacer is greater than the surface roughness of the third sidewall spacer; The density of the second spacer is lower than that of the third spacer.

14. A semiconductor structure, characterized in that include: substrate; a gate structure, located on the substrate; A gate spacer is formed on the sidewall of the gate structure, and the gate spacer includes: a first spacer located on the sidewall of the gate structure; a second spacer located on the sidewall of the first spacer; and a third spacer located on the sidewall of the second spacer; The second side wall is formed by using a first reaction source gas in an oxygen-containing environment; the third side wall is formed by using a second reaction source gas in an oxygen-and-helium mixed gas environment, and the fluorine content in the first reaction source gas is higher than the fluorine content in the second reaction source gas.

15. The semiconductor structure according to claim 14, wherein: The second sidewall and the third sidewall satisfy one or more of the following requirements: The surface roughness of the second sidewall spacer is greater than the surface roughness of the third sidewall spacer; The density of the second spacer is lower than that of the third spacer.

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