Integrated circuit device and method of manufacturing the same

Abstract

Integrated circuit devices and methods of manufacturing the same are provided. The integrated circuit device includes a first semiconductor substrate having a front side surface and a back side surface; the FEOL structure is located on the surface of the front side of the first semiconductor substrate, and the FEOL structure comprises a plurality of fin type active regions; a first subsequent process BEOL structure, wherein the first BEOL structure is located on the FEOL structure; a second BEOL structure on a back side surface of the first semiconductor substrate; and a second semiconductor substrate, the second semiconductor substrate being spaced apart from the first semiconductor substrate in a vertical direction in such a manner that the FEOL structure and the first BEOL structure are located between the second semiconductor substrate and the first semiconductor substrate, a Young's modulus of a first crystal orientation extending parallel to the front side surface in the first semiconductor substrate is different from a Young's modulus of a second crystal orientation overlapping the first crystal orientation in the vertical direction and extending parallel to the first crystal orientation in the second semiconductor substrate.

Description

Technical Field

[0001] The inventive concept relates to an integrated circuit (IC) device and a method of manufacturing the same, and more particularly to an IC device having a back side power supply network (BSPDN) structure having a wiring structure formed on a back side of a substrate and a method of manufacturing the IC device. Background Art

[0002] Due to the development of electronic technology, the downscaling of IC devices has been rapidly progressing. Therefore, research is being conducted to efficiently design wiring structures to achieve high integration while ensuring the functions and operating speeds required by IC devices. In addition, in IC devices manufactured by using single-crystal semiconductor substrates, as the semiconductor substrate gradually becomes thinner and the size of the pattern to be formed on the semiconductor substrate becomes smaller, the overlap consistency of the patterns formed at different vertical heights deteriorates. Therefore, even when the semiconductor substrate gradually becomes thinner and the size of the pattern to be formed on the semiconductor substrate becomes smaller, it is desirable to develop an IC device with a structure having excellent overlay consistency and a method for manufacturing the IC device. Summary of the invention

[0003] The present invention is conceived to provide an integrated circuit (IC) device having a structure capable of minimizing distortion of a semiconductor substrate and overlay errors of patterns formed at different vertical heights on the semiconductor substrate even when the semiconductor substrate gradually becomes thinner and the size of the patterns to be formed on the semiconductor substrate becomes smaller.

[0004] The present invention also provides a method for manufacturing IC devices, which can improve the critical dimension (CD) uniformity of patterns required for manufacturing IC devices and enable the manufacture of reliable IC devices by minimizing process failures caused by warping of the semiconductor substrate and overlay errors in patterns at different vertical heights formed on the semiconductor substrate, even when the semiconductor substrate gradually becomes thinner and the size of the pattern to be formed on the semiconductor substrate becomes smaller.

[0005] According to one aspect of the inventive concept, an IC device is provided, the IC device comprising: a first semiconductor substrate, the first semiconductor substrate having a front side surface and a back side surface opposite to each other; a front end of line (FEOL) structure, the FEOL structure being located on the front side surface of the first semiconductor substrate, the FEOL structure comprising a plurality of fin-type active regions; a first back end of line (BEOL) structure, the first BEOL structure being located on the FEOL structure, the first BEOL structure being spaced apart from the first semiconductor substrate in a vertical direction in such a manner that the FEOL structure is located between the first BEOL structure and the first semiconductor substrate; a second BEOL structure, the second BEOL structure being located on the front side surface of the first semiconductor substrate, the FEOL structure comprising a plurality of fin-type active regions; a first back end of line (BEOL) structure, the first BEOL structure being located on the FEOL structure, the first BEOL structure being spaced apart from the first semiconductor substrate in a vertical direction in such a manner that the FEOL structure is located between the first BEOL structure and the first semiconductor substrate; and a second BEOL structure, the second BEOL structure being located on the front side surface of the first semiconductor substrate. On the backside surface of the first semiconductor substrate, the second BEOL structure is spaced apart from the FEOL structure in the vertical direction in such a manner that the first semiconductor substrate is located between the second BEOL structure and the FEOL structure; and a second semiconductor substrate, the second semiconductor substrate is spaced apart from the first semiconductor substrate in the vertical direction in such a manner that the FEOL structure and the first BEOL structure are located between the second semiconductor substrate and the first semiconductor substrate, wherein the Young's modulus of a first crystal direction extending parallel to the frontside surface in the first semiconductor substrate is different from the Young's modulus of a second crystal direction in the second semiconductor substrate that overlaps with the first crystal direction in the vertical direction and extends parallel to the first crystal direction.

[0006] According to another aspect of the inventive concept, an IC device is provided, the IC device comprising: a first semiconductor substrate, the first semiconductor substrate having a front side surface and a back side surface opposite to each other; a FEOL structure, the FEOL structure being located on the front side surface of the first semiconductor substrate, the FEOL structure constituting a logic unit; a first BEOL structure, the first BEOL structure being located on the FEOL structure, the first BEOL structure being spaced apart from the first semiconductor substrate in a vertical direction in a manner that the FEOL structure is located between the first BEOL structure and the first semiconductor substrate; a second BEOL structure, the second BEOL structure being located on the back side surface of the first semiconductor substrate, the second BEOL structure being spaced apart from the FEOL structure in a vertical direction in a manner that the first semiconductor substrate is located between the second BEOL structure and the FEOL structure; and a second semiconductor substrate, the second semiconductor substrate being spaced apart from the first semiconductor substrate in a vertical direction in a manner that the FEOL structure and the first BEOL structure are located between the second semiconductor substrate and the first semiconductor substrate, wherein the FEOL structure comprises: a fin-type active region, the fin-type active region being integrally formed connected to the first semiconductor substrate; a source / drain region, the source / drain region is located on the fin-type active region, the source / drain region is spaced apart from the first semiconductor substrate in a vertical direction in a manner that the fin-type active region is located between the source / drain region and the first semiconductor substrate; a source / drain contact, the source / drain contact is spaced apart from the first semiconductor substrate in a vertical direction in a manner that the fin-type active region and the source / drain region are located between the source / drain contact and the first semiconductor substrate, the source / drain contact is connected to the source / drain region; a power rail wiring, the power rail wiring is spaced apart from the first semiconductor substrate in a vertical direction and a contact structure having one end connected to a selected one of a source / drain region and a source / drain contact and another end connected to a power rail wiring, wherein the second BEOL structure includes a wiring layer located on a backside surface of the first semiconductor substrate, the wiring layer connected to the power rail wiring, and wherein a Young's modulus of a first crystal direction extending parallel to the frontside surface in the first semiconductor substrate is different from a Young's modulus of a second crystal direction in the second semiconductor substrate that overlaps the first crystal direction in a vertical direction and extends parallel to the first crystal direction.

[0007] According to another aspect of the inventive concept, an IC device is provided, the IC device comprising: a first semiconductor substrate, the first semiconductor substrate having a front side surface and a back side surface opposite to each other; a FEOL structure, the FEOL structure comprising a fin-type active region, a gate line, and at least one nanosheet, the fin-type active region being integrally connected to the first semiconductor substrate, the gate line being located above the fin-type active region, and the at least one nanosheet being surrounded by the gate line between the fin-type active region and the gate line; a first BEOL structure, the first BEOL structure being located on the FEOL structure, the first BEOL structure being spaced apart from the first semiconductor substrate in a vertical direction in such a manner that the FEOL structure is located between the first BEOL structure and the first semiconductor substrate, and the first BEOL structure comprising a front side wiring structure; a second BEOL structure, the second BEOL structure being located on the back side surface of the first semiconductor substrate, the first BEOL structure being located on the back side surface of the first semiconductor substrate, and the second BEOL structure being located on the back side surface of the first semiconductor substrate. The second BEOL structure is spaced apart from the FEOL structure in a vertical direction in such a manner that the first semiconductor substrate is located between the second BEOL structure and the FEOL structure, and the second BEOL structure includes a backside wiring structure; and a second semiconductor substrate, the second semiconductor substrate is spaced apart from the first semiconductor substrate in a vertical direction in such a manner that the FEOL structure and the first BEOL structure are located between the second semiconductor substrate and the first semiconductor substrate, wherein a front side surface of the first semiconductor substrate has a (100) crystal plane, wherein a main surface of the second semiconductor substrate facing the first semiconductor substrate has a (100) crystal plane or a (111) crystal plane, and wherein a Young's modulus of a first crystal direction extending parallel to the front side surface in the first semiconductor substrate is different from a Young's modulus of a second crystal direction in the second semiconductor substrate that overlaps with the first crystal direction in a vertical direction and extends parallel to the first crystal direction.

[0008] According to another aspect of the inventive concept, a method for manufacturing an IC device is provided. The method includes: preparing a first semiconductor substrate, the first semiconductor substrate having a front side surface and a back side surface opposite to the front side surface, the front side surface having a (100) crystal plane. A FEOL structure is formed on the front side surface of the first semiconductor substrate. A first BEOL structure is formed on the FEOL structure. A bonding layer is formed on the first BEOL structure. The first BEOL structure is bonded to a second semiconductor substrate by using the bonding layer so that the second semiconductor substrate faces the first semiconductor substrate in a vertical direction. The Young's modulus of the second semiconductor substrate is different from the Young's modulus of the first semiconductor substrate. When the first BEOL structure is being bonded to the second semiconductor substrate, the first semiconductor substrate is polished from the back side surface of the first semiconductor substrate to reduce the thickness of the first semiconductor substrate. When the first BEOL structure is being bonded to the second semiconductor substrate, a second BEOL structure is formed on the polished back side surface of the first semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a top view of a unit block of an integrated circuit (IC) device according to an example embodiment;

[0011] Figure 2 is a cross-sectional view of an IC device according to an example embodiment;

[0012] Figure 3A Can be used to form Figure 2 A top view of an example of a first wafer of a first semiconductor substrate is shown;

[0013] Figure 3B Can be used to form Figure 2 A top view of an example of a second wafer of a second semiconductor substrate is shown;

[0014] Figure 4A is based on Figure 3A a graph of Young's modulus of the crystal orientation of the first wafer shown;

[0015] Figure 4B is based on Figure 4A An enlarged view of the Young's modulus of the crystal directions in a local area of ​​the first wafer is shown;

[0016] Figure 5A is based on Figure 3B a graph of Young's modulus of the crystal orientation of the second wafer shown;

[0017] Figure 5B is based on Figure 5A An enlarged view of the Young's modulus of the crystal directions in a local area of ​​the second wafer is shown;

[0018] Fig. 6A Can be used to form Figure 2 A top view of another example of a first wafer of a first semiconductor substrate is shown;

[0019] Figure 6B Can be used to form Figure 2 A top view of another example of a second wafer of a second semiconductor substrate is shown;

[0020] Figure 7 is based on Figure 6B a graph of Young's modulus of the crystal orientation of the second wafer shown;

[0021] Fig. 8A is a plan layout diagram of a partial area of ​​an IC device according to an example embodiment;

[0022] Figure 8B It is along Fig. 8AA cross-sectional view taken along the line X1-X1';

[0023] Figure 8C It is along Fig. 8A A cross-sectional view taken along the line Y1-Y1';

[0024] Fig.8D It is along Fig. 8A A cross-sectional view taken along line Y2-Y2';

[0025] Fig.9A is a plan layout diagram of a partial area of ​​an IC device according to an example embodiment;

[0026] Fig. 9B It is along Fig.9A A cross-sectional view taken along line X4-X4';

[0027] Fig. 9C It is along Fig.9A A cross-sectional view taken along line Y4-Y4';

[0028] Fig.10 is a flowchart of a method of manufacturing an IC device according to an example embodiment; and

[0029] FIG. 11A to FIG. 11F are cross-sectional views illustrating a process sequence of a method of manufacturing an IC device according to example embodiments. DETAILED DESCRIPTION

[0030] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used to denote the same elements, and repeated descriptions thereof are omitted.

[0031] It should be understood that when an element is referred to as being "connected" or "coupled" to another element or being "on" another element, it can be directly connected or coupled to another element or "on" another element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as being "contacting" or "in contact with" another element (or any form of the word "contacting"), there are no intervening elements at the point of contact.

[0032] Terms such as "same," "equal," "planar," or "coplanar" as used herein in reference to orientation, layout, position, shape, size, amount, or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, amount, or other measurement, but are intended to encompass nearly the same orientation, layout, position, shape, size, amount, or other measurement within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0033] For ease of description, spatially relative terms such as "under ...", "below ...", "below ...", "above ...", "on ...", etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the various figures. It should be understood that, in addition to the orientations depicted in the various figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the various figures is turned over, the element described as "under" or "below" other elements or features would then be oriented "above" other elements or features. Therefore, the term "under ..." can cover both orientations of above ..." and below ...". The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein are interpreted accordingly.

[0034] As used herein, the term "integrally connected" may refer to structures, patterns, and / or layers that are formed simultaneously and from the same material without interruption in the continuity of the materials forming them. As an example, an "integrally connected" structure, pattern, and / or layer may be a homogenous monolithic structure.

[0035] Figure 1 is a top view of a cell block 12 of an integrated circuit (IC) device 10 according to an example embodiment.

[0036] refer to Figure 1 The cell block 12 of the IC device 10 may include a plurality of cells LC including circuit patterns configured to constitute various circuits. In the cell block 12, the plurality of cells LC may be arranged along a width or a first lateral direction ( Figure 1 X direction) and height or second lateral direction ( Figure 1 The first lateral direction (X direction) and the second lateral direction (Y direction) may be perpendicular to each other and may be aligned with the semiconductor substrate (e.g., Figure 2 The top surface of the first semiconductor substrate 102 or the second semiconductor substrate 104 is parallel to the top surface of the first semiconductor substrate 102 or the second semiconductor substrate 104.

[0037] Each of the plurality of cells LC may constitute a logic cell. Each of the plurality of cells LC may include a circuit pattern having a layout designed according to a layout and routing (PnR) technology to perform at least one logic function. The plurality of cells LC may perform various logic functions. In an embodiment, the plurality of cells LC may include a plurality of standard cells, respectively. In an embodiment, at least some of the plurality of cells LC may perform the same logic function. In other embodiments, at least some of the plurality of cells LC may perform different logic functions.

[0038] The plurality of cells LC may include various types of cells having a plurality of circuit elements. For example, each of the plurality of cells LC may include AND, NAND, OR, NOR, XOR, XNOR, INV, ADD, BUF, DLY, FIL, MUX (MXT / MXIT), OR / AND / Inverter (OAI), AND / OR (AO), AND / OR / Inverter (AOI), D-type flip-flop, reset flip-flop, master-slave flip-flop, latch, or a combination thereof, but is not limited thereto.

[0039] In the unit block 12, in the first lateral direction ( Figure 1 At least some of the plurality of cells LC forming one row R01, R02, R03, R04, R05, or R06 in the X direction (in the X direction) may have the same width as each other. In addition, at least some of the plurality of cells LC forming one row R01, R02, R03, R04, R05, or R06 may have the same height as each other. However, the inventive concept is not limited to Figure 1 , and at least some of the plurality of cells LC forming one row R01, R02, R03, R04, R05, or R06 may have different widths and heights from each other.

[0040] The area of ​​each of the plurality of cells LC included in the cell block 12 of the IC device 10 may be defined by a cell boundary CBD. Figure 1 X direction) or the second lateral direction ( Figure 1 A cell boundary contact portion CBC where cell boundaries CBD of two cells LC adjacent to each other in the Y direction (in the Y direction of FIG. 4 ) meet each other may be located between the two adjacent cells LC.

[0041] In an embodiment, two cell LCs adjacent to each other in the first lateral direction (X direction) from among the plurality of cell LCs forming one row R01, R02, R03, R04, R05, or R06 may contact each other at the cell boundary contact portion CBC without a distance therebetween. In other embodiments, two cell LCs adjacent to each other in the first lateral direction (X direction) from among the plurality of cell LCs forming one row R01, R02, R03, R04, R05, or R06 may be spaced apart from each other by a predetermined distance.

[0042] In an embodiment, from among the plurality of cells LC forming one row R01, R02, R03, R04, R05, or R06, two adjacent cells LC may perform the same function as each other. In this case, the two adjacent cells LC may have the same structure as each other. In other embodiments, from among the plurality of cells LC forming one row R01, R02, R03, R04, R05, or R06, two adjacent cells may perform different functions from each other.

[0043] In an embodiment, one cell LC selected from a plurality of cells LC included in the cell block 12 of the IC device 10 may have a width that is different from that in the second lateral direction ( Figure 1 The reference logic cell LC_R in the third row R03 may have a structure symmetrical with another cell LC adjacent to the selected cell LC in the Y direction of the reference logic cell LC_R with respect to the cell boundary contact portion CBC therebetween. For example, the reference logic cell LC_R in the third row R03 may have a structure symmetrical with the lower logic cell LC_L in the second row R02 with respect to the cell boundary contact portion CBC therebetween. In addition, the reference logic cell LC_R in the third row R03 may have a structure symmetrical with the upper logic cell LC_H in the fourth row R04 with respect to the cell boundary contact portion CBC therebetween.

[0044] although Figure 1 An example in which the cell block 12 includes six rows R01, R02, R03, R04, R05, and R06 is illustrated, but the inventive concept is not limited thereto. The cell block 12 may include various other numbers of rows selected as needed, and one row may include various numbers of logic cells selected as needed.

[0045] A selected one of a plurality of ground lines VSS and a plurality of power lines VDD may be located between a plurality of rows (eg, R01, R02, R03, R04, R05, and R06), each of the plurality of rows including a plurality of ground lines VSS and a plurality of power lines VDD along a first lateral direction ( Figure 1 A plurality of logic cells LC are arranged in a row in a first lateral direction (X direction). A plurality of ground lines VSS and a plurality of power lines VDD may each be connected in a first lateral direction ( Figure 1 The X direction of the Figure 1Therefore, the plurality of ground lines VSS and the plurality of power lines VDD may each overlap the cell boundary CBD of the cell LC in the second lateral direction (the Y direction).

[0046] Figure 2 is a cross-sectional view of an IC device 100 according to an example embodiment. Figure 2 The components of the IC device 100 described may constitute Figure 1 Some of the plurality of cell LCs are shown.

[0047] refer to Figure 2 , the IC device 100 may include a first semiconductor substrate 102 and a second semiconductor substrate 104 overlapping each other in a vertical direction (Z direction). The first semiconductor substrate 102 may have a front side surface 102F and a back side surface 102B opposite to each other. The second semiconductor substrate 104 may have a main surface 104A facing the front side surface 102F of the first semiconductor substrate 102. Each of the first semiconductor substrate 102 and the second semiconductor substrate 104 may be formed of a semiconductor substrate (e.g., a silicon substrate) or include a semiconductor substrate (e.g., a silicon substrate). The vertical direction (Z direction) may be perpendicular to the front side surface 102F of the first semiconductor substrate 102.

[0048] A front end of line (FEOL) structure FS may be located on the front side surface 102F of the first semiconductor substrate 102. The FEOL structure FS may include a plurality of fin-type active regions (eg, FIG. 8A to FIG. 8D The fin-type active region F1 shown in the figure). The FEOL structure FS may include components required to form a logic unit. For example, the FEOL structure FS may include multiple active regions, multiple source / drain regions, multiple gate lines, and multiple wiring structures, which are configured to selectively connect the multiple active regions, multiple source / drain regions, and multiple gate lines to each other or to the outside.

[0049] The first back-end-of-line (BEOL) structure BS1 may be located on the FEOL structure FS. The first BEOL structure BS1 may be spaced apart from the first semiconductor substrate 102 in a vertical direction (Z direction) in such a manner that the FEOL structure FS is located between the first BEOL structure BS1 and the first semiconductor substrate 102 .

[0050] The second BEOL structure BS2 may be located on the backside surface 102B of the first semiconductor substrate 102. The second BEOL structure BS2 may be spaced apart from the FEOL structure FS in a vertical direction (Z direction) in such a manner that the first semiconductor substrate 102 is located between the second BEOL structure BS2 and the FEOL structure FS.

[0051] The second semiconductor substrate 104 may be spaced apart from the first semiconductor substrate 102 in the vertical direction (Z direction) in such a manner that the FEOL structure FS and the first BEOL structure BS1 are located between the second semiconductor substrate 104 and the first semiconductor substrate 102. In the first semiconductor substrate 102, a Young's modulus of a first crystal direction extending parallel to the front side surface 102F may be different from a Young's modulus of a second crystal direction in the second semiconductor substrate 104 overlapping the first crystal direction in the vertical direction (Z direction) and extending parallel to the first crystal orientation.

[0052] Figure 3A Can be used to form Figure 2 A top view of a first wafer 102W of a first semiconductor substrate 102 is shown. Figure 3B Can be used to form Figure 2 FIG. 1 is a top view of a second wafer 104W of a second semiconductor substrate 104 .

[0053] In an embodiment, Figure 2 The first semiconductor substrate 102 shown may be Figure 3A At least a portion of the first wafer 102W is shown, and Figure 2 The second semiconductor substrate 104 shown may be Figure 3B As used herein, the first wafer 102W may be referred to as the first semiconductor substrate 102, and the second wafer 104W may be referred to as the second semiconductor substrate 104. As used herein, the characteristics of the first wafer 102W described below may be equally applicable to the first semiconductor substrate 102. As used herein, the characteristics of the second wafer 104W described below may be equally applicable to the second semiconductor substrate 104.

[0054] refer to Figure 2 , Figure 3A and Figure 3B , each of the first wafer 102W and the second wafer 104W may have a (100) crystal plane. That is, Figure 2 The illustrated front side surface 102F of the first semiconductor substrate 102 and a main surface 104A of the second semiconductor substrate 104 facing the first semiconductor substrate 102 may each have a (100) crystal plane.

[0055] The first wafer 102W may include a first notch 102N. The first notch 102N is formed along the <110> The second wafer 104W may include a second notch 104N, the second notch 104N being formed in an edge of the first wafer 102W in the first radial direction RA1 from the center 102C of the first wafer 102W. <100> The direction is formed in the edge of the second wafer 104W in the second radial direction RA2 from the center 104C of the second wafer 104W. The second radial direction RA2 may correspond to a direction rotated from the first radial direction RA1 by an angle θ selected in the range of about 40° to about 50° (eg, 45°).

[0056] In an embodiment, Figure 2 The first semiconductor substrate 102 shown may be obtained from a first wafer 102W, and Figure 2 The second semiconductor substrate 104 shown may be obtained from a second wafer 104W. Figure 2 In the IC device 100 shown, the alignment structure of the first semiconductor substrate 102 and the second semiconductor substrate 104 can be obtained by aligning the first wafer 102W with the second wafer 104W by rotating the second wafer 104W at an angle selected within a range of about 40° to about 50° (e.g., 45°) relative to the first wafer 102W so that the center 102C of the first wafer 102W and the center 104C of the second wafer 104W are aligned in a vertical direction ( Figure 2 The first notch 102N of the first wafer 102W and the second notch 104N of the second wafer 104W are located on a vertical line in the vertical direction ( Figure 2 The first and second radial directions RA1 and RA2 overlap each other in the Z direction, and the first and second radial directions RA1 are in the same direction. <110> Direction and second wafer 104W <100> The directions may overlap each other in the vertical direction (Z direction) and extend parallel to each other. Figure 2 In the IC device 100 shown, the first semiconductor substrate 102 can be aligned with the second semiconductor substrate 104 so that the front side surface 102F of the first semiconductor substrate 102 extends parallel to the front side surface 102F of the first semiconductor substrate 102. <110> direction and extending parallel to the main surface 104A of the second semiconductor substrate 104 <100> The directions overlap each other in the vertical direction (Z direction), and extend parallel to each other.

[0057] Figure 4A and Figure 4B is based on Figure 3A A graph of Young's modulus of the crystal orientation of the first wafer 102W is shown. Figure 4B is based on Figure 4A An enlarged view of the Young's modulus of the crystal directions in a local area Q1A of the first wafer 102W is shown. Figure 5A and Figure 5B is based on Figure 3B A graph of Young's modulus of the crystal orientation of the second wafer 104W is shown. Figure 5B is based on Figure 5A An enlarged view of the Young's modulus of the crystal directions in the local area Q1B of the second wafer 104W is shown.

[0058] refer to Figure 4A , Figure 4B , Figure 5A and Figure 5B , the Young's modulus of each of the first wafer 102W and the second wafer 104W may vary depending on its crystal orientation. As used herein, the term "Young's modulus" refers to the degree to which a material resists external pressure. Figure 4A , Figure 4B , Figure 5A and Figure 5B In FIG. 1 , (100) represents the Miller index indicating the crystal plane.

[0059] like Figure 4A , Figure 4B , Figure 5A and Figure 5B As shown, each of the first wafer 102W and the second wafer 104W having a (100) crystal plane can be <100> It has a relatively large Young's modulus in the crystal direction, and <110> The Young's modulus is relatively small in the crystal direction. In the second wafer 104W, <100> and <110> Each representation indicates a Miller index indicating a crystal direction.

[0060] As mentioned above, in Figure 2 In the IC device 100 shown, the alignment structure of the first semiconductor substrate 102 and the second semiconductor substrate 104 can be obtained by aligning the first wafer 102W with the second wafer 104W by the following operations: when the center 102C of the first wafer 102W and the center 104C of the second wafer 104W are aligned in the vertical direction ( Figure 2 When the second wafer 104W is located on a vertical line in the Z direction (in the vertical direction of the Z direction), the second wafer 104W is rotated relative to the first wafer 102W at an angle selected in the range of about 40° to about 50° (for example, 45°). Therefore, the Young's modulus of any crystal direction extending parallel to the front side surface 102F in the first semiconductor substrate 102 (for example, the crystal direction in the first radial direction RA1) may be different from the Young's modulus of the crystal direction overlapping with the arbitrary crystal direction in the vertical direction (Z direction) and extending parallel to the arbitrary crystal direction in the second semiconductor substrate 104 (for example, the crystal direction in the second radial direction RA2).

[0061] Generally, during the process of manufacturing IC devices, the biggest factor of overlap degradation may include stress on the wafer and distortion generated thereby in the wafer. In particular, in the process of manufacturing IC devices including a process of bonding two wafers to each other, the stress induced during the bonding process may have a direction due to a difference in mechanical properties depending on the crystal structure of the wafer, thereby causing distortion in the wafer. The distortion in the wafer may cause overlap degradation in the photolithography process performed after the bonding process. Therefore, it is desirable to minimize the distortion in the wafer and suppress overlap degradation in the process of manufacturing IC devices.

[0062] In the IC device 100 according to the present invention, the alignment structure of the first semiconductor substrate 102 and the second semiconductor substrate 104 overlapping each other in the vertical direction (Z direction) can be obtained by aligning the first wafer 102W and the second wafer 104W through the following operations: when the center 102C of the first wafer 102W and the center 104C of the second wafer 104W are aligned in the vertical direction (Z direction) Figure 2 When the second wafer 104W is located on a vertical line in the Z direction (in the Z direction), the second wafer 104W is rotated relative to the first wafer 102W at an angle selected in the range of about 40° to about 50° (for example, 45°). Therefore, the Young's modulus of any crystal direction extending parallel to the front side surface 102F in the first semiconductor substrate 102 (for example, the crystal direction in the first radial direction RA1) may be different from the Young's modulus of the crystal direction overlapping with the any crystal direction in the vertical direction (Z direction) and extending parallel to the any crystal direction in the second semiconductor substrate 104 (for example, the crystal direction in the second radial direction RA2). During the process of manufacturing the IC device 100, non-uniform mechanical deformation (for example, distortion) and overlay degradation may be minimized.

[0063] Fig. 6A Can be used to form Figure 2 A top view of a first wafer 202W of a first semiconductor substrate 102 is shown. Figure 6B Can be used to form Figure 2 FIG. 2 is a top view of a second wafer 204W of a second semiconductor substrate 104 .

[0064] In an embodiment, Figure 2 The first semiconductor substrate 102 shown may be Fig. 6A At least a portion of the first wafer 102W is shown, and Figure 2 The second semiconductor substrate 104 shown may be Figure 6BAs used herein, the first wafer 202W may be referred to as the first semiconductor substrate 102, and the second wafer 204W may be referred to as the second semiconductor substrate 104. As used herein, the following characteristics of the first wafer 202W may be equally applicable to the first semiconductor substrate 102. As used herein, the following characteristics of the second wafer 204W may be equally applicable to the second semiconductor substrate 104.

[0065] refer to Figure 2 , Fig. 6A and Figure 6B , the first wafer 202W may have a (100) crystal plane, and the second wafer 204W may have a (111) crystal plane. That is, Figure 2 The front side surfaces 102F of the illustrated first semiconductor substrate 102 may each have a (100) crystal plane, and the main surface 104A of the second semiconductor substrate 104 facing the first semiconductor substrate 102 may have a (111) crystal plane.

[0066] The details of the first wafer 202W are substantially the same as the details of the first wafer 102W described with reference to FIG. 3. That is, the first wafer 202W may include a first notch 202N, the first notch 202N along <110> The direction is formed in the edge of the first wafer 202W in the first radial direction RB1 from the center 202C of the first wafer 202W.

[0067] The second wafer 204W may include a second notch 204N along <100> Direction or <112> The direction is formed in the edge of the second wafer 204W in the second radial direction RB2 from the center 204C of the second wafer 204W.

[0068] In an embodiment, Figure 2 The first semiconductor substrate 102 shown may be obtained from a first wafer 202W, and Figure 2 The second semiconductor substrate 104 shown may be obtained from a second wafer 204W. Figure 2 In the IC device 100 shown in FIG. 1 , when the center 202C of the first wafer 202W and the center 204C of the second wafer 204W are in the vertical direction ( Figure 2 The first notch 202N of the first wafer 202W and the second notch 204N of the second wafer 204W are located on a vertical line in the vertical direction ( Figure 2When the first wafer 202W overlaps each other in the Z direction, and the first wafer 202W is aligned with the second wafer 204W so that the first radial direction RB1 and the second radial direction RB2 are in the same direction, an alignment structure of the first semiconductor substrate 102 and the second semiconductor substrate 104 can be obtained. In the alignment structure, the first wafer 202W <110> Direction and second wafer 204W <100> Direction or <112> The directions may overlap each other in the vertical direction (Z direction) and extend parallel to each other. Figure 2 In the IC device 100 shown, the first semiconductor substrate 102 can be aligned with the second semiconductor substrate 104 so that the front side surface 102F of the first semiconductor substrate 102 extends parallel to the front side surface 102F of the first semiconductor substrate 102. <110> direction and extending parallel to the main surface 104A of the second semiconductor substrate 104 <100> Direction or <112> The directions overlap each other in the vertical direction (Z direction) and extend parallel to each other.

[0069] Like reference Figure 4A and Figure 4B Like the first wafer 102W described above, the first wafer 202W may be <100> It has a relatively large Young's modulus in the crystal direction, and <110> The Young's modulus is relatively small in the crystal direction.

[0070] Figure 7 is based on Figure 6B A graph of Young's modulus of the crystal orientation of the second wafer 204W is shown.

[0071] refer to Figure 7 , the second wafer 204W may have a substantially constant Young's modulus according to the crystal orientation. Therefore, unlike the first wafer 202W, the Young's modulus, which is a unique material property of the second wafer 204W, may have physical isotropy that does not vary according to the orientation of the second wafer 204W. Therefore, when an external force is applied to the second wafer 204W, the second wafer 204W may be deformed to a uniform degree regardless of the direction in which the external force is applied.

[0072] exist Figure 2 In the IC device 100 shown in the figure, when the first wafer 202W is aligned with the second wafer 204W, the center 202C of the first wafer 202W and the center 204C of the second wafer 204W are in the vertical direction ( Figure 2When the first semiconductor substrate 102 and the second semiconductor substrate 104 are located on a vertical line in the Z direction (Z direction), an alignment structure of the first semiconductor substrate 102 and the second semiconductor substrate 104 can be obtained. Therefore, the Young's modulus of an arbitrary crystal direction extending parallel to the front side surface 102F in the first semiconductor substrate 102 (for example, the crystal direction in the first radial direction RB1) can be different from the Young's modulus of a crystal direction overlapping with the arbitrary crystal direction in the vertical direction (Z direction) and extending parallel to the arbitrary crystal direction in the second semiconductor substrate 104 (for example, the crystal direction in the second radial direction RB2). Therefore, due to the combination of the anisotropy of the properties of the first semiconductor substrate 102 and the isotropy of the properties of the second semiconductor substrate 104, during the process of manufacturing the IC device 100, non-uniform mechanical deformation (for example, distortion) and overlay degradation can be minimized.

[0073] Return to reference Figure 2 , the IC device 100 may further include a bonding layer BL between the first BEOL structure BS1 and the second semiconductor substrate 104. For example, the bonding layer BL may contact the first BEOL structure BS1 and the second semiconductor substrate 104. The bonding layer BL may be formed of or include a silicon oxide film, a silicon nitride film, a silicon carbonitride film, or a combination thereof, but is not limited thereto.

[0074] In an embodiment, Figure 2 The IC device 100 shown may constitute part of: logic chips, such as analog-to-digital converters (ADCs) and application-specific integrated circuits (ASICs); memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), and flash memory; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and / or power management chips, such as power management ICs (PMICs).

[0075] FIG. 8A to FIG. 8D is a diagram of an IC device 100A according to an example embodiment, which illustrates Figure 2 The specific configuration of the example of part "EX1". More specifically, Fig. 8A FIG. 1 is a plan layout diagram of a partial region of the IC device 100A. Figure 8B It is along Fig. 8A A cross-sectional view taken along line X1-X1'. Figure 8C It is along Fig. 8A A cross-sectional view taken along line Y1-Y1'. Fig.8D It is along Fig. 8A A cross-sectional view taken along the line Y2-Y2'. FIG. 8A to FIG. 8DAn IC device 100A is described that includes a field effect transistor (FET) having a gate-all-around structure that includes a nanowire or nanosheet type active region and a gate surrounding the active region. FIG. 8A to FIG. 8D In the drawings, the same reference numerals are used to denote Figure 2 The same components are described in detail herein, and their repeated description is omitted here. In the IC device 100A, FIG. 8A to FIG. 8D The components shown can be constructed Figure 1 Some of the plurality of cell LCs are shown.

[0076] refer to Figures 8A to 8D The first semiconductor substrate 102 may include a conductive region, such as a doped well or a doped structure.

[0077] A plurality of fin-type active regions F1 may protrude from the front side surface 102F of the first semiconductor substrate 102 in a vertical direction (Z direction). In some embodiments, the plurality of fin-type active regions F1 may be part of the first semiconductor substrate 102 (e.g., formed by etching the first semiconductor substrate 102), or may be formed on the first semiconductor substrate 102 (e.g., an epitaxial layer grown from the first semiconductor substrate 102). The plurality of fin-type active regions F1 may extend longitudinally along a first lateral direction (X direction) on the front side surface 102F of the first semiconductor substrate 102, and may be spaced apart from each other in a second lateral direction (Y direction) perpendicular to the first lateral direction (X direction). A plurality of trench regions T1 may be defined by the plurality of fin-type active regions F1 on the front side surface 102F of the first semiconductor substrate 102.

[0078] like Fig. 8A As shown, the IC device 100A may include a power rail region PRR. The power rail region PRR may be spaced apart from the plurality of fin-type active regions F1 in the second lateral direction (Y direction) and may extend longitudinally in the first lateral direction (X direction). The power rail wiring MPR may be located in a portion of the power rail region PRR adjacent to the backside surface 102B of the first semiconductor substrate 102. In an embodiment, the power rail wiring MPR may constitute Figure 1 The power rail region PRR and the power rail wiring MPR may constitute a ground line VSS as shown. The power rail wiring MPR may pass through a portion of the first semiconductor substrate 102 from the back side surface 102B of the first semiconductor substrate 102 in the vertical direction (Z direction). Figure 2 A second BEOL structure BS2 is shown.

[0079] In an embodiment, the power rail wiring MPR may include a metal wiring layer. In other embodiments, the power rail wiring MPR may include a metal wiring layer and a conductive barrier film surrounding the metal wiring layer. The metal wiring layer may be formed of or include Ru, Co, W, or a combination thereof. The conductive barrier film may be formed of or include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0080] like Figure 8C and Fig.8D As shown, the device isolation film 112 may be located between two adjacent fin-type active regions F1 among the plurality of fin-type active regions F1. The device isolation film 112 may fill the plurality of trench regions T1 and cover the sidewalls of each of the plurality of fin-type active regions F1. For example, the device isolation film 112 may contact the front side surface 102F of the first semiconductor substrate 102 and the side surfaces of the plurality of fin-type active regions F1. The device isolation film 112 may be formed of a silicon oxide film or include a silicon oxide film, but is not limited thereto.

[0081] like Figure 8B and Fig.8D As shown, a plurality of gate lines 160 may be located on a plurality of fin-type active areas F1 and a device isolation film 112. Each of the plurality of gate lines 160 may extend longitudinally in a second lateral direction (Y direction) to intersect with a plurality of fin-type active areas F1. In the region where the plurality of fin-type active areas F1 intersect with the plurality of gate lines 160, a plurality of nanosheet stacks NSS may be respectively disposed on the fin top surfaces FF of the plurality of fin-type active areas F1. Each of the plurality of nanosheet stacks NSS may include at least one nanosheet that is spaced apart from the fin top surface FF of the fin-type active area F1 in a vertical direction (Z direction) and faces the fin top surface FF of the fin-type active area F1. As used herein, the term "nanosheet" refers to a conductive structure having a cross section substantially perpendicular to the direction of current flow. A nanosheet may be interpreted as including a nanowire.

[0082] Each of the plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 overlapping each other in a vertical direction (Z direction) on the fin-type active region F1. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may be at different vertical distances (Z direction distances) from the fin top surface FF of the fin-type active region F1. Each of the plurality of gate lines 160 may surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 overlapping each other in a vertical direction (Z direction). Each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in the nanosheet stack NSS may be used as a channel region. In an embodiment, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in the nanosheet stack NSS may include a Si layer, a SiGe layer, or a combination thereof.

[0083] like Figure 8B and Fig.8D As shown, each of the plurality of gate lines 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M may cover the top surface of the nanosheet stack NSS and extend in the second lateral direction (Y direction). The plurality of sub-gate portions 160S may be integrally connected to the main gate portion 160M, and each is arranged between adjacent two nanosheets of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and between the first nanosheet N1 and the fin top surface FF of the fin-type active region F1.

[0084] like Figure 8B and Figure 8C As shown, a plurality of recesses R1 may be formed in the fin-type active region F1. The lowermost surface of each of the plurality of recesses R1 may be located at a lower vertical height than the fin top surface FF of the fin-type active region F1. As used herein, the term "vertical height" refers to the distance from the front side surface 102F of the first semiconductor substrate 102 in the vertical direction (Z direction or -Z direction).

[0085] A plurality of source / drain regions 130 may be located inside the plurality of recesses R1. Each of the plurality of source / drain regions 130 may be located on the fin-type active region F1 and spaced apart from the front side surface 102F of the first semiconductor substrate 102 in a vertical direction (Z direction) in a manner that the fin-type active region F1 is located between each of the source / drain regions 130 and the front side surface 102F of the first semiconductor substrate 102. Each of the plurality of source / drain regions 130 may be adjacent to at least one gate line 160 selected from the plurality of gate lines 160. Each of the plurality of source / drain regions 130 may have a surface in contact with the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS adjacent thereto.

[0086] Each of the plurality of source / drain regions 130 may include an epitaxially grown semiconductor layer. In an embodiment, each of the plurality of source / drain regions 130 may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or an embedded SiGe structure including a plurality of epitaxially grown SiGe layers. When the source / drain region 130 constitutes an NMOS transistor, the source / drain region 130 may include a SiC layer doped with an n-type dopant. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb). When the source / drain region 130 constitutes a PMOS transistor, the source / drain region 130 may include a SiGe layer doped with a p-type dopant. The p-type dopant may be selected from boron (B) and gallium (Ga).

[0087] Each of the plurality of gate lines 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide may include titanium aluminum carbide (TiAlC). However, the materials included in the plurality of gate lines 160 are not limited to the above examples.

[0088] The gate dielectric film 152 may be located between the nanosheet stack NSS and the gate line 160. The gate dielectric film 152 may contact the fin top surface FF of the fin-type active region F1 and the top surface of the device isolation film 112. The gate dielectric film 152 may have a stacked structure of an interface dielectric film and a high-k dielectric film. The interface dielectric film may include a low-k dielectric material film having a dielectric constant of 9 or less (e.g., a silicon oxide film, a silicon oxynitride film, or a combination thereof). In an embodiment, the interface dielectric film may be omitted. The high-k dielectric film may include a material having a higher dielectric constant than the silicon oxide film. For example, the high-k dielectric film may have a dielectric constant of about 10 to about 25. The high-k dielectric film may include hafnium oxide, but is not limited thereto.

[0089] Both sidewalls of each of the plurality of sub-gate portions 160S included in the plurality of gate lines 160 may be spaced apart from the source / drain region 130 in such a manner that the gate dielectric film 152 is located between the two sidewalls and the source / drain region 130. The gate dielectric film 152 may be located between the sub-gate portion 160S included in the gate line 160 and each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and between the sub-gate portion 160S included in the gate line 160 and the source / drain region 130.

[0090] In the region where the plurality of fin-type active regions F1 intersect with the plurality of gate lines 160, the plurality of nanosheet stacks NSS may be respectively located on the fin top surfaces FF of the plurality of fin-type active regions F1. Each of the plurality of nanosheet stacks NSS may be spaced apart from the fin-type active region F1 and face the fin top surface FF of the fin-type active region F1. A plurality of nanosheet transistors may be formed in the portion where the plurality of fin-type active regions F1 intersect with the plurality of gate lines 160. Each of the plurality of nanosheet transistors may include an NMOS transistor, a PMOS transistor, or a combination thereof.

[0091] like Figure 8B As shown, both sidewalls of the gate line 160 may be covered by a plurality of insulating spacers 118. Each of the plurality of insulating spacers 118 may cover the sidewall of the main gate portion 160M on the top surface of the nanosheet stack NSS. Each of the plurality of insulating spacers 118 may be spaced apart from the gate line 160 in such a manner that a gate dielectric film 152 is located between each insulating spacer 118 and the gate line 160. The gate dielectric film 152 may contact the sidewall of the main gate portion 160M. Figure 8CAs shown, a plurality of recessed side insulating spacers 119 may be located on the device isolation film 112. At least some of the plurality of recessed side insulating spacers 119 may cover the sidewalls of the source / drain region 130. In example embodiments, the plurality of recessed side insulating spacers 119 may contact the top surface of the device isolation film 112 and the sidewalls of the source / drain region 130. In an embodiment, each of the plurality of recessed side insulating spacers 119 may be integrally connected to the insulating spacer 118 adjacent thereto. Each of the plurality of insulating spacers 118 and the plurality of recessed side insulating spacers 119 may be formed of or include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. As used herein, each of the terms “SiCN,” “SiBN,” “SiON,” “SiOCN,” “SiBCN,” and “SiOC” refers to a material including elements included therein, rather than a chemical formula representing a stoichiometric relationship.

[0092] A top surface of each of the gate line 160, the gate dielectric film 152, and the insulating spacer 118 may be covered by a capping insulating pattern 168. The capping insulating pattern 168 may contact top surfaces of the gate line 160, the gate dielectric film 152, and the insulating spacer 118. The capping insulating pattern 168 may be formed of or include a silicon nitride film.

[0093] The plurality of source / drain regions 130, the device isolation film 112, the plurality of insulating spacers 118, and the plurality of recessed side insulating spacers 119 may be covered by an insulating liner 142. The insulating liner 142 may contact the plurality of source / drain regions 130, the device isolation film 112, the plurality of insulating spacers 118, and the plurality of recessed side insulating spacers 119. An inter-gate dielectric film 144 may be located on the insulating liner 142. The inter-gate dielectric film 144 may contact the insulating liner 142. The inter-gate dielectric film 144 may be located between pairs of source / drain regions 130 adjacent to each other, which are located between pairs of gate lines 160 adjacent to each other in the first lateral direction (X direction). In an embodiment, the insulating liner 142 may be formed of silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, or include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but is not limited thereto. The inter-gate dielectric film 144 may be formed of a silicon oxide film or include a silicon oxide film, but is not limited thereto. The device isolation film 112, the insulating liner 142, and the inter-gate dielectric film 144 may constitute an insulating structure.

[0094] like Figure 8B and Figure 8C As shown, the plurality of source / drain contacts CA may be located on the plurality of source / drain regions 130. Each of the plurality of source / drain contacts CA may be spaced apart from the front side surface 102F of the first semiconductor substrate 102 in a vertical direction (Z direction) in such a manner that the fin type active region F1 and the source / drain region 130 are located between each source / drain contact CA and the front side surface 102F of the first semiconductor substrate 102.

[0095] Each of the plurality of source / drain contacts CA may be electrically connected to at least one source / drain region 130 selected from the plurality of source / drain regions 130. For example, Figure 8C As shown, one source / drain contact CA may be two connected source / drain regions 130 adjacent thereto, but is not limited thereto. Fig. 8A As shown, the source / drain contacts CA may extend longitudinally along the second lateral direction (Y direction) between pairs of gate lines 160 adjacent to each other along the first lateral direction (X direction). Figure 8B As shown, the source / drain contact CA may be spaced apart from the main gate portion 160M of the gate line 160 adjacent thereto in the first lateral direction (X direction) by an insulating spacer 118 being located between the source / drain contact CA and the main gate portion 160M of the gate line 160 adjacent thereto.

[0096] In an embodiment, the source / drain region 130 and the source / drain contact CA connected to each other may contact each other. In other embodiments, a metal silicide film (not shown) may be located between the source / drain region 130 and the source / drain contact CA connected to each other. The metal silicide film may be formed of or include a metal including titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er) and palladium (Pd). For example, the metal silicide film may include titanium silicide, but is not limited thereto.

[0097] In an embodiment, the source / drain contact CA may include only a metal plug having a single metal. In other embodiments, the source / drain contact CA may include a metal plug and a conductive barrier film including the metal plug. The metal plug may be formed of molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof, or include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof, but is not limited thereto. The conductive barrier film may include a metal or a conductive metal silicide. For example, the conductive barrier film can be formed of titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbon nitride (WCN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN) or a combination thereof, or include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbon nitride (WCN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN) or a combination thereof, but is not limited to this.

[0098] like Figure 8C As shown, the IC device 100A may include a via power rail VPR extending longitudinally in a vertical direction (Z direction) between the power rail wiring MPR and the source / drain contacts CA. The via power rail VPR may include a portion passing through an insulating structure including a device isolation film 112, an insulating liner 142, and a gate dielectric film 144 in the vertical direction (Z direction) and a portion passing through a portion of the front side surface 102F of the first semiconductor substrate 102 in the vertical direction (Z direction). The portion of the via power rail VPR passing through the insulating structure in the vertical direction (Z direction) may include a conductive barrier film BM and a metal plug MP surrounded by the conductive barrier film BM. The conductive barrier film BM may contact the metal plug MP. The via power rail VPR may constitute Figure 2The second BEOL structure BS2 is shown. The metal plug MP may be formed of molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof, or include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof, but is not limited thereto. The conductive barrier film BM may be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, or include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto.

[0099] The power rail wiring MPR and the via power rail VPR may constitute a contact structure. In the contact structure, the power rail wiring MPR may constitute a first plug portion passing through the first semiconductor substrate 102 in the vertical direction (Z direction), and the via power rail VPR may constitute a second plug portion passing through the insulating structure in the vertical direction (Z direction). An insulating spacer including an inorganic material (e.g., a silicon oxide film and a silicon nitride film) may be located between the power rail wiring MPR and the first semiconductor substrate 102 and / or between the via power rail VPR and the insulating structure.

[0100] The top surface of each of the source / drain contacts CA, the plurality of capping insulating patterns 168, and the inter-gate dielectric film 144 may be covered by an upper insulating structure 180. The upper insulating structure 180 may include an etch stop film 182 and an upper insulating film 184 sequentially stacked on each of the source / drain contacts CA, the plurality of capping insulating patterns 168, and the inter-gate dielectric film 144. The etch stop film 182 may be formed of or include silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), silicon oxycarbide (SiOC), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), aluminum oxycarbide (AlOC), or a combination thereof. The upper insulating film 184 may be formed of an oxide film, a nitride film, an ultra low k (ULK) film having an ultra low dielectric constant K of approximately 2.2 to approximately 2.4, or a combination thereof, or include an oxide film, a nitride film, an ultra low k (ULK) film having an ultra low dielectric constant K of approximately 2.2 to approximately 2.4, or a combination thereof. For example, the upper insulating film 184 may be formed of, or include, a tetraethyl orthosilicate (TEOS) film, a high-density plasma (HDP) film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a silicon oxynitride (SiON) film, a silicon nitride (SiN) film, a silicon oxycarbide (SiOC) film, a SiCOH film, or a combination thereof, but is not limited thereto.

[0101] like Figure 8B and Figure 8C As shown, the source / drain via contact VA may be located on the source / drain contact CA. The source / drain via contact VA may pass through the upper insulating structure 180 and contact the source / drain contact CA. Each of the plurality of source / drain regions 130 may be electrically connected to the source / drain via contact VA through the source / drain contact CA. The bottom surface of the source / drain via contact VA may contact the top surface of the source / drain contact CA.

[0102] like Fig.8DAs shown, the gate contact CB may be located on the gate line 160. The gate contact CB may pass through the upper insulating structure 180 and the capping insulating pattern 168 in the vertical direction (Z direction) and be connected to the gate line 160. The bottom surface of the gate contact CB may contact the top surface of the gate line 160.

[0103] Each of the source / drain via contact VA and the gate contact CB may include a contact plug including molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof, but the constituent material of the contact plug is not limited thereto. In an embodiment, the source / drain via contact VA and the gate contact CB may further include a conductive barrier pattern surrounding a portion of the contact plug. The conductive barrier pattern included in the source / drain via contact VA and the gate contact CB may include a metal or a metal silicide. For example, the conductive barrier pattern may be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, or include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto.

[0104] The top surface of each of the upper insulating structure 180, the source / drain via contact VA, and the gate contact CB may be covered by the interlayer insulating film 186. For example, the interlayer insulating film 186 may contact the top surfaces of the upper insulating structure 180, the source / drain via contact VA, and the gate contact CB. The constituent material of the interlayer insulating film 186 is substantially the same as the constituent material of the upper insulating film 184. The plurality of upper wiring layers M1 may pass through the interlayer insulating film 186. Each of the plurality of upper wiring layers M1 may be connected to the source / drain via contact VA or the gate contact CB located therebelow. The top and bottom surfaces of the plurality of upper wiring layers M1 may be coplanar with the corresponding top and bottom surfaces of the interlayer insulating film 186. The plurality of upper wiring layers M1 may be formed of, or include, molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but is not limited thereto.

[0105] The front side wiring structure FWS may be located on the plurality of upper wiring layers M1 and the interlayer insulating film 186. The front side wiring structure FWS may include a plurality of wiring layers MN1, a plurality of via contacts CT1, and an interlayer insulating film 194 covering the plurality of wiring layers MN1 and the plurality of via contacts CT1. The via power rail VPR may be connected to a selected wiring layer MN1 among the plurality of wiring layers MN1 through the source / drain contact CA, the source / drain via contact VA, the upper wiring layer M1, and the via contact CT1. The constituent materials of the plurality of wiring layers MN1 and the plurality of via contacts CT1 are substantially the same as the constituent materials of the plurality of upper wiring layers M1 already described above. The constituent materials of the interlayer insulating film 194 are substantially the same as the constituent materials of the upper insulating film 184 already described above.

[0106] The backside surface 102B of the first semiconductor substrate 102 may be covered by a backside insulating film 109. For example, the backside insulating film 109 may contact the backside surface 102B of the first semiconductor substrate 102. The backside insulating film 109 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, a low-k dielectric film, or a combination thereof, or include a silicon oxide film, a silicon nitride film, a silicon carbide film, a low-k dielectric film, or a combination thereof. The low-k dielectric film may be formed of fluorine-doped silicon oxide, organic silicate glass, carbon-doped oxide, porous silicon oxide, porous organic silicate glass, spin-on organic polymeric dielectric, spin-on silicon-based polymeric dielectric, or a combination thereof, or include fluorine-doped silicon oxide, organic silicate glass, carbon-doped oxide, porous silicon oxide, porous organic silicate glass, spin-on organic polymeric dielectric, spin-on silicon-based polymeric dielectric, or a combination thereof, but is not limited thereto.

[0107] The backside wiring structure BWS may be located on the backside insulating film 109. The backside wiring structure BWS may include a plurality of wiring layers MN2, a plurality of via contacts CT2, and an interlayer insulating film 196 covering the plurality of wiring layers MN2 and the plurality of via contacts CT2. A selected via contact CT2 among the plurality of via contacts CT2 may have one end contacted by the backside insulating film 109 and another end contacted with a selected wiring layer MN2 among the plurality of wiring layers MN2. The power rail wiring MPR may be connected to a selected wiring layer MN2 among the plurality of wiring layers MN2 through one via contact CT2. The constituent materials of the plurality of wiring layers MN2 and the plurality of via contacts CT2 are substantially the same as the constituent materials of the plurality of upper wiring layers M1 already described above. The constituent materials of the interlayer insulating film 196 are substantially the same as the constituent materials of the above-mentioned upper insulating film 184.

[0108] 9A to 9C is a diagram of an IC device 100B according to an example embodiment, which illustrates Figure 2 Another example of a specific configuration of the portion "EX1" is shown in FIG. More specifically, Fig.9AFIG. 1 is a plan layout diagram of a partial region of the IC device 100B. Fig. 9B It is along Fig.9A A cross-sectional view taken along line X4-X4'. Fig. 9C It is along Fig.9A A cross-sectional view taken along the line Y4-Y4'. 9A to 9C In the drawings, the same reference numerals are used to denote Figure 2 and FIG. 8A to FIG. 8D The same elements are described above and their repeated description is omitted here.

[0109] refer to 9A to 9C , the IC device 100B can be composed of Figure 1 Some of the plurality of unit LCs shown in FIG. 100B may have substantially the same structure as that of the reference LC. FIG. 8A to FIG. 8D However, the IC device 100B may include a contact structure having a power rail wiring MPR4 and a backside source / drain contact DBC.

[0110] The selected fin-type active region F1 among the plurality of fin-type active regions F1 may include a first fin portion F1A and a second fin portion F1B, the first fin portion F1A and the second fin portion F1B are spaced apart from each other in a first lateral direction (X direction) in such a manner that a backside source / drain contact DBC included in the contact structure is located between the first fin portion F1A and the second fin portion F1B, and the first fin portion F1A and the second fin portion F1B extend longitudinally in a straight line in the first lateral direction (X direction). Each of the first fin portion F1A and the second fin portion F1B may have a sidewall covered by a device isolation film 112. The device isolation film 112 may constitute an insulating structure.

[0111] A plurality of gate lines 160 may be located on the plurality of fin-type active regions F1. Each of the plurality of gate lines 160 may extend longitudinally in a second lateral direction (Y direction) intersecting the first lateral direction (X direction). In regions where the plurality of fin-type active regions F1 intersect the plurality of gate lines 160, a plurality of nanosheet stacks NSS may be located above the plurality of fin-type active regions F1, respectively.

[0112] A plurality of source / drain regions 130 may be located on the plurality of fin-type active regions F1. Each of the plurality of source / drain regions 130 may be adjacent to at least one gate line 160 selected from the plurality of gate lines 160. Each of the plurality of source / drain regions 130 may contact the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS adjacent thereto.

[0113] like Fig. 9CAs shown, a plurality of recessed side insulating spacers 119 may be located on the top surface of the device isolation film 112. At least some of the plurality of recessed side insulating spacers 119 may cover the sidewalls of the source / drain region 130. In an embodiment, each of the plurality of recessed side insulating spacers 119 may be integrally connected to the insulating spacer 118 adjacent thereto.

[0114] A metal silicide film 172 may be formed on top surfaces of some selected source / drain regions 130 among the plurality of source / drain regions 130 toward the upper insulating structure 180, and a metal silicide film 172 may be formed on bottom surfaces of some other selected source / drain regions 130 among the plurality of source / drain regions 130 toward the first semiconductor substrate 102. The plurality of source / drain regions 130 and the device isolation film 112 may be covered by an insulating liner 142. An inter-gate dielectric film 144 may be located on the insulating liner 142.

[0115] like Fig. 9C As shown, a plurality of front side source / drain contacts CA4 may be located on the fin type active region F1. Each of the plurality of front side source / drain contacts CA4 may be electrically connected to a selected source / drain region 130 among the plurality of source / drain regions 130. Each of the plurality of front side source / drain contacts CA4 may be spaced apart from the fin type active region F1 in a vertical direction (Z direction) in such a manner that the source / drain region 130 is located between each of the front side source / drain contacts CA4 and the fin type active region F1.

[0116] Each of the plurality of front side source / drain contacts CA4 may penetrate the inter-gate dielectric film 144 and the insulating liner 142 in the vertical direction (Z direction) and contact the metal silicide film 172. Fig. 9B As shown, the front side source / drain contact CA4 can be spaced apart from the main gate portion 160M of the gate line 160 in the first lateral direction (X direction) in a manner that the insulating spacer 118 is located between the front side source / drain contact CA4 and the main gate portion 160M of the gate line 160. Details of the front side source / drain contact CA4 are similar to those of reference 1 Figure 2 and FIG. 3A to FIG. 3B The details of the described source / drain contacts CA are essentially the same.

[0117] A plurality of back side source / drain contacts DBC may be located at a back side opposite to the front side where the front side source / drain contacts CA are located, with a plurality of source / drain regions 130 located between the back side and the front side. Each of the plurality of back side source / drain contacts DBC may be electrically connected to some other source / drain regions 130 selected from the plurality of source / drain regions 130 and not connected to the front side source / drain contacts CA4.

[0118] Each of the plurality of back side source / drain contacts DBC may pass through a selected fin type active region F1 among the plurality of fin type active regions F1 in the vertical direction (Z direction). As described above, the selected fin type active region F1 may include a first fin portion F1A and a second fin portion F1B, the first fin portion F1A and the second fin portion F1B being spaced apart from each other in the first lateral direction (X direction) in such a manner that the back side source / drain contact DBC is located between the first fin portion F1A and the second fin portion F1B, and the first fin portion F1A and the second fin portion F1B extending longitudinally in a straight line in the first lateral direction (X direction).

[0119] Among the multiple source / drain regions 130, the source / drain region 130 to which the front source / drain contact CA4 is connected and the source / drain region 130 to which the back source / drain contact DBC is connected may be spaced apart from each other in a lateral direction (e.g., a first lateral direction (X direction) or a second lateral direction (Y direction)).

[0120] Each of the plurality of back side source / drain contacts DBC may have a sidewall facing each of the fin type active regions F1 and the device isolation film 112 adjacent thereto, each of the fin type active regions F1 being penetrated by the back side source / drain contact DBC in a vertical direction (Z direction).

[0121] like Fig. 9B As shown, the plurality of gate lines 160 may include a gate line 160 located on the first fin portion F1A and a gate line 160 located on the second fin portion F1B. Each of the plurality of front side source / drain contacts CA4 may be connected to the source / drain region 130 located on the first fin portion F1A or the second fin portion F1B.

[0122] like Fig. 9CAs shown, the device isolation film 112 may cover both sidewalls of each of the first fin portion F1A and the second fin portion F1B in the second lateral direction (Y direction), and define a width of the contact space DBH in the second lateral direction (Y direction). The back side source / drain contact DBC may overlap the source / drain region 130 in the contact space DBH along the vertical direction (Z direction), and extend longitudinally in the contact space DBH along the vertical direction (Z direction).

[0123] The width of the back side source / drain contact DBC in the first lateral direction (X direction) and the second lateral direction (Y direction) may gradually increase in the vertical direction (Z direction) toward the first semiconductor substrate 102. Fig. 9B and Fig. 9C As shown, the width of the front side source / drain contact CA4 in the first lateral direction (X direction) and the second lateral direction (Y direction) may gradually increase away from the first semiconductor substrate 102 in the vertical direction (Z direction).

[0124] The metal silicide film 192 may be located between the back side source / drain contact DBC and the source / drain region 130. The metal silicide film 192 may contact the back side source / drain contact DBC and the source / drain region 130. Details of the metal silicide film 192 are substantially the same as those of the metal silicide film 172 described above.

[0125] like Fig. 9C As shown, in the contact space DBH, the sidewall of the back side source / drain contact DBC facing the device isolation film 112 may be in contact with the device isolation film 112 .

[0126] In the contact space DBC, the insulating film 406 may be located between the first fin portion F1A and the back side source / drain contact DBC and between the second fin portion F1B and the back side source / drain contact DBC. Likewise, the insulating film 406 may be located between the first semiconductor substrate 102 and the power rail wiring MPR4. The insulating film 406 may be formed of or include a silicon oxide film.

[0127] In the IC device 100B, the power rail wiring MPR4 may pass through the first semiconductor substrate 102 in the vertical direction (Z direction) from the backside surface 102B of the first semiconductor substrate 102 to the frontside surface 102F thereof, and be connected to the backside source / drain contact DBC. The backside source / drain contact DBC may include a first end connected to the power rail wiring MPR4 and a second end connected to the source / drain region 130 through the metal silicide film 192. In an embodiment, the power rail wiring MPR4 may be integrally connected to the backside source / drain contact DBC. In an embodiment, the power rail wiring MPR4 and the backside source / drain contact DBC may be formed of or include the same metal as each other. In an embodiment, each of the power rail wiring MPR4 and the back side source / drain contact DBC may include a metal plug formed of molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof, or includes molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof.

[0128] The power rail wiring MPR4 and the back side source / drain contact DBC may constitute a contact structure. The power rail wiring MPR4 passing through the first semiconductor substrate 102 in the vertical direction (Z direction) may constitute a first plug portion of the contact structure, and the back side source / drain contact DBC may constitute a second plug portion of the contact structure.

[0129] like Fig. 9B and Fig. 9C As shown, the top surface of each of the plurality of front side source / drain contacts CA4, the plurality of capping insulating patterns 168 and the inter-gate dielectric film 144 may be covered by an upper insulating structure 180. The upper insulating structure 180 may include an etching stop film 182 and an upper insulating film 184. A plurality of source / drain via contacts VA may be located on the plurality of front side source / drain contacts CA4. Each source / drain via contact VA in the plurality of source / drain via contacts VA may pass through the upper insulating structure 180 and contact the front side source / drain contact CA4. From among the plurality of source / drain regions 130, the source / drain region 130 connected to the front side source / drain contact CA4 may be electrically connected to the source / drain via contact VA through the metal silicide film 172 and the front side source / drain contact CA4. The top surface of the upper insulating structure 180 may be covered by an interlayer insulating film 186. A plurality of upper wiring layers M1 may pass through the interlayer insulating film 186. Each of the plurality of upper wiring layers M1 may be connected to a selected source / drain via contact VA or a plurality of gate contacts (see Fig.9A A selected gate contact in CB).

[0130] The front side wiring structure FWS may be located on the plurality of upper wiring layers M1 and the interlayer insulating film 186. The back side surface 102B of the first semiconductor substrate 102 may be covered by the back side insulating film 109. The back side wiring structure BWS may be located on the back side insulating film 109.

[0131] refer to Figures 2 to 9C The described IC devices 100, 100A, and 100B may each include a first semiconductor substrate 102 and a second semiconductor substrate 104, which are spaced apart from each other in the vertical direction (Z direction) in such a manner that the FEOL structure FS and the first BEOL structure BS1 are located between the first semiconductor substrate 102 and the second semiconductor substrate 104, and the first semiconductor substrate 102 and the second semiconductor substrate 104 overlap each other in the vertical direction (Z direction). Likewise, the Young's modulus of an arbitrary crystal direction extending parallel to the front side surface 102F in the first semiconductor substrate 102 may be different from the Young's modulus of a crystal direction overlapping with and extending parallel to the arbitrary crystal direction in the second semiconductor substrate 104 in the vertical direction (Z direction). Therefore, in the IC devices 100, 100A, and 100B according to the inventive concept, even when the first semiconductor substrate 102 gradually becomes thinner and the size of the pattern to be formed on the first semiconductor substrate 102 becomes smaller, the distortion of the first semiconductor substrate 102 and the overlay error in the patterns at different vertical heights formed on the first semiconductor substrate 102 can be minimized. Therefore, according to the inventive concept, the uniformity of the critical dimension (CD) of the pattern required to manufacture the IC devices 100, 100A, and 100B can be improved, and the reliability of the IC devices 100, 100A, and 100B can be improved.

[0132] Fig.10 is a flow chart of a method of manufacturing an IC device according to an example embodiment. FIG. 11A to FIG. 11F is a cross-sectional view of a process sequence of a method for manufacturing an IC device according to an example embodiment. Fig.10 and FIG. 11A to FIG. 11F Describe manufacturing reference Figure 2 The method of IC device 100 is described. FIG. 11A to FIG. 11F In the drawings, the same reference numerals are used to denote Figure 2 The same elements are described above and their repeated description is omitted here.

[0133] refer to Fig.10 and Fig.11AIn process P502 , a first semiconductor substrate 102 may be prepared, and a FEOL structure FS may be formed on a front side surface 102F of the first semiconductor substrate 102 .

[0134] In an embodiment, the first semiconductor substrate 102 may include a front side surface 102F having a (100) crystal plane. For example, the first semiconductor substrate 102 may include a reference Figure 4A and Figure 4B A first wafer 102W is depicted.

[0135] In an embodiment, the FEOL structure FS may be formed to include a reference FIG. 8A to FIG. 8D Components of the IC device 100 described and / or referenced 9A to 9C Components of IC device 100B are described.

[0136] refer to Fig.10 and Fig. 11B In process P504, a first BEOL structure BS1 may be formed on the FEOL structure FS. In an embodiment, the first BEOL structure BS1 may be formed to include reference FIG. 8A to FIG. 8D and 9A to 9C Described is the front side wiring structure FWS.

[0137] refer to Fig.10 and Fig. 11C In process P506 , a bonding layer BL may be formed on the first BEOL structure BS1 .

[0138] refer to Fig.10 and Fig.11D In process P508, the first BEOL structure BS1 and the second semiconductor substrate 104 may be bonded to each other using a bonding layer BL so that the second semiconductor substrate 104 having a Young's modulus different from that of the first semiconductor substrate 102 faces the first semiconductor substrate 102 in a vertical direction (Z direction).

[0139] In an embodiment, a main surface 104A of the second semiconductor substrate 104 facing the first semiconductor substrate 102 may have a (100) crystal plane. Figure 5A and Figure 5B A second wafer 104W is depicted.

[0140] You can use reference Figure 4A and Figure 4B The first wafer 102W described is used as the first semiconductor substrate 102 and uses the reference Figure 5A and Figure 5BThe second wafer 104W described above is used as the second semiconductor substrate 104 to perform bonding of the first BEOL structure BS1 and the second semiconductor substrate 104 to each other. Fig.10 In process P508, bonding the first BEOL structure BS1 to the second semiconductor substrate 104 may include aligning the first wafer 102W with the second wafer 104W so that the first wafer 102W is aligned with the second wafer 104W. <110> The first notch 102N and the second wafer 104W in the direction <100> The second notches 104N in the directions overlap each other in the vertical direction (Z direction), and the first radial direction RA1 from the center 102C of the first wafer 102W and the second radial direction RA2 from the center 104C of the second wafer 104W are in the same direction. The second radial direction RA2 may correspond to a direction rotated at an angle selected in the range of about 40° to about 50° (e.g., 45°) from the first radial direction RA1.

[0141] In an embodiment, Fig.10 Process P508 can be used by using reference Figure 4A and Figure 4B The first wafer 102W described is used as the first semiconductor substrate 102 and uses the reference Figure 5A and Figure 5B The second wafer 104W is described as the second semiconductor substrate 104 to perform the bonding of the first BEOL structure BS1 to the second semiconductor substrate 104. In this case, Fig.10 In process P508, bonding the first BEOL structure BS1 to the second semiconductor substrate 104 may include aligning the first semiconductor substrate 102 with the second semiconductor substrate 104 so that the front side surface 102F of the first semiconductor substrate 102 including the first wafer 102W extends parallel to the front side surface 102F of the first semiconductor substrate 102 including the first wafer 102W. <110> The main surface 104A of the second semiconductor substrate 104 including the second wafer 104W extends parallel to the main surface 104A of the second semiconductor substrate 104 including the second wafer 104W. <100> The directions overlap each other in the vertical direction (Z direction), and extend parallel to each other.

[0142] In other embodiments, the main surface 104A of the second semiconductor substrate 104 facing the first semiconductor substrate 102 may have a (111) crystal plane. Figure 6B A second wafer 204W is depicted.

[0143] You can use reference Fig. 6A The first wafer 202W is described as the first semiconductor substrate 102 and uses the reference Figure 6BThe second wafer 204W is described as the second semiconductor substrate 104 to perform the bonding of the first BEOL structure BS1 to the second semiconductor substrate 104. In this case, Fig.10 In process P508, bonding the first BEOL structure BS1 to the second semiconductor substrate 104 may include aligning the first wafer 202W with the second wafer 204W so that the first wafer 202W is aligned with the second wafer 204W. <110> The first notch 202N and the second wafer 204W in the direction <100> The second notches 404N in the direction overlap each other in the vertical direction (Z direction), and a first radial direction RB1 from the center 202C of the first wafer 202W and a second radial direction RB2 from the center 204C of the second wafer 204W are in the same direction.

[0144] In an embodiment, Fig.10 Process P508 can be used by using reference Fig. 6A The first wafer 202W is described as the first semiconductor substrate 102 and uses the reference Figure 6B The second wafer 204W is described as the second semiconductor substrate 104 to perform the bonding of the first BEOL structure BS1 to the second semiconductor substrate 104. In this case, Fig.10 In process P508, bonding the first BEOL structure BS1 to the second semiconductor substrate 104 may include aligning the first semiconductor substrate 102 with the second semiconductor substrate 104 so that the front side surface 102F of the first semiconductor substrate 102 including the first wafer 202W extends parallel to the front side surface 102F of the first semiconductor substrate 102 including the first wafer 202W. <110> The main surface 104A of the second semiconductor substrate 104 including the second wafer 204W extends parallel to the main surface 104A of the second semiconductor substrate 104 including the second wafer 204W. <100> Direction or <112> The directions overlap each other in the vertical direction (Z direction), and extend parallel to each other.

[0145] In an embodiment, Fig.10 In process P508, bonding the first BEOL structure BS1 to the second semiconductor substrate 104 may include aligning the first semiconductor substrate 102 with the second semiconductor substrate 104 so that any crystal orientation (e.g., Figure 3A The Young's modulus of a crystal direction in the first radial direction RA1 shown in FIG. 1 is different from that of a crystal direction (eg, Figure 3A and Figure 3B Young's modulus of the crystal direction in the second radial direction RA2 shown.

[0146] In an embodiment, Fig.10 In process P508, bonding the first BEOL structure BS1 to the second semiconductor substrate 104 may include: cleaning Fig. 11C The resulting structure in which the bonding layer BL is formed and the second semiconductor substrate 104; Fig. 11C The resulting structure in which the bonding layer BL is formed is bonded to the second semiconductor substrate 104 so that the bonding layer BL is in contact with the main surface 104A of the second semiconductor substrate 104; and an annealing process is performed.

[0147] refer to Fig.10 and Fig.11E , in process P510, Fig.11D In the resulting structure in which the first BEOL structure BS1 is bonded to the second semiconductor substrate 104, the first semiconductor substrate 102 may be polished from the backside surface 102B of the first semiconductor substrate 102 to reduce the thickness of the first semiconductor substrate 102. As a result, the backside surface 102B of the first semiconductor substrate 102 may become closer to the frontside surface 102F than before.

[0148] In an embodiment, the first semiconductor substrate 102 may be polished from the backside surface 102B by using at least one selected from a mechanical grinding process, a chemical mechanical polishing (CMP) process, a wet etching process, and a combination thereof.

[0149] refer to Fig.10 and Fig.11F , in process P512, it can be Fig.11E In the resulting structure, a second BEOL structure BS2 is formed on the polished backside surface 102B of the first semiconductor substrate 102 .

[0150] In an embodiment, the second BEOL structure BS2 may be formed to include reference FIG. 8A to FIG. 8D and 9A to 9C A backside wiring structure BWS is described.

[0151] In an embodiment, Fig.10 After polishing the first semiconductor substrate 102 in process P510 and Fig.10 Before forming the second BEOL structure BS2 in the process P512 of the embodiment, a process of forming a contact structure may be further performed, the contact structure including a plug portion penetrating the first semiconductor substrate 102 from the polished backside surface 102B of the first semiconductor substrate 102 in the vertical direction (Z direction). For example, the formation of the contact structure may further include forming a contact structure including a reference FIG. 8A to FIG. 8D The contact structure of the via power rail VPR and the power rail wiring MPR described, formed including reference 9A to 9CThe contact structures of the back side source / drain contacts DBC and the power rail wiring MPR4 described above, or contact structures formed therefrom modified and changed in various ways.

[0152] In the method of manufacturing an IC device according to the inventive concept, even when the first semiconductor substrate 102 gradually becomes thinner and the size of the pattern to be formed on the first semiconductor substrate 102 becomes smaller, during the manufacturing process of the IC devices 100, 100A, and 100B, process failures caused by the distortion of the first semiconductor substrate 102 and overlay errors in patterns at different vertical heights formed on the first semiconductor substrate 102 can be minimized. Therefore, in the method of manufacturing an IC device according to the inventive concept, by improving the CD uniformity of the pattern required for manufacturing the IC device, a reliable IC device can be provided, and the IC device manufacturing productivity can be improved.

[0153] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: a first semiconductor substrate having a front side surface and a back side surface opposite to each other; A front-end process structure, the front-end process structure is located on the front side surface of the first semiconductor substrate, and the front-end process structure includes a plurality of fin-type active areas; a first back-end-of-process structure, the first back-end-of-process structure being located on the front-end-of-process structure, the first back-end-of-process structure being spaced apart from the first semiconductor substrate in a vertical direction in such a manner that the front-end-of-process structure is located between the first back-end-of-process structure and the first semiconductor substrate; a second back-end-of-process structure, the second back-end-of-process structure being located on the backside surface of the first semiconductor substrate, the second back-end-of-process structure being spaced apart from the front-end-of-process structure in the vertical direction in such a manner that the first semiconductor substrate is located between the second back-end-of-process structure and the front-end-of-process structure; as well as a second semiconductor substrate, the second semiconductor substrate being spaced apart from the first semiconductor substrate in the vertical direction in such a manner that the front-end-of-the-line structure and the first back-end-of-the-line structure are located between the second semiconductor substrate and the first semiconductor substrate, The Young's modulus of a first crystal direction extending parallel to the front surface in the first semiconductor substrate is different from the Young's modulus of a second crystal direction overlapping with the first crystal direction in the vertical direction and extending parallel to the first crystal direction in the second semiconductor substrate.

2. The integrated circuit device according to claim 1, in, Each of the front side surface of the first semiconductor substrate and the main surface of the second semiconductor substrate facing the first semiconductor substrate has a (100) crystal plane, and The front side surface of the first semiconductor substrate extends parallel to the front side surface of the first semiconductor substrate. <110> direction and the main surface of the second semiconductor substrate extending parallel to the main surface of the second semiconductor substrate <100> directions overlap each other in the vertical direction, and extend parallel to each other.

3. The integrated circuit device according to claim 1, in, The front side surface of the first semiconductor substrate has a (100) crystal plane, and The main surface of the second semiconductor substrate facing the first semiconductor substrate has a (111) crystal plane. 4 . The integrated circuit device of claim 1 , further comprising an adhesive layer between the first back-end-of-line structure and the second semiconductor substrate.

5. The integrated circuit device according to claim 1, further comprising: a power rail wiring, the power rail wiring passing through the first semiconductor substrate in the vertical direction, The second back-end process structure includes a wiring layer located on the backside surface of the first semiconductor substrate, and the wiring layer is connected to the power rail wiring.

6. The integrated circuit device according to claim 1, further comprising: a contact structure, the contact structure passing through the first semiconductor substrate in the vertical direction, Wherein, the front-end process structure also includes: a source / drain region, the source / drain region being located on a first fin-type active region selected from the plurality of fin-type active regions, the source / drain region being spaced apart from the first semiconductor substrate in the vertical direction in such a manner that the first fin-type active region is located between the source / drain region and the first semiconductor substrate; and a source / drain contact, the source / drain contact being spaced apart from the first semiconductor substrate in the vertical direction in such a manner that the first fin-type active region and the source / drain region are located between the source / drain contact and the first semiconductor substrate, the source / drain contact being connected to the source / drain region, and The contact structure is connected to a selected one of the source / drain region and the source / drain contact.

7. The integrated circuit device according to claim 1, further comprising: a power rail wiring, the power rail wiring passing through the first semiconductor substrate in the vertical direction; as well as a backside source / drain contact passing through a selected fin-type active region of the plurality of fin-type active regions in the vertical direction, the backside source / drain contact being connected to the power rail wiring, The front-end process structure further includes a source / drain region located on the selected fin-type active region among the plurality of fin-type active regions, the source / drain region being spaced apart from the first semiconductor substrate in the vertical direction in such a manner that the selected fin-type active region among the plurality of fin-type active regions is located between the source / drain region and the first semiconductor substrate, and Wherein, the back side source / drain contact is connected to the source / drain region.

8. The integrated circuit device according to claim 1, wherein: The front-end process structure also includes: A gate line, the gate line being located on a first fin type active region selected from the plurality of fin type active regions; At least one nanosheet, the at least one nanosheet is located between the first fin-type active region and the gate line, and the at least one nanosheet is surrounded by the gate line; A source / drain region, the source / drain region is located on the first fin-type active region, and the source / drain region is in contact with the at least one nanosheet; a source / drain contact, the source / drain contact being located between the source / drain region and the first back-end structure, the source / drain contact being connected to the source / drain region; an insulating structure, the insulating structure comprising a device isolation film covering two side walls of the first fin type active region; and A contact structure passes through the first semiconductor substrate and the insulating structure in the vertical direction and is connected to a selected one of the source / drain region and the source / drain contact.

9. An integrated circuit device, comprising: a first semiconductor substrate having a front side surface and a back side surface opposite to each other; A front-end process structure, the front-end process structure is located on the front side surface of the first semiconductor substrate, and the front-end process structure constitutes a logic unit; a first back-end-of-process structure, the first back-end-of-process structure being located on the front-end-of-process structure, the first back-end-of-process structure being spaced apart from the first semiconductor substrate in a vertical direction in such a manner that the front-end-of-process structure is located between the first back-end-of-process structure and the first semiconductor substrate; a second back-end-of-process structure, the second back-end-of-process structure being located on the backside surface of the first semiconductor substrate, the second back-end-of-process structure being spaced apart from the front-end-of-process structure in the vertical direction in such a manner that the first semiconductor substrate is located between the second back-end-of-process structure and the front-end-of-process structure; as well as a second semiconductor substrate, the second semiconductor substrate being spaced apart from the first semiconductor substrate in the vertical direction in such a manner that the front-end-of-the-line structure and the first back-end-of-the-line structure are located between the second semiconductor substrate and the first semiconductor substrate, Wherein, the front-end process structure includes: a fin-type active region, the fin-type active region being integrally connected to the first semiconductor substrate; a source / drain region, the source / drain region being located on the fin-type active region, the source / drain region being spaced apart from the first semiconductor substrate in the vertical direction in such a manner that the fin-type active region is located between the source / drain region and the first semiconductor substrate; a source / drain contact, the source / drain contact being spaced apart from the first semiconductor substrate in the vertical direction in such a manner that the fin-type active region and the source / drain region are located between the source / drain contact and the first semiconductor substrate, the source / drain contact being connected to the source / drain region; a power rail wiring that passes through the first semiconductor substrate in the vertical direction; and a contact structure having one end connected to a selected one of the source / drain region and the source / drain contact and another end connected to the power rail wiring, wherein the second back-end process structure comprises a wiring layer located on the backside surface of the first semiconductor substrate, the wiring layer being connected to the power rail wiring, and The Young's modulus of a first crystal direction extending parallel to the front surface in the first semiconductor substrate is different from the Young's modulus of a second crystal direction overlapping with the first crystal direction in the vertical direction and extending parallel to the first crystal direction in the second semiconductor substrate.

10. The integrated circuit device according to claim 9, in, Each of the front side surface of the first semiconductor substrate and the main surface of the second semiconductor substrate facing the first semiconductor substrate has a (100) crystal plane, and The front side surface of the first semiconductor substrate extends parallel to the front side surface of the first semiconductor substrate. <110> direction and the main surface of the second semiconductor substrate extending parallel to the main surface of the second semiconductor substrate <100> directions overlap each other in the vertical direction, and extend parallel to each other.

11. The integrated circuit device according to claim 9, in, The front side surface of the first semiconductor substrate has a (100) crystal plane, and The main surface of the second semiconductor substrate facing the first semiconductor substrate has a (111) crystal plane.

12. An integrated circuit device, comprising: a first semiconductor substrate having a front side surface and a back side surface opposite to each other; A front-end process structure, the front-end process structure comprising a fin-type active area, a gate line and at least one nanosheet, the fin-type active area is integrally connected to the first semiconductor substrate, the gate line is located above the fin-type active area, and the at least one nanosheet is between the fin-type active area and the gate line and surrounded by the gate line; a first back-end-of-the-process structure, the first back-end-of-the-process structure being located on the front-end-of-the-process structure, the first back-end-of-the-process structure being vertically spaced from the first semiconductor substrate in such a manner that the front-end-of-the-process structure is located between the first back-end-of-the-process structure and the first semiconductor substrate, and the first back-end-of-the-process structure comprising a front-side wiring structure; a second back-end-of-process structure, the second back-end-of-process structure being located on the backside surface of the first semiconductor substrate, the second back-end-of-process structure being spaced apart from the front-end-of-process structure in the vertical direction in such a manner that the first semiconductor substrate is located between the second back-end-of-process structure and the front-end-of-process structure, and the second back-end-of-process structure comprising a backside wiring structure; as well as a second semiconductor substrate, the second semiconductor substrate being spaced apart from the first semiconductor substrate in the vertical direction in such a manner that the front-end-of-the-line structure and the first back-end-of-the-line structure are located between the second semiconductor substrate and the first semiconductor substrate, wherein the front surface of the first semiconductor substrate has a (100) crystal plane, The main surface of the second semiconductor substrate facing the first semiconductor substrate has a (100) crystal plane or a (111) crystal plane, and The Young's modulus of a first crystal direction extending parallel to the front surface in the first semiconductor substrate is different from the Young's modulus of a second crystal direction overlapping with the first crystal direction in the vertical direction and extending parallel to the first crystal direction in the second semiconductor substrate.

13. A method of manufacturing an integrated circuit device, the method comprising: preparing a first semiconductor substrate, the first semiconductor substrate having a front surface and a back surface opposite to the front surface, the front surface having a (100) crystal plane; forming a front-end process structure on the front side surface of the first semiconductor substrate; forming a first back-end process structure on the front-end process structure; forming a bonding layer on the first back-end process structure; bonding the first back-end structure to a second semiconductor substrate by using the bonding layer so that the second semiconductor substrate faces the first semiconductor substrate in a vertical direction, the second semiconductor substrate having a Young's modulus different from that of the first semiconductor substrate; polishing the first semiconductor substrate from the backside surface of the first semiconductor substrate to reduce the thickness of the first semiconductor substrate while the first back-end structure is being bonded to the second semiconductor substrate; as well as A second back-end-of-process structure is formed on the polished backside surface of the first semiconductor substrate while the first back-end-of-process structure is being bonded to the second semiconductor substrate.

14. The method according to claim 13, wherein: A main surface of the second semiconductor substrate facing the first semiconductor substrate has a (100) crystal plane.

15. The method according to claim 13, wherein: A main surface of the second semiconductor substrate facing the first semiconductor substrate has a (111) crystal plane.

16. The method according to claim 13, in, The main surface of the second semiconductor substrate facing the first semiconductor substrate has a (100) crystal plane, The first semiconductor substrate includes a first notch, the first notch along <110> direction is formed in an edge of the front side surface of the first semiconductor substrate in a first radial direction, The second semiconductor substrate includes a second notch, the second notch being <100> direction is formed in an edge of the main surface in the second radial direction facing the first semiconductor substrate, and Wherein, bonding the first back-end process structure to the second semiconductor substrate comprises: aligning the first semiconductor substrate with the second semiconductor substrate so that the first recess and the second recess overlap each other in the vertical direction and the first radial direction and the second radial direction are in the same direction.

17. The method according to claim 13, in, A main surface of the second semiconductor substrate facing the first semiconductor substrate has a (100) crystal plane, and The step of bonding the first back-end process structure to the second semiconductor substrate comprises: aligning the first semiconductor substrate with the second semiconductor substrate so that the front side surface of the first semiconductor substrate is parallel to the front side surface of the first semiconductor substrate. <110> direction and the main surface of the second semiconductor substrate extending parallel to the main surface of the second semiconductor substrate <100> directions overlap each other in the vertical direction, and extend parallel to each other.

18. The method according to claim 13, in, A main surface of the second semiconductor substrate facing the first semiconductor substrate has a (111) crystal plane, The first semiconductor substrate includes a first notch, the first notch along <110> direction is formed in an edge of the front side surface of the first semiconductor substrate in a first radial direction, The second semiconductor substrate includes a second notch, the second notch being <100> Direction or <112> direction is formed in an edge of the main surface in the second radial direction facing the first semiconductor substrate, and Wherein, bonding the first back-end process structure to the second semiconductor substrate comprises: aligning the first semiconductor substrate with the second semiconductor substrate so that the first recess and the second recess overlap each other in the vertical direction, and the first radial direction and the second radial direction are in the same direction.

19. The method according to claim 13, in, A main surface of the second semiconductor substrate facing the first semiconductor substrate has a (111) crystal plane, and The step of bonding the first back-end process structure to the second semiconductor substrate comprises: aligning the first semiconductor substrate with the second semiconductor substrate so that the front side surface of the first semiconductor substrate is parallel to the front side surface of the first semiconductor substrate. <110> direction and the main surface of the second semiconductor substrate extending parallel to the main surface of the second semiconductor substrate <100> Direction or <112> directions overlap each other in the vertical direction, and extend parallel to each other.

20. The method according to claim 13, wherein: Joining the first back-end process structure to the second semiconductor substrate includes: aligning the first semiconductor substrate with the second semiconductor substrate so that the Young's modulus of a first crystal direction extending parallel to the front side surface in the first semiconductor substrate is different from the Young's modulus of a second crystal direction overlapping with the first crystal direction in the vertical direction and extending parallel to the first crystal direction in the second semiconductor substrate.

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