Array substrate, display panel and display device

Abstract

The invention relates to an array substrate, a display panel and a display device. The array substrate comprises a plurality of pixel circuits arranged in an array mode, a plurality of data signal lines arranged in the first direction and a plurality of electrostatic discharge lines arranged in the second direction. Wherein the data signal lines are connected with the same column of pixel circuits; the electrostatic discharge line is connected with each column of pixel circuit; a target pixel circuit in the plurality of pixel circuits comprises a first transistor and a second transistor, and the first transistor and the second transistor are arranged on an electrostatic discharge path between the data signal line and the electrostatic discharge line. According to the scheme, the problem that the array substrate is abnormal due to electrostatic damage can be avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] The array substrate is the core component of the display panel. The ESD circuit is an electrostatic discharge circuit used to release static electricity in the array substrate. The current ESD circuits are connected to the TFT (Thin Film Transistor) of each pixel circuit in the array substrate. Among them, each TFT is connected to the data signal line and works under the control of the data signal transmitted by the data signal line to drive the pixel circuit to display.

[0003] Static electricity is transmitted to the TFT along with the data signal, and then released through the TFT to the release line of the ESD circuit. However, when the static voltage is high, the static electricity will break down the TFT, causing the level of the data signal connected to the broken down TFT to be changed, thus causing all TFTs connected to the data signal line transmitting the data signal to be abnormal, and a column of pixel circuits on the array substrate to display abnormally, resulting in good or bad. Summary of the invention

[0004] Based on this, it is necessary to provide an array substrate, a display panel and a display device to address the above technical problems, which can avoid the problem of abnormal array substrate caused by electrostatic damage.

[0005] In a first aspect, the present application provides an array substrate, the array substrate comprising:

[0006] A plurality of pixel circuits arranged in an array;

[0007] A plurality of data signal lines arranged along a first direction, the data signal lines being connected to the pixel circuits in the same column;

[0008] A plurality of electrostatic release lines arranged along the second direction, the electrostatic release lines being connected to each column of the pixel circuit;

[0009] The target pixel circuit among the plurality of pixel circuits comprises a first transistor and a second transistor, and both the first transistor and the second transistor are arranged on an electrostatic release path between the data signal line and the electrostatic release line.

[0010] In one embodiment, the target pixel circuit is located in a target area of ​​the array substrate, and the target area is an area that meets an electrostatic damage condition; the electrostatic damage condition is that the probability that the voltage of the transmitted static electricity is within a preset damage voltage range is greater than a preset probability threshold.

[0011] In one embodiment, the preset wounding voltage range is a voltage range greater than a first voltage threshold and a voltage range less than a second voltage threshold.

[0012] In one embodiment, the target area includes a left area divided by a left boundary line of the array substrate and a first dividing line, a right area divided by a right boundary line of the array substrate and a second dividing line, and a middle area that does not overlap with the left area and the right area.

[0013] In one embodiment, the source of the first transistor and the source of the second transistor are connected to corresponding data signal lines, and the gates and drains of the first transistor and the second transistor are short-circuited and connected to the electrostatic release line.

[0014] In one embodiment, the array substrate also includes a plurality of connecting lines arranged between the data signal line and each target pixel circuit for transmitting the data signal output by the data signal line to the first transistor and the second transistor in the target pixel circuit; wherein the metal routing included in the connecting line is connected by a plurality of vias.

[0015] In one embodiment, the plurality of via holes are 2 via holes or 4 via holes.

[0016] In one embodiment, the connecting line also includes a target routing line; the target routing line is a routing line after the gate and drain of the first transistor are short-circuited, and the gate and drain of the second transistor are short-circuited; the routing width of the target routing line is greater than a preset width threshold.

[0017] In a second aspect, the present application further provides a display panel, comprising an array substrate as described in any one of the above-mentioned first aspects.

[0018] In a third aspect, the present application further provides a display device, which includes the display panel as described in the second aspect above.

[0019] In the above array substrate, display panel and display device, the array substrate includes a plurality of pixel circuits arranged in an array, a plurality of data signal lines arranged along a first direction and a plurality of electrostatic release lines arranged along a second direction; wherein the data signal line is connected to the pixel circuits in the same column, and the electrostatic release line is connected to the pixel circuits in each column; the target pixel circuit in the plurality of pixel circuits includes a first transistor and a second transistor, and the first transistor and the second transistor are both arranged on the electrostatic release path between the data signal line and the electrostatic release line. In this way, since the target pixel circuit includes two TFTs, the static electricity tolerance of the target pixel circuit is enhanced, and when the static electricity voltage is high, the probability of the TFT being damaged is reduced. In addition, even if the static electricity voltage is high, only one of the TFTs will be damaged, and the damaged TFT will be short-circuited, so the other TFT can still work normally, ensuring that the target pixel circuit is normal, and ensuring that the entire column of pixel circuits connected to the data signal line is normal, thereby avoiding the problem of abnormal array substrate caused by static electricity damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a schematic diagram of an array substrate in one embodiment;

[0022] Figure 2 is a schematic diagram of another array substrate in one embodiment;

[0023] Figure 3 is a schematic diagram of another array substrate in one embodiment;

[0024] Figure 4 is a schematic diagram of another array substrate in one embodiment;

[0025] Figure 5 is a schematic diagram of another array substrate in one embodiment;

[0026] Figure 6 A schematic diagram of hierarchical wiring in an embodiment;

[0027] Figure 7 A schematic cross-sectional view of an embodiment;

[0028] Figure 8 Another cross-sectional schematic diagram in one embodiment;

[0029] Fig. 9Another cross-sectional schematic diagram in one embodiment;

[0030] Fig.10 Another cross-sectional schematic diagram in one embodiment;

[0031] Fig.11 Another cross-sectional schematic diagram in one embodiment;

[0032] Fig.12 Another schematic diagram of hierarchical wiring in one embodiment;

[0033] Fig.13 A schematic diagram for verifying the relationship between electrostatic voltage and target trace width in one embodiment;

[0034] Fig.14 A schematic diagram for verifying another relationship between electrostatic voltage and target trace width in one embodiment;

[0035] Fig.15 FIG. 4 is a schematic diagram showing the distribution of target pixel circuits and non-target pixel circuits in an array substrate in one embodiment. DETAILED DESCRIPTION

[0036] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0037] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0038] In this document, spatially related terms such as "upper" and "lower" are defined with reference to the accompanying drawings. Therefore, it will be understood that "upper" and "lower" are used interchangeably. It will be understood that when a layer is referred to as being "on" another layer, it can be directly formed on the other layer, or intervening layers may also be present. Therefore, it will be understood that when a layer is referred to as being "directly on" another layer, there are no intervening layers interposed therebetween.

[0039] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be intervening layers. In addition, it is also understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers. In addition, the same reference numerals always represent the same elements.

[0040] Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another component. It will also be understood that expressions used in the singular form include plural expressions, unless the expression in the singular form has a significantly different meaning in the context. In addition, in the following embodiments, it will also be understood that the terms "comprising" and / or "having" used herein illustrate the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0041] In the following embodiments, when a layer, region, or element is "connected", it can be interpreted that the layer, region, or element is not only directly connected but also connected through other constituent elements placed therebetween. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. can be connected or electrically connected not only directly or directly, but also through another layer, region, element, etc. placed therebetween.

[0042] As used in the application documents, the term "and / or" includes any and all combinations of one or more of the related listed items. When a statement such as "at least one (one) of..." is placed after a list of elements (elements), it modifies the entire list of elements (elements), rather than modifying the individual elements (elements) in the list (elements).

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present invention pertains. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0044] It should also be understood that the terms “include / comprises” or “having” and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0045] The array substrate is the core component of the display panel. Existing array substrates have poor anti-static damage capabilities. For example, during the evaporation process of the array substrate, a large amount of electrostatic discharge is easily generated. The good-quality loss caused by ESD circuit damage is about 1.5%, which has a great impact on the yield rate. At the same time, the static electricity level of the production line cannot be effectively improved and reduced.

[0046] The ESD circuit is an electrostatic discharge circuit used to release static electricity in the array substrate. The current ESD circuits are connected to the transistors (TFTs) of each pixel circuit in the array substrate. Among them, each TFT is connected to the data signal line and works under the control of the data signal transmitted by the data signal line to drive the pixel circuit to display. Static electricity will be transmitted to the TFT along with the data signal, and then transmitted to the release line of the ESD circuit through the TFT for release. However, when the static voltage is high, static electricity will damage or even break down the TFT, causing the level of the data signal connected to the broken-down TFT to be changed, thereby causing all TFTs connected to the data signal line transmitting the data signal to be abnormal, and a column of pixel circuits on the array substrate will display abnormally, which can be judged as a single line defect in the S direction, and good damage will occur.

[0047] In view of this, an embodiment of the present application provides an array substrate, which can avoid the problem of array substrate abnormality caused by electrostatic damage.

[0048] In one embodiment, Figure 1 As shown, an array substrate is provided, the array substrate 100 includes a plurality of pixel circuits 101 arranged in an array, a plurality of data signal lines 102 arranged along a first direction, and a plurality of electrostatic release lines 103 arranged along a second direction. The data signal lines 102 are connected to the same column of pixel circuits; the electrostatic release lines 103 are connected to each column of pixel circuits; the target pixel circuit in the plurality of pixel circuits 101 includes a first transistor 101A and a second transistor 101B, and the first transistor 101A and the second transistor 101B are both arranged in an electrostatic release path ( Figure 1 not shown).

[0049] It should be noted that Figure 1 Only part of the pixel circuits 101 in the array substrate 100 is shown as an example, and not all the pixel circuits 101 in the complete array substrate 100 are shown.

[0050] It can be understood that the line between the data signal line 102 and the electrostatic release line 103 is the electrostatic release path.

[0051] Among them, the data signal line 102 is connected to the same column of pixel circuits 101, and the pixel circuit 101 includes transistors and other devices; the data signal line 102 outputs a data signal (that is, a data signal), and the data signal drives the transistors in the pixel circuit 101 to work, and then the entire pixel circuit 101 is displayed when the transistors work normally.

[0052] Optional, such as Figure 1 As shown, the data signal line 102 is connected to all pixel circuits 101 in the same column.

[0053] Optionally, each electrostatic release line 103 is connected to part of the pixel circuits 101 in each column of pixel circuits 101 , and it is ensured that each pixel circuit 101 is connected to at least one electrostatic release line 103 .

[0054] Normally, when the electrostatic voltage is within the normal voltage range, static electricity can be transmitted to the electrostatic release line 103 via the data signal line 102 and the electrostatic release path along with the data signal, and then released on the electrostatic release line 103. However, when the electrostatic voltage is not within the normal voltage range, static electricity may damage or even break down the transistors on the electrostatic release path, and the damaged transistors will short-circuit and fail, thereby directly short-circuiting the data signal line 102 and the electrostatic release line 103, changing the level of the data signal, and causing the array substrate 100 to work abnormally.

[0055] In the embodiment of the present application, the target pixel circuit among the multiple pixel circuits 101 includes a first transistor 101A and a second transistor 101B. When the electrostatic voltage is not within the normal voltage range, static electricity damages one of the first transistor 101A and the second transistor 101B and is released, while the other undamaged transistor can still operate normally, and there will be no interference between the data signal line 102 and the electrostatic release line 103.

[0056] For example, when the electrostatic voltage is within the normal voltage range, the static electricity first passes through the first transistor 101A, and then passes through the second transistor 101B to be released after being transmitted to the electrostatic release line 103. When the electrostatic voltage is not within the normal voltage range, the static electricity first damages the first transistor 101A and is released. At this time, the first transistor 101A is short-circuited and there is no static electricity on the electrostatic release path, and the second transistor 101B works normally.

[0057] Optional, such as Figure 1 As shown, all pixel circuits 101 can be used as target pixel circuits, and all include a first transistor 101A and a second transistor 101B. In this way, no matter to which pixel circuit 101 the static electricity follows the data signal to be transmitted, the data signal will not be changed due to static electricity damage, that is, the static electricity damage problem of each pixel circuit 101 can be avoided.

[0058] Exemplarily, the first transistor and the second transistor may be TFTs.

[0059] Optional, such as Figure 1 As shown, the first direction is arranged perpendicular to the second direction, thus saving substrate space.

[0060] Optional, such as Figure 2 1 shows a schematic diagram of another array substrate 100 , wherein one data signal line 102 is connected to part of the pixel circuits 101 in the same column of pixel circuits 101 . Two data signal lines 102 may be connected to all the pixel circuits 101 in one column of pixel circuits 101 .

[0061] In addition, the plurality of electrostatic release lines 103 may include a high-level electrostatic release line PVGH and a low-level electrostatic release line PVGL; the low-level electrostatic release line PVGL may be two, refer to Figure 2 As shown. Optionally, three electrostatic release lines 103 can be set at the edge of the array substrate 100, for example, at the bottom frame of the array substrate 100, and each pixel circuit 101 can be connected to the electrostatic release line 103 accordingly. Here, optionally, each pixel circuit 101 is connected to PVGH or PVGL, for example, referring to Figure 2 As shown, in each pixel circuit 101 in a column of pixel circuits 101, every two pixel circuits 101 form a group, and in a group of pixel circuits 101, one pixel circuit 101 is connected to PVGH, and the other is connected to PVGL. The specific electrostatic transmission route can be referred to the description below.

[0062] Optionally, some pixel circuits 101 with a higher probability of being damaged by static electricity among all pixel circuits 101 are used as target pixels, and the target pixel circuits include the first transistor 101A and the second transistor 101B, while other non-target pixel circuits include a single TFT. In this way, abnormalities of the array substrate 100 caused by static electricity damage can be avoided, and space and cost can be saved.

[0063] In addition, the first transistor 101A and the second transistor 101B are connected in the same manner. Exemplarily, for each target pixel circuit, the source of the first transistor 101A and the source of the second transistor 101B are both connected to the corresponding data signal line 102, and the gate and drain of the first transistor 101A and the second transistor 101B are short-circuited and connected to the electrostatic release line 103.

[0064] In the above array substrate 100, display panel and display device, the array substrate 100 includes a plurality of pixel circuits 101 arranged in an array, a plurality of data signal lines 102 arranged along a first direction and a plurality of electrostatic release lines 103 arranged along a second direction; wherein the data signal lines 102 are connected to the pixel circuits 101 in the same column, and the electrostatic release lines 103 are connected to the pixel circuits 101 in each column; the target pixel circuit in the plurality of pixel circuits 101 includes a first transistor 101A and a second transistor 101B, and the first transistor 101A and the second transistor 101B are both arranged on the electrostatic release path between the data signal line 102 and the electrostatic release line 103. In this way, since the target pixel circuit includes two TFTs, the target pixel circuit has an enhanced tolerance to static electricity, and when the electrostatic voltage is high, the probability of the TFT being damaged is reduced. In addition, even if the electrostatic voltage is high, only one of the TFTs will be damaged, causing a short circuit in the damaged TFT, so the other TFT can still work normally, ensuring that the target pixel circuit is normal and that the entire column of pixel circuits 101 connected to the data signal line 102 is normal, thereby avoiding abnormalities in the array substrate 100 caused by electrostatic damage.

[0065] In one embodiment, the target pixel circuit is located in the target area of ​​the array substrate 100, and the target area is an area that meets the electrostatic damage condition; the electrostatic damage condition is that the probability that the voltage of the transmitted static electricity is within the preset damage voltage range is greater than a preset probability threshold. If the static electricity voltage is within the preset damage voltage range, the static electricity can damage the TFT.

[0066] That is, the target area is an area where the static voltage passing through is more likely to damage the TFT, and the pixel circuits 101 in the target area can all be used as target pixel circuits, with the first transistor 101A and the second transistor 101B set, while the pixel circuits 101 in other non-target areas can be set with a single TFT.

[0067] In the embodiment of the present application, the target pixel circuit is determined according to the electrostatic damage condition, which can avoid abnormal problems of the array substrate 100 caused by electrostatic damage and save costs.

[0068] In one embodiment, the preset wounding voltage range is a voltage range greater than a first voltage threshold and a voltage range less than a second voltage threshold.

[0069] Exemplary, reference Figure 3Taking the target pixel circuit X and the target pixel circuit Y in the lower left corner as an example, when the electrostatic voltage is higher than the VGH voltage (7V), the static electricity will be introduced into the PVGH wiring after passing through X to complete the release; when the electrostatic voltage is lower than the VGL voltage (-7V), the static electricity will be introduced into the PVGL wiring after passing through Y to complete the release; when the static electricity is between -7V and 7V, the circuit is not conductive and the ESD circuit is not started.

[0070] When the electrostatic voltage is much larger than 7V and does not reach the PVGH line (or much smaller than -7V and does not reach the PVGL line), it directly breaks down a TFT in the target pixel circuit.

[0071] For example, the condition for a TFT to turn on is: |Vgs| (gate voltage - source voltage) > |Vth| (threshold voltage: the voltage required to form a conductive channel).

[0072] When the electrostatic voltage is 10V, the static electricity needs to be released along the data signal line 102 through the TFT in X into the PVGH line. At this time, for each TFT in X, Vgs=VGH-electrostatic voltage=|7-10|V=3V. Since Vth=-1.5V, |Vth|=1.5V, Vgs>Vth, so the circuit can be turned on. At this time, due to the insufficient anti-damage ability of TFT, a TFT in the target pixel circuit is damaged before the static electricity reaches the PVGH line. In the embodiment of the present application, another TFT is used to ensure the normal operation of the target pixel circuit.

[0073] Therefore, optionally, the first voltage threshold may be a voltage value greater than 7V that may damage the TFT, and the second voltage threshold may be a voltage value less than -7V that may damage the TFT.

[0074] In the embodiment of the present application, the principle of electrostatic damage is combined with the array substrate 100 product. By designing a target pixel circuit in the target area, the number of TFTs connected in the ESD circuit of the array substrate 100 is improved, thereby reducing the impact of static electricity on the array substrate 100 and reducing the risk of short circuits, thereby achieving the effect of improving the yield of the array substrate 100.

[0075] In one embodiment, please refer to Figure 4 , which shows a schematic diagram of another array substrate 100 provided in an embodiment of the present application. The target area includes a left area divided by the left boundary line of the array substrate 100 and the first dividing line, a right area divided by the right boundary line of the array substrate 100 and the second dividing line, and a middle area that does not overlap with the left area and the right area.

[0076] Among them, the inventors of the present application have discovered through long-term experiments, research and testing that in the current production line evaporation process, the electrostatic voltage in the left, middle and right areas of the array substrate 100 is relatively high, and electrostatic damage basically occurs in these areas. Therefore, these areas with a higher probability of electrostatic damage can be used as target areas to determine the target pixel circuit, and the first transistor 101A and the second transistor 101B are set in the target pixel circuit.

[0077] Optionally, the pixel circuit 101 in other non-target areas may include the first transistor 101A.

[0078] In addition to providing two TFTs in the target pixel circuit, on this basis, other methods may be combined to increase the static electricity absorption capacity of the array substrate 100 and reduce the probability of static electricity damage.

[0079] exist Figure 2 Based on this, the present application exemplifies Figure 5 Schematic diagram of another array substrate 100 shown. The array substrate 100 further includes a plurality of connection lines 104 disposed between the data signal line 102 and each target pixel circuit for transmitting the data signal output by the data signal line 102 to the first transistor 101A and the second transistor 101B in the target pixel circuit; wherein the metal wiring included in the connection line 104 is connected through a plurality of vias, and it should be noted that Figure 5 Vias are not shown.

[0080] In other words, the metal wiring on the connection line 104 is interrupted and then connected through a plurality of vias. Optionally, the vias may be ILD (Inter layer dielectric) holes.

[0081] The connection line 104 includes multiple levels of wiring, and the metal wiring is one of the levels.

[0082] For ease of understanding, Figure 6 Schematic diagram of hierarchical wiring of the array substrate 100 is shown. Figure 7 A schematic cross-sectional view at position A is shown; Figure 8 A schematic cross-sectional view at position B is shown; Fig. 9 A schematic cross-sectional view at position C is shown; Fig.10 A schematic cross-sectional view at position D is shown; Fig.11The cross-sectional schematic diagram at position E is shown. Among them, M1, M2, and M3 are all metal layers, M1 and M2 are the routing of the data signal line 102, and M3 is the routing of the electrostatic release line 103; the P-Si layer is also the routing of the data signal line 102. Here, the P-Si layer is the routing after the gate and drain of the TFT in the pixel circuit 101 are short-circuited, which is called the P-Si routing. M1 is the gate routing of the TFT. CI (capacitor insulation) is the capacitor insulation layer, GI (gate insulation) is the gate insulation layer, and the bottom CVD (Chemical Vapor Deposition) is chemical vapor deposition.

[0083] Figure 6 The array substrate 100 shown in FIG. 1 is a target pixel circuit, and each includes two TFTs. As mentioned above, the pixel circuit 101 in the target area is a target pixel circuit, and the pixel circuit 101 in the non-target area is not a target pixel circuit. Fig.12 A schematic diagram of the hierarchical wiring of the pixel circuit 101 in a non-target area is shown.

[0084] In one embodiment, the plurality of vias is 2 vias or 4 vias.

[0085] refer to Figure 6 As shown, the area E contains four vias on the connection line 104. As mentioned above, the vias may be ILD holes.

[0086] In one embodiment, the connection line 104 also includes a target wiring, and the target wiring is located below the metal layer. The static electricity is transmitted to the target wiring through the via hole and is released after being absorbed by the target wiring.

[0087] In this way, when static electricity enters from the Data routing, if the static electricity voltage is within the preset damage voltage range, the static electricity will first be transmitted to the target routing under the metal layer through the via on the connecting line 104. The target routing absorbs the static electricity and is broken, and the static electricity is released. At this time, there will be no defects. In addition, if the static electricity also damages a TFT in the target pixel circuit, there will be no defects at this time, thereby achieving the effect of improving the yield.

[0088] In one embodiment, the connection line 104 further includes a target wiring; the target wiring is a wiring after the gate and the drain of the first transistor 101A are short-circuited, and a wiring after the gate and the drain of the second transistor 101B are short-circuited.

[0089] The routing after the gate and drain are short-circuited is the above-mentioned P-Si routing.

[0090] In one embodiment, the routing width of the target routing line is greater than a preset width threshold.

[0091] Among them, the larger the width of the P-Si line, the larger the amount of charge it can accommodate. Therefore, increasing the width of the P-Si line can increase the amount of charge that the circuit can accommodate, and can also enhance the anti-static ability of the TFT in the pixel unit, thereby reducing the impact of static electricity on the array substrate 100.

[0092] Optionally, the routing width of the target routing may be 10 um.

[0093] It should be noted that the widths of M1, M2, M3 and vias on the array substrate 100 remain unchanged, and only the width of the P-Si wiring becomes larger. This can save space and enhance the charge capacity of the circuit.

[0094] like Fig.13 The figure shows the relationship between the static voltage and the target trace width. It can be seen that when the static voltage is constant, the width of the P-Si trace increases by 1um, and the defect rate decreases by about 0.5%. Fig.14 Another schematic diagram for verifying the relationship between the electrostatic voltage and the target wiring width is shown. It can be seen that when the width of the P-Si wiring is constant, the defect rate will increase by about 0.5% for every 500V increase in the static electricity. Therefore, by increasing the width of the P-Si wiring, the impact of electrostatic breakdown on the array substrate can be further improved.

[0095] Take the case where the target pixel circuits are distributed in multiple areas of the array substrate as an example. Fig.15 The schematic diagram of the distribution of target pixel circuits and non-target pixel circuits in the array substrate is shown. The ESD circuit part includes multiple electrostatic discharge lines. All pixel circuits connected to the electrostatic discharge line 1, 3, and 5 are target pixel circuits, and all pixel circuits connected to the 2 and 4 parts are not target pixel circuits. In this way, the array substrate can break through the bottleneck of yield improvement and make the yield meet the standard. All processes involved in this design are mature, with low unknown risks and easy to implement.

[0096] In one embodiment, the present application further provides a display panel. The display panel may include the array substrate in the above embodiment. For the specific content of the array substrate, please refer to the relevant description in the above embodiment, which can achieve the technical effect of the array substrate in the above embodiment and will not be repeated here.

[0097] In one embodiment, the present application further provides a display device. The display device includes the display panel in the above embodiment. For the specific content of the array substrate in the display panel, please refer to the relevant description in the above embodiment, which will not be repeated here. The display device can be, for example, a mobile phone, a computer, a tablet computer, a television, an electronic paper, or other device with a display function, which is not limited here.

[0098] It should be clear that each embodiment of the present application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. For the display panel embodiment and the display device embodiment, the relevant parts can refer to the description part of the array substrate embodiment. The embodiments of the present application are not limited to the specific structures described above and shown in the figures. Those skilled in the art can make various changes, modifications and additions after understanding the spirit of the present application. In addition, for the sake of brevity, a detailed description of the known technology is omitted here.

[0099] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises: A plurality of pixel circuits arranged in an array; A plurality of data signal lines arranged along a first direction, wherein the data signal lines are connected to the pixel circuits in the same column; A plurality of electrostatic release lines arranged along the second direction, wherein the electrostatic release lines are connected to the pixel circuits in each column; The target pixel circuit among the plurality of pixel circuits comprises a first transistor and a second transistor, and both the first transistor and the second transistor are arranged on an electrostatic release path between the data signal line and the electrostatic release line.

2. The array substrate according to claim 1, characterized in that: The target pixel circuit is located in a target area of ​​the array substrate, and the target area is an area that meets the electrostatic damage condition; The electrostatic injury condition is that the probability that the voltage of the transmitted static electricity is within a preset injury voltage range is greater than a preset probability threshold.

3. The array substrate according to claim 2, characterized in that: The preset injury voltage range is a voltage range greater than a first voltage threshold and a voltage range less than a second voltage threshold.

4. The array substrate according to claim 2, characterized in that: The target area includes a left area divided by a left boundary line and a first dividing line of the array substrate, a right area divided by a right boundary line and a second dividing line of the array substrate, and a middle area that does not overlap with the left area and the right area.

5. The array substrate according to claim 1, characterized in that: The source of the first transistor and the source of the second transistor are connected to corresponding data signal lines, and the gates and drains of the first transistor and the second transistor are short-circuited and connected to the electrostatic release line.

6. The array substrate according to claim 1, characterized in that: The array substrate further comprises a plurality of connection lines disposed between the data signal lines and each of the target pixel circuits and used for transmitting the data signal output by the data signal lines to the first transistor and the second transistor in the target pixel circuit; Wherein, the metal wiring included in the connecting line is connected through a plurality of vias.

7. The array substrate according to claim 6, characterized in that: The multiple via holes are 2 via holes or 4 via holes.

8. The array substrate according to claim 6, characterized in that: The connecting line also includes a target wiring; the target wiring is a wiring after the gate and the drain of the first transistor are short-circuited, and a wiring after the gate and the drain of the second transistor are short-circuited; The routing width of the target routing is greater than a preset width threshold.

9. A display panel, characterized in that: The display panel includes the array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that: The display device comprises the display panel as claimed in claim 9.

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