Semiconductor device

Abstract

A semiconductor device includes: a power switching component configured to control a flow of a current through a load path; a current sensing component configured to sense the flow of the current through the load path; and an electrostatic discharge "ESD" protection component configured to protect the current sensing component from electrostatic discharge, in which the ESD protection component includes an ESD transistor having a gate connected to a discharge path, the discharge path being configured to discharge the current from the current sensing component, and the ESD protection component being configured to protect the current sensing component from electrostatic discharge. The ESD transistor is configured such that the presence of the discharge of the first polarity turns on the ESD transistor to form a further path for dissipating the discharge.

Description

Technical Field

[0001] Embodiments described herein generally relate to semiconductor devices. Background Art

[0002] In power electronics, it is necessary to accurately sense the current flowing through a load path controlled by a semiconductor switch such as a transistor. This can be achieved by various current sensing techniques, such as a current mirror arrangement using transistors. The current through the load path can be measured by measuring the current flowing through the sensing transistor.

[0003] However, the sense transistors are typically small and therefore any electrostatic discharge that may occur may damage the sense transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure will now be described with reference to the accompanying drawings, which are provided to aid explanation and understanding. The drawings should not be considered to limit the present disclosure to the specific embodiments described herein.

[0005] Figure 1 is a schematic diagram showing an electrostatic discharge (ESD) protection component according to an embodiment;

[0006] Figure 2 is a schematic diagram showing an ESD protection component and a resistor according to an embodiment;

[0007] Figure 3A is a circuit diagram of a semiconductor device having a MOSFET according to an embodiment;

[0008] Figure 3B is a circuit diagram of a semiconductor device having a GaN-based transistor according to an embodiment;

[0009] FIG. 4A to FIG. 4B is a circuit diagram illustrating an ESD transistor and a resistor in operation as part of an exemplary sensing circuit system in accordance with an embodiment.

[0010] Figure 5 is a circuit diagram showing a configuration of a plurality of ESD transistors and resistors according to an embodiment;

[0011] Figure 6 is a graph showing a standard ESD distribution;

[0012] Fig. 7A is shown with respect to the main source (V LS ) of the negative sense supply voltage (-V LSS ) circuit diagram of a simulation test bench;

[0013] Figure 7B is shown with respect to the main source (V LS) of the positive sense supply voltage (+V LSS ) circuit diagram of a simulation test bench;

[0014] Figure 8 is a circuit diagram showing a simulation test bench with a gate driver connected;

[0015] Fig. 9 is a schematic diagram showing an ESD resistor according to an embodiment;

[0016] Fig. 10A is a circuit diagram showing an ESD resistor in more detail;

[0017] Fig. 10B and Fig. 10C is a circuit diagram illustrating an ESD resistor in operation as part of an exemplary sensing circuit system in accordance with an embodiment.

[0018] Fig.11 is a circuit diagram showing a general smart power stage (SPS) sense FET configuration. DETAILED DESCRIPTION

[0019] In an embodiment, a semiconductor device is provided, the semiconductor device comprising:

[0020] a power switching component configured to control the flow of current through the load path;

[0021] a current sensing component configured to sense current flowing through the load path; and

[0022] An electrostatic discharge (ESD) protection component is configured to protect a current sensing component from electrostatic discharge, wherein the ESD protection component includes an ESD transistor having a gate connected to a discharge path such that the presence of a discharge of a first polarity turns on the ESD transistor to form another path for dissipating the discharge.

[0023] Thus, when the ESD transistor is turned on, a low impedance current dissipation path is opened to allow a discharge having a first polarity to be dissipated. In an embodiment, a reverse path for dissipating a discharge of a second polarity is provided by the reverse conduction capability of the ESD transistor in an off state.

[0024] The ESD transistor may be any type of transistor, for example, a field effect transistor (FET) such as a MOSFET, HEMT or IGBT transistor using a range of materials (eg, Si, GaN or SiC).

[0025] In yet another embodiment, a diode is provided in parallel with the ESD transistor to allow a current dissipation path to dissipate the discharge having the second polarity. The diode may be inherent to the ESD transistor, for example, the body diode is inherent to the MOSFET, or the diode may be provided separately. For GaN FETs, the diode (if present) would be provided separately in parallel with the FET. The reverse conduction capability of GaN may also be relied upon to replace the diode.

[0026] In addition to the path through the ESD diode, there is also dissipation of a discharge having a second polarity, and thus when the ESD transistor is turned on, current can flow through the ESD component in both directions.

[0027] A current sensing transistor (often referred to as a sense transistor or sense FET) is an example of such a device that can perform a current sensing function. The sense transistor can be configured as a smaller portion of a larger main current carrying semiconductor device, such as a conventional transistor device (main transistor / FET).

[0028] During normal operation of the current sensing circuit system, the sensing transistor samples an accurate replica current from the semiconductor device, which may be a smaller fraction of the current of the semiconductor device. This can be accomplished by designing the replica sensing transistor M accordingly. LS With the main transistor M L The transistor current ratio between them (e.g. 1:N S (For example, N S =100,000)) to achieve this.

[0029] However, due to its tiny size, the sensing transistor is susceptible to damage caused by electrostatic discharge (ESD), especially ESD occurring at the sensing source pin. Therefore, it is necessary to protect the sensing transistor from ESD damage.

[0030] The above embodiments provide an ESD protection component that is configured to allow current caused by electrostatic discharge of any polarity to dissipate. The above embodiments increase the ESD robustness of the current sensing component by providing bipolar protection to the current sensing component to prevent damage caused by ESD. The ESD protection provides two low inductance paths that allow ESD current to dissipate.

[0031] In an embodiment, the power switching component includes a transistor (which will be referred to as a "main FET" or main transistor), and the current sensing component includes a sense transistor.

[0032] The sensing transistor may be any type of transistor, for example, a field effect transistor (FET), such as MOSFET, HEMT, or IGBT-based technologies using a range of materials (e.g., Si, GaN, or SiC). The main transistor may be any type of transistor, for example, a field effect transistor (FET), such as MOSFET, HEMT, or IGBT-based technologies using a range of materials (e.g., Si, GaN, or SiC).

[0033] In an embodiment, the ESD transistor, the sense transistor and the main transistor are of the same type, ie, all MOSFET or all GaN or the like.

[0034] The ESD transistor includes a gate, and the ESD transistor gate can be configured such that when an electrostatic discharge of a first polarity is applied, the ESD transistor is turned "on" to allow current to flow. Thus, the ESD of the first polarity causes the discharge to dissipate in a first direction in a first low inductance loop including the ESD transistor, while the ESD of a second polarity opposite to the first polarity causes the discharge to dissipate in a second direction in a second low inductance loop including the body diode of the ESD transistor.

[0035] In an embodiment, the main transistor has a first terminal and a second terminal, and the sensing transistor has a first terminal and a second terminal, the first terminal is one of the source and the drain, and the second terminal is the other of the source and the drain, the main transistor and the sensing transistor have their first terminals connected to a common first terminal, and the second terminals are connected to a connection path including a resistor. The provision of the resistor helps dissipate ESD. However, since the second terminals of the main transistor and the sensing transistor are connected, it also allows both the sensing transistor and the main transistor to be tested by connecting to the same second terminal. This reduces the possibility of damaging the sensing transistor during testing via a separate connection to the sensing source terminal.

[0036] In the above-described embodiments, the gate of the ESD transistor is connected to the terminal of the main transistor. In the configuration described herein, it is connected to the source terminal. To achieve this, in an embodiment, the gate of the ESD transistor is connected to a connection path including a resistor. Therefore, when the potential applied to the second terminal of the main transistor is equal to the potential applied to the second terminal of the sensing transistor, no signal is applied to the gate of the ESD transistor, and the ESD transistor is turned off, and current is not allowed to flow through the channel of the ESD transistor. However, when an ESD of a first polarity is applied to the second terminal of the sensing transistor, the gate of the ESD transistor is turned on, thereby allowing current to flow through the channel of the ESD.

[0037] In another embodiment, the gate of the ESD transistor is directly connected to a terminal of the main transistor. This allows the gate of the transistor to turn on when ESD of the first polarity appears at the second terminal of the sense transistor.

[0038] In an embodiment, the main transistor includes a plurality of constituent transistors (or cells) arranged in parallel, and the sensing transistor includes at least one constituent transistor, the number of constituent transistors in the main transistor being greater than the number of constituent transistors in the sensing transistor. The ESD transistor may also include a plurality of constituent transistors, the number of constituent FETs in the ESD transistor being greater than the number of constituent transistors in the sensing transistor. For example, the main transistor has 100,000 constituent transistors, while the sensing transistor has only one constituent transistor. In an embodiment, the ESD transistor will have 10 to 1000 constituent transistors, for example 100 constituent transistors.

[0039] The constituent transistors of the ESD transistor may be of the same type as the constituent transistors in the sensing transistor. This has particular advantages, since the same layer structure may be used for the sensing transistor and the ESD transistor, and allows the use of existing manufacturing frameworks to implement ESD protection, while avoiding the need for additional processing masks during the photolithography process of the semiconductor device. Furthermore, in order to achieve better layout matching, the implementation of the sensing transistor inevitably introduces some dummy transistors, which may be redesigned as ESD transistors.

[0040] Furthermore, the above resistor in the connection path “ESD resistor” can also be implemented in a dummy area. Therefore, the chip area occupied by the ESD resistor and the transistor can be ignored.

[0041] In yet another embodiment, the ESD protection component includes a plurality of ESD transistors connected in parallel with each other.

[0042] The ESD resistor can also be used independently of the ESD transistor. Therefore, in a second aspect, a semiconductor device is provided, comprising:

[0043] a power switching component including a main transistor configured to control the flow of current through a load path; and

[0044] a current sensing component including a sense transistor configured to sense current flowing through the load path,

[0045] Wherein the main transistor has a first terminal and a second terminal, and the sensing transistor has a first terminal and a second terminal, the first terminal of the main transistor and the sensing transistor is one of a source and a drain, and the second terminal of the main transistor and the sensing transistor is the other of a source and a drain, the main transistor and the sensing transistor have their first terminals connected to a common first terminal, and the second terminals connected to a connection path including a resistor.

[0046] The resistor may have a resistance between 1 kΩ and 1 MΩ, and in yet other embodiments, may have a resistance between 50 kΩ and 500 kΩ.

[0047] The above-mentioned resistor can also be used in combination with the above-mentioned ESD protection component, which is arranged in parallel with the current sensing component, wherein the ESD protection component includes an ESD transistor, the ESD transistor having a gate connected to the discharge path, so that the presence of a discharge of the first polarity turns on the ESD transistor to form another path for dissipating the discharge.

[0048] Exemplary dimensions of an ESD transistor (e.g., 0.008 mm 2 ) is 100 times larger than the sense transistor and 100 times larger than the main transistor (e.g., 8 mm 2 ) is 1000 times smaller. In some examples, the layout size of the ESD transistor is only 0.1% of the total die size. ESD transistors are more efficient than ESD resistors in dissipating ESD energy. This is achieved at least in part because ESD transistors have an inherent reverse diode or reverse conduction capability.

[0049] The present invention thus provides the described advantages within an existing manufacturing framework and avoids the need for additional process steps, since the ESD protection component can be manufactured using the same transistors as the sensing transistor and the main transistor.

[0050] The embodiments described herein are applicable to applications including SPS, DrMOS, DrGaN, hot-swap MOSFET, bidirectional switch, smart MOS, etc. The semiconductor device with the sense FET concept can also be based on MOSFET, GaN, SiC or IGBT technology.

[0051] The embodiments described herein may be provided on the same semiconductor die as a monolithic integrated circuit.

[0052] The figures and descriptions provided below disclose various semiconductor devices. The components and terminals of the disclosed devices described herein are connected to each other via conductive traces. The conductive traces are capable of carrying current between the components and the terminals.

[0053] Figure 1is a very high level illustration of an electrostatic discharge (ESD) protection component 102 according to an embodiment.

[0054] The ESD protection component 102 is provided as a part of the semiconductor device 100. Figure 1 In the embodiment, the semiconductor device 100 comprises a power switch, which in this embodiment is a power transistor 103. The power transistor 103 is configured to switch in a load path 111. The load path 111 is used to pass current between a main source terminal 104 and a main drain terminal 105.

[0055] The current sensing component 101 is disposed in the sensing path between the main drain 106 and the sensing source 105. The current sensing component 101 allows the current flowing through the load path 111 to be measured, because if the sensing source V LSS With power switch source V LS The same voltage level (V LSS ≈V LS ), the current flowing through the sensing path (replica current) will be proportional to the current flowing through the load path 111.

[0056] The above is an example of a current mirror mechanism.

[0057] The measurement of the current flowing through the sense path via the sense source terminal may sometimes cause electrostatic discharge at the sense source terminal.The current sensing component 101 is smaller than a power transistor and is therefore easily damaged by electrostatic discharge.

[0058] The electrostatic discharge (ESD) protection component 102 is arranged in parallel with the current sensing component. The ESD protection component provides two paths for the dissipation of discharge, the first path is caused by the current flowing through the ESD protection component in a first direction, and the second path is caused by the current flowing through the ESD protection component in a second direction opposite to the first direction. The electrostatic discharge can be positive or negative. The function of the ESD protection component will refer to Figure 3A Give a description.

[0059] Figure 2 Show Figure 1 A variation of the arrangement of where a path is formed between the sense source terminal and the main source terminal. This is illustrated by resistor 206.

[0060] Resistor 206 has two functions:

[0061] (i) it helps dissipate the ESD current appearing at the sense source terminal; and

[0062] (ii) It allows the current sensing component 101 to be tested by connecting to the main source and main drain only, ie without using the sense source terminal. This reduces the possibility of damaging the current sensing component during testing via connection to the sense source terminal.

[0063] The semiconductor device 100 includes an ESD resistor 206. The ESD resistor 206 is connected in series across the main source 104 and the sensing source 105. The ESD resistor 206 may represent one resistor, or may represent a plurality of resistors connected in combination to achieve a desired resistance value. The plurality of resistors may be connected in series and / or in parallel with each other.

[0064] The ESD resistor 206 is designed or configured to have a specific resistance value. In some examples, the resistance value of the resistor 206 is between 1 kΩ and 1 MΩ, inclusive.

[0065] Figure 3A FIG. 4 is a schematic diagram of a semiconductor device 400 according to an embodiment. The device 400 has a Figure 2 However, the device 100 is shown to be similar in structure to the device 100 described above. Figure 1 and 2 An example of an arrangement of a power switching component 103, a current sensing component 101 and an ESD protection component 102.

[0066] In this embodiment, the power switch component is a power transistor 403. The power transistor 403 is a FET, which is sometimes referred to as a main FET. The main FET 403 includes a gate 411, which is used to switch the channel of the main FET 403 between an "on" state and an "off" state. In the "on" state, current flows from the main source terminal 404 to the main drain terminal 407. The gate 411 of the main FET 403 is connected to the gate terminal 408, and the control of the main FET gate 411 is achieved through the gate terminal. The main FET 403 also has a source and a drain, and the channel of the FET is arranged between the source and the drain of the FET. The source of the main FET 403 is electrically connected to the main source 404, and the drain of the FET is electrically connected to the drain 407.

[0067] A body diode 413 is arranged in parallel with the main FET. The body diode allows current to flow from the main source 404 to the drain 407 in a first direction and blocks current from flowing in the opposite direction. Figure 3A, the main FET is shown as a single FET. However, in practice, there may be multiple FETs connected together in parallel, which form the main FET. A diode is connected in parallel with each FET. The multiple FETs forming the main FET 403 will be referred to as "constituent" FETs or cells. The diode can be a body diode inherent to each FET (as in the case of a MOSFET), or provided separately.

[0068] The main diode may be an intrinsic diode of the main FET (such as provided in MOSFET technology), or may be provided in addition to the main FET, such as a GaN FET which typically does not have an intrinsic diode, and the diode would therefore be provided in parallel with the main FET. In an embodiment, multiple main FETs may be provided in parallel with each other, and the diodes provided in parallel with the multiple main FETs. In other words, the number of main diodes does not have to match the number of main FETs. For example, multiple GaN FETs may be provided in parallel with a single silicon-based diode.

[0069] exist Figure 3A In the embodiment of the present invention, the current sensing component is also a FET 401, which will be referred to as sense FET 401. The sense FET 401 is arranged in the current sensing path 415. The sense FET 401 has a gate 417, which is used to switch the channel of the sense FET 401 between an "on" state and an "off" state. In the "on" state, current flows from the sense source terminal 405 to the main drain terminal 407. The gate 417 of the sense FET 401 is connected to the gate terminal 408, through which the control of the sense FET gate 417 is achieved. In this embodiment, the gate 417 of the sense FET 401 and the gate 411 of the main FET 403 are both tied to the same gate terminal 408.

[0070] The sense FET may be of the same technology type as the main FET 403, which has the advantage that the same processing steps may be used for both the sense FET and the main FET, thus providing processing efficiencies. The sense FET and the main FET may be integrated in a monolithic manner. Both the sense FET and the main FET may be based on a range of different technologies, such as MOSFET, GaN, SiC, and IGBT. However, in other embodiments, the sense FET 401 may be based on a different semiconductor technology than the main FET (e.g., MOSFET, GaN, SiC, and IGBT).

[0071] The sense FET 401 also has a source and a drain, with the channel of the sense FET being disposed between the source and drain of the FET. The source of the sense FET 401 is electrically connected to the sense source 405, and the drain of the sense FET is electrically connected to the drain 407. A sense FET diode 419 is also disposed in parallel with the sense FET 401. The sense FET diode 419 is configured to allow current to flow from the sense source 405 to the drain 407 in a first direction.

[0072] The configuration of the sense FET 401 and the main FET 403 forms a current mirror arrangement in which the current flowing through the sense path 415 is a fraction of the current flowing through the load path. The ratio of the current between the sense path and the load path is set by the relative sizes of the main FET 401 and the sense FET 401. If the main FET 403 and the sense FET 401 include constituent transistors, the ratio of the number of constituent transistors in the main FET 403 and the sense FET 401 provides the current ratio.

[0073] The ESD protection component is also implemented by a FET, which is an ESD FET 402. The ESD FET is arranged in parallel with the sensing FET 401. The ESD FET 402 is arranged in a discharge path 423. The ESD FET 402 includes a gate 421, which is used to switch the channel of the ESD FET 402 between an "on" state and an "off" state. In the "on" state, current flows through the channel of the ESD FET. The gate 421 of the ESD FET 402 is connected to the main FET source 404, so that the main FET source 404 acts as a control signal for the ESD FET 402. The ESD FET 402 also has a source and a drain, and the channel of the ESD FET is arranged between the source and the drain of the ESD FET. The source of the ESD FET 402 is electrically connected to the sensing source 405, and the drain of the ESD FET is electrically connected to the drain 407.

[0074] The ESD FET 402 can be of the same technology type as the main FET 403 and the sense FET 401, which has the advantage that the ESD FET, the sense FET, and the main FET can all use the same processing steps, thereby providing processing efficiencies. The ESD FET, the sense FET, and the main FET can be integrated in a monolithic manner. The ESD FET, the sense FET, and the main FET can all be based on a range of different technologies, such as MOSFET, GaN, SiC, and IGBT. However, in other embodiments, the ESD FET can be based on a different semiconductor technology (e.g., MOSFET, GaN, SiC, and IGBT) than the main FET and the sense FET 401.

[0075] A diode 425 is provided in parallel with the ESD FET 402. The ESD FET diode 425 allows current to flow from the sensing source 405 to the drain 407 in a first direction, and blocks current from flowing in the opposite direction. In FIG. 3 , the ESD FET 402 is shown as a single FET. However, in practice, there may be multiple FETs connected together in parallel that form the ESD FET. The multiple FETs that form the main FET 403 will be referred to as “constituent” FETs or cells. A diode is provided in parallel with each constituent FET.

[0076] The ESD diode may be an intrinsic diode of the ESD FET (such as provided in MOSFET technology), or may be provided in addition to the ESD FET, such as a GaN FET which typically does not have an intrinsic diode, and thus the diode will be provided in parallel with the ESD FET. In an embodiment, multiple ESD FETs may be provided in parallel with each other, and the diode is provided in parallel with the multiple ESD FETs. In other words, the number of ESD diodes does not have to match the number of ESD FETs. For example, multiple GaN FETs may be provided in parallel with a single silicon-based diode.

[0077] In normal operation, the ESD FET is operated in the off state and has no effect on the current sensing accuracy during steady state because the sense source voltage is equal to the voltage of the main source (V GS_ESD =0V, where V GS_ESD is the gate voltage on the ESD FET gate 421).

[0078] The sense FET 401 performs a current sensing function based on the operating principle of a current mirror mechanism. As described above, when the sense source voltage is equal to the main source voltage, an accurate replica current is obtained. Therefore, during normal operation, there is no potential difference (V GS_ESD =0V). Therefore, the ESD FET 402 operates in the off state and has no effect on the current sensing accuracy during the steady state. When the ESD FET 402 is in the off state, the ESD FET 402 does not conduct current.

[0079] The constituent FETs of the sensing FET, the main FET, and the ESD FET may be of the same type. However, the number of constituent FETs in the sensing FET and the main FET is different. For example, the sensing FET may include one or more FETs connected in parallel, and the ESD FET may include a larger number of parallel FETs than the number of FETs in the sensing FET. For example, the ESD FET may include at least 2 times, 5 times, or 10 times the number of FETs in the sensing FET. The main FET may include a larger number of parallel FETs than the number of FETs in the ESD FET. For example, the main FET may include at least 2 times, 5 times, or 10 times the number of FETs in the ESD FET. In an embodiment, the main FET has 100,000 constituent FETs, while the sensing FET has a small number of constituent FETs, such as 1, 2 to 10. In an embodiment, the ESD FET will have 10 to 1000 constituent FETs, such as 100 constituent FETs.

[0080] Using the same type of constituent FETs for the sense FET, ESD FET, and main FET simplifies the fabrication of the device because the sense FET, ESD FET, and main FET require the same layer structure.

[0081] The semiconductor device 400 also includes an ESD resistor 406, which is an example of the resistor 206. The ESD resistor 406 is connected in series across the main source 404 and the sensing source 405, as shown in FIG3. The ESD resistor 406 can represent one resistor, or can represent a plurality of resistors connected in combination to achieve a desired resistance value. The plurality of resistors can be connected in series and / or in parallel with each other.

[0082] Figure 3B yes Figure 3A Variations of the device. Figure 3A The device is suitable for use with a FET having an intrinsic body diode, such as a FETMOSFET. Figure 3A The transistors in the circle can be replaced by other types of transistors. Figure 3BA variation is shown in which a transistor without an additional diode is used, which device is suitable for using a transistor without an intrinsic body diode, such as a GaN FET. To avoid any unnecessary repetition, the same reference numerals will be used to represent the same features. The ESD protection component is provided by GaN FET 512. The GaN FET has a channel, and conduction through the channel is controlled via gate 521. There is no body diode in GaN 512. The sensing transistor is provided by GaN FET 511. GaN FET 511 has a channel, and conduction through the channel is controlled via gate 517. There is no body diode in GaN 511. The main transistor is provided by GaN FET 513. The GaN FET has a channel, and conduction through the channel is controlled via gate 531. There is no body diode in GaN 513.

[0083] Now refer to FIG. 4A to FIG. 4B The operation of the ESD protection is described. The same reference numerals as described with reference to FIG. 3 will be used. Figure 4A 4 is a circuit diagram of a semiconductor device 400 showing the current flow and operation of an ESDFET 402 and an ESD resistor 406 when a negative ESD is present at a sense source 405. In this case, relative to the main source 404 (V LS ) to generate a negative sense source 405 voltage (-V LSS ). Therefore, the normal current flows from the main source 404. The path of the current flow is Figure 4A The circuit components that form the main part of the discharge path are shown in black, and the other components are shown in gray. The thick dashed arrows indicate the direction of charge flow.

[0084] When reaching junction 400-a, the current is shunted and some of the current is dissipated by ESD resistor 406. In addition, ESDFET 402 is GS_ESD >V TH The ESD FET 402 is configured / designed to have a low R DSON (e.g. 1Ω). The body diode of the main FET 403 is configured in a forward biased position, thus allowing current to flow easily through the diode. The main FET 403 is off, so little or no current will flow through the channel of the main FET 403. In an embodiment, the diode and channel of the FET are integrated in a monolithic manner.

[0085] The current shunted and diverted from the main current path at junctions 400-a and 400-b avoids the sense FET 401 and is dissipated. The remaining current through the body diode of the main FET 403 then reaches the junction 400-c. Here, the current will flow primarily along the path of least impedance, that is, through the "on" ESD FET 402. In an embodiment, the resistance of the ESD FET 402 can be 100 times smaller than the resistance of the sense FET 401.

[0086] Therefore, a low impedance path consisting of the main FET 403 body diode and the ESDFET 402 is generated in response to a negative ESD occurring at the sense source 405. An alternative path consisting of the resistor 406, the ESD FET 402, and the body diode of the main FET 403 is thereby generated through which the ESD current can flow. The ESD energy can be quickly dissipated on this low impedance path, thus protecting the sense FET 401.

[0087] Therefore, the ESD FET 402 can protect the sense FET 401 from damage caused by negative ESD.

[0088] Figure 4B 4 is a circuit diagram of a semiconductor device 400 showing the current flow and operation of an ESD FET 402 and an ESD resistor 406 when a positive ESD occurs at a sensing source 405. In this case, relative to the main source 404 (V LS ) to generate a positive sense source 405 voltage (+V LSS ). Therefore, the normal current starts to flow from the sensing source 405. The path of the current flow is Figure 4B The arrow in shows.

[0089] Upon reaching junction 400 - e , current flows through both the diode 419 of the sense FET in the sense path and the diode 425 of the ESD FET in the discharge path.

[0090] The body diode of ESD FET 402 and the diode energy of sense FET 401 are transferred to the main FET, and the large main FET output capacitance COSS Energy will be absorbed. Therefore, ESD FET 402 is able to protect sense FET 401 from damage caused by positive ESD. In addition, as a result of ESD FET 402 being connected in parallel with sense FET 401, the current flowing through the sense FET 401 branch will be shunted, thus reducing the energy passing through the sense FET 401 body diode.

[0091] Therefore, if Figure 4A and Figure 4B As shown in , ESD protection allows both negative and positive ESD to be dissipated at the sense source. Figure 4B In the configuration shown in , for positive ESD, the dissipation path is through the diode of the discharge path in a first direction. For negative ESD, the current flows through the discharge path in the opposite direction. It achieves this by configuring the device so that negative ESD allows a signal to be applied to the gate of the ESD FET to allow the ESD FET to turn on.

[0092] In some embodiments, the main FET 403 does not have a body diode, but relies on an internal parasitic capacitor (C OSS , C GS and / or C GD ) to absorb ESD energy, such as Figure 4A and Figure 4B In this implementation, the capacitor can be large enough to absorb the ESD energy.

[0093] Resistor 406 provides further protection for sense FET 401 from ESD present at sense source 405 by assisting in dissipation. However, resistor 406 provides additional ESD protection benefits. Specifically, ESD resistor 406 protects sense source 405 from ESD introduced by charging device testing and reduces device wafer level testing time. In more detail, due to Figure 1 In the embodiment of the present invention, the main source 104 and the sense source 105 are separated (i.e., not connected), so the power transistor 103 and the current sensing component 101 need to be tested independently. However, by adding resistor 406, the main FET 403 and the sense FET 401 can be tested simultaneously, including terms such as BVOX, BVDSS, and leakage currents IDSS and IGSS. This is because the voltage drop across the resistor 406 (e.g., 50mV) caused by the small sense FET 401 gate leakage current (e.g., 1uA) is negligible compared to the large BVOX voltage (e.g., 27V). Therefore, the test time is significantly reduced.

[0094] An exemplary size of the ESD FET 402 is 100 times larger than the sense FET 401 and 1000 times smaller than the main FET 403. For example, if the size of the ESD FET 402 is 0.008 mm 2 , the size of the main FET 403 is 8mm 2 .

[0095] Since both devices can be tested simultaneously, a test device such as a wafer probe does not need to contact or touch the sense source 405 pin. This eliminates the risk of ESD being introduced into the pin. Therefore, the sense source 405 is further protected from ESD damage. The sense FET is small, and therefore it has a tiny leakage current that is difficult to measure accurately. The provision of resistors 206, 406 means that the challenge of measuring the <1nA leakage current of a small sense FET is avoided. In addition, since the initial voltage of the sense source 405 is equal to the voltage of the main source 404, this helps to minimize the stabilization time of the current sensor circuit on the gate driver IC during startup.

[0096] Furthermore, as with the ESD FET 402, the introduction of the ESD resistor 406 does not affect the current sensing accuracy of the sense FET 401 configuration during normal operation. During steady state, the same drain voltage, gate voltage, and source voltage are achieved for the sense FET 401 and the main FET 403. Therefore, there is almost no voltage drop across the resistor 406. Therefore, there is almost no current through the resistor 406 in steady state.

[0097] Figure 4A and Figure 4B The discharge path is described when the ESD FET has a body diode 425. Figure 3B GaN implementation, in an embodiment, relies on the reverse conduction capability of GaN to transfer charge Figure 4B dissipates in the directions shown in .

[0098] Figure 5 4 is a circuit diagram of a semiconductor device 400, showing an exemplary configuration of multiple ESD transistors and resistors according to an embodiment. To avoid any unnecessary repetition, the same reference numerals will be used to represent the same features. Here, the ESD protection component 102 includes two ESD FETs 402-a and 402-b with diodes.

[0099] The ESD protection component includes a first ESD FET 402-a connected in parallel across the sense FET 401 in a first discharge path 431 and a second ESD FET 402-b connected in parallel across the sense FET 401 in a second discharge path 433. Both the first ESD FET 402-a and the second ESD FET 402-b are provided with body diodes in parallel with the ESD FETs.

[0100] In addition, a first resistor 406-a, a second resistor 406-b, and a third resistor 406-c are provided and are connected in series between the sensing source 405 and the main source 404. The gate of the first ESD FET 402-a is connected to a point between the first resistor 406-a and the second resistor 406-b. The gate of the second ESD FET 402-b is connected to a point between the second resistor 406-b and the third resistor 406-c. The operation of the first ESDFET and the second ESD FET is the same as described above with respect to FIG. 4A to FIG. 4B The operation of the individual ESD FETs described is identical in that their gates respond to ESD provided at the sense source terminal 405 .

[0101] Although Figure 5 A specific combination of ESD FETs and resistors is shown, but those skilled in the art understand that other combinations are possible. In other embodiments, multiple ESD FETs and ESD resistors are provided in semiconductor device 400 in various combinations. Figure 5 The purpose of FIG. 4 is to provide an exemplary framework for how these multiple ESD devices may be interconnected while effectively providing the same ESD protection as the semiconductor device 400 of FIG. 3 .

[0102] Figure 6 is a graph showing ESD distribution. To verify the performance of the proposed ESD FET and resistor, a charge device model (CDM) and a human body model (HBM) were used to perform Figure 6 Simulation of ESD testing.

[0103] Fig. 7A is shown relative to the main source (V LS ) with a negative sense supply voltage (-V LSS ) is a circuit diagram of a simulation test bench. The semiconductor device and Figure 4A The semiconductor device shown in FIG. 5 is the same as that shown in FIG. 5 , and the same reference numbers are used to denote the same features. Model 501 is used to simulate negative ESD. The current flow during ESD is similar to that of reference Figure 4A The current flow described is the same.

[0104] Figure 7B is shown with respect to the main source (V LS ) of the positive sense supply voltage (+V LSS ) is a circuit diagram of a simulation test bench. The semiconductor device and Figure 4B The semiconductor device shown in FIG. 5 is the same as that shown in FIG. 5 , and the same reference numbers are used to denote the same features. Model 503 is used to simulate positive ESD. The current flow during ESD is similar to that of reference Figure 4A The current flow described is the same.

[0105] Both CDM simulations and HBM simulations were performed and tabulated in Table 1. The table shows that without ESD protection, the sense FET encounters CDM and HBM issues of ≥ 200 V. However, when an ESD FET and resistor are provided, these issues are alleviated.

[0106] Table I MOSFET simulation with gate driver off

[0107]

[0108]

[0109] In more detail, Table 1 shows experimental results of voltage readings obtained during testing of a sense FET with and without an ESD protection component, as shown in reference Figures 1 to 4B described.

[0110] As shown in Table 1, in the absence of the ESD FET, a large drain voltage V is measured for the sense FET. DS and gate voltage V GS , as shown in columns 1 and 2 of Table 1.

[0111] Columns 3 and 4 of Table 1 show the measured drain voltage V of the ESD FET to the sense FET. DS and gate voltage V GS In the case of negative ESD, the charge flows through an alternative path with lower impedance, causing the sense FET drain voltage V DS and gate voltage V GS Similarly, in the case of positive ESD, the current is split between the body diode of the sense FET and the body diode of the ESD FET, causing the sense FET drain voltage V DS and gate voltage V GS However, it is still possible to measure a negligible or minute voltage across the sense FET, such as less than 20V.

[0112] Figure 8 is a circuit diagram showing a simulation test bench with a gate driver connected.

[0113] The above semiconductor device can be used together with a gate driver IC that provides an ESD protection block for each I / O pin. Figure 8 In order to verify Figures 1 to 4B The ESD performance of a semiconductor device having a gate driver IC, such as Figure 8As shown in , simulations were performed and the results are summarized in Table II, which shows the sense FET characteristics for 1 kV CDM and 2 kV HBM.

[0114] Table II. MOSFET simulation with gate driver connected

[0115]

[0116] In fact, in order to achieve better layout matching, the implementation of the sense FET inevitably introduces some dummy transistors, which can be redesigned as ESD transistors. Similarly, the ESD resistor can also be implemented in the dummy area. Therefore, the chip area occupied by the ESD resistor and transistor can be ignored.

[0117] The above description focuses on using the discharge FET to dissipate ESD. However, when used alone, using Figure 2 The resistors shown as 206, 406 in Figure 3 also provide advantages.

[0118] Fig. 9 6 is a schematic diagram showing an ESD resistor 606 according to an embodiment without a discharge FET. The semiconductor device 600 is similar to Figure 2 Therefore, the ESD resistor 606 is an example of the ESD resistor 206. However, the semiconductor device 600 is different from the semiconductor device 200 in that the semiconductor device 600 does not have the ESD protection component 202. Therefore, in the present embodiment, the resistor 606 is mainly responsible for the ESD protection of the sensing source 605.

[0119] The ESD resistor 606 is connected in series across the main source 604 and the sensing source 605, as shown in FIG10. The ESD resistor 606 may represent one resistor, or may represent a plurality of resistors connected in combination to achieve a desired resistance value. The plurality of resistors may be connected in series and / or in parallel with each other.

[0120] The resistor 606 protects the current sensing component 601 from ESD damage by providing an alternate path for current flow, such that negligible or no current caused by ESD flows through the current sensing component 601 .

[0121] In the event of a negative ESD at the sensing source 605, the resistor 606 can provide an alternative path for the conventional current flowing from the main source 604 to the sensing source 605. The current is shunted between the resistor 606 and the power transistor 603. Subsequently, due to the high resistance value of the resistor 606, the resistor is able to dissipate the energy generated by the current passing through it. Subsequently, due to the high resistance of the resistor 606, a small portion of the current passes through the resistor, and therefore the power consumption on the resistor is low. The remaining large current (i.e., the shunted current that does not flow through the resistor 606) passes through the low on-resistance power transistor 603. The main energy is transferred to the outside.

[0122] In the event of positive or negative ESD at the sense source 605, the resistor 606 can provide an alternative path for the normal current flowing from the sense source 605 to the main source 604. After the current is shunted at the junction 600-a, the remaining current passes through the resistor 606. The resistor can dissipate the energy generated by the current passing through it.

[0123] The resistor 606 may be configured to have a resistance value between 50 kΩ and 500 kΩ to ensure that negligible energy is transferred to the current sensing component 601 in both positive and negative ESD situations.

[0124] In addition to providing a dissipation path for ESD, resistor 606 also provides additional ESD protection benefits. Specifically, ESD resistor 606 protects sense source 605 from ESD introduced by live device testing and reduces device wafer level testing time. In more detail, since main source 104 and sense source 105 are connected at Figure 1 6. The power transistor 103 and the current sensing component 101 are separated (ie, not connected) in FIG. 6, and therefore the power transistor 103 and the current sensing component 101 need to be tested independently. However, by adding the resistor 606, the power transistor 603 and the current sensing component 601 can be tested simultaneously.

[0125] Since both devices can be tested simultaneously, a test device such as a wafer prober does not need to contact or touch the sense source 605 pin. This eliminates the risk of ESD being generated by contact with the sense source terminal 605. The lead pin is introduced. Thus, the current sensing component is protected from ESD damage caused by contact with the sense source terminal 605.

[0126] Fig. 10A 7 is a circuit diagram of a semiconductor device 700 illustrating an ESD resistor 706 according to an embodiment. The semiconductor device 700 is an example of the semiconductor device 600 .

[0127] In this embodiment, the power switch component is a power transistor 703. The power transistor 703 is a transistor sometimes referred to as a main FET. The main FET 703 includes a gate 711, which is used to switch the channel of the main FET 703 between an "on" state and an "off" state. In the "on" state, current flows from the main source terminal 704 to the main drain terminal 707. The gate 711 of the main FET 703 is connected to the gate terminal 708, and the control of the main FET gate 711 is achieved through the gate terminal. The main FET 703 also has a source and a drain, and the channel of the FET is arranged between the source and the drain of the FET. The source of the main FET 703 is electrically connected to the main source 704, and the drain of the FET is electrically connected to the drain 707.

[0128] A body diode 713 is arranged in parallel with the main FET. The body diode allows current to flow from the main source 704 to the drain 707 in a first direction and blocks current from flowing in the opposite direction. Fig.11 , the main FET is shown as a single FET. However, in practice, there may be multiple FETs connected together in parallel, which form the main FET. A body diode is connected in parallel with each FET. The multiple FETs that form the main FET 703 will be referred to as "constituent" FETs.

[0129] exist Fig. 10A In the embodiment of the present invention, the current sensing component is also a transistor 701, which will be referred to as a sense FET 701 in this embodiment. The sense FET 701 can be based on different semiconductor devices (e.g., MOSFET, GaN, SiC, and IGBT). The sense FET 701 is arranged in the current sensing path 715. The sense FET 701 has a gate 717, which is used to switch the channel of the main FET 703 between an "on" state and an "off" state. In the "on" state, current flows from the sense source terminal 705 to the main drain terminal 707. The gate 717 of the sense FET 701 is connected to the gate terminal 708, through which the control of the sense FET gate 717 is achieved. In this embodiment, the gate 717 of the sense FET 701 and the gate 711 of the main FET 703 are both tied to the same gate terminal 708.

[0130] The sense FET 701 also has a source and a drain, with the channel of the sense FET being disposed between the source and drain of the FET. The source of the sense FET 701 is electrically connected to the sense source 705, and the drain of the sense FET is electrically connected to the drain 707. A sense FET diode 719 is also disposed in parallel with the sense FET 701. The sense FET diode 719 is configured to allow current to flow from the sense source 705 to the drain 707 in a first direction.

[0131] The configuration of the sense FET 701 and the main FET 703 forms a current mirror arrangement in which the current flowing through the sense path 715 is proportional to the current flowing through the load path. The current ratio between the sense path and the load path is set by the relative sizes of the main FET 701 and the sense FET 701. If the main FET 703 and the sense FET 701 include constituent transistors, the ratio of the number of constituent transistors in the main FET 703 and the sense FET 701 provides the current ratio.

[0132] The ESD resistor 706 is Figure 6 The resistor 606 is an example of a resistor 606 , and is provided between the sensing source 705 and the main source 704 .

[0133] In addition to reference Figure 6 In addition to the ESD protection provided by resistor 706 described above, resistor 706 also provides additional ESD protection benefits. Specifically, ESD resistor 706 protects sense source 705 from ESD introduced by live device testing and reduces device wafer level testing time. Return to Reference Figure 1 , the main source 104 and the sense source 105 are separate (i.e., not connected), so the power transistor 103 and the current sensing component 101 need to be tested independently. However, by adding resistor 706, the main FET 703 and the sense FET 701 can be tested simultaneously, including terms such as BVOX, BVDSS, and leakage currents IDSS and IGSS. This is because the voltage drop across the resistor 706 (e.g., 50mV) caused by the small sense FET 701 gate leakage current (e.g., 1uA) is negligible compared to the large BVOX voltage (e.g., 27V). Therefore, the test time is significantly reduced.

[0134] Since the same terminal (main source terminal 704) can be used to test the sense FET and the main FET, a test device such as a wafer probe does not need to contact or touch the sense source 705 pin, and only needs to connect to the main source terminal 704 once to test both the sense FET 701 and the main FET 703. This eliminates the risk of ESD generated by contact with the sense source terminal 705. Therefore, the sense FET 701 is further protected from ESD damage. In addition, the initial voltage of the sense source 705 is equal to the voltage of the main source 704, which is beneficial during startup. For example, if a reference is used Figure 8 With a gate driver IC of the type described, the stabilization time of the current sensor circuit can be minimized during startup.

[0135] Furthermore, the introduction of the ESD transistor 706 does not affect the current sensing accuracy of the sense FET 701 configuration during normal operation. During steady state, the sense FET 701 and the main FET 703 obtain the same drain, gate, and source voltages. Therefore, there is almost no voltage drop across the resistor 706. Therefore, there is almost no current through the resistor 706 in steady state.

[0136] Fig. 10B 7 shows the current flow in the semiconductor device 700 in response to a negative ESD occurring at the sensing source 705. In this case, relative to the main source 704 (V LS ) to generate a negative sense source 705 voltage (-V LSS ). Therefore, the normal current flows from the main source 704. The path of the current flow is Fig. 10B The arrows in the figure indicate the

[0137] Upon reaching junction 700-a, the current is shunted and a portion of the current is dissipated by ESD resistor 706. Thus, the current is shunted between resistor 706 and the body diode of main FET 703. In an embodiment, resistor 706 is configured to have at least a certain resistance value so as to ensure that negligible energy is transferred to sense FET 701 via the body diode of main FET 703. The body diode of main FET 703 is configured in a forward biased position, thus allowing current to flow easily through the diode. Thus, almost no current flows through main FET 703 itself.

[0138] The current shunted from the main current path at junction 700-a avoids the sense FET 701 and is dissipated. The remaining current through the body diode of the main FET 703 is also quickly dissipated before reaching the sense FET 701.

[0139] Therefore, an alternative path is created through which the ESD current can flow, consisting of resistor 706 and the body diode of the main FET 703. The ESD energy can be dissipated on this path, thus protecting the sense FET 701.

[0140] Therefore, the ESD resistor 706 can protect the sense FET 701 from damage caused by negative voltage ESD.

[0141] Fig.11 7 shows the current flow in the semiconductor device 700 in response to a positive ESD occurring at the sensing source 705. In this case, relative to the main source 704 (V LS ) to generate a positive sensing source 705 voltage (+V LSS ). Therefore, the normal current starts to flow from the sensing source 705. The path of the current flow is Fig. 10C The arrow in shows.

[0142] Upon reaching junction 700-e, the current is split between the sense FET 701 branch and the main current path. However, since the body diode of the sense FET 701 is in a forward biased configuration, the current will flow through the body diode of the sense FET 701. The remaining current flows through resistor 706.

[0143] Therefore, the ESD resistor 706 can protect the sense FET 701 from damage caused by positive ESD. In addition, due to the presence of the resistor 706, the current flowing through the sense FET 701 branch will be shunted, thus reducing the energy through the sense FET 701 body diode.

[0144] In some embodiments, the main FET 703 does not have a body diode, but relies on an internal parasitic capacitor (C OSS , C GS and / or C GD ) to absorb ESD energy. Figure 4B , in an example of sensing positive ESD at source 405. The capacitor may be sized large enough to absorb the ESD energy.

[0145] The sense FET / transistor may also not have a body diode. For example, the sense transistor may have a Figure 3B The GaN architecture described.

[0146] The sense transistor and the main transistor may be any type of transistor, for example a field effect transistor (FET) such as a MOSFET, HEMT or IGBT transistor using a range of materials such as Si, GaN or SiC. In an embodiment, the sense transistor is the same type of transistor as the main transistor.

[0147] FIG. 10A to FIG. 10C The circuit may also be provided with additional ESD protection components (e.g., diodes provided across the current sensing component) to provide Fig. 10C An additional discharge path is connected in parallel with the sense transistor in the direction shown in. The additional discharge path works with the resistor to dissipate the discharge.

[0148] Figure 3A , Figure 3B , FIG. 4A to FIG. 4B , Figure 5 , FIG. 7A to FIG. 7B and FIG. 10A to FIG. 10C The device can be considered as a discrete four-terminal device, the terminals being the main source terminal, the sense source terminal, the gate terminal, and the drain terminal. This four-terminal configuration can provide a backup power supply (SPS) configuration. Fig.11 Such an SPS with a sense FET configuration is depicted with a representative FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4B , Figure 5 , FIG. 7A to FIG. 7B and FIG. 10A to FIG. 10C A four-terminal device 800 of any semiconductor device.

[0149] The device 800 is arranged to be connected to a resonant circuit 803, which includes a load inductor 805 and a capacitor. The resonant circuit is connected across the main source terminal and the drain terminal to allow an output voltage V to be output from the circuit. out The input voltage is provided through a switch (transistor) 809 .

[0150] The circuit diagrams depicted and described in this application are provided by way of example only, and those skilled in the art will appreciate that alternative circuit configurations can be devised that achieve equivalent results.

[0151] Although described herein with respect to MOSFET transistor technology, the ESD protection devices and methods described herein may be implemented using equivalent concepts and solutions described with respect to MOSFETs.

[0152] Although the present disclosure has been described according to the preferred embodiments described above, it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. In view of what is disclosed, those skilled in the art will be able to make modifications and substitutions, which are considered to fall within the scope of the appended claims. Each feature disclosed or shown in this specification may be incorporated into the present disclosure, either alone or in any appropriate combination with any other features disclosed or shown herein.

[0153] Many other effective alternatives will occur to those skilled in the art.It will be understood that the present disclosure is not limited to the embodiments described, but encompasses all modifications that fall within the scope of the appended claims.

Claims

1. A semiconductor device comprising: a power switching component configured to control the flow of current through a load path; a current sensing component configured to sense the current flowing through the load path; as well as An electrostatic discharge (ESD) protection component configured to protect the current sensing component from electrostatic discharge, wherein the ESD protection component includes an ESD transistor having a gate connected to a discharge path such that the presence of a discharge of a first polarity turns on the ESD transistor to form a further path for dissipating the discharge. 2 . The semiconductor device according to claim 1 , wherein an ESD diode is provided in parallel with the ESD transistor, the ESD diode being configured to allow current from the discharge having the second polarity to flow.

3. A semiconductor device according to any preceding claim, wherein the power switching component comprises a main transistor and the current sensing component comprises a sense transistor.

4. A semiconductor device according to any preceding claim, wherein the main transistor has a first terminal and a second terminal, and the sensing transistor has a first terminal and a second terminal, the first terminal being one of a source and a drain, and the second terminal being the other of a source and a drain, the main transistor and the sensing transistor having their first terminals connected to a common first terminal, and the second terminals connected to a connection path including a resistor. 5 . The semiconductor device according to claim 4 , wherein the gate of the ESD transistor is connected to the connection path including the resistor. 6 . The semiconductor device according to claim 3 , wherein the gate of the ESD transistor is connected to a terminal of the main transistor. 7 . The semiconductor device according to claim 3 , wherein the sense transistor is configured as a current mirror of the main transistor.

8. A semiconductor device according to any one of claims 3 to 7, wherein the main transistor includes a plurality of constituent transistors arranged in parallel, and the sensing transistor includes at least one of the constituent transistors, the number of constituent transistors in the main transistor being greater than the number of constituent transistors in the sensing transistor. 9 . The semiconductor device according to claim 8 , wherein the ESD transistor includes a plurality of the constituent transistors, the number of constituent transistors in the discharge transistor being greater than the number of constituent transistors in the sense transistor. 10 . The semiconductor device according to claim 8 , wherein the constituent transistor of the ESD transistor is of the same type as the constituent transistor in the sense transistor.

11. The semiconductor device according to any preceding claim, wherein the ESD protection component comprises a plurality of ESD transistors connected in parallel with each other.

12. A semiconductor device according to any preceding claim, configured as a monolithic integrated circuit.

13. A semiconductor device comprising: a power switch component including a main transistor configured to control the flow of current through a load path; as well as a current sensing component including a sensing transistor configured to sense the current flowing through the load path, The main transistor has a first terminal and a second terminal, and the sensing transistor has a first terminal and a second terminal, the first terminal of the main transistor and the sensing transistor is one of a source and a drain, and the second terminal of the main transistor and the sensing transistor is the other of a source and a drain, the main transistor and the sensing transistor have their first terminals connected to a common first terminal, and the second terminals are connected to a connection path including a resistor. 14 . The semiconductor device according to claim 13 , wherein the resistor has a resistance between 1 kΩ and 1 MΩ.

15. The semiconductor device according to any one of claims 13 or 14, further comprising an ESD protection component arranged in parallel with the current sensing component, wherein the ESD protection component comprises an ESD transistor having a gate connected to a discharge path, so that the presence of a discharge of a first polarity turns on the EST transistor to form another path for dissipating the discharge.

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