Preparation method of photoelectric synapse device and photoelectric synapse device

Abstract

The invention discloses a preparation method of a photoelectric synapse device and the photoelectric synapse device, and belongs to the technical field of semiconductors. The preparation method of the photoelectric synapse device comprises the following steps: providing a grid electrode and a grid electrode oxide layer located at one side of the grid electrode; forming a channel layer on one side, deviating from the grid electrode, of the grid electrode oxide layer; forming a source and a drain on one side, deviating from the gate oxide layer, of the channel layer, wherein the source and the drain are connected with the channel layer; and in a high-temperature environment, carrying out lewis acid doping on the channel layer for a preset duration so as to introduce a trap center into an energy band structure of the channel layer. According to the invention, the simulation of the photoelectric synapse function can be realized, and the device has extremely low operation voltage, relatively weak light pulse intensity and extremely low power consumption during simulation.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a method for preparing a photoelectric synapse device and a photoelectric synapse device. Background Art

[0002] In the era of big data, traditional computers face great challenges in processing large and complex information quickly and efficiently, mainly due to the inherent separation between processors and memory. In contrast, the human brain uses a large number of synapses to connect neural networks, showing an excellent ability to process and store data simultaneously with minimal energy consumption. Therefore, artificial neural networks inspired by the brain have become one of the most promising information processing technologies, which is expected to overcome the performance bottleneck caused by the mismatch in data transmission speed between memory and processor. This has triggered a renewed interest in developing artificial synaptic devices to build neuromorphic systems. Early efforts focused on using silicon-based complementary metal oxide semiconductor (CMOS) analog circuits to simulate synaptic functions, such as using 5.4 billion transistors to simulate 1 million neurons and 256 million configurable synapses. With the development of artificial neural networks, it is found that imitating visual perception functions is a key step in realizing artificial intelligence. Optical synapses have been proposed as the basic unit of neuromorphic visual systems, which require the integration of light detection and synaptic functions to process light signals and extract relevant information such as color, intensity, and frequency.

[0003] Among transition metal dichalcogenides (TMDs), WSe2 has attracted much attention due to its easily tunable bandgap structure and excellent photoelectric response. However, WSe2-based optoelectronic synaptic devices suffer from high readout voltage and significant energy consumption during operation, which may hinder their further development in the field of neuromorphic computing architectures. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for preparing a photoelectric synapse device and a photoelectric synapse device, which can simulate the function of a photoelectric synapse, and has extremely low operating voltage, weak light pulse intensity and extremely low power consumption during simulation.

[0005] In a first aspect, the present application provides a method for preparing a photoelectric synapse device, comprising:

[0006] Providing a gate and a gate oxide layer located on one side of the gate;

[0007] forming a channel layer on a side of the gate oxide layer facing away from the gate;

[0008] Forming a source and a drain on a side of the channel layer away from the gate oxide layer, and the source and the drain are connected to the channel layer;

[0009] In a high temperature environment, the channel layer is doped with Lewis acid for a preset time to introduce trap centers into the energy band structure of the channel layer.

[0010] According to the preparation method of the photoelectric synapse device of the present application, the channel layer is doped with Lewis acid for a preset time under a high temperature environment to introduce trap centers in the band structure of the channel layer, capture photogenerated charges, and produce a continuous photoconductivity effect, thereby realizing the simulation of the photoelectric synapse function, and having an extremely low operating voltage, weak light pulse intensity and extremely low power consumption during the simulation.

[0011] According to an embodiment of the present application, forming a source and a drain on a side of the channel layer away from the gate oxide layer includes:

[0012] forming a capping layer on a side of the channel layer away from the gate oxide layer;

[0013] forming an opening in the cover layer to expose the channel layer;

[0014] forming a source and a drain electrode connected to the exposed channel layer in the opening;

[0015] The covering layer is removed.

[0016] According to an embodiment of the present application, the step of performing Lewis acid doping on the channel layer for a preset time under a high temperature environment includes:

[0017] Dissolving a liquid Lewis acid in an alcoholic polar protic solvent;

[0018] The solvent containing the Lewis acid is transferred into a polytetrafluoroethylene reactor and heated;

[0019] In a high temperature environment, the channel layer is immersed in the reaction kettle to perform Lewis acid doping on the channel layer for a preset time.

[0020] According to one embodiment of the present application, the high temperature is 70°C-160°C.

[0021] According to one embodiment of the present application, the preset duration is 10 minutes to 1 hour.

[0022] According to one embodiment of the present application, the doping concentration of the Lewis acid is 0.01 mol %-1 mol %.

[0023] According to one embodiment of the present application, the Lewis acid includes SnCl4.

[0024] According to one embodiment of the present application, the channel layer includes a two-dimensional material layer.

[0025] According to one embodiment of the present application, the two-dimensional material layer includes WSe2.

[0026] In a second aspect, the present application provides a photoelectric synapse device, which is prepared by the method for preparing the photoelectric synapse device described in the first aspect, and the photoelectric synapse device comprises:

[0027] Gate;

[0028] A gate oxide layer, located on one side of the gate;

[0029] A channel layer is located on a side of the gate oxide layer away from the gate; the channel layer is doped with Lewis acid to introduce trap centers in the energy band structure of the channel layer;

[0030] The source and drain are located on a side of the channel layer away from the gate oxide layer and connected to the channel layer.

[0031] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0032] By doping the channel layer with Lewis acid for a preset time under high temperature environment, trap centers are introduced in the band structure of the channel layer to capture photogenerated charges and produce a continuous photoconductivity effect, thereby simulating the functions of photoelectric synapses, such as excitatory postsynaptic current (EPSC), double pulse facilitation (PPF), long-term memory (STM), short-term memory (LTM), etc., and realizing optical and electrical dual-modal regulation of conductivity. During simulation, the system has extremely low operating voltage, weak light pulse intensity and extremely low power consumption. It has an extremely fast and sensitive response to electrical pulses, and can be applied to high-pass filtering for image preprocessing, as well as to simulate Boolean logic commands.

[0033] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0035] Figure 1 is a schematic flow chart of a method for preparing a photoelectric synapse device provided in an embodiment of the present application;

[0036] Figure 2 is a schematic diagram of the structure of the optoelectronic synapse device provided in an embodiment of the present application;

[0037] Figure 3 is an optical microscope image of the optoelectronic synapse device provided in an embodiment of the present application;

[0038] Figure 4 is a Raman spectrum diagram of the optoelectronic synapse device provided in an embodiment of the present application;

[0039] Figure 5 is a PL (photoluminescence) spectrum diagram of the optoelectronic synapse device provided in an embodiment of the present application;

[0040] Figure 6 is an AFM (atomic force microscope) image of the optoelectronic synapse device provided in an embodiment of the present application;

[0041] Figure 7 is a high-angle annular dark field-scanning transmission electron microscope (HAADF-STEM) image of the optoelectronic synapse device provided in an embodiment of the present application;

[0042] Figure 8 It is an It curve diagram of the channel layer in the optoelectronic synapse device provided in an embodiment of the present application before Lewis acid is doped at high temperature;

[0043] Fig. 9 This is a photoelectric synapse function simulation test diagram of the photoelectric synapse device provided in an embodiment of the present application;

[0044] Fig.10 It is an It curve diagram of the optoelectronic synapse device provided in the embodiment of the present application;

[0045] Fig.11 This is a high-pass filtering application diagram of the optoelectronic synapse device provided in an embodiment of the present application;

[0046] Fig.12 This is a Boolean logic command application diagram of the optoelectronic synapse device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0048] The following describes a method for preparing a photoelectric synapse device and a photoelectric synapse device provided in an embodiment of the present application with reference to the accompanying drawings.

[0049] Figure 1 A schematic flow chart of a method for preparing a photoelectric synapse device provided in an embodiment of the present application.

[0050] like Figure 1 As shown, the method for preparing the optoelectronic synapse device provided in the embodiment of the present application includes steps 110 to 140.

[0051] Step 110: Provide a gate and a gate oxide layer located on one side of the gate.

[0052] Combination Figure 2 As shown, a gate 1 is first provided. The gate 1 may be a semiconductor layer including silicon or a semiconductor layer including other elements. The gate 1 is a highly doped semiconductor layer, and the doping type of the gate 1 may be N-type or P-type. For example, a dopant with reducing ability is used to dope pentavalent elements such as phosphorus, antimony, arsenic, etc. into the gate 1 to form an N-type gate. Alternatively, a dopant with oxidizing ability is used to dope trivalent elements such as boron, indium, gallium, aluminum, etc. into the gate 1 to form a P-type gate.

[0053] Then, a gate oxide layer 2 is formed on one side of the gate 1 by a thin film deposition process. The thin film deposition process includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, etc. The gate oxide layer 2 may include one or more combinations of silicon oxide, silicon nitride, etc.

[0054] In some embodiments, the overall thickness of the gate 1 and the gate oxide layer 2 is 300 nm.

[0055] Step 120 : forming a channel layer on a side of the gate oxide layer away from the gate.

[0056] Combination Figure 2 As shown, a thin film deposition process is used to form a channel layer 3 on the side of the gate oxide layer 2 away from the gate 1. The channel layer 3 is a semiconductor layer. The channel layer 3 covers a portion of the gate oxide layer 2. In some embodiments, the Figure 3 As shown, the transverse cross section of the channel layer 3 is triangular, and the transverse direction refers to a direction parallel to the upper surface of the gate oxide layer 2 (ie, the surface of the gate oxide layer 2 facing away from the gate 1).

[0057] In some embodiments, the channel layer 3 includes a two-dimensional material layer. Two-dimensional material refers to a material in which electrons can move freely only in two dimensions at a non-nanoscale, that is, a two-dimensional atomic crystal material. The two-dimensional material has a nanometer-level thickness, so that the short channel effect of the device is effectively suppressed, the device size can be reduced, and the power consumption can be reduced.

[0058] In some embodiments, the two-dimensional material layer includes WSe 2. The two-dimensional material layer may also include other types of two-dimensional materials, such as MoS 2, WS 2, and MoSe 2, etc., which are not specifically limited here.

[0059] In some embodiments, the thickness of the channel layer 3 is relatively thin, for example, the thickness of the channel layer 3 is 5 nm.

[0060] For example, a thin channel layer 3 (such as WSe2) is grown on the side of the gate oxide layer 2 away from the gate 1 through a chemical vapor deposition process, wherein the precursor mass of the chemical vapor deposition is 0.3g sodium tungstate and 0.8g selenium powder, the temperature is 945°C, the flow rate is 65:7 (Ar:H2), and the holding time is 3min.

[0061] Step 130 : forming source and drain electrodes on a side of the channel layer away from the gate oxide layer, and the source and drain electrodes are connected to the channel layer.

[0062] Combination Figure 2 As shown, a source electrode 4 and a drain electrode 5 are formed on the side of the channel layer 3 away from the gate oxide layer 2, and the source electrode 4 and the drain electrode 5 are arranged laterally. The source electrode 4 is connected to the channel layer 3 and extends to the gate oxide layer 2, and the drain electrode 5 is connected to the channel layer 3 and extends to the gate oxide layer 2. Among them, the source electrode 4 can include one or more combinations of copper, titanium, aluminum, nickel, gold, etc. The drain electrode 5 can include one or more combinations of copper, titanium, aluminum, nickel, gold, etc.

[0063] In some embodiments, forming a source and a drain on a side of the channel layer away from the gate oxide layer in step 130 includes:

[0064] forming a capping layer on a side of the channel layer facing away from the gate oxide layer;

[0065] forming an opening in the cover layer to expose the channel layer;

[0066] forming source and drain electrodes connected to the exposed channel layer in the opening;

[0067] Remove the covering layer.

[0068] A coating layer is spin-coated on the side of the channel layer 3 away from the gate oxide layer 2 by using a coating machine, and the coating layer covers the channel layer 3 and the gate oxide layer 2. The coating layer is heated by a heating table to solidify the coating layer. The coating layer may include PMMA (Polymethyl Methacrylate). The coating parameters of the coating layer are: 600 rpm, 6 seconds; 4000 rpm, 60 seconds. The heating temperature of the heating table is 150° C., and the heating time is 5 minutes.

[0069] Then, an exposure pattern is designed in the area corresponding to the channel layer 3 using an electron beam exposure system. The exposure system controls the light source and the electron beam to realize pattern processing exposure in a specific area of ​​the cover layer with the assistance of a mask or a pattern template. After the development and fixing process, the exposure pattern is exposed to form an opening in a specific area of ​​the cover layer.

[0070] The opening of the cover layer includes a first sub-opening and a second sub-opening which are arranged laterally and spaced apart from each other. The first sub-opening exposes a portion of the channel layer 3 and a portion of the gate oxide layer 2 , and the second sub-opening exposes a portion of the channel layer 3 and a portion of the gate oxide layer 2 .

[0071] The source and drain electrodes are deposited in the openings by using a vacuum thermal evaporation system. The source electrode 4 is deposited in the first sub-opening, so that the source electrode 4 is connected to the channel layer 3 and extends to the gate oxide layer 2. The drain electrode 5 is deposited in the second sub-opening, so that the drain electrode 5 is connected to the channel layer 3 and extends to the gate oxide layer 2.

[0072] After forming the source and drain electrodes, the remaining capping layer is removed.

[0073] Step 140 : In a high temperature environment, the channel layer is doped with Lewis acid for a preset time to introduce trap centers into the energy band structure of the channel layer.

[0074] The band structure of the channel layer 3 can be adjusted by adjusting the doping temperature, doping duration and / or doping concentration of the Lewis acid. In this embodiment, the channel layer 3 is doped with Lewis acid for a preset duration under a high temperature environment to introduce trap centers in the band structure of the channel layer 3, capture photogenerated charges, generate a continuous photoconductivity effect, and simulate the photoelectric synapse function.

[0075] In some embodiments, the high temperature is 70° C.-160° C. For example, the high temperature is 160° C., that is, Lewis acid doping is performed on the channel layer 3 in an environment of 160° C.

[0076] In some embodiments, the preset time length is 10 minutes to 1 hour. For example, the preset time length is 1 hour, that is, the channel layer 3 is Lewis acid doped for 1 hour in a high temperature environment.

[0077] In some embodiments, the doping concentration of the Lewis acid is 0.01 mol % to 1 mol %.

[0078] In some embodiments, the Lewis acid includes SnCl4. Lewis acid refers to any molecule, ion or atom group that can accept an external electron pair. Lewis acid can also include other liquid electrophilic reagents, such as BF3, AlCl3 and SO3, etc., which are not specifically limited here.

[0079] In some embodiments, the step 140 of performing Lewis acid doping on the channel layer for a preset time under a high temperature environment includes:

[0080] Dissolving a liquid Lewis acid in an alcoholic polar protic solvent;

[0081] The solvent containing the Lewis acid is transferred into a polytetrafluoroethylene reactor and heated;

[0082] Under high temperature environment, the channel layer is immersed in a reaction kettle to perform Lewis acid doping on the channel layer for a preset time.

[0083] Liquid Lewis acid (such as SnCl4) is measured into an alcoholic polar protic solvent (such as ethanol), and a magnetic stirrer is added until the Lewis acid is completely dissolved in the alcoholic polar protic solvent. The volume of the Lewis acid (such as liquid SnCl4) can be 1.6 ml, and the volume of the alcoholic polar protic solvent (such as anhydrous ethanol) is 10 ml.

[0084] Then, an alcohol polar proton solution (such as ethanol) dissolved with a Lewis acid (such as SnCl4) is transferred to a polytetrafluoroethylene reactor and placed on a heating table for heating. The substrate is placed in a polytetrafluoroethylene reactor, and the channel layer 3 (such as a thin layer of WSe2) is immersed in the polytetrafluoroethylene reactor to perform Lewis acid doping on the channel layer 3 under a high temperature environment. Among them, the temperature required for heating (i.e., high temperature) can be 160°C, and the duration of immersion in the polytetrafluoroethylene reactor (i.e., preset duration) can be 1h. The substrate refers to the structure after the source and drain are formed, that is, the substrate includes a gate 1, a gate oxide layer 2 located on one side of the gate 1, a channel layer 3 located on the side of the gate oxide layer 2 away from the gate 1, and a source and drain located on the side of the channel layer 3 away from the gate oxide layer 2 and connected to the channel layer 3.

[0085] Then, the substrate is rinsed with an alcoholic polar protic solution (such as anhydrous ethanol) and the surface is blown dry with high-purity nitrogen gas.

[0086] The performance of the channel layer 3 changes after being doped with Lewis acid in a high temperature environment. Figure 4 As shown in the figure, compared with the channel layer before doping (such as WSe2), the WSe2 characteristic peak position of the channel layer after high temperature Lewis acid doping (such as Sn-WSe2) is slightly blue-shifted, which affects the electrical properties of the channel layer. Figure 5 As shown, compared with the channel layer before doping (such as WSe2), the WSe2 characteristic peak position of the channel layer after high-temperature Lewis acid doping (such as Sn-WSe2) is slightly red-shifted, which affects the band structure of the channel layer.

[0087] The thickness of the channel layer 3 remains unchanged after being doped with Lewis acid in a high temperature environment. For example, the thickness of the channel layer before doping is 5 nm. AFM (atomic force microscope) measurement is performed on the channel layer after high temperature Lewis acid doping. The AFM image of the channel layer (such as Sn-WSe2) after high temperature Lewis acid doping is as follows: Figure 6 (a) shows the thickness (i.e., height) of the edge and surrounding positions of the channel layer (such as Sn-WSe2) doped with high-temperature Lewis acid. The measurement results are shown in Figure 6As shown in (b), it can be seen that the thickness of the channel layer after high-temperature Lewis acid doping (such as Sn-WSe2) is 5 nm, and the thickness of the channel layer before doping (such as WSe2) is also 5 nm, that is, there is no difference in the thickness of the channel layer before and after doping.

[0088] The high-angle annular dark field-scanning transmission electron microscopy (HAADF-STEM) image of the channel layer (such as Sn-WSe2) after high-temperature Lewis acid doping is shown in the figure below. Figure 7 (a) shows. Read three columns of atoms and detect the intensities of the three columns of atomic peaks, respectively. Figure 7 (b), 7(c) and 7(d). The intensities of different atomic peaks are different. Figure 7 (b) The intensities of the two atomic peaks were detected. Figure 7 (c) The intensities of the two atomic peaks were detected. Figure 7 (d) The intensity of one atomic peak is detected, and the intensity of three atomic peaks is detected in total, indicating that Sn atoms are doped into the channel layer. The high-temperature Lewis acid doping process causes Sn to enter the WSe2 lattice and replace the W site.

[0089] The It (source-drain current-time) curve of the channel layer (such as WSe2) without high-temperature Lewis acid doping treatment is as follows: Figure 8 As shown, when the light pulse frequency is 1 Hz and a source-drain voltage of 0.1 V is applied, the change in source-drain current exhibits a fast switching light response characteristic, which cannot simulate the performance of the photoelectric synapse.

[0090] After the high-temperature Lewis acid doped channel layer, this embodiment can simulate synaptic behavior by changing the gate voltage and the number, width and frequency of light pulses, including excitatory postsynaptic current (EPSC), double pulse facilitation (PPF), long-term memory (STM), short-term memory (LTM) and other functions. Fig. 9 As shown in (a), the source-drain current changes were detected at 50, 100, 200, and 400 light pulses, and the transition from short-term memory (STM) to long-term memory (LTM) was observed, which is consistent with the performance of optoelectronic synaptic devices. Fig. 9 As shown in (b), the source-drain current changes were detected at light pulse widths of 0.05, 0.2, 0.4, and 1 s, and the transition from short-term memory (STM) to long-term memory (LTM) was observed, which is consistent with the performance of optoelectronic synaptic devices. Fig. 9 As shown in (c), the source-drain current changes were detected at light pulse frequencies of 1, 1.67, 3.33, and 20 Hz, and the transition from short-term memory (STM) to long-term memory (LTM) was observed, which is consistent with the performance of optoelectronic synaptic devices.

[0091] The EPSC (excitatory aftercurrent) of the Sn-WSe2-based optoelectronic synaptic device under the lowest power consumption condition is shown in Figure 2. Fig.10 As shown. The power consumption calculation formula is: E erasing =V d ×I d ×T duration Among them, E erasing is the power consumption, V d is the operating voltage, I d is the peak current, T duration is the optical pulse width. The minimum power consumption conditions are: operating voltage 0.004V, optical pulse intensity 0.6mWcm 2 , the optical pulse width is 50ms and the minimum power consumption is 0.1fJ.

[0092] The optoelectronic synapse device in this embodiment has an extremely fast and sensitive response to light pulses and can be applied to high-pass filtering for image preprocessing. Fig.11 As shown in (a), the changes in source-drain current are detected at light pulse frequencies of 0.2, 1, 2, 3, 3.5, 4, 4.5 and 5 Hz respectively. Fig.11 As shown in (b), the source-drain current of the 30th light pulse is ratioed to the source-drain current of the 1st light pulse, and this ratio is named gain. A curve is drawn with gain as the ordinate and light pulse frequency as the abscissa, and a curve is fitted according to the curve, and the cutoff frequency f is determined according to the fitted curve. c It is 0.95Hz. Fig.11 (c) is the image before high-pass filtering. Fig.11 (d) is the cut-off frequency f c The high-pass filtered image is Fig.11 (e) is a high-pass filtered image at 5 Hz. It can be seen that when the cutoff frequency is greater than or equal to f c Under this condition, the image edge is more obvious.

[0093] The optoelectronic synapse device in this embodiment can be applied to Boolean logic commands. Fig.12 As shown in (a), under the dual-mode coordinated modulation of light and electricity, input A is a light pulse, and the light state is defined as logic "1" and the light-free state is defined as logic "0"; input B is the gate voltage, and no gate voltage is defined as logic "1" and gate voltage is defined as logic "0". The threshold current is set to 100pA, and the source-drain current after the AND Boolean logic command is detected. It can be seen that the AND Boolean logic command is successfully simulated. Fig.12As shown in (b), under the dual-mode cooperative modulation of light and electricity, input A is a light pulse, and the light state is defined as logic "1" and the light-free state is defined as logic "0"; input B is the gate voltage, and no gate voltage is defined as logic "1" and gate voltage is defined as logic "0". The threshold current is set to 100pA, and the source-drain current after the OR (or) Boolean logic command is detected. It can be seen that the OR (or) Boolean logic command is successfully simulated.

[0094] In summary, according to the preparation method of the photoelectric synapse device provided in the embodiment of the present application, by doping the channel layer with Lewis acid for a preset time under a high temperature environment, a trap center is introduced into the band structure of the channel layer to capture the photogenerated charge and produce a continuous photoconductivity effect, thereby realizing the simulation of the photoelectric synapse function. The photoelectric synapse function includes excitatory postsynaptic current (EPSC), double pulse facilitation (PPF), long-term memory (STM), short-term memory (LTM) and other functions, and at the same time, optical and electrical dual-mode regulation of conductivity is realized, and during simulation, it has extremely low operating voltage (0.004V) and weak light pulse intensity (0.6mWcm 2 ) and extremely low power consumption (0.1fJ). It has an extremely fast and sensitive response to electrical pulses and can be applied to high-pass filtering for image preprocessing or to simulate Boolean logic commands.

[0095] Correspondingly, an embodiment of the present application further provides a photoelectric synapse device, which can be prepared by using the preparation method of the photoelectric synapse device in the above embodiment.

[0096] like Figure 2 As shown, the optoelectronic synapse device provided in the embodiment of the present application includes a gate 1, a gate oxide layer 2, a channel layer 3 and a source and drain.

[0097] The gate 1 may be a semiconductor layer including silicon or a semiconductor layer including other elements. The gate 1 is a highly doped semiconductor layer, and the doping type of the gate 1 may be N-type or P-type.

[0098] The gate oxide layer 2 is located on one side of the gate 1. The gate oxide layer 2 may include one or more combinations of silicon oxide, silicon nitride, and the like.

[0099] The channel layer 3 is located on the side of the gate oxide layer 2 away from the gate 1. The channel layer 3 covers a portion of the gate oxide layer 2. The channel layer 3 is a semiconductor layer. Figure 3 As shown, the lateral cross section of the channel layer 3 is triangular.

[0100] Lewis acid is doped in the channel layer 3 to introduce trap centers in the energy band structure of the channel layer 3. By adjusting the doping temperature (e.g., 70°C-160°C), doping time (10min-1h) and / or doping concentration (0.01mol%-1mol%) of the Lewis acid, the energy band structure of the channel layer 3 can be adjusted to introduce trap centers in the energy band structure of the channel layer 3, capture photogenerated charges, generate a continuous photoconductivity effect, and achieve simulation of the photoelectric synapse function.

[0101] The source and drain are located on the side of the channel layer 3 away from the gate oxide layer 2, and the source and drain are connected to the channel layer 3. The source and drain include a source 4 and a drain 5, and the source 4 and the drain 5 are arranged laterally spaced. The source 4 is located on the side of the channel layer 3 away from the gate oxide layer 2, and is connected to the channel layer 3. The source 4 can also extend onto the gate oxide layer 2. The drain 5 is located on the side of the channel layer 3 away from the gate oxide layer 2, and is connected to the channel layer 3. The drain 5 can also extend onto the gate oxide layer 2. Among them, the source 4 can include one or more combinations of copper, titanium, aluminum, nickel, gold, etc. The drain 5 can include one or more combinations of copper, titanium, aluminum, nickel, gold, etc.

[0102] In some embodiments, the channel layer 3 includes a two-dimensional material layer.

[0103] In some embodiments, the two-dimensional material layer includes WSe 2. The two-dimensional material layer may also include other types of two-dimensional materials, such as MoS 2, WS 2, and MoSe 2, etc., which are not specifically limited here.

[0104] In some embodiments, the thickness of the channel layer 3 is relatively thin, for example, the thickness of the channel layer 3 is 5 nm.

[0105] In some embodiments, the Lewis acid includes SnCl4. Lewis acid refers to any molecule, ion or atom group that can accept an external electron pair. Lewis acid can also include other liquid electrophilic reagents, such as BF3, AlCl3 and SO3, etc., which are not specifically limited here.

[0106] In summary, according to the photoelectric synapse device provided in the embodiment of the present application, by doping the channel layer with Lewis acid for a preset time under a high temperature environment, a trap center is introduced into the band structure of the channel layer to capture photogenerated charges and produce a continuous photoconductivity effect, thereby simulating the photoelectric synapse function. The photoelectric synapse function includes excitatory postsynaptic current (EPSC), double pulse facilitation (PPF), long-term memory (STM), short-term memory (LTM) and other functions, and at the same time, optical and electrical dual-mode regulation of conductivity is achieved, and during simulation, it has extremely low operating voltage (0.004V) and weak light pulse intensity (0.6mWcm 2) and extremely low power consumption (0.1fJ). It has an extremely fast and sensitive response to electrical pulses and can be applied to high-pass filtering for image preprocessing or to simulate Boolean logic commands.

[0107] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0108] In the description of the present application, “plurality” means two or more.

[0109] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0110] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a photoelectric synapse device, characterized in that: include: Providing a gate and a gate oxide layer located on one side of the gate; forming a channel layer on a side of the gate oxide layer facing away from the gate; Forming a source and a drain on a side of the channel layer away from the gate oxide layer, and the source and the drain are connected to the channel layer; In a high temperature environment, the channel layer is doped with Lewis acid for a preset time to introduce trap centers into the energy band structure of the channel layer.

2. The method for preparing the optoelectronic synapse device according to claim 1, characterized in that: The forming of a source and a drain on a side of the channel layer away from the gate oxide layer comprises: forming a capping layer on a side of the channel layer away from the gate oxide layer; forming an opening in the cover layer to expose the channel layer; forming a source and a drain electrode connected to the exposed channel layer in the opening; The covering layer is removed.

3. The method for preparing the optoelectronic synapse device according to claim 1, characterized in that: The step of performing Lewis acid doping on the channel layer for a preset time under a high temperature environment includes: Dissolving a liquid Lewis acid in an alcoholic polar protic solvent; The solvent containing the Lewis acid is transferred into a polytetrafluoroethylene reactor and heated; In a high temperature environment, the channel layer is immersed in the reaction kettle to perform Lewis acid doping on the channel layer for a preset time.

4. The method for preparing the optoelectronic synapse device according to claim 1, characterized in that: The high temperature is 70°C-160°C.

5. The method for preparing the optoelectronic synapse device according to claim 1, characterized in that: The preset duration is 10min-1h.

6. The method for preparing a photoelectric synapse device according to claim 1, characterized in that: The doping concentration of the Lewis acid is 0.01 mol % to 1 mol %.

7. The method for preparing the optoelectronic synapse device according to claim 1, characterized in that: The Lewis acid includes SnCl4.

8. The method for preparing the optoelectronic synapse device according to any one of claims 1 to 7, characterized in that: The channel layer includes a two-dimensional material layer.

9. The method for preparing the optoelectronic synapse device according to claim 8, characterized in that: The two-dimensional material layer includes WSe2.

10. A photoelectric synapse device, characterized in that: The photoelectric synapse device is prepared by the method for preparing the photoelectric synapse device according to any one of claims 1 to 9, wherein the photoelectric synapse device comprises: Gate; A gate oxide layer, located on one side of the gate; A channel layer is located on a side of the gate oxide layer away from the gate; the channel layer is doped with Lewis acid to introduce trap centers in the energy band structure of the channel layer; The source and drain are located on a side of the channel layer away from the gate oxide layer and connected to the channel layer.

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