Back contact battery post-texturing method with specific laser opening mode and battery

Abstract

The invention belongs to the technical field of back contact batteries, and particularly relates to a back contact battery post-texturing method with a specific laser opening mode and a battery, and the process of forming a second semiconductor opening area comprises the following steps: rotating a target silicon wafer from a feeding position to a CCD camera position, and obtaining the position information of the target silicon wafer through a CCD camera, the position information is fed back to a laser marking mechanism and a mask mechanism which are arranged at a processing position, and the laser marking mechanism and the mask mechanism carry out alignment position adjustment according to the fed-back position information; and laser emitted by the laser marking mechanism passes through the mask plate and then is marked on a target silicon wafer to be processed. According to the invention, the edge of the opening area of the second semiconductor can be flat, the proportion of a laser opening edge transition area in the opening area of the second semiconductor is reduced to the greatest extent, the gradient of the junction of the opening area and the non-opening area is effectively improved, and Josc is obviously improved in a minority carrier lifetime test of a battery body, so that the battery efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery post-texturing method and a battery with a specific laser opening method. Background Art

[0002] At present, one method for preparing a back contact battery is a post-texturing method, which specifically involves performing texturing and cleaning after etching an opening in the first semiconductor layer on the back to form a second semiconductor opening area, and then depositing the second semiconductor layer.

[0003] The etching opening of the second semiconductor opening region is generally performed by laser etching. However, due to factors such as the light spot shape and energy distribution, the edge of the laser opening is very uneven. Figure 1 As shown; and a steeper transition area will be formed at the junction of the opening area and the non-opening area, such as Figure 2 As shown; therefore, in the subsequent texturing and cleaning of the multi-layer structure of the back contact battery, the transition zone will have hidden dangers such as excessive solution etching and side etching of the polycrystalline layer, and the uneven edge of the opening will increase the proportion of this transition zone, resulting in a high internal defect density, increasing the carrier recombination centers inside the material, and affecting the battery efficiency.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0005] The purpose of the present invention is to overcome the defect of the prior art that the internal defect density of the film layer is large in the back contact post-texturing method, which affects the battery efficiency, and to provide a back contact battery post-texturing method and a battery with a specific laser opening method, which can make the edge of the second semiconductor opening area smooth, minimize the proportion of the laser opening edge transition zone in the second semiconductor opening area, and effectively improve the slope at the junction of the opening area and the non-opening area, which is reflected in the battery body minority carrier life test as a significant improvement in Josc, thereby improving the battery efficiency.

[0006] In order to achieve the above-mentioned purpose, in the first aspect, the present invention provides a back contact battery post-texturing method with a specific laser opening method, comprising: depositing a first semiconductor layer and a mask layer on the back side of a silicon wafer in sequence, then performing a first laser opening on the back side to form a second semiconductor opening area, then performing texturing cleaning, and then depositing a second semiconductor layer on the back side. The process of performing the first laser opening to form the second semiconductor opening area includes: A laser marking mechanism and a mask mechanism including a mask plate are arranged at the processing position in advance, the mask plate is arranged between the laser marking mechanism and the target silicon wafer at the processing position, and the distance d between the mask plate and the target silicon wafer at the processing position is controlled to be 0.5 mm-2 mm; a grid-shaped hollow area is arranged on the mask plate; the width D of a single grid-shaped hollow area of ​​the mask plate is greater than the width of the second semiconductor opening area; During the first laser opening, the target silicon wafer is rotated from the loading position to the CCD camera position, the position information of the target silicon wafer is obtained by the CCD camera, and the position information is fed back to the laser marking mechanism and the mask mechanism set at the processing position. The laser marking mechanism and the mask mechanism adjust the alignment position according to the fed-back position information; when the target silicon wafer is rotated from the CCD camera position to the processing position, the laser emitted by the laser marking mechanism hits the target silicon wafer to be processed after passing through the mask plate, forming a second semiconductor opening area.

[0007] In some preferred embodiments of the present invention, the position information of the target silicon wafer includes X-axis position information, Y-axis position information, and rotation angle position information of the target silicon wafer.

[0008] In some preferred embodiments of the present invention, the laser emitted by the laser marking mechanism is fired from top to bottom, the laser marking mechanism performs position compensation adjustment of the laser processing pattern according to the feedback position information, and the mask mechanism adjusts the corresponding position of the mask plate according to the feedback position information, so that the laser acts on the target area of ​​the target silicon wafer through the mask plate.

[0009] In some preferred embodiments of the present invention, the mask is black.

[0010] In some preferred embodiments of the present invention, the ratio of D to the width of the second semiconductor opening region is 1.02-1.08:1.

[0011] In some preferred embodiments of the present invention, the width of the second semiconductor opening region is 300-700 μm.

[0012] In some preferred embodiments of the present invention, D / d=0.26-0.54:1, more preferably 0.51-0.54:1.

[0013] In some preferred embodiments of the present invention, the back contact battery back texturing method further comprises: A front passivation layer and an anti-reflection layer are formed on the front side of the silicon wafer after texturing and cleaning, and then a second semiconductor layer is deposited; Performing a second laser opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; Depositing a conductive film layer on the back side; Performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; Metal fine gate electrodes are respectively formed on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located.

[0014] In some preferred embodiments of the present invention, the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer.

[0015] In a second aspect, the present invention provides a back-contact battery, which is produced by the back-contact battery post-texturing method with a specific laser opening method as described in the first aspect.

[0016] Beneficial effects: The present invention adopts the above technical scheme, especially in the process of forming the second semiconductor opening area in the post-texturing method, a mask mechanism including a specific mask plate is added to the processing position, and the position information of the target silicon wafer is obtained in cooperation with the CCD camera position, and the position information is fed back to the laser marking mechanism and the mask mechanism set at the processing position. The laser marking mechanism and the mask mechanism adjust the alignment position according to the feedback position information to ensure that the mask plate is accurately aligned and the laser processing is completed; and in particular, the mask plate with a suitable distance added between the laser beam and the target silicon wafer can filter out the uneven area of ​​the spot edge, so that the edge of the second semiconductor opening area is flat (in one embodiment, as Figure 3-4 As shown, the edge is close to a straight line), combined with D being greater than the width of the second semiconductor opening area, the proportion of the laser opening edge transition area in the second semiconductor opening area can be minimized, effectively avoiding the hidden dangers of excessive solution etching and polycrystalline layer side etching in subsequent texturing and cleaning due to the large proportion of the transition area. At the same time, it can effectively improve the slope at the junction of the opening area and the non-opening area, which is reflected as Josc in the battery body minority carrier life test (refers to a specific composite current density parameter, the unit is nA / cm 2 ) has been significantly improved, while also improving battery efficiency.

[0017] Among them, the present invention controls the distance d between the mask plate and the target silicon wafer on the processing position to be 0.5mm-2mm, so that the mask plate is as close to the target silicon wafer to be processed as possible, and prevents the refraction of the light beam when it hits the edge of the mask plate, which leads to poor edge effect, and is conducive to ensuring that the edge of the laser beam hitting the silicon wafer through the mask plate is smoother. Under the same conditions, when d is too large, the laser is prone to scattering, refraction, etc. after passing through the mask plate, thereby damaging the film layer in the non-processing area, and the edge of the processing area is prone to unevenness. When d is too small, the mask plate directly contacts the surface of the silicon wafer when the processing stage rotates, which will damage the film layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 This is a 3D microscope image of the laser opening edge of the second semiconductor opening region in the post-texturing method of the prior art.

[0020] Figure 2 This is a SEM electron microscope image of the laser opening edge of the second semiconductor opening area in the post-texturing method of the prior art.

[0021] Figure 3 This is a 3D microscope image of the laser opening edge of the second semiconductor opening region in Example 1 of the present invention.

[0022] Figure 4 This is a SEM electron microscope image of the laser opening edge of the second semiconductor opening region in Example 1 of the present invention.

[0023] Figure 5 It is a schematic diagram of the arrangement structure of each station in the process of forming the second semiconductor opening region in one implementation manner.

[0024] Figure 6 A schematic structural diagram of an implementation scheme of a mask plate.

[0025] Figure 7 It is a structural schematic diagram of the mask plate of the mask mechanism and the silicon wafer cooperating with each other.

[0026] Figure 8 for Figure 7 Schematic diagram of the three-dimensional structure.

[0027] Description of Reference Numerals 1. Loading position, 2. CCD camera position, 3. Processing position, 4. Waiting position, 5. Rotating axis, 6. Mask mechanism, 601. Mask plate, 602. Hollow area, 7. Silicon wafer. DETAILED DESCRIPTION

[0028] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0029] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0030] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0031] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0032] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0033] In the first aspect, the present invention provides a back contact battery post-texturing method with a specific laser opening method, comprising: depositing a first semiconductor layer and a mask layer on the back of a silicon wafer in sequence, then performing a first laser opening on the back to form a second semiconductor opening area, then performing texturing cleaning, and then depositing a second semiconductor layer on the back. The process of performing the first laser opening to form the second semiconductor opening area includes: A laser marking mechanism and a mask mechanism including a mask plate are arranged at the processing position in advance, the mask plate is arranged between the laser marking mechanism and the target silicon wafer at the processing position, and the distance d between the mask plate and the target silicon wafer at the processing position is controlled to be 0.5 mm-2 mm; a grid-shaped hollow area is arranged on the mask plate; the width D of a single grid-shaped hollow area of ​​the mask plate is greater than the width of the second semiconductor opening area; During the first laser opening, the target silicon wafer is rotated from the loading position to the CCD camera position, and the position information of the target silicon wafer is obtained through the CCD camera, and the position information is fed back to the laser marking mechanism and the mask mechanism set at the processing position. The laser marking mechanism and the mask mechanism adjust the alignment position according to the feedback position information; when the target silicon wafer is rotated from the CCD camera position to the processing position, the laser emitted by the laser marking mechanism hits the target silicon wafer to be processed after passing through the mask plate to form the second semiconductor opening area. The mask mechanism drives the mask plate to the target position to align the target silicon wafer to perform laser opening on the preset area. The position information of the target silicon wafer is obtained through the CCD camera.

[0034] The above solution of the present invention makes the edge of the second semiconductor opening region smooth (in one embodiment, as Figure 3-Figure 4 As shown, the edge is close to a straight line), compared with the steep transition area of ​​the corresponding opening area edge in the prior art, it can minimize the proportion of the laser opening edge transition area in the second semiconductor opening area (such as area proportion and / or length proportion), effectively avoid the hidden dangers of excessive solution etching and polycrystalline layer side etching in subsequent texturing and cleaning due to the large proportion of the transition area, and at the same time effectively improve the slope at the junction of the opening area and the non-opening area, which is reflected in the battery body minority carrier life test as an effective reduction of Josc (refers to a specific composite current density parameter, the unit is nA / cm 2 ), while improving battery efficiency.

[0035] In some preferred embodiments of the present invention, the position information of the target silicon wafer includes X-axis position information, Y-axis position information, and rotation angle position information of the target silicon wafer, which is more conducive to accurate alignment of the area to be laser opened.

[0036] Due to the angle of laser processing, when the silicon wafer is sent to the loading position via the conveyor belt, after vacuum adsorption, the position of the silicon wafer adsorbed on the carrier to be processed is different each time, and there will be differences in the horizontal / vertical / rotational angles. Therefore, a set of compensation values ​​is required to ensure that the position of each silicon wafer processing is consistent. In this regard, in some preferred embodiments of the present invention, the laser marking mechanism performs position compensation adjustment of the laser processing pattern according to the feedback position information, and the mask mechanism adjusts the corresponding position of the mask plate according to the feedback position information, so that the laser acts on the target area of ​​the target silicon wafer through the mask plate. The role of the mask mechanism is to make corresponding adjustments to the position masked by the mask plate through the received signal.

[0037] It can be understood that the position compensation refers to the correction of the X-axis position information, Y-axis position information, and rotation angle position information by comparing the calibration value after the CCD camera captures the mark. The correction value obtained is the position compensation value, which is used to ensure that the drawings processed by the laser are in the same position relative to the silicon wafer, and to feed back the correction information to the laser marking mechanism and the mask mechanism at the same time, so that the relative position of the graphics processed by the laser and the mask plate in the mask mechanism can be adjusted to ensure that the position of the graphics processed on the silicon wafer is consistent.

[0038] Preferably, the laser emitted by the laser marking mechanism is emitted from top to bottom.

[0039] In some preferred embodiments of the present invention, the mask plate is black, which has good light absorption performance and is more conducive to effectively preventing factors such as refraction when the light beam hits the edge of the mask plate, resulting in poor edge effects.

[0040] The mask plate is preferably made of stainless steel.

[0041] The present invention controls D to be greater than the width of the second semiconductor opening area, which is beneficial to ensuring effective shielding processing through the mask plate during laser processing.

[0042] Preferably, the grid-like hollow areas in the mask plate are arranged at equal intervals.

[0043] In some preferred embodiments of the present invention, the ratio of D to the width of the second semiconductor opening region is 1.02-1.08:1, more preferably 1.03-1.07:1, which is more conducive to minimizing the proportion of the laser opening edge transition region in the second semiconductor opening region.

[0044] In some preferred embodiments of the present invention, the width of the second semiconductor opening region is 300-700 μm.

[0045] In some preferred embodiments of the present invention, D / d=0.26-0.54:1, and further preferably 0.51-0.54:1. Adopting the preferred range is more conducive to controlling the flatness of the edge of the second semiconductor opening region.

[0046] After depositing the first semiconductor layer, the present invention can further perform the steps of removing PSG and backwashing, and then depositing the mask layer. And after texturing and cleaning, the present invention can further select whether to perform the step of removing the mask layer according to actual needs.

[0047] In some preferred embodiments of the present invention, the back contact cell post texturing method further includes: forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer after texturing and cleaning, and then depositing a second semiconductor layer.

[0048] In some preferred embodiments of the present invention, the back contact cell post texturing method further includes: performing a second laser opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

[0049] Preferably, the width of the first semiconductor opening region is 150-350 μm.

[0050] In some preferred embodiments of the present invention, the back contact battery texturing method further includes: depositing a conductive film layer on the back side.

[0051] In some preferred embodiments of the present invention, the back contact battery post texturing method further includes: performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove.

[0052] Preferably, the width of the isolation groove is 30-200 μm.

[0053] In some preferred embodiments of the present invention, the back contact battery back texturing method further includes: forming metal fine gate electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0054] In the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer, and the first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon or microcrystalline silicon.

[0055] In some preferred embodiments of the present invention, the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer. The second doped silicon layer may be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer. One of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type.

[0056] The thickness of the tunnel oxide layer, the intrinsic silicon layer, the first doped polysilicon layer and the second doped silicon layer and the corresponding doping concentration of the tunnel oxide layer, the intrinsic silicon layer and the first doped polysilicon layer and the second doped silicon layer of the present invention can refer to the range of the prior art, and can be used in the present invention. For example, the thickness of the tunnel oxide layer is 1-2nm, the thickness of the intrinsic silicon layer is 5-15nm; the thickness of the second doped silicon layer is 7-45nm, and the effective doping concentration is 2e18cm -3 -3e20cm -3 The thickness of the first doped polysilicon layer is 80-200 nm, and the effective doping concentration is greater than 5e18 cm -3 .

[0057] In a second aspect, the present invention provides a back-contact battery, which is produced by the back-contact battery post-texturing method with a specific laser opening method as described in the first aspect.

[0058] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0059] Example 1 A back contact battery is prepared by a post-texturing method comprising: S01, double-sided polishing of silicon wafer 7; S02, the back of the silicon wafer 7 is coated with a first semiconductor layer in sequence, wherein the first semiconductor layer is a tunneling oxide layer with a thickness of 1.5 nm and an N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer is 100 nm, and the effective doping concentration is 1e19 cm -3 ; S03, removing PSG and back-washing and then plating the mask layer on the back side; S04, performing a first laser opening on the back side of the silicon wafer 7, removing the mask layer and a portion of the first semiconductor layer in the target area, and forming a second semiconductor opening area; When laser processing the second semiconductor opening region, Figure 5 As shown, the silicon wafer 7 is rotated from the loading position 1 to the CCD camera position 2 by the rotating shaft 5. After the CCD camera completes the labeling, it obtains the position information of the target silicon wafer 7 (including the X-axis position information, the Y-axis position information, and the rotation angle position information of the target silicon wafer 7), and feeds back the position information to the laser marking mechanism of the processing position 3 and the mask mechanism 6 including the mask plate 601 (black stainless steel). The laser marking mechanism completes the pattern position compensation, and the mask mechanism 6 adjusts the position of the mask plate 601 accordingly according to the feedback signal, so that the laser acts on the target area of ​​the target silicon wafer 7 through the mask plate 601; When the silicon wafer 7 at the CCD camera position 2 rotates to the processing position 3, the laser beam is shot from top to bottom, and then hits the target silicon wafer 7 to be processed after passing through the mask plate 601 of the mask mechanism 6. The mask plate 601 is designed with an equidistant grid shape (such as Figure 6 As shown), the distance d between the mask plate 601 and the target silicon wafer 7 on the processing position 3 is 1 mm. Figure 7 and Figure 8 As shown; the laser opening formed by the hollow area 602 (i.e., the area through which the light beam can pass) in the mask plate 601 is the second semiconductor opening area, the width of the second semiconductor opening area is 500 μm, the width D of the single grid-shaped hollow area 602 of the mask plate 601 is greater than the width of the second semiconductor opening area, and the ratio of D to the width of the second semiconductor opening area is 1.04:1, D / d=0.52:1; after the laser processing is completed, the silicon wafer 7 is transferred to the waiting position 4 for subsequent operations; The edge diagrams of the second semiconductor opening region are respectively as follows Figure 3 and Figure 4 As shown, it can be seen that the edge of the second semiconductor opening region is smooth, and the proportion of the laser opening edge transition region in the second semiconductor opening region is minimized.

[0060] S05, texturing and cleaning, forming a pyramid texture surface on the front side of the silicon wafer 7, and removing the first semiconductor layer in the second semiconductor opening area on the back side of the silicon wafer 7, and then removing all remaining mask layers; S06, forming a passivation layer and an anti-reflection layer by deposition on the front side, and forming a second semiconductor layer by deposition on the back side, wherein the second semiconductor layer is an intrinsic amorphous silicon layer with a thickness of 10 nm and a P-type doped amorphous silicon layer, wherein the thickness of the P-type doped amorphous silicon layer is 15 nm and the effective doping concentration is 9e19 cm -3 , the deposition method is formed by PECVD; S07, performing laser opening on the second semiconductor layer at the back side to form first semiconductor opening regions alternately arranged with the second semiconductor opening regions, wherein the width of the first semiconductor opening regions is 250 μm; S08, cleaning, removing the oxide layer in the first semiconductor opening area, and then depositing a transparent conductive film layer on the back side; S09, forming an isolation groove between the first semiconductor opening region and the second semiconductor opening region by etching, wherein the width of the isolation groove is 100 μm, and the isolation groove is formed at the junction of the texturing region and the polishing region; S10, forming a silver paste gate line electrode on the first semiconductor opening region and the second semiconductor opening region.

[0061] Example 2 The process is carried out in accordance with Example 1, except that the distance d between the mask plate and the target silicon wafer on the processing position is 2 mm.

[0062] Example 3 The same is carried out with reference to Example 1, except that D is adjusted so that the ratio of D to the width of the second semiconductor opening region is 1.08:1.

[0063] Example 4 The process is carried out in accordance with Example 1, except that D is adjusted so that D / d=0.51:1.

[0064] Comparative Example 1 The process is carried out with reference to Example 1, except that a mask mechanism including a mask plate is not provided, but a laser marking mechanism is used to directly mark the target silicon wafer to be processed to form a second semiconductor opening region.

[0065] Comparative Example 2 The process is carried out in accordance with Example 1, except that the distance d between the mask plate and the target silicon wafer on the processing position is 0.3 mm.

[0066] Comparative Example 3 The same is carried out as in Example 1, except that D is adjusted to 480 μm so that D is less than the width of the second semiconductor opening region.

[0067] Test Case The back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. Wherein, Josc refers to a specific composite current density parameter, with the unit of nA / cm 2 , which is obtained by testing the Sinton minority carrier lifetime tester.

[0068] Table 1

[0069] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can make the edge of the second semiconductor opening area smooth, thereby minimizing the proportion of the laser opening edge transition area in the second semiconductor opening area, and effectively improving the slope at the junction of the opening area and the non-opening area. In the battery body minority carrier life test, it is reflected in the significant improvement of Josc, the increase of short-circuit current, and the improvement of battery efficiency.

[0070] Furthermore, according to Example 1 and Examples 2-4, the preferred solution of the present invention is more conducive to the effective shielding of the mask plate to process the first laser processing area, ensuring that the edge transition area of ​​the second semiconductor opening area is minimized, which is more conducive to improving battery efficiency while reducing Josc.

[0071] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A back contact cell post texturing method with a specific laser opening method, comprising: A first semiconductor layer and a mask layer are sequentially deposited on the back of a silicon wafer, and then a first laser opening is performed on the back to form a second semiconductor opening area, and then a texturing and cleaning process is performed, and then a second semiconductor layer is deposited on the back. The process of performing the first laser opening to form the second semiconductor opening area includes: A laser marking mechanism and a mask mechanism including a mask plate are arranged at the processing position in advance, the mask plate is arranged between the laser marking mechanism and the target silicon wafer at the processing position, and the distance d between the mask plate and the target silicon wafer at the processing position is controlled to be 0.5 mm-2 mm; a grid-shaped hollow area is arranged on the mask plate; the width D of a single grid-shaped hollow area of ​​the mask plate is greater than the width of the second semiconductor opening area; During the first laser opening, the target silicon wafer is rotated from the loading position to the CCD camera position, the position information of the target silicon wafer is obtained by the CCD camera, and the position information is fed back to the laser marking mechanism and the mask mechanism set at the processing position. The laser marking mechanism and the mask mechanism adjust the alignment position according to the fed-back position information; when the target silicon wafer is rotated from the CCD camera position to the processing position, the laser emitted by the laser marking mechanism hits the target silicon wafer to be processed after passing through the mask plate, forming a second semiconductor opening area.

2. The back contact cell post texturing method with a specific laser opening method according to claim 1 is characterized in that: The position information of the target silicon wafer includes X-axis position information, Y-axis position information, and rotation angle position information of the target silicon wafer.

3. The back contact cell post texturing method with a specific laser opening method according to claim 1 or 2, characterized in that: The laser emitted by the laser marking mechanism is fired from top to bottom. The laser marking mechanism performs position compensation adjustment of the laser processing pattern according to the feedback position information. The mask mechanism adjusts the corresponding position of the mask plate according to the feedback position information, so that the laser acts on the target area of ​​the target silicon wafer through the mask plate.

4. The back contact cell post texturing method with a specific laser opening method according to claim 1, characterized in that: The mask is black.

5. The back contact cell post texturing method with a specific laser opening method according to claim 1, characterized in that: The ratio of D to the width of the second semiconductor opening region is 1.02-1.08:

1.

6. The back contact cell post texturing method with a specific laser opening method according to claim 1, characterized in that: The width of the second semiconductor opening region is 300-700 μm.

7. The back contact cell post texturing method with a specific laser opening method according to claim 1, characterized in that: D / d=0.26-0.54:

1.

8. The back contact cell post texturing method with a specific laser opening method according to claim 7, characterized in that: The back contact battery post texturing process also includes: A front passivation layer and an anti-reflection layer are formed on the front side of the silicon wafer after texturing and cleaning, and then a second semiconductor layer is deposited; Performing a second laser opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; Depositing a conductive film layer on the back side; Performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; Metal fine gate electrodes are respectively formed on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located.

9. The back contact cell post texturing method with a specific laser opening method according to claim 1, characterized in that: The first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer, and the first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon or microcrystalline silicon.

10. A back contact battery, characterized in that: It is manufactured by a back contact cell post texturing method with a specific laser opening method as described in any one of claims 1 to 9.

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