Solar cells and their manufacturing methods, photovoltaic modules

Abstract

This disclosure relates to the photovoltaic field, providing a solar cell and its manufacturing method, and a photovoltaic module. The solar cell includes: a substrate comprising a front side and a back side; a first sub-busbar and a second sub-busbar located on the back side; a first main busbar electrically connected to the first sub-busbar, and a second main busbar electrically connected to the second sub-busbar; a first insulating layer covering a portion of the surface of the first sub-busbar; and a second insulating layer covering a portion of the surface of the second sub-busbar. The distance between the second sub-busbar directly opposite and adjacent to the first pad and the first pad is a first distance L1, and the distance between the end of the second insulating layer covering the second sub-busbar and the first pad is a second distance L2, where 7L2 / 6≤L1≤6L2. Alternatively, in a second direction, the distance between the first sub-busbar directly opposite and adjacent to the second pad and the second pad is a third distance L3, and the distance between the end of the first insulating layer covering the first sub-busbar and the second pad is a fourth distance L4, where 7L2 / 6≤L1≤6L2. This can improve the performance of the solar cell.

Description

Technical Field

[0001] This disclosure relates to the photovoltaic field, and in particular to a solar cell, a method for manufacturing the same, and a photovoltaic module. Background Technology

[0002] Solar cell power generation is a sustainable and clean energy source that uses the photovoltaic effect of semiconductor pn junctions to convert sunlight into electrical energy.

[0003] During the process of connecting solar cells in series to form a solar cell string, the solder ribbon may shift, causing a short circuit in the solar cell string. Therefore, an insulating layer is usually installed to improve the reliability of the photovoltaic module.

[0004] However, how to set up the insulation layer has become an urgent problem to be solved. Summary of the Invention

[0005] This disclosure provides a solar cell and its manufacturing method, as well as a photovoltaic module, which can at least improve the performance of the solar cell.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a battery cell, comprising: a substrate, the substrate including a front side and a back side opposite to each other; a plurality of first sub-gates and a plurality of second sub-gates arranged alternately at intervals along a first direction, the first sub-gates and the second sub-gates being located on the back side of the substrate; a first main gate and a second main gate arranged alternately at intervals along a second direction, the first main gates being electrically connected to the plurality of first sub-gates and spaced apart from the second sub-gates, the second main gates being electrically connected to the plurality of second sub-gates and spaced apart from the first sub-gates; a first insulating layer, the first insulating layer at least covering a portion of the surface of the first sub-gates; and a second insulating layer, the second insulating layer at least covering a portion of the surface of the second sub-gates. The first main gate has a first pad, and in the second direction, the distance between the second sub-gate, which is directly opposite and adjacent to the first pad, and the first pad is a first distance L1. The distance between the end of the second insulating layer covering the second sub-gate and the first pad is a second distance L2, where 7L2 / 6≤L1≤6L2. Alternatively, the second main gate has a second pad, and in the second direction, the distance between the first sub-gate, which is directly opposite and adjacent to the second pad, and the second pad is a third distance L3. The distance between the end of the first insulating layer covering the first sub-gate and the second pad is a fourth distance L4, where 7L2 / 6≤L1≤6L2.

[0007] In some embodiments, the first main gate is provided with a first pad, the height of the first pad being greater than the height of the second insulating layer, and / or, the second main gate is provided with a second pad, the height of the second pad being greater than the height of the first insulating layer.

[0008] In some embodiments, the substrate includes two edge regions arranged along a first direction and a central region located between the two edge regions, wherein in a second direction, the width of the first insulating layer located in the edge region is greater than the width of the first insulating layer located in the central region, and / or, the width of the second insulating layer located in the edge region is greater than the width of the second insulating layer located in the central region.

[0009] In some embodiments, the width of the first insulating layer located in the edge region is 3mm to 10mm, and / or the width of the second insulating layer located in the edge region is 3mm to 10mm.

[0010] In some embodiments, along the second direction, the first sub-gate includes a first connecting portion and a first discontinuity portion arranged at intervals, the first discontinuity portion being directly opposite the second main gate; along the second direction, the second sub-gate includes a second connecting portion and a second discontinuity portion arranged at intervals, the second discontinuity portion being directly opposite the first main gate.

[0011] In some embodiments, the first insulating layer covers the end of the first connection near the first interruption and also covers a portion of the surface of the first interruption, exposing the top surface of the second main gate; the second insulating layer covers the end of the second connection near the second interruption and also covers a portion of the surface of the second interruption, exposing the top surface of the first main gate.

[0012] In some embodiments, the first main gate is provided with the first pad, and in the second direction, the width of the second discontinuity of the second sub-gate directly opposite the first pad is greater than the width of the second discontinuity of the second sub-gate offset from the first pad, and / or, the second main gate is provided with the second pad, and in the second direction, the width of the first discontinuity of the first sub-gate directly opposite the second pad is greater than the width of the first discontinuity of the first sub-gate offset from the second pad.

[0013] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a battery cell, comprising: providing a substrate, the substrate including opposing front and back sides; forming a plurality of first sub-gates and a plurality of second sub-gates arranged alternately along a first direction, the first sub-gates and the second sub-gates located on the back side of the substrate; forming a first main gate and a second main gate arranged alternately along a second direction, the first main gate being electrically connected to the plurality of first sub-gates, and the second main gate being electrically connected to the plurality of second sub-gates; forming a first insulating layer covering a portion of the surface of the first sub-gates; forming a second insulating layer covering a portion of the surface of the second sub-gates; and so on. In the first main gate, a first pad is provided. In the second direction, the distance between the second sub-gate, which is directly opposite and adjacent to the first pad, and the first pad is a first distance L1. The distance between the end of the second insulating layer covering the second sub-gate and the first pad is a second distance L2, where 7L2 / 6≤L1≤6L2. Or, the second main gate is provided with a second pad. In the second direction, the distance between the first sub-gate, which is directly opposite and adjacent to the second pad, and the second pad is a third distance L3. The distance between the end of the first insulating layer covering the first sub-gate and the second pad is a fourth distance L4, where 7L2 / 6≤L1≤6L2.

[0014] In some embodiments, the first main gate is provided with a first pad, and the second main gate is provided with a second pad. Before forming the first insulating layer, the method further includes: forming a protective film, the protective film corresponding to the positions of the first pad and the second pad; after forming the second insulating layer, the method further includes: removing the protective film and the first insulating layer and the second insulating layer formed on the surface of the protective film.

[0015] According to some embodiments of this disclosure, another aspect of this disclosure also provides a photovoltaic module, including: a battery string, which is formed by connecting multiple battery cells as described above, or by connecting multiple battery cells formed by the manufacturing method of the battery cells as described above; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film away from the battery string.

[0016] The technical solution provided in this disclosure has at least the following advantages: First, setting a first insulating layer and a second insulating layer can prevent short circuits between the solder strip and the secondary grid that does not require electrical connection when connecting the battery strings in series, thereby improving the reliability of the process of connecting the battery cells into a battery string; moreover, when there is a first pad on the first main grid, setting the distance between the second secondary grid and the first pad and the distance between the end of the second insulating layer and the first pad to satisfy 7L2 / 6≤L1≤6L2 can prevent the distance between the second insulating layer and the first pad from being too close, thereby preventing the second insulating layer from collapsing and extending to the first pad. On a single pad, the second insulating layer is used to prevent it from affecting the welding of the first pad and subsequent solder strips. At the same time, it also prevents the distance between the second sub-gate and the first pad from being too large, thus avoiding affecting the ability of the second sub-gate to collect charge carriers. This improves the performance of the cell while avoiding affecting its reliability. Similarly, when there is a second pad on the second main gate, setting the distance between the first sub-gate and the second pad and the distance between the end of the first insulating layer and the second pad to satisfy 7L4 / 6≤L3≤6L4 can also prevent the first insulating layer from affecting the welding of the second pad and subsequent solder strips, while avoiding affecting the ability of the first sub-gate to collect charge carriers. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A top view of a battery cell provided in an embodiment of this disclosure;

[0019] Figure 2 A cross-sectional view of a substrate provided in an embodiment of this disclosure;

[0020] Figure 3 This is a top view of a first and second sub-gate provided in one embodiment of the present disclosure;

[0021] Figure 4 This is a partial structural diagram of a battery cell provided in one embodiment of the present disclosure;

[0022] Figure 5 This is a partial structural diagram of another part of the battery cell provided in one embodiment of the present disclosure;

[0023] Figure 6 Another top view of a battery cell provided in an embodiment of this disclosure;

[0024] Figures 7 to 10 This is a schematic diagram of the structure corresponding to each step of the method for manufacturing a battery cell according to another embodiment of this disclosure;

[0025] Figure 11 A partial three-dimensional structural schematic diagram of a photovoltaic module provided in yet another embodiment of this disclosure;

[0026] Figure 12 for Figure 11 A schematic diagram of a cross-sectional structure along the cross-sectional direction MM1. Detailed Implementation

[0027] As the background technology shows, for back contact batteries, the positive and negative grid lines are located on the back of the cell. An insulating layer is covered on the opposite-shaped sub-grid corresponding to the main grid to prevent short circuit between the solder ribbon and the opposite-shaped sub-grid. However, during the formation of the insulating layer or in other subsequent processes, it may collapse, causing the insulating layer to cover the pad of the main grid. This will affect the connection between the pad and the solder ribbon, and may lead to an unreliable connection between the solder ribbon and the pad, or even detachment.

[0028] This disclosure provides a solar cell and its manufacturing method, as well as a photovoltaic module. The solar cell incorporates a first insulating layer and a second insulating layer, which prevents short circuits between the solder strip and the secondary grid (which does not require electrical connection) when connecting the cells in series, thereby improving the reliability of the process. Furthermore, when a first pad exists on the first main grid, setting the distance between the second secondary grid and the first pad, and the distance between the end of the second insulating layer and the first pad, satisfies 7L² / 6≤L1≤6L². This prevents the second insulating layer from becoming too close to the first pad, thus preventing the second insulating layer from collapsing. Extending the insulation layer to the first pad prevents the second insulating layer from affecting the welding of the first pad and subsequent solder strips. It also prevents the distance between the second sub-gate and the first pad from being too large, thus avoiding affecting the second sub-gate's ability to collect carriers. This improves cell performance while maintaining cell reliability. Similarly, when a second pad exists on the second main gate, setting the distance between the first sub-gate and the second pad, and the distance between the end of the first insulating layer and the second pad, to satisfy 7L4 / 6≤L3≤6L4, also prevents the first insulating layer from affecting the welding of the second pad and subsequent solder strips while avoiding affecting the first sub-gate's ability to collect carriers.

[0029] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly defined.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0032] In the description of the embodiments of this disclosure, the term "multiple" refers to two or more (including two), similarly, "multiple groups" refers to two or more (including two groups), and "multiple pieces" refers to two or more (including two pieces).

[0033] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0034] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0035] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0036] In the description of embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly" on the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0037] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0038] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0039] refer to Figures 1 to 5 , Figure 1 This is a top view of a battery cell provided according to an embodiment of the present disclosure. Figure 2 A cross-sectional view of a substrate provided in an embodiment of this disclosure. Figure 3 This is a top view of the first and second sub-gates provided in one embodiment of the present disclosure. Figure 4 This is a partial structural diagram of a battery cell provided in one embodiment of the present disclosure. Figure 5This is a partial structural diagram of another part of the battery cell provided in one embodiment of the present disclosure. It should be noted that, for clarity of illustration, Figure 3 The first main gate, the second main gate, the first insulating layer, and the second insulating layer are hidden in the middle. Figure 4 Only the first pad, the second sub-gate, and the second insulating layer are shown in the diagram. Figure 5 Only the second pad, the first subgate, and the first insulating layer are shown in the diagram.

[0040] In some embodiments, the battery cell may include a substrate 100, which includes an opposing front side 110 and a back side 120.

[0041] The solar cell may also include a plurality of first sub-grids 101 and a plurality of second sub-grids 102 arranged alternately along a first direction X, wherein the first sub-grids 101 and the second sub-grids 102 are located on the back side 120 of the substrate 100.

[0042] The solar cell may further include: a first main grid 103 and a second main grid 104 arranged alternately along the second direction Y, wherein the first main grid 103 is electrically connected to a plurality of first sub-grids 101 and spaced apart from the second sub-grids 102, and the second main grid 104 is electrically connected to a plurality of second sub-grids 102 and spaced apart from the first sub-grids 101.

[0043] The solar cell may also include a first insulating layer 105, which at least covers a portion of the surface of the first sub-grid 101.

[0044] The battery cell may further include: a second insulating layer 106, the second insulating layer 106 at least covering a portion of the surface of the second sub-gate 102, wherein the first main gate 103 is provided with a first pad 113, and in the second direction Y, the distance between the second sub-gate 102 and the first pad 113 that is directly opposite and adjacent to the first pad 113 is a first distance L1, the distance between the end of the second insulating layer 106 covering the second sub-gate 102 and the first pad 113 is a second distance L2, 7L2 / 6≤L1≤6L2, and / or, the second main gate 104 is provided with a second pad 114, and in the second direction Y, the distance between the first sub-gate 101 and the second pad 114 that is directly opposite and adjacent to the second pad 114 is a third distance L3, and the distance between the end of the first insulating layer 105 covering the first sub-gate 101 and the second pad 114 is a fourth distance L4, 7L4 / 6≤L3≤6L4.

[0045] This embodiment of the disclosure, by providing a first insulating layer 105 and a second insulating layer 106 in the provided battery cells, can prevent short circuits between the solder ribbon and the sub-grid that does not require electrical connection when the battery cells are connected in series, thereby improving the reliability of the process of connecting the battery cells into a battery string. Furthermore, when a first pad 113 exists on the first main grid 103, setting the distance between the second sub-grid 102 and the first pad 113, and the distance between the end of the second insulating layer 106 and the first pad 113, satisfies 7L² / 6 ≤ L1 ≤ 6L². This prevents the distance between the second insulating layer 106 and the first pad 113 from becoming too close, thus preventing the second insulating layer 106 from collapsing and extending onto the first pad 113. To avoid the second insulating layer 106 affecting the welding of the first pad 113 to the subsequent solder strips, and to prevent the distance between the second sub-gate 102 and the first pad 113 from being too large, thus avoiding affecting the ability of the second sub-gate 102 to collect charge carriers, thereby improving the performance of the cell while avoiding affecting the reliability of the cell. Similarly, when there is a second pad 114 on the second main gate 104, setting the distance between the first sub-gate 101 and the second pad 114 and the distance between the end of the first insulating layer 105 and the second pad 114 to satisfy 7L4 / 6≤L3≤6L4 can also avoid the first insulating layer 105 affecting the welding of the second pad 114 to the subsequent solder strips while avoiding affecting the ability of the first sub-gate 101 to collect charge carriers.

[0046] For the substrate 100, the substrate 100 can have a textured surface structure, and the substrate 100 can include a substrate 130. A front passivation layer 140 is formed on the front side 110 of the substrate 130, and a first doped region 150 and a second doped region 160 are formed on the back side 120 of the substrate 130. The first doped region 150 may be doped with dopant ions of the same conductivity type as the substrate 130, and the second doped region 160 may be doped with dopant ions of a different conductivity type than the substrate 130. For example, the substrate 130 is an N-type substrate 130, the first doped region 150 is an N-type doped region, and the second doped region 160 is a P-type doped region.

[0047] The substrate 100 may also form a back passivation layer 170 on the back side 120 of the substrate 130. The back passivation layer 170 is located on the surface of the first doped region 150 and the second doped region 160. The back passivation layer 170 may include a single-layer film structure or a stacked film structure.

[0048] In other words, the substrate 100 can be formed on the back contact cell, with other structures besides the main grid and sub-grid formed. After the main grid and sub-grid are formed, a complete cell structure can be formed. The corresponding structure of the back contact cell will not be described in detail here.

[0049] Regarding the front side 110 and the back side 120, the front side 110 is the light-receiving surface of the solar cell, used to receive incident light, while the back side 120 of the substrate 100 serves as the backlight surface.

[0050] The first sub-gate 101 is used to make contact with the first doped region 150 and collect the charge carriers in the first doped region 150.

[0051] Reference Figure 1 and Figure 3 In some embodiments, along the second direction Y, the first sub-gate 101 includes a first connecting portion 111 and a first interruption portion 121 arranged at intervals, with the first interruption portion 121 facing the second main gate 104. In other words, the first sub-gate 101 has an intermittent structure, with an interruption in the portion of the first sub-gate 101 facing the second main gate 104. Thus, even if the second main gate 104 penetrates into the surface of the substrate 100 during the formation of the second main gate 104, there will be no contact between the second main gate 104 and the first sub-gate 101, further avoiding electrical connection between the second main gate 104 and the first sub-gate 101, thereby further avoiding short circuits and improving the reliability of the solar cell.

[0052] The second sub-gate 102 is used to make contact with the second doped region 160 and collect the charge carriers in the second doped region 160.

[0053] In some embodiments, along the second direction Y, the second sub-gate 102 includes second connecting portions 112 and second discontinuities 122 spaced apart, with the second discontinuities 122 directly opposite the first main gate 103. In other words, the second sub-gate 102 has an intermittent structure, with a discontinuity in the portion of the second sub-gate 102 directly opposite the first main gate 103. Thus, even if the first main gate 103 penetrates into the surface of the substrate 100 during the formation of the first main gate 103, there will be no contact between the first main gate 103 and the second sub-gate 102. This further avoids electrical connections between the first main gate 103 and the second sub-gate 102, thereby further preventing short circuits and improving the reliability of the solar cell.

[0054] The first main gate 103 is used to make contact with the first sub-gate 101, thereby collecting the charge carriers on the first sub-gate 101 onto the first main gate 103 and outputting them through the first main gate 103.

[0055] In some embodiments, the second sub-gate 102 is a continuous structure along the second direction Y. In other words, the second sub-gate 102 does not have a second discontinuity 122. An insulating structure (not shown in the figure) is also provided in the portion corresponding to the second sub-gate 102 and the first main gate 103, so as to avoid the first main gate 103 being connected to the first sub-gate 101 and the second sub-gate 102 at the same time when the first main gate 103 is formed, thus avoiding the short circuit of the battery cell.

[0056] The second main gate 104 is used to make contact with the second sub-gate 102, thereby collecting the charge carriers on the second sub-gate 102 onto the second main gate 104 and outputting them through the second main gate 104.

[0057] In some embodiments, the first sub-gate 101 is a continuous structure along the second direction Y. In other words, the first sub-gate 101 does not have a first discontinuity 121. An insulating structure (not shown in the figure) is also provided in the corresponding part of the first sub-gate 101 and the second main gate 104, so as to avoid the second main gate 104 from being connected to the first sub-gate 101 and the second sub-gate 102 at the same time when the second main gate 104 is formed, thus avoiding the short circuit of the battery cell.

[0058] The first insulating layer 105 may be formed by printing insulating adhesive or by depositing a material with a relative permittivity of less than 2.8.

[0059] In some embodiments, the second main gate 104 is provided with a second pad 114, the height of which is greater than the height of the first insulating layer 105. On the one hand, by setting the height of the second pad 114 higher, the first insulating layer 105 can be prevented from covering the surface of the second pad 114 during its formation, and the first insulating layer 105 can be prevented from collapsing onto the surface of the second pad 114 if it does collapse. This prevents the first insulating layer 105 from affecting the connection between the second pad 114 and the solder ribbon. On the other hand, when connecting the second pad 114 and the solder ribbon, solder paste is usually applied to the surface of the second pad 114. Setting the height of the second pad 114 higher can prevent the solder paste from flowing outside the second pad 114 after melting.

[0060] In some embodiments, the substrate 100 includes two edge regions 180 arranged along a first direction X and a central region 190 located between the two edge regions 180. In the second direction Y, the width of the first insulating layer 105 located in the edge region 180 is greater than the width of the first insulating layer 105 located in the central region 190. Understandably, for a solar cell, the edge region 180 is actually the part located at the edge of the cell. During the formation of the cell string, the solder ribbon located at the edge of the solar cell is usually subjected to stress and bent. When the solder ribbon is bent, it may cause the solder ribbon to be electrically connected to the adjacent sub-busbar. For example, the solder ribbon is electrically connected to the second sub-busbar 102. When the solder ribbon is connected in series with other solar cells, it may cause the solder ribbon to be misaligned with the first insulating layer 105, resulting in overlap with the first sub-busbar 101, which may cause the solar cell to malfunction. Therefore, the width of the first insulating layer 105 is increased in the edge region 180 of the solar cell so that even if the solder ribbon is bent, the first insulating layer 105 still separates the solder ribbon from the first sub-busbar 101, thereby increasing the reliability of the solar cell.

[0061] In some embodiments, the width of the first insulating layer 105 located in the edge region 180 is 3mm to 10mm, for example, 4mm, 5mm, 6mm, 7mm, 8mm or 9mm, etc. For the first insulating layer 105, the larger the width of the first insulating layer 105, the stronger the ability to improve the reliability of the solar cell. However, the larger the width of the first insulating layer 105, the higher the cost of the first insulating layer 105. Moreover, for the solder ribbon, there is a certain extreme value for the offset of the solder ribbon. Setting the first insulating layer 105 too wide will cause a waste of cost. Therefore, setting the width of the first insulating layer 105 located in the edge region 180 to 3mm to 10mm improves the reliability of the solar cell while avoiding a waste of cost.

[0062] In some embodiments, the first insulating layer 105 may cover the top surface of the second main gate 104. By directly setting the first insulating layer 105 to cover the top surface of the second main gate 104, the process difficulty of forming the first insulating layer 105 can be reduced, and the control of the process of forming the first insulating layer 105 can be reduced.

[0063] In some embodiments, the first sub-gate 101 includes a first connecting portion 111 and a first discontinuity portion 121 arranged at intervals. The first insulating layer 105 covering the top surface of the second main gate 104 can also make the top surface of the solder strip relatively flat. For example, the solder strip is electrically connected to the second main gate 104. The second main gate 104 is also electrically connected to the second sub-gate 102. Therefore, at a certain position of the solder strip, there are the second main gate 104 and the second sub-gate 102 below the solder strip. If the first insulating layer 105 does not cover the top surface of the second main gate 104, then at a certain position of the solder strip, due to the presence of the first discontinuity portion 121, only the second main gate 104 exists below the solder strip. There is a certain height difference between these two parts of the solder strip. By setting the first insulating layer 105 to cover the top surface of the second main gate 104, the height of the solder strip can also be filled by the first insulating layer 105, thereby reducing the height difference between the various parts of the solder strip and improving the reliability of the battery cells after forming the battery string.

[0064] refer to Figure 6 , Figure 6 Another top view of a battery cell provided in an embodiment of this disclosure.

[0065] In some embodiments, the first sub-gate 101 includes first connecting portions 111 and first interrupted portions 121 arranged at intervals. A first insulating layer 105 covers the end of the first connecting portion 111 near the first interrupted portion 121 and also covers a portion of the surface of the first interrupted portion 121, exposing the top surface of the second main gate 104. In other words, the first insulating layer 105 is also intermittently arranged. On the one hand, the intermittent arrangement of the first insulating layer 105 can reduce the cost of the first insulating layer 105. At the same time, since the first insulating layer 105 covers a portion of the surface of the first interrupted portion 121, that is, the first insulating layer 105 covers the side of the first interrupted portion 121, even if the solder ribbon is misaligned, the solder ribbon will not be electrically connected to the first sub-gate 101. On the other hand, by exposing the top surface of the second main gate 104, the reliability of the connection between the solder ribbon and the second main gate 104 can be increased.

[0066] The first insulating layer 105 can contact the sidewall of the second main gate 104, exposing the top surface of the second main gate 104, or the first insulating layer 105 can be spaced apart from the sidewall of the second main gate 104, exposing the top surface of the second main gate 104.

[0067] Continue to refer to Figure 1In some embodiments, the second main gate 104 is provided with a second pad 114. In the second direction Y, the width of the first discontinuity 121 of the first sub-gate 101 directly opposite the second pad 114 is greater than the width of the first discontinuity 121 of the first sub-gate 101 offset from the second pad 114. In other words, the discontinuity distance of the first sub-gate 101 directly opposite the second pad 114 is larger. For the second pad 114, the width of the second pad 114 is greater than the width of the second main gate 104. If the discontinuity distance of the first sub-gate 101 is kept constant, the distance between the first sub-gate 101 and the second pad 114 will be reduced, which may lead to an electrical connection between the first sub-gate 101 and the second pad 114. Therefore, by setting the width of the first discontinuity 121 of the first sub-gate 101 directly opposite the second pad 114 to make room for the second pad 114, the reliability of the solar cell can be improved.

[0068] The second insulating layer 106 may be formed by printing insulating adhesive or by depositing a material with a relative permittivity of less than 2.8.

[0069] In some embodiments, the first main gate 103 is provided with a first pad 113, the height of which is greater than the height of the second insulating layer 106. On the one hand, by setting the height of the first pad 113 higher, the second insulating layer 106 can be prevented from covering the surface of the first pad 113 when it is formed, and the second insulating layer 106 can be prevented from collapsing onto the surface of the first pad 113 if it collapses. This prevents the second insulating layer 106 from affecting the connection between the first pad 113 and the solder ribbon. On the other hand, when connecting the first pad 113 and the solder ribbon, solder paste is usually applied to the surface of the pad. Setting the height of the first pad 113 higher can prevent the solder paste from flowing outside the first pad 113 after melting.

[0070] In some embodiments, the substrate 100 includes two edge regions 180 arranged along a first direction X and a central region 190 located between the two edge regions 180. In the second direction Y, the width of the second insulating layer 106 located in the edge region 180 is greater than the width of the second insulating layer 106 located in the central region 190. Similarly, for the solder ribbon electrically connected to the first sub-gate 101, the portion located at the edge may also bend when connected in series with other solar cells. Therefore, setting the width of the second insulating layer 106 located in the edge region 180 to be greater than the width of the second insulating layer 106 located in the central region 190 can increase the reliability of the solar cell, so that even if the solder ribbon bends, the second insulating layer 106 still exists to separate the solder ribbon from the second sub-gate 102.

[0071] In some embodiments, the width of the second insulating layer 106 located in the edge region 180 is 3mm to 10mm, for example, 4mm, 5mm, 6mm, 7mm, 8mm, or 9mm, etc. For the second insulating layer 106, a larger width improves the reliability of the solar cell; however, a larger width also increases the cost. Furthermore, for solder ribbons, there are certain extreme values ​​for ribbon misalignment. Setting an excessively wide second insulating layer 106 would result in wasted cost. Therefore, setting the width of the second insulating layer 106 located in the edge region 180 to 3mm to 10mm improves the reliability of the solar cell while avoiding wasted cost.

[0072] The second insulating layer 106 can cover the top surface of the first main gate 103. By directly setting the second insulating layer 106 to cover the top surface of the first main gate 103, the process difficulty of forming the second insulating layer 106 can be reduced, and the control of the process of forming the second insulating layer 106 can be reduced.

[0073] In some embodiments, the second sub-grid 102 includes second connecting portions 112 and second discontinuities 122 arranged at intervals. The second insulating layer 106 covering the top surface of the first main grid 103 can also make the top surface of the solder strip relatively flat, thereby reducing the height difference between different parts of the solder strip and improving the reliability of the battery cells after forming a battery string. The same or corresponding description can be referred to the above description of the first insulating layer 105, which will not be repeated here.

[0074] refer to Figure 6 In some embodiments, the second sub-gate 102 includes second connecting portions 112 and second interruptions 122 arranged at intervals. The second insulating layer 106 covers the end of the second connecting portion 112 near the second interruption 122 and also covers part of the surface of the second interruption 122, exposing the top surface of the first main gate 103. Similarly, the second insulating layer 106 can also be intermittently arranged. On the one hand, this can reduce the cost of the second insulating layer 106 and increase the reliability of the solar cell. The same or corresponding description can be referred to the above description of the first insulating layer 105, and will not be repeated here.

[0075] The second insulating layer 106 can contact the sidewall of the first main gate 103, exposing the top surface of the first main gate 103, or the second insulating layer 106 can be spaced apart from the sidewall of the first main gate 103, exposing the top surface of the first main gate 103.

[0076] Continue to refer to Figure 1In some embodiments, the first main gate 103 is provided with a first pad 113. In the second direction Y, the width of the second discontinuity 122 of the second sub-gate 102 directly opposite the first pad 113 is greater than the width of the second discontinuity 122 of the second sub-gate 102 that is offset from the first pad 113. Similarly, setting the first pad 113 will also reduce the distance between the second sub-gate 102 and the first pad 113, which may lead to an electrical connection between the second sub-gate 102 and the first pad 113. Therefore, by setting the second sub-gate 102 to make way for the first pad 113, the situation of the second sub-gate 102 and the first pad 113 being electrically connected is avoided, thereby improving the reliability of the solar cell.

[0077] This embodiment of the disclosure, by providing a first insulating layer 105 and a second insulating layer 106 in the provided battery cells, can prevent short circuits between the solder strip and the secondary grid that does not require electrical connection when connecting the battery cells in series, thereby improving the reliability of the process of connecting the battery cells into a battery string. Furthermore, when a first pad 113 exists on the first main grid 103, setting the distance between the second secondary grid 102 and the first pad 113, and the distance between the end of the second insulating layer 106 and the first pad 113, satisfies 7L² / 6 ≤ L1 ≤ 6L². This prevents the distance between the second insulating layer 106 and the first pad 113 from becoming too close, thus preventing the second insulating layer 106 from collapsing and extending onto the first pad 113. To avoid the second insulating layer 106 affecting the welding of the first pad 113 to the subsequent solder strips, and to prevent the distance between the second sub-gate 102 and the first pad 113 from being too large, thus avoiding affecting the ability of the second sub-gate 102 to collect charge carriers, thereby improving the performance of the cell while avoiding affecting the reliability of the cell. Similarly, when there is a second pad 114 on the second main gate 104, setting the distance between the first sub-gate 101 and the second pad 114 and the distance between the end of the first insulating layer 105 and the second pad 114 to satisfy 7L4 / 6≤L3≤6L4 can also avoid the first insulating layer 105 affecting the welding of the second pad 114 to the subsequent solder strips while avoiding affecting the ability of the first sub-gate 101 to collect charge carriers.

[0078] Another embodiment of this disclosure also provides a method for manufacturing a battery cell. This method can be used to form the aforementioned battery cell. The preparation method of the battery cell provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments will not be described again below.

[0079] refer to Figures 7 to 10 and Figure 1 , Figures 7 to 10 and Figure 1 This is a schematic diagram of the structure corresponding to each step of the method for manufacturing a battery cell according to another embodiment of this disclosure.

[0080] refer to Figure 7 , Figure 7 This is a top view of the substrate. In some embodiments, a method of manufacturing a solar cell may include providing a substrate 100, which includes a front side 110 and a back side 120.

[0081] The substrate 100 can be other structures that have already been formed in the back contact cell, except for the main grid and the sub-grid. For a corresponding description, please refer to the description in the above cell. It will not be repeated here.

[0082] refer to Figure 8 , Figure 8 In order to be in Figure 7 The first sub-grid and the second sub-grid are formed on the basis of the substrate. The method of manufacturing the solar cell may include: forming a plurality of first sub-grids 101 and a plurality of second sub-grids 102 arranged alternately along a first direction X, wherein the first sub-grids 101 and the second sub-grids 102 are located on the back side 120 of the substrate 100.

[0083] The first grid 101 can be formed first by screen printing, and then the second grid 102 can be formed, or the first grid and the second grid can be formed in the same process step.

[0084] refer to Figure 9 , Figure 9 In order to be in Figure 8 Based on this, a first main grid and a second main grid are formed. The method of manufacturing the solar cell may include: forming a first main grid 103 and a second main grid 104 arranged alternately along a second direction Y, wherein the first main grid 103 is electrically connected to a plurality of first sub-grids 101, and the second main grid 104 is electrically connected to a plurality of second sub-grids 102, and a first pad 113 is provided on the first main grid 103.

[0085] Similarly, the first main grid 103 can be formed first, and then the second main grid 104 can be formed, by using screen printing.

[0086] refer to Figure 10 , Figure 10 exist Figure 9A protective film is formed on the basis of the first main gate 103 and the second main gate 104. Before forming the first insulating layer 105, a protective film 107 is formed, the protective film 107 being located at the same position as the first pad 113 and the second pad 114. After forming the second insulating layer 106, the protective film 107 and the first insulating layer 105 and the second insulating layer 106 formed on the surface of the protective film 107 are removed. In other words, before forming the first insulating layer 105 and the second insulating layer 106, a protective film 107 is first formed at the positions corresponding to the first pad 113 and the second pad 114. Thus, even if there is a deviation in the process of forming the first insulating layer 105 and the second insulating layer 106, the material of the first insulating layer 105 and the second insulating layer 106 will only cover the surface of the protective film 107, thereby preventing the insulating material from covering the surface of the first pad 113 and the second pad 114. Subsequently, the protective film 107 is removed to expose the surface of the first pad 113 and the second pad 114, thereby improving the reliability of the manufacturing method.

[0087] refer to Figure 1 A first insulating layer 105 is formed, covering a portion of the surface of the first sub-gate 101; a second insulating layer 106 is formed, covering a portion of the surface of the second sub-gate 102; wherein, a first pad 113 is provided on the first main gate 103, and in the second direction Y, the distance between the second sub-gate 102, which is directly opposite and adjacent to the first pad 113, and the first pad 113 is a first distance L1, and the end of the second insulating layer 106 covering the second sub-gate 102 is... The distance between the first pad 113 and the second pad is L2, where 7L2 / 6≤L1≤6L2, and / or, the second main gate 104 is provided with a second pad 114, and in the second direction Y, the distance between the first sub-gate 101, which is directly opposite and adjacent to the second pad 114, and the second pad 114 is L3, and the distance between the end of the first insulating layer 105 covering the first sub-gate 101 and the second pad 114 is L4, where 7L2 / 6≤L1≤6L2.

[0088] By controlling the distance between the second sub-gate 102 and the first pad 113 and the distance between the end of the second insulating layer 106 and the first pad 113 to satisfy 7L2 / 6≤L1≤6L2, and / or controlling the distance between the first sub-gate 101 and the second pad 114 and the distance between the end of the first insulating layer 105 and the second pad 114 to satisfy 7L4 / 6≤L3≤6L4, the first insulating layer 105 or the second insulating layer 106 can be prevented from affecting the subsequent series connection of the battery cells, thereby improving the performance of the subsequent battery string formation.

[0089] Another embodiment of this disclosure provides a photovoltaic module for converting received light energy into electrical energy. The following will describe in detail a method for fabricating a solar cell according to another embodiment of this disclosure, with reference to the accompanying drawings. Figure 11 A partial three-dimensional structural schematic diagram of a photovoltaic module provided in yet another embodiment of this disclosure; Figure 12 for Figure 11 A schematic diagram of a cross-sectional structure along the cross-sectional direction MM1. It should be noted that parts that are the same as or corresponding to those in the aforementioned embodiments will not be described again here.

[0090] refer to Figure 11 and Figure 12 The photovoltaic module includes: a battery string, which is formed by connecting multiple battery cells as described in all or part of the above embodiments, or by connecting multiple battery cells formed by the manufacturing method of the battery cells as described in all or part of the above embodiments; an encapsulating film 41 for covering the surface of the battery string; and a cover plate 42 for covering the surface of the encapsulating film 41 facing away from the battery string.

[0091] It is worth noting that the solar cells are electrically connected to form multiple cell strings, which are electrically connected in series and / or parallel. The solar cells may include sliced ​​solar cells, which are formed by dividing a whole solar cell into smaller segments. Thus, the reduced current from the sliced ​​solar cells can improve the power loss of the photovoltaic module, thereby increasing the photoelectric conversion efficiency of the photovoltaic module.

[0092] In some embodiments, reference Figure 11 Multiple battery strings can be electrically connected by soldering ribbon 402. Figure 11 This illustration only depicts one possible positional relationship between battery cells, where the electrodes of the same polarity are arranged in the same direction, or where the positive electrode of each battery cell faces the same side. Thus, the solder ribbon 402 connects different sides of two adjacent battery cells. In some embodiments, the battery cells can also be arranged with electrodes of different polarities facing the same side, i.e., the electrodes of multiple adjacent battery cells are arranged in the order of first polarity, second polarity, and first polarity again. In this case, the solder ribbon 402 connects two adjacent battery cells on the same side.

[0093] In some embodiments, a fixing film is also provided at the edge of the solar cell, which abuts against the solder ribbon 402, thereby improving the stress resistance of the solder ribbon 402 when different solar cells are connected in series, thereby reducing the possibility of deformation of the solder ribbon 402, avoiding the solder ribbon 402 from overlapping with the opposite-shaped sub-busbar after deformation, thereby improving the reliability of the formed photovoltaic module.

[0094] In some embodiments, there is no spacing between the solar cells, meaning that the solar cells overlap each other.

[0095] In some embodiments, the encapsulating film 41 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back of the battery cell, and the second encapsulating layer covers the other of the front or back of the battery cell. Specifically, at least one of the first encapsulating layer or the second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, or polyethylene terephthalate (PET) film.

[0096] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0097] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulating film 41 can be an uneven surface, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0098] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A type of battery cell, characterized in that, include: A substrate, the substrate comprising opposing front and back sides; Multiple first sub-gates and multiple second sub-gates are arranged alternately along a first direction, wherein the first sub-gates and the second sub-gates are located on the back side of the substrate; A first main gate and a second main gate are arranged alternately along a second direction. The first main gate is electrically connected to multiple first sub-gates and spaced apart from the second sub-gates. The second main gate is electrically connected to multiple second sub-gates and spaced apart from the first sub-gates. A first insulating layer, wherein the first insulating layer at least covers a portion of the surface of the first sub-gate; A second insulating layer, wherein the second insulating layer at least covers a portion of the surface of the second sub-gate; Wherein, the first main gate is provided with a first pad, and in the second direction, the distance between the second sub-gate, which is directly opposite and adjacent to the first pad, and the first pad is a first distance L1, and the distance between the end of the second insulating layer covering the second sub-gate and the first pad is a second distance L2, 7L2 / 6≤L1≤6L2, and / or, the second main gate is provided with a second pad, and in the second direction, the distance between the first sub-gate, which is directly opposite and adjacent to the second pad, and the second pad is a third distance L3, and the distance between the end of the first insulating layer covering the first sub-gate and the second pad is a fourth distance L4, 7L4 / 6≤L3≤6L4.

2. The battery cell according to claim 1, characterized in that, The first main gate is provided with a first pad, the height of which is greater than the height of the second insulating layer, and / or the second main gate is provided with a second pad, the height of which is greater than the height of the first insulating layer.

3. The battery cell according to claim 1, characterized in that, The substrate includes two edge regions arranged along a first direction and a central region located between the two edge regions. In the second direction, the width of the first insulating layer located in the edge region is greater than the width of the first insulating layer located in the central region, and / or, the width of the second insulating layer located in the edge region is greater than the width of the second insulating layer located in the central region.

4. The battery cell according to claim 3, characterized in that, The width of the first insulating layer located in the edge region is 3mm to 10mm, and / or the width of the second insulating layer located in the edge region is 3mm to 10mm.

5. The battery cell according to claim 1, characterized in that, Along the second direction, the first sub-gate includes a first connecting portion and a first discontinuity portion arranged at intervals, the first discontinuity portion being directly opposite the second main gate; Along the second direction, the second sub-gate includes second connecting portions and second discontinuities arranged at intervals, with the second discontinuities facing the first main gate.

6. The battery cell according to claim 5, characterized in that, The first insulating layer covers the end of the first connection near the first interruption and also covers part of the surface of the first interruption, exposing the top surface of the second main gate; The second insulating layer covers the end of the second connection near the second interruption and also covers part of the surface of the second interruption, exposing the top surface of the first main gate.

7. The battery cell according to claim 5, characterized in that, The first main gate is provided with the first pad, and in the second direction, the width of the second discontinuity of the second sub-gate directly opposite the first pad is greater than the width of the second discontinuity of the second sub-gate offset from the first pad, and / or, the second main gate is provided with the second pad, and in the second direction, the width of the first discontinuity of the first sub-gate directly opposite the second pad is greater than the width of the first discontinuity of the first sub-gate offset from the second pad.

8. A method for manufacturing a battery cell, characterized in that, include: A substrate is provided, the substrate comprising opposing front and back sides; Multiple first sub-gates and multiple second sub-gates are formed and arranged alternately along a first direction, wherein the first sub-gates and the second sub-gates are located on the back side of the substrate; A first main gate and a second main gate are arranged alternately along a second direction. The first main gate is electrically connected to multiple first sub-gates, and the second main gate is electrically connected to multiple second sub-gates. A first insulating layer is formed, which covers a portion of the surface of the first sub-gate; A second insulating layer is formed, which covers a portion of the surface of the second sub-gate; Wherein, the first main gate is provided with a first pad, and in the second direction, the distance between the second sub-gate, which is directly opposite and adjacent to the first pad, and the first pad is a first distance L1, and the distance between the end of the second insulating layer covering the second sub-gate and the first pad is a second distance L2, 7L2 / 6≤L1≤6L2, and / or, the second main gate is provided with a second pad, and in the second direction, the distance between the first sub-gate, which is directly opposite and adjacent to the second pad, and the second pad is a third distance L3, and the distance between the end of the first insulating layer covering the first sub-gate and the second pad is a fourth distance L4, 7L2 / 6≤L1≤6L2.

9. The method for manufacturing a battery cell according to claim 8, characterized in that, The first main gate is provided with a first pad, and the second main gate is provided with a second pad. Before forming the first insulating layer, the method further includes: forming a protective film, wherein the protective film corresponds to the positions of the first pad and the second pad. After forming the second insulating layer, the process further includes: removing the protective film and the first and second insulating layers formed on the surface of the protective film.

10. A photovoltaic module, characterized in that, include: A battery string, consisting of multiple battery cells connected as described in any one of claims 1 to 7, or consisting of multiple battery cells as described in the claims. The battery cells formed by the manufacturing method of any one of claims 8 to 9 are connected together; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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